2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
60 #include <llvm-c/TargetMachine.h>
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t
;
66 typedef uint32_t xcb_visualid_t
;
67 typedef uint32_t xcb_window_t
;
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
73 #include "radv_entrypoints.h"
75 #include "wsi_common.h"
77 #define ATI_VENDOR_ID 0x1002
80 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
105 RADV_MEM_TYPE_GTT_CACHED
,
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111 static inline uint32_t
112 align_u32(uint32_t v
, uint32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 static inline uint32_t
119 align_u32_npot(uint32_t v
, uint32_t a
)
121 return (v
+ a
- 1) / a
* a
;
124 static inline uint64_t
125 align_u64(uint64_t v
, uint64_t a
)
127 assert(a
!= 0 && a
== (a
& -a
));
128 return (v
+ a
- 1) & ~(a
- 1);
131 static inline int32_t
132 align_i32(int32_t v
, int32_t a
)
134 assert(a
!= 0 && a
== (a
& -a
));
135 return (v
+ a
- 1) & ~(a
- 1);
138 /** Alignment must be a power of 2. */
140 radv_is_aligned(uintmax_t n
, uintmax_t a
)
142 assert(a
== (a
& -a
));
143 return (n
& (a
- 1)) == 0;
146 static inline uint32_t
147 round_up_u32(uint32_t v
, uint32_t a
)
149 return (v
+ a
- 1) / a
;
152 static inline uint64_t
153 round_up_u64(uint64_t v
, uint64_t a
)
155 return (v
+ a
- 1) / a
;
158 static inline uint32_t
159 radv_minify(uint32_t n
, uint32_t levels
)
161 if (unlikely(n
== 0))
164 return MAX2(n
>> levels
, 1);
167 radv_clamp_f(float f
, float min
, float max
)
180 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
182 if (*inout_mask
& clear_mask
) {
183 *inout_mask
&= ~clear_mask
;
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
205 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
215 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format
, va_list va
);
221 * Print a FINISHME message, including its source location.
223 #define radv_finishme(format, ...) \
225 static bool reported = false; \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
232 /* A non-fatal assert. Useful for debugging. */
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
239 #define radv_assert(x)
242 #define stub_return(v) \
244 radv_finishme("stub %s", __func__); \
250 radv_finishme("stub %s", __func__); \
254 void *radv_lookup_entrypoint(const char *name
);
256 struct radv_physical_device
{
257 VK_LOADER_DATA _loader_data
;
259 struct radv_instance
* instance
;
261 struct radeon_winsys
*ws
;
262 struct radeon_info rad_info
;
264 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
265 uint8_t driver_uuid
[VK_UUID_SIZE
];
266 uint8_t device_uuid
[VK_UUID_SIZE
];
267 uint8_t cache_uuid
[VK_UUID_SIZE
];
270 struct wsi_device wsi_device
;
272 bool has_rbplus
; /* if RB+ register exist */
273 bool rbplus_allowed
; /* if RB+ is allowed */
274 bool has_clear_state
;
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
279 struct disk_cache
* disk_cache
;
281 VkPhysicalDeviceMemoryProperties memory_properties
;
282 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
285 struct radv_instance
{
286 VK_LOADER_DATA _loader_data
;
288 VkAllocationCallbacks alloc
;
291 int physicalDeviceCount
;
292 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
294 uint64_t debug_flags
;
295 uint64_t perftest_flags
;
298 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
299 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
301 bool radv_instance_extension_supported(const char *name
);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
303 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
308 struct radv_pipeline_cache
{
309 struct radv_device
* device
;
310 pthread_mutex_t mutex
;
314 uint32_t kernel_count
;
315 struct cache_entry
** hash_table
;
318 VkAllocationCallbacks alloc
;
321 struct radv_pipeline_key
{
322 uint32_t instance_rate_inputs
;
323 unsigned tess_input_vertices
;
327 uint32_t multisample
: 1;
328 uint32_t has_multiview_view_index
: 1;
332 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
333 struct radv_device
*device
);
335 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
337 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
338 const void *data
, size_t size
);
340 struct radv_shader_variant
;
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
344 struct radv_pipeline_cache
*cache
,
345 const unsigned char *sha1
,
346 struct radv_shader_variant
**variants
);
349 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
350 struct radv_pipeline_cache
*cache
,
351 const unsigned char *sha1
,
352 struct radv_shader_variant
**variants
,
353 const void *const *codes
,
354 const unsigned *code_sizes
);
356 struct radv_meta_state
{
357 VkAllocationCallbacks alloc
;
359 struct radv_pipeline_cache cache
;
362 * Use array element `i` for images with `2^i` samples.
365 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
366 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
368 VkRenderPass depthstencil_rp
;
369 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
370 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
371 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
372 } clear
[1 + MAX_SAMPLES_LOG2
];
374 VkPipelineLayout clear_color_p_layout
;
375 VkPipelineLayout clear_depth_p_layout
;
377 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
379 /** Pipeline that blits from a 1D image. */
380 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
382 /** Pipeline that blits from a 2D image. */
383 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
385 /** Pipeline that blits from a 3D image. */
386 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
388 VkRenderPass depth_only_rp
;
389 VkPipeline depth_only_1d_pipeline
;
390 VkPipeline depth_only_2d_pipeline
;
391 VkPipeline depth_only_3d_pipeline
;
393 VkRenderPass stencil_only_rp
;
394 VkPipeline stencil_only_1d_pipeline
;
395 VkPipeline stencil_only_2d_pipeline
;
396 VkPipeline stencil_only_3d_pipeline
;
397 VkPipelineLayout pipeline_layout
;
398 VkDescriptorSetLayout ds_layout
;
402 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
404 VkPipelineLayout p_layouts
[2];
405 VkDescriptorSetLayout ds_layouts
[2];
406 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
408 VkRenderPass depth_only_rp
;
409 VkPipeline depth_only_pipeline
[2];
411 VkRenderPass stencil_only_rp
;
412 VkPipeline stencil_only_pipeline
[2];
416 VkPipelineLayout img_p_layout
;
417 VkDescriptorSetLayout img_ds_layout
;
421 VkPipelineLayout img_p_layout
;
422 VkDescriptorSetLayout img_ds_layout
;
426 VkPipelineLayout img_p_layout
;
427 VkDescriptorSetLayout img_ds_layout
;
431 VkPipelineLayout img_p_layout
;
432 VkDescriptorSetLayout img_ds_layout
;
442 VkDescriptorSetLayout ds_layout
;
443 VkPipelineLayout p_layout
;
446 VkPipeline i_pipeline
;
447 VkPipeline srgb_pipeline
;
448 } rc
[MAX_SAMPLES_LOG2
];
452 VkDescriptorSetLayout ds_layout
;
453 VkPipelineLayout p_layout
;
456 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
457 VkPipeline pipeline
[NUM_META_FS_KEYS
];
458 } rc
[MAX_SAMPLES_LOG2
];
462 VkPipeline decompress_pipeline
;
463 VkPipeline resummarize_pipeline
;
465 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
468 VkPipeline cmask_eliminate_pipeline
;
469 VkPipeline fmask_decompress_pipeline
;
474 VkPipelineLayout fill_p_layout
;
475 VkPipelineLayout copy_p_layout
;
476 VkDescriptorSetLayout fill_ds_layout
;
477 VkDescriptorSetLayout copy_ds_layout
;
478 VkPipeline fill_pipeline
;
479 VkPipeline copy_pipeline
;
483 VkDescriptorSetLayout ds_layout
;
484 VkPipelineLayout p_layout
;
485 VkPipeline occlusion_query_pipeline
;
486 VkPipeline pipeline_statistics_query_pipeline
;
491 #define RADV_QUEUE_GENERAL 0
492 #define RADV_QUEUE_COMPUTE 1
493 #define RADV_QUEUE_TRANSFER 2
495 #define RADV_MAX_QUEUE_FAMILIES 3
497 enum ring_type
radv_queue_family_to_ring(int f
);
500 VK_LOADER_DATA _loader_data
;
501 struct radv_device
* device
;
502 struct radeon_winsys_ctx
*hw_ctx
;
503 enum radeon_ctx_priority priority
;
504 uint32_t queue_family_index
;
507 uint32_t scratch_size
;
508 uint32_t compute_scratch_size
;
509 uint32_t esgs_ring_size
;
510 uint32_t gsvs_ring_size
;
512 bool has_sample_positions
;
514 struct radeon_winsys_bo
*scratch_bo
;
515 struct radeon_winsys_bo
*descriptor_bo
;
516 struct radeon_winsys_bo
*compute_scratch_bo
;
517 struct radeon_winsys_bo
*esgs_ring_bo
;
518 struct radeon_winsys_bo
*gsvs_ring_bo
;
519 struct radeon_winsys_bo
*tess_factor_ring_bo
;
520 struct radeon_winsys_bo
*tess_offchip_ring_bo
;
521 struct radeon_winsys_cs
*initial_preamble_cs
;
522 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
523 struct radeon_winsys_cs
*continue_preamble_cs
;
527 VK_LOADER_DATA _loader_data
;
529 VkAllocationCallbacks alloc
;
531 struct radv_instance
* instance
;
532 struct radeon_winsys
*ws
;
534 struct radv_meta_state meta_state
;
536 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
537 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
538 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
540 bool llvm_supports_spill
;
541 bool has_distributed_tess
;
543 uint32_t tess_offchip_block_dw_size
;
544 uint32_t scratch_waves
;
545 uint32_t dispatch_initiator
;
547 uint32_t gs_table_depth
;
549 /* MSAA sample locations.
550 * The first index is the sample index.
551 * The second index is the coordinate: X, Y. */
552 float sample_locations_1x
[1][2];
553 float sample_locations_2x
[2][2];
554 float sample_locations_4x
[4][2];
555 float sample_locations_8x
[8][2];
556 float sample_locations_16x
[16][2];
559 uint32_t gfx_init_size_dw
;
560 struct radeon_winsys_bo
*gfx_init
;
562 struct radeon_winsys_bo
*trace_bo
;
563 uint32_t *trace_id_ptr
;
565 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
566 bool keep_shader_info
;
568 struct radv_physical_device
*physical_device
;
570 /* Backup in-memory cache to be used if the app doesn't provide one */
571 struct radv_pipeline_cache
* mem_cache
;
574 * use different counters so MSAA MRTs get consecutive surface indices,
575 * even if MASK is allocated in between.
577 uint32_t image_mrt_offset_counter
;
578 uint32_t fmask_mrt_offset_counter
;
579 struct list_head shader_slabs
;
580 mtx_t shader_slab_mutex
;
582 /* For detecting VM faults reported by dmesg. */
583 uint64_t dmesg_timestamp
;
586 struct radv_device_memory
{
587 struct radeon_winsys_bo
*bo
;
588 /* for dedicated allocations */
589 struct radv_image
*image
;
590 struct radv_buffer
*buffer
;
592 VkDeviceSize map_size
;
597 struct radv_descriptor_range
{
602 struct radv_descriptor_set
{
603 const struct radv_descriptor_set_layout
*layout
;
606 struct radeon_winsys_bo
*bo
;
608 uint32_t *mapped_ptr
;
609 struct radv_descriptor_range
*dynamic_descriptors
;
611 struct radeon_winsys_bo
*descriptors
[0];
614 struct radv_push_descriptor_set
616 struct radv_descriptor_set set
;
620 struct radv_descriptor_pool_entry
{
623 struct radv_descriptor_set
*set
;
626 struct radv_descriptor_pool
{
627 struct radeon_winsys_bo
*bo
;
629 uint64_t current_offset
;
632 uint8_t *host_memory_base
;
633 uint8_t *host_memory_ptr
;
634 uint8_t *host_memory_end
;
636 uint32_t entry_count
;
637 uint32_t max_entry_count
;
638 struct radv_descriptor_pool_entry entries
[0];
641 struct radv_descriptor_update_template_entry
{
642 VkDescriptorType descriptor_type
;
644 /* The number of descriptors to update */
645 uint32_t descriptor_count
;
647 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
650 /* In dwords. Not valid/used for dynamic descriptors */
653 uint32_t buffer_offset
;
655 /* Only valid for combined image samplers and samplers */
656 uint16_t has_sampler
;
662 /* For push descriptors */
663 const uint32_t *immutable_samplers
;
666 struct radv_descriptor_update_template
{
667 uint32_t entry_count
;
668 struct radv_descriptor_update_template_entry entry
[0];
672 struct radv_device
* device
;
675 VkBufferUsageFlags usage
;
676 VkBufferCreateFlags flags
;
679 struct radeon_winsys_bo
* bo
;
686 enum radv_cmd_dirty_bits
{
687 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
688 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
689 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
690 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
691 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
692 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
693 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
694 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
695 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
696 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
697 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
698 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
699 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 11,
700 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 12,
703 enum radv_cmd_flush_bits
{
704 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
705 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
706 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
707 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
708 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
709 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
710 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
711 /* Same as above, but only writes back and doesn't invalidate */
712 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
713 /* Framebuffer caches */
714 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
715 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
716 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
717 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
718 /* Engine synchronization. */
719 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
720 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
721 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
722 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
724 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
725 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
726 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
727 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
730 struct radv_vertex_binding
{
731 struct radv_buffer
* buffer
;
735 struct radv_viewport_state
{
737 VkViewport viewports
[MAX_VIEWPORTS
];
740 struct radv_scissor_state
{
742 VkRect2D scissors
[MAX_SCISSORS
];
745 struct radv_dynamic_state
{
747 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
748 * Defines the set of saved dynamic state.
752 struct radv_viewport_state viewport
;
754 struct radv_scissor_state scissor
;
764 float blend_constants
[4];
774 } stencil_compare_mask
;
779 } stencil_write_mask
;
787 extern const struct radv_dynamic_state default_dynamic_state
;
790 radv_get_debug_option_name(int id
);
793 radv_get_perftest_option_name(int id
);
796 * Attachment state when recording a renderpass instance.
798 * The clear value is valid only if there exists a pending clear.
800 struct radv_attachment_state
{
801 VkImageAspectFlags pending_clear_aspects
;
802 uint32_t cleared_views
;
803 VkClearValue clear_value
;
804 VkImageLayout current_layout
;
807 struct radv_cmd_state
{
808 /* Vertex descriptors */
809 bool vb_prefetch_dirty
;
813 bool push_descriptors_dirty
;
817 struct radv_pipeline
* pipeline
;
818 struct radv_pipeline
* emitted_pipeline
;
819 struct radv_pipeline
* compute_pipeline
;
820 struct radv_pipeline
* emitted_compute_pipeline
;
821 struct radv_framebuffer
* framebuffer
;
822 struct radv_render_pass
* pass
;
823 const struct radv_subpass
* subpass
;
824 struct radv_dynamic_state dynamic
;
825 struct radv_attachment_state
* attachments
;
826 VkRect2D render_area
;
829 struct radv_buffer
*index_buffer
;
830 uint64_t index_offset
;
832 uint32_t max_index_count
;
834 int32_t last_index_type
;
836 int32_t last_primitive_reset_en
;
837 uint32_t last_primitive_reset_index
;
838 enum radv_cmd_flush_bits flush_bits
;
839 unsigned active_occlusion_queries
;
841 uint32_t descriptors_dirty
;
842 uint32_t valid_descriptors
;
844 uint32_t last_ia_multi_vgt_param
;
847 struct radv_cmd_pool
{
848 VkAllocationCallbacks alloc
;
849 struct list_head cmd_buffers
;
850 struct list_head free_cmd_buffers
;
851 uint32_t queue_family_index
;
854 struct radv_cmd_buffer_upload
{
858 struct radeon_winsys_bo
*upload_bo
;
859 struct list_head list
;
862 enum radv_cmd_buffer_status
{
863 RADV_CMD_BUFFER_STATUS_INVALID
,
864 RADV_CMD_BUFFER_STATUS_INITIAL
,
865 RADV_CMD_BUFFER_STATUS_RECORDING
,
866 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
867 RADV_CMD_BUFFER_STATUS_PENDING
,
870 struct radv_cmd_buffer
{
871 VK_LOADER_DATA _loader_data
;
873 struct radv_device
* device
;
875 struct radv_cmd_pool
* pool
;
876 struct list_head pool_link
;
878 VkCommandBufferUsageFlags usage_flags
;
879 VkCommandBufferLevel level
;
880 enum radv_cmd_buffer_status status
;
881 struct radeon_winsys_cs
*cs
;
882 struct radv_cmd_state state
;
883 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
884 uint32_t queue_family_index
;
886 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
887 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
888 VkShaderStageFlags push_constant_stages
;
889 struct radv_push_descriptor_set push_descriptors
;
890 struct radv_descriptor_set meta_push_descriptors
;
891 struct radv_descriptor_set
*descriptors
[MAX_SETS
];
893 struct radv_cmd_buffer_upload upload
;
895 uint32_t scratch_size_needed
;
896 uint32_t compute_scratch_size_needed
;
897 uint32_t esgs_ring_size_needed
;
898 uint32_t gsvs_ring_size_needed
;
899 bool tess_rings_needed
;
900 bool sample_positions_needed
;
902 VkResult record_result
;
904 int ring_offsets_idx
; /* just used for verification */
905 uint32_t gfx9_fence_offset
;
906 struct radeon_winsys_bo
*gfx9_fence_bo
;
907 uint32_t gfx9_fence_idx
;
912 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
914 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
915 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
917 void cik_create_gfx_config(struct radv_device
*device
);
919 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
920 int count
, const VkViewport
*viewports
);
921 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
922 int count
, const VkRect2D
*scissors
,
923 const VkViewport
*viewports
, bool can_use_guardband
);
924 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
925 bool instanced_draw
, bool indirect_draw
,
926 uint32_t draw_vertex_count
);
927 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
929 enum chip_class chip_class
,
931 unsigned event
, unsigned event_flags
,
937 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
939 uint64_t va
, uint32_t ref
,
941 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
943 enum chip_class chip_class
,
944 uint32_t *fence_ptr
, uint64_t va
,
946 enum radv_cmd_flush_bits flush_bits
);
947 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
948 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
949 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
950 uint64_t src_va
, uint64_t dest_va
,
952 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
954 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
955 uint64_t size
, unsigned value
);
956 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
958 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
961 unsigned *out_offset
,
964 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
965 const struct radv_subpass
*subpass
,
968 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
969 unsigned size
, unsigned alignmnet
,
970 const void *data
, unsigned *out_offset
);
972 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
973 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
974 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
975 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
976 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
977 unsigned radv_cayman_get_maxdist(int log_samples
);
978 void radv_device_init_msaa(struct radv_device
*device
);
979 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
980 struct radv_image
*image
,
981 VkClearDepthStencilValue ds_clear_value
,
982 VkImageAspectFlags aspects
);
983 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
984 struct radv_image
*image
,
986 uint32_t color_values
[2]);
987 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
988 struct radv_image
*image
,
990 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
991 struct radeon_winsys_bo
*bo
,
992 uint64_t offset
, uint64_t size
, uint32_t value
);
993 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
994 bool radv_get_memory_fd(struct radv_device
*device
,
995 struct radv_device_memory
*memory
,
999 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1001 * Limitations: Can't call normal dispatch functions without binding or rebinding
1002 * the compute pipeline.
1004 void radv_unaligned_dispatch(
1005 struct radv_cmd_buffer
*cmd_buffer
,
1011 struct radeon_winsys_bo
*bo
;
1015 struct radv_shader_module
;
1017 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1018 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1019 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1021 radv_hash_shaders(unsigned char *hash
,
1022 const VkPipelineShaderStageCreateInfo
**stages
,
1023 const struct radv_pipeline_layout
*layout
,
1024 const struct radv_pipeline_key
*key
,
1027 static inline gl_shader_stage
1028 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1030 assert(__builtin_popcount(vk_stage
) == 1);
1031 return ffs(vk_stage
) - 1;
1034 static inline VkShaderStageFlagBits
1035 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1037 return (1 << mesa_stage
);
1040 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1042 #define radv_foreach_stage(stage, stage_bits) \
1043 for (gl_shader_stage stage, \
1044 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1045 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1046 __tmp &= ~(1 << (stage)))
1048 struct radv_depth_stencil_state
{
1049 uint32_t db_depth_control
;
1050 uint32_t db_stencil_control
;
1051 uint32_t db_render_control
;
1052 uint32_t db_render_override2
;
1055 struct radv_blend_state
{
1056 uint32_t cb_color_control
;
1057 uint32_t cb_target_mask
;
1058 uint32_t sx_mrt_blend_opt
[8];
1059 uint32_t cb_blend_control
[8];
1061 uint32_t spi_shader_col_format
;
1062 uint32_t cb_shader_mask
;
1063 uint32_t db_alpha_to_mask
;
1066 unsigned radv_format_meta_fs_key(VkFormat format
);
1068 struct radv_raster_state
{
1069 uint32_t pa_cl_clip_cntl
;
1070 uint32_t spi_interp_control
;
1071 uint32_t pa_su_vtx_cntl
;
1072 uint32_t pa_su_sc_mode_cntl
;
1075 struct radv_multisample_state
{
1077 uint32_t pa_sc_line_cntl
;
1078 uint32_t pa_sc_mode_cntl_0
;
1079 uint32_t pa_sc_mode_cntl_1
;
1080 uint32_t pa_sc_aa_config
;
1081 uint32_t pa_sc_aa_mask
[2];
1082 unsigned num_samples
;
1085 struct radv_prim_vertex_count
{
1090 struct radv_tessellation_state
{
1091 uint32_t ls_hs_config
;
1092 uint32_t tcs_in_layout
;
1093 uint32_t tcs_out_layout
;
1094 uint32_t tcs_out_offsets
;
1095 uint32_t offchip_layout
;
1096 unsigned num_patches
;
1098 unsigned num_tcs_input_cp
;
1102 struct radv_gs_state
{
1103 uint32_t vgt_gs_onchip_cntl
;
1104 uint32_t vgt_gs_max_prims_per_subgroup
;
1105 uint32_t vgt_esgs_ring_itemsize
;
1109 struct radv_vertex_elements_info
{
1110 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1111 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1112 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1113 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1117 struct radv_vs_state
{
1118 uint32_t pa_cl_vs_out_cntl
;
1119 uint32_t spi_shader_pos_format
;
1120 uint32_t spi_vs_out_config
;
1121 uint32_t vgt_reuse_off
;
1124 #define SI_GS_PER_ES 128
1126 struct radv_pipeline
{
1127 struct radv_device
* device
;
1128 struct radv_dynamic_state dynamic_state
;
1130 struct radv_pipeline_layout
* layout
;
1132 bool needs_data_cache
;
1133 bool need_indirect_descriptor_sets
;
1134 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1135 struct radv_shader_variant
*gs_copy_shader
;
1136 VkShaderStageFlags active_stages
;
1138 struct radv_vertex_elements_info vertex_elements
;
1140 uint32_t binding_stride
[MAX_VBS
];
1142 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1145 struct radv_blend_state blend
;
1146 struct radv_depth_stencil_state ds
;
1147 struct radv_raster_state raster
;
1148 struct radv_multisample_state ms
;
1149 struct radv_tessellation_state tess
;
1150 struct radv_gs_state gs
;
1151 struct radv_vs_state vs
;
1152 uint32_t db_shader_control
;
1153 uint32_t shader_z_format
;
1156 uint32_t vgt_gs_mode
;
1157 bool vgt_primitiveid_en
;
1158 bool prim_restart_enable
;
1159 bool partial_es_wave
;
1160 uint8_t primgroup_size
;
1161 unsigned esgs_ring_size
;
1162 unsigned gsvs_ring_size
;
1163 uint32_t ps_input_cntl
[32];
1164 uint32_t ps_input_cntl_num
;
1165 uint32_t vgt_shader_stages_en
;
1166 uint32_t vtx_base_sgpr
;
1167 uint32_t base_ia_multi_vgt_param
;
1168 bool wd_switch_on_eop
;
1169 bool ia_switch_on_eoi
;
1170 bool partial_vs_wave
;
1171 uint8_t vtx_emit_num
;
1172 uint32_t vtx_reuse_depth
;
1173 struct radv_prim_vertex_count prim_vertex_count
;
1174 bool can_use_guardband
;
1179 unsigned scratch_bytes_per_wave
;
1182 static inline bool radv_pipeline_has_gs(struct radv_pipeline
*pipeline
)
1184 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1187 static inline bool radv_pipeline_has_tess(struct radv_pipeline
*pipeline
)
1189 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1192 struct ac_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1193 gl_shader_stage stage
,
1196 struct radv_shader_variant
*radv_get_vertex_shader(struct radv_pipeline
*pipeline
);
1198 struct radv_graphics_pipeline_create_info
{
1200 bool db_depth_clear
;
1201 bool db_stencil_clear
;
1202 bool db_depth_disable_expclear
;
1203 bool db_stencil_disable_expclear
;
1204 bool db_flush_depth_inplace
;
1205 bool db_flush_stencil_inplace
;
1206 bool db_resummarize
;
1207 uint32_t custom_blend_mode
;
1211 radv_graphics_pipeline_create(VkDevice device
,
1212 VkPipelineCache cache
,
1213 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1214 const struct radv_graphics_pipeline_create_info
*extra
,
1215 const VkAllocationCallbacks
*alloc
,
1216 VkPipeline
*pPipeline
);
1218 struct vk_format_description
;
1219 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1220 int first_non_void
);
1221 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1222 int first_non_void
);
1223 uint32_t radv_translate_colorformat(VkFormat format
);
1224 uint32_t radv_translate_color_numformat(VkFormat format
,
1225 const struct vk_format_description
*desc
,
1226 int first_non_void
);
1227 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1228 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1229 uint32_t radv_translate_dbformat(VkFormat format
);
1230 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1231 const struct vk_format_description
*desc
,
1232 int first_non_void
);
1233 uint32_t radv_translate_tex_numformat(VkFormat format
,
1234 const struct vk_format_description
*desc
,
1235 int first_non_void
);
1236 bool radv_format_pack_clear_color(VkFormat format
,
1237 uint32_t clear_vals
[2],
1238 VkClearColorValue
*value
);
1239 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1240 bool radv_dcc_formats_compatible(VkFormat format1
,
1243 struct radv_fmask_info
{
1247 unsigned pitch_in_pixels
;
1248 unsigned bank_height
;
1249 unsigned slice_tile_max
;
1250 unsigned tile_mode_index
;
1251 unsigned tile_swizzle
;
1254 struct radv_cmask_info
{
1258 unsigned slice_tile_max
;
1259 unsigned base_address_reg
;
1264 /* The original VkFormat provided by the client. This may not match any
1265 * of the actual surface formats.
1268 VkImageAspectFlags aspects
;
1269 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1270 struct ac_surf_info info
;
1271 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1272 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1277 unsigned queue_family_mask
;
1281 /* Set when bound */
1282 struct radeon_winsys_bo
*bo
;
1283 VkDeviceSize offset
;
1284 uint64_t dcc_offset
;
1285 uint64_t htile_offset
;
1286 bool tc_compatible_htile
;
1287 struct radeon_surf surface
;
1289 struct radv_fmask_info fmask
;
1290 struct radv_cmask_info cmask
;
1291 uint64_t clear_value_offset
;
1292 uint64_t dcc_pred_offset
;
1295 /* Whether the image has a htile that is known consistent with the contents of
1297 bool radv_layout_has_htile(const struct radv_image
*image
,
1298 VkImageLayout layout
,
1299 unsigned queue_mask
);
1301 /* Whether the image has a htile that is known consistent with the contents of
1302 * the image and is allowed to be in compressed form.
1304 * If this is false reads that don't use the htile should be able to return
1307 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1308 VkImageLayout layout
,
1309 unsigned queue_mask
);
1311 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1312 VkImageLayout layout
,
1313 unsigned queue_mask
);
1316 radv_vi_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1318 return image
->surface
.dcc_size
&& level
< image
->surface
.num_dcc_levels
;
1322 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1324 return image
->surface
.htile_size
&& level
== 0;
1327 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1329 static inline uint32_t
1330 radv_get_layerCount(const struct radv_image
*image
,
1331 const VkImageSubresourceRange
*range
)
1333 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1334 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1337 static inline uint32_t
1338 radv_get_levelCount(const struct radv_image
*image
,
1339 const VkImageSubresourceRange
*range
)
1341 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1342 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1345 struct radeon_bo_metadata
;
1347 radv_init_metadata(struct radv_device
*device
,
1348 struct radv_image
*image
,
1349 struct radeon_bo_metadata
*metadata
);
1351 struct radv_image_view
{
1352 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1353 struct radeon_winsys_bo
*bo
;
1355 VkImageViewType type
;
1356 VkImageAspectFlags aspect_mask
;
1358 uint32_t base_layer
;
1359 uint32_t layer_count
;
1361 uint32_t level_count
;
1362 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1364 uint32_t descriptor
[16];
1366 /* Descriptor for use as a storage image as opposed to a sampled image.
1367 * This has a few differences for cube maps (e.g. type).
1369 uint32_t storage_descriptor
[16];
1372 struct radv_image_create_info
{
1373 const VkImageCreateInfo
*vk_info
;
1377 VkResult
radv_image_create(VkDevice _device
,
1378 const struct radv_image_create_info
*info
,
1379 const VkAllocationCallbacks
* alloc
,
1382 void radv_image_view_init(struct radv_image_view
*view
,
1383 struct radv_device
*device
,
1384 const VkImageViewCreateInfo
* pCreateInfo
);
1386 struct radv_buffer_view
{
1387 struct radeon_winsys_bo
*bo
;
1389 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1392 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1393 struct radv_device
*device
,
1394 const VkBufferViewCreateInfo
* pCreateInfo
);
1396 static inline struct VkExtent3D
1397 radv_sanitize_image_extent(const VkImageType imageType
,
1398 const struct VkExtent3D imageExtent
)
1400 switch (imageType
) {
1401 case VK_IMAGE_TYPE_1D
:
1402 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1403 case VK_IMAGE_TYPE_2D
:
1404 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1405 case VK_IMAGE_TYPE_3D
:
1408 unreachable("invalid image type");
1412 static inline struct VkOffset3D
1413 radv_sanitize_image_offset(const VkImageType imageType
,
1414 const struct VkOffset3D imageOffset
)
1416 switch (imageType
) {
1417 case VK_IMAGE_TYPE_1D
:
1418 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1419 case VK_IMAGE_TYPE_2D
:
1420 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1421 case VK_IMAGE_TYPE_3D
:
1424 unreachable("invalid image type");
1429 radv_image_extent_compare(const struct radv_image
*image
,
1430 const VkExtent3D
*extent
)
1432 if (extent
->width
!= image
->info
.width
||
1433 extent
->height
!= image
->info
.height
||
1434 extent
->depth
!= image
->info
.depth
)
1439 struct radv_sampler
{
1443 struct radv_color_buffer_info
{
1444 uint64_t cb_color_base
;
1445 uint64_t cb_color_cmask
;
1446 uint64_t cb_color_fmask
;
1447 uint64_t cb_dcc_base
;
1448 uint32_t cb_color_pitch
;
1449 uint32_t cb_color_slice
;
1450 uint32_t cb_color_view
;
1451 uint32_t cb_color_info
;
1452 uint32_t cb_color_attrib
;
1453 uint32_t cb_color_attrib2
;
1454 uint32_t cb_dcc_control
;
1455 uint32_t cb_color_cmask_slice
;
1456 uint32_t cb_color_fmask_slice
;
1457 uint32_t cb_clear_value0
;
1458 uint32_t cb_clear_value1
;
1461 struct radv_ds_buffer_info
{
1462 uint64_t db_z_read_base
;
1463 uint64_t db_stencil_read_base
;
1464 uint64_t db_z_write_base
;
1465 uint64_t db_stencil_write_base
;
1466 uint64_t db_htile_data_base
;
1467 uint32_t db_depth_info
;
1469 uint32_t db_stencil_info
;
1470 uint32_t db_depth_view
;
1471 uint32_t db_depth_size
;
1472 uint32_t db_depth_slice
;
1473 uint32_t db_htile_surface
;
1474 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1475 uint32_t db_z_info2
;
1476 uint32_t db_stencil_info2
;
1480 struct radv_attachment_info
{
1482 struct radv_color_buffer_info cb
;
1483 struct radv_ds_buffer_info ds
;
1485 struct radv_image_view
*attachment
;
1488 struct radv_framebuffer
{
1493 uint32_t attachment_count
;
1494 struct radv_attachment_info attachments
[0];
1497 struct radv_subpass_barrier
{
1498 VkPipelineStageFlags src_stage_mask
;
1499 VkAccessFlags src_access_mask
;
1500 VkAccessFlags dst_access_mask
;
1503 struct radv_subpass
{
1504 uint32_t input_count
;
1505 uint32_t color_count
;
1506 VkAttachmentReference
* input_attachments
;
1507 VkAttachmentReference
* color_attachments
;
1508 VkAttachmentReference
* resolve_attachments
;
1509 VkAttachmentReference depth_stencil_attachment
;
1511 /** Subpass has at least one resolve attachment */
1514 struct radv_subpass_barrier start_barrier
;
1519 struct radv_render_pass_attachment
{
1522 VkAttachmentLoadOp load_op
;
1523 VkAttachmentLoadOp stencil_load_op
;
1524 VkImageLayout initial_layout
;
1525 VkImageLayout final_layout
;
1529 struct radv_render_pass
{
1530 uint32_t attachment_count
;
1531 uint32_t subpass_count
;
1532 VkAttachmentReference
* subpass_attachments
;
1533 struct radv_render_pass_attachment
* attachments
;
1534 struct radv_subpass_barrier end_barrier
;
1535 struct radv_subpass subpasses
[0];
1538 VkResult
radv_device_init_meta(struct radv_device
*device
);
1539 void radv_device_finish_meta(struct radv_device
*device
);
1541 struct radv_query_pool
{
1542 struct radeon_winsys_bo
*bo
;
1544 uint32_t availability_offset
;
1547 uint32_t pipeline_stats_mask
;
1550 struct radv_semaphore
{
1551 /* use a winsys sem for non-exportable */
1552 struct radeon_winsys_sem
*sem
;
1554 uint32_t temp_syncobj
;
1557 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1559 const VkSemaphore
*wait_sems
,
1560 int num_signal_sems
,
1561 const VkSemaphore
*signal_sems
);
1562 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1564 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1565 struct radv_descriptor_set
*set
,
1569 radv_update_descriptor_sets(struct radv_device
*device
,
1570 struct radv_cmd_buffer
*cmd_buffer
,
1571 VkDescriptorSet overrideSet
,
1572 uint32_t descriptorWriteCount
,
1573 const VkWriteDescriptorSet
*pDescriptorWrites
,
1574 uint32_t descriptorCopyCount
,
1575 const VkCopyDescriptorSet
*pDescriptorCopies
);
1578 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1579 struct radv_cmd_buffer
*cmd_buffer
,
1580 struct radv_descriptor_set
*set
,
1581 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1584 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1585 VkPipelineBindPoint pipelineBindPoint
,
1586 VkPipelineLayout _layout
,
1588 uint32_t descriptorWriteCount
,
1589 const VkWriteDescriptorSet
*pDescriptorWrites
);
1591 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1592 struct radv_image
*image
, uint32_t value
);
1593 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1594 struct radv_image
*image
, uint32_t value
);
1597 struct radeon_winsys_fence
*fence
;
1602 struct radeon_winsys_sem
;
1604 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1606 static inline struct __radv_type * \
1607 __radv_type ## _from_handle(__VkType _handle) \
1609 return (struct __radv_type *) _handle; \
1612 static inline __VkType \
1613 __radv_type ## _to_handle(struct __radv_type *_obj) \
1615 return (__VkType) _obj; \
1618 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1620 static inline struct __radv_type * \
1621 __radv_type ## _from_handle(__VkType _handle) \
1623 return (struct __radv_type *)(uintptr_t) _handle; \
1626 static inline __VkType \
1627 __radv_type ## _to_handle(struct __radv_type *_obj) \
1629 return (__VkType)(uintptr_t) _obj; \
1632 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1633 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1635 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1636 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1637 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1638 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1639 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1641 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1642 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1643 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1644 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1645 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1646 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1647 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1648 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1649 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1650 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1651 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1652 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1653 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1654 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1655 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1656 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1657 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1658 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1659 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1660 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1661 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1663 #endif /* RADV_PRIVATE_H */