2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
80 #include <vulkan/vk_android_native_buffer.h>
82 #include "radv_entrypoints.h"
84 #include "wsi_common.h"
85 #include "wsi_common_display.h"
87 /* Helper to determine if we should compile
88 * any of the Android AHB support.
90 * To actually enable the ext we also need
91 * the necessary kernel support.
93 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
94 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
96 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
100 struct gfx10_format
{
101 unsigned img_format
:9;
103 /* Various formats are only supported with workarounds for vertex fetch,
104 * and some 32_32_32 formats are supported natively, but only for buffers
105 * (possibly with some image support, actually, but no filtering). */
109 #include "gfx10_format_table.h"
113 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
120 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
121 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
122 RADV_MEM_TYPE_GTT_CACHED
,
126 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
128 static inline uint32_t
129 align_u32(uint32_t v
, uint32_t a
)
131 assert(a
!= 0 && a
== (a
& -a
));
132 return (v
+ a
- 1) & ~(a
- 1);
135 static inline uint32_t
136 align_u32_npot(uint32_t v
, uint32_t a
)
138 return (v
+ a
- 1) / a
* a
;
141 static inline uint64_t
142 align_u64(uint64_t v
, uint64_t a
)
144 assert(a
!= 0 && a
== (a
& -a
));
145 return (v
+ a
- 1) & ~(a
- 1);
148 static inline int32_t
149 align_i32(int32_t v
, int32_t a
)
151 assert(a
!= 0 && a
== (a
& -a
));
152 return (v
+ a
- 1) & ~(a
- 1);
155 /** Alignment must be a power of 2. */
157 radv_is_aligned(uintmax_t n
, uintmax_t a
)
159 assert(a
== (a
& -a
));
160 return (n
& (a
- 1)) == 0;
163 static inline uint32_t
164 round_up_u32(uint32_t v
, uint32_t a
)
166 return (v
+ a
- 1) / a
;
169 static inline uint64_t
170 round_up_u64(uint64_t v
, uint64_t a
)
172 return (v
+ a
- 1) / a
;
175 static inline uint32_t
176 radv_minify(uint32_t n
, uint32_t levels
)
178 if (unlikely(n
== 0))
181 return MAX2(n
>> levels
, 1);
184 radv_clamp_f(float f
, float min
, float max
)
197 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
199 if (*inout_mask
& clear_mask
) {
200 *inout_mask
&= ~clear_mask
;
207 #define for_each_bit(b, dword) \
208 for (uint32_t __dword = (dword); \
209 (b) = __builtin_ffs(__dword) - 1, __dword; \
210 __dword &= ~(1 << (b)))
212 #define typed_memcpy(dest, src, count) ({ \
213 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
214 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 /* Whenever we generate an error, pass it through this function. Useful for
218 * debugging, where we can break on it. Only call at error site, not when
219 * propagating errors. Might be useful to plug in a stack trace here.
222 struct radv_image_view
;
223 struct radv_instance
;
225 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
227 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
228 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
230 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
231 radv_printflike(3, 4);
232 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
233 void radv_loge_v(const char *format
, va_list va
);
234 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
235 void radv_logi_v(const char *format
, va_list va
);
238 * Print a FINISHME message, including its source location.
240 #define radv_finishme(format, ...) \
242 static bool reported = false; \
244 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 /* A non-fatal assert. Useful for debugging. */
251 #define radv_assert(x) ({ \
252 if (unlikely(!(x))) \
253 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
256 #define radv_assert(x)
259 #define stub_return(v) \
261 radv_finishme("stub %s", __func__); \
267 radv_finishme("stub %s", __func__); \
271 void *radv_lookup_entrypoint_unchecked(const char *name
);
272 void *radv_lookup_entrypoint_checked(const char *name
,
273 uint32_t core_version
,
274 const struct radv_instance_extension_table
*instance
,
275 const struct radv_device_extension_table
*device
);
276 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
277 uint32_t core_version
,
278 const struct radv_instance_extension_table
*instance
);
280 struct radv_physical_device
{
281 VK_LOADER_DATA _loader_data
;
283 struct radv_instance
* instance
;
285 struct radeon_winsys
*ws
;
286 struct radeon_info rad_info
;
287 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
288 uint8_t driver_uuid
[VK_UUID_SIZE
];
289 uint8_t device_uuid
[VK_UUID_SIZE
];
290 uint8_t cache_uuid
[VK_UUID_SIZE
];
294 struct wsi_device wsi_device
;
296 bool out_of_order_rast_allowed
;
298 /* Whether DCC should be enabled for MSAA textures. */
299 bool dcc_msaa_allowed
;
301 /* Whether to enable the AMD_shader_ballot extension */
302 bool use_shader_ballot
;
304 /* Whether to enable NGG. */
307 /* Whether to enable NGG streamout. */
308 bool use_ngg_streamout
;
310 /* Number of threads per wave. */
311 uint8_t ps_wave_size
;
312 uint8_t cs_wave_size
;
313 uint8_t ge_wave_size
;
315 /* Whether to use the experimental compiler backend */
318 /* This is the drivers on-disk cache used as a fallback as opposed to
319 * the pipeline cache defined by apps.
321 struct disk_cache
* disk_cache
;
323 VkPhysicalDeviceMemoryProperties memory_properties
;
324 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
326 drmPciBusInfo bus_info
;
328 struct radv_device_extension_table supported_extensions
;
331 struct radv_instance
{
332 VK_LOADER_DATA _loader_data
;
334 VkAllocationCallbacks alloc
;
337 int physicalDeviceCount
;
338 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
341 uint32_t engineVersion
;
343 uint64_t debug_flags
;
344 uint64_t perftest_flags
;
346 struct vk_debug_report_instance debug_report_callbacks
;
348 struct radv_instance_extension_table enabled_extensions
;
350 struct driOptionCache dri_options
;
351 struct driOptionCache available_dri_options
;
354 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
355 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
357 bool radv_instance_extension_supported(const char *name
);
358 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
359 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
364 struct radv_pipeline_cache
{
365 struct radv_device
* device
;
366 pthread_mutex_t mutex
;
370 uint32_t kernel_count
;
371 struct cache_entry
** hash_table
;
374 VkAllocationCallbacks alloc
;
377 struct radv_pipeline_key
{
378 uint32_t instance_rate_inputs
;
379 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
380 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
381 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
382 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
383 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
384 uint64_t vertex_alpha_adjust
;
385 uint32_t vertex_post_shuffle
;
386 unsigned tess_input_vertices
;
390 uint8_t log2_ps_iter_samples
;
392 uint32_t has_multiview_view_index
: 1;
393 uint32_t optimisations_disabled
: 1;
397 struct radv_shader_binary
;
398 struct radv_shader_variant
;
401 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
402 struct radv_device
*device
);
404 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
406 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
407 const void *data
, size_t size
);
410 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
411 struct radv_pipeline_cache
*cache
,
412 const unsigned char *sha1
,
413 struct radv_shader_variant
**variants
,
414 bool *found_in_application_cache
);
417 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
418 struct radv_pipeline_cache
*cache
,
419 const unsigned char *sha1
,
420 struct radv_shader_variant
**variants
,
421 struct radv_shader_binary
*const *binaries
);
423 enum radv_blit_ds_layout
{
424 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
425 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
426 RADV_BLIT_DS_LAYOUT_COUNT
,
429 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
431 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
434 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
436 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
439 enum radv_meta_dst_layout
{
440 RADV_META_DST_LAYOUT_GENERAL
,
441 RADV_META_DST_LAYOUT_OPTIMAL
,
442 RADV_META_DST_LAYOUT_COUNT
,
445 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
447 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
450 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
452 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
455 struct radv_meta_state
{
456 VkAllocationCallbacks alloc
;
458 struct radv_pipeline_cache cache
;
461 * For on-demand pipeline creation, makes sure that
462 * only one thread tries to build a pipeline at the same time.
467 * Use array element `i` for images with `2^i` samples.
470 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
471 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
473 VkRenderPass depthstencil_rp
;
474 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
475 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
476 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
477 } clear
[1 + MAX_SAMPLES_LOG2
];
479 VkPipelineLayout clear_color_p_layout
;
480 VkPipelineLayout clear_depth_p_layout
;
482 /* Optimized compute fast HTILE clear for stencil or depth only. */
483 VkPipeline clear_htile_mask_pipeline
;
484 VkPipelineLayout clear_htile_mask_p_layout
;
485 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
488 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
490 /** Pipeline that blits from a 1D image. */
491 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
493 /** Pipeline that blits from a 2D image. */
494 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
496 /** Pipeline that blits from a 3D image. */
497 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
499 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
500 VkPipeline depth_only_1d_pipeline
;
501 VkPipeline depth_only_2d_pipeline
;
502 VkPipeline depth_only_3d_pipeline
;
504 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
505 VkPipeline stencil_only_1d_pipeline
;
506 VkPipeline stencil_only_2d_pipeline
;
507 VkPipeline stencil_only_3d_pipeline
;
508 VkPipelineLayout pipeline_layout
;
509 VkDescriptorSetLayout ds_layout
;
513 VkPipelineLayout p_layouts
[5];
514 VkDescriptorSetLayout ds_layouts
[5];
515 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
517 VkPipeline depth_only_pipeline
[5];
519 VkPipeline stencil_only_pipeline
[5];
520 } blit2d
[1 + MAX_SAMPLES_LOG2
];
522 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
523 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
524 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
527 VkPipelineLayout img_p_layout
;
528 VkDescriptorSetLayout img_ds_layout
;
530 VkPipeline pipeline_3d
;
533 VkPipelineLayout img_p_layout
;
534 VkDescriptorSetLayout img_ds_layout
;
536 VkPipeline pipeline_3d
;
539 VkPipelineLayout img_p_layout
;
540 VkDescriptorSetLayout img_ds_layout
;
544 VkPipelineLayout img_p_layout
;
545 VkDescriptorSetLayout img_ds_layout
;
547 VkPipeline pipeline_3d
;
550 VkPipelineLayout img_p_layout
;
551 VkDescriptorSetLayout img_ds_layout
;
555 VkPipelineLayout img_p_layout
;
556 VkDescriptorSetLayout img_ds_layout
;
558 VkPipeline pipeline_3d
;
561 VkPipelineLayout img_p_layout
;
562 VkDescriptorSetLayout img_ds_layout
;
567 VkPipelineLayout p_layout
;
568 VkPipeline pipeline
[NUM_META_FS_KEYS
];
569 VkRenderPass pass
[NUM_META_FS_KEYS
];
573 VkDescriptorSetLayout ds_layout
;
574 VkPipelineLayout p_layout
;
577 VkPipeline i_pipeline
;
578 VkPipeline srgb_pipeline
;
579 } rc
[MAX_SAMPLES_LOG2
];
581 VkPipeline depth_zero_pipeline
;
583 VkPipeline average_pipeline
;
584 VkPipeline max_pipeline
;
585 VkPipeline min_pipeline
;
586 } depth
[MAX_SAMPLES_LOG2
];
588 VkPipeline stencil_zero_pipeline
;
590 VkPipeline max_pipeline
;
591 VkPipeline min_pipeline
;
592 } stencil
[MAX_SAMPLES_LOG2
];
596 VkDescriptorSetLayout ds_layout
;
597 VkPipelineLayout p_layout
;
600 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
601 VkPipeline pipeline
[NUM_META_FS_KEYS
];
602 } rc
[MAX_SAMPLES_LOG2
];
604 VkRenderPass depth_render_pass
;
605 VkPipeline depth_zero_pipeline
;
607 VkPipeline average_pipeline
;
608 VkPipeline max_pipeline
;
609 VkPipeline min_pipeline
;
610 } depth
[MAX_SAMPLES_LOG2
];
612 VkRenderPass stencil_render_pass
;
613 VkPipeline stencil_zero_pipeline
;
615 VkPipeline max_pipeline
;
616 VkPipeline min_pipeline
;
617 } stencil
[MAX_SAMPLES_LOG2
];
621 VkPipelineLayout p_layout
;
622 VkPipeline decompress_pipeline
;
623 VkPipeline resummarize_pipeline
;
625 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
628 VkPipelineLayout p_layout
;
629 VkPipeline cmask_eliminate_pipeline
;
630 VkPipeline fmask_decompress_pipeline
;
631 VkPipeline dcc_decompress_pipeline
;
634 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
635 VkPipelineLayout dcc_decompress_compute_p_layout
;
636 VkPipeline dcc_decompress_compute_pipeline
;
640 VkPipelineLayout fill_p_layout
;
641 VkPipelineLayout copy_p_layout
;
642 VkDescriptorSetLayout fill_ds_layout
;
643 VkDescriptorSetLayout copy_ds_layout
;
644 VkPipeline fill_pipeline
;
645 VkPipeline copy_pipeline
;
649 VkDescriptorSetLayout ds_layout
;
650 VkPipelineLayout p_layout
;
651 VkPipeline occlusion_query_pipeline
;
652 VkPipeline pipeline_statistics_query_pipeline
;
653 VkPipeline tfb_query_pipeline
;
654 VkPipeline timestamp_query_pipeline
;
658 VkDescriptorSetLayout ds_layout
;
659 VkPipelineLayout p_layout
;
660 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
665 #define RADV_QUEUE_GENERAL 0
666 #define RADV_QUEUE_COMPUTE 1
667 #define RADV_QUEUE_TRANSFER 2
669 #define RADV_MAX_QUEUE_FAMILIES 3
671 enum ring_type
radv_queue_family_to_ring(int f
);
674 VK_LOADER_DATA _loader_data
;
675 struct radv_device
* device
;
676 struct radeon_winsys_ctx
*hw_ctx
;
677 enum radeon_ctx_priority priority
;
678 uint32_t queue_family_index
;
680 VkDeviceQueueCreateFlags flags
;
682 uint32_t scratch_size
;
683 uint32_t compute_scratch_size
;
684 uint32_t esgs_ring_size
;
685 uint32_t gsvs_ring_size
;
688 bool has_sample_positions
;
690 struct radeon_winsys_bo
*scratch_bo
;
691 struct radeon_winsys_bo
*descriptor_bo
;
692 struct radeon_winsys_bo
*compute_scratch_bo
;
693 struct radeon_winsys_bo
*esgs_ring_bo
;
694 struct radeon_winsys_bo
*gsvs_ring_bo
;
695 struct radeon_winsys_bo
*tess_rings_bo
;
696 struct radeon_winsys_bo
*gds_bo
;
697 struct radeon_winsys_bo
*gds_oa_bo
;
698 struct radeon_cmdbuf
*initial_preamble_cs
;
699 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
700 struct radeon_cmdbuf
*continue_preamble_cs
;
703 struct radv_bo_list
{
704 struct radv_winsys_bo_list list
;
706 pthread_mutex_t mutex
;
710 VK_LOADER_DATA _loader_data
;
712 VkAllocationCallbacks alloc
;
714 struct radv_instance
* instance
;
715 struct radeon_winsys
*ws
;
717 struct radv_meta_state meta_state
;
719 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
720 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
721 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
723 bool always_use_syncobj
;
726 uint32_t tess_offchip_block_dw_size
;
727 uint32_t scratch_waves
;
728 uint32_t dispatch_initiator
;
730 uint32_t gs_table_depth
;
732 /* MSAA sample locations.
733 * The first index is the sample index.
734 * The second index is the coordinate: X, Y. */
735 float sample_locations_1x
[1][2];
736 float sample_locations_2x
[2][2];
737 float sample_locations_4x
[4][2];
738 float sample_locations_8x
[8][2];
741 uint32_t gfx_init_size_dw
;
742 struct radeon_winsys_bo
*gfx_init
;
744 struct radeon_winsys_bo
*trace_bo
;
745 uint32_t *trace_id_ptr
;
747 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
748 bool keep_shader_info
;
750 struct radv_physical_device
*physical_device
;
752 /* Backup in-memory cache to be used if the app doesn't provide one */
753 struct radv_pipeline_cache
* mem_cache
;
756 * use different counters so MSAA MRTs get consecutive surface indices,
757 * even if MASK is allocated in between.
759 uint32_t image_mrt_offset_counter
;
760 uint32_t fmask_mrt_offset_counter
;
761 struct list_head shader_slabs
;
762 mtx_t shader_slab_mutex
;
764 /* For detecting VM faults reported by dmesg. */
765 uint64_t dmesg_timestamp
;
767 struct radv_device_extension_table enabled_extensions
;
769 /* Whether the app has enabled the robustBufferAccess feature. */
770 bool robust_buffer_access
;
772 /* Whether the driver uses a global BO list. */
773 bool use_global_bo_list
;
775 struct radv_bo_list bo_list
;
777 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
781 struct radv_device_memory
{
782 struct radeon_winsys_bo
*bo
;
783 /* for dedicated allocations */
784 struct radv_image
*image
;
785 struct radv_buffer
*buffer
;
787 VkDeviceSize map_size
;
793 struct radv_descriptor_range
{
798 struct radv_descriptor_set
{
799 const struct radv_descriptor_set_layout
*layout
;
802 struct radeon_winsys_bo
*bo
;
804 uint32_t *mapped_ptr
;
805 struct radv_descriptor_range
*dynamic_descriptors
;
807 struct radeon_winsys_bo
*descriptors
[0];
810 struct radv_push_descriptor_set
812 struct radv_descriptor_set set
;
816 struct radv_descriptor_pool_entry
{
819 struct radv_descriptor_set
*set
;
822 struct radv_descriptor_pool
{
823 struct radeon_winsys_bo
*bo
;
825 uint64_t current_offset
;
828 uint8_t *host_memory_base
;
829 uint8_t *host_memory_ptr
;
830 uint8_t *host_memory_end
;
832 uint32_t entry_count
;
833 uint32_t max_entry_count
;
834 struct radv_descriptor_pool_entry entries
[0];
837 struct radv_descriptor_update_template_entry
{
838 VkDescriptorType descriptor_type
;
840 /* The number of descriptors to update */
841 uint32_t descriptor_count
;
843 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
846 /* In dwords. Not valid/used for dynamic descriptors */
849 uint32_t buffer_offset
;
851 /* Only valid for combined image samplers and samplers */
853 uint8_t sampler_offset
;
859 /* For push descriptors */
860 const uint32_t *immutable_samplers
;
863 struct radv_descriptor_update_template
{
864 uint32_t entry_count
;
865 VkPipelineBindPoint bind_point
;
866 struct radv_descriptor_update_template_entry entry
[0];
872 VkBufferUsageFlags usage
;
873 VkBufferCreateFlags flags
;
876 struct radeon_winsys_bo
* bo
;
882 enum radv_dynamic_state_bits
{
883 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
884 RADV_DYNAMIC_SCISSOR
= 1 << 1,
885 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
886 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
887 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
888 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
889 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
890 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
891 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
892 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
893 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
894 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
897 enum radv_cmd_dirty_bits
{
898 /* Keep the dynamic state dirty bits in sync with
899 * enum radv_dynamic_state_bits */
900 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
901 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
902 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
903 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
904 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
905 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
906 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
907 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
908 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
909 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
910 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
911 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
912 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
913 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
914 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
915 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
916 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
919 enum radv_cmd_flush_bits
{
920 /* Instruction cache. */
921 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
922 /* Scalar L1 cache. */
923 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
924 /* Vector L1 cache. */
925 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
926 /* L2 cache + L2 metadata cache writeback & invalidate.
927 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
928 RADV_CMD_FLAG_INV_L2
= 1 << 3,
929 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
930 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
931 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
932 RADV_CMD_FLAG_WB_L2
= 1 << 4,
933 /* Framebuffer caches */
934 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
935 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
936 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
937 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
938 /* Engine synchronization. */
939 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
940 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
941 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
942 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
943 /* Pipeline query controls. */
944 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
945 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
946 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
948 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
949 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
950 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
951 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
954 struct radv_vertex_binding
{
955 struct radv_buffer
* buffer
;
959 struct radv_streamout_binding
{
960 struct radv_buffer
*buffer
;
965 struct radv_streamout_state
{
966 /* Mask of bound streamout buffers. */
967 uint8_t enabled_mask
;
969 /* External state that comes from the last vertex stage, it must be
970 * set explicitely when binding a new graphics pipeline.
972 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
973 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
975 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
976 uint32_t hw_enabled_mask
;
978 /* State of VGT_STRMOUT_(CONFIG|EN) */
979 bool streamout_enabled
;
982 struct radv_viewport_state
{
984 VkViewport viewports
[MAX_VIEWPORTS
];
987 struct radv_scissor_state
{
989 VkRect2D scissors
[MAX_SCISSORS
];
992 struct radv_discard_rectangle_state
{
994 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
997 struct radv_sample_locations_state
{
998 VkSampleCountFlagBits per_pixel
;
999 VkExtent2D grid_size
;
1001 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1004 struct radv_dynamic_state
{
1006 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1007 * Defines the set of saved dynamic state.
1011 struct radv_viewport_state viewport
;
1013 struct radv_scissor_state scissor
;
1023 float blend_constants
[4];
1033 } stencil_compare_mask
;
1038 } stencil_write_mask
;
1043 } stencil_reference
;
1045 struct radv_discard_rectangle_state discard_rectangle
;
1047 struct radv_sample_locations_state sample_location
;
1050 extern const struct radv_dynamic_state default_dynamic_state
;
1053 radv_get_debug_option_name(int id
);
1056 radv_get_perftest_option_name(int id
);
1058 struct radv_color_buffer_info
{
1059 uint64_t cb_color_base
;
1060 uint64_t cb_color_cmask
;
1061 uint64_t cb_color_fmask
;
1062 uint64_t cb_dcc_base
;
1063 uint32_t cb_color_slice
;
1064 uint32_t cb_color_view
;
1065 uint32_t cb_color_info
;
1066 uint32_t cb_color_attrib
;
1067 uint32_t cb_color_attrib2
; /* GFX9 and later */
1068 uint32_t cb_color_attrib3
; /* GFX10 and later */
1069 uint32_t cb_dcc_control
;
1070 uint32_t cb_color_cmask_slice
;
1071 uint32_t cb_color_fmask_slice
;
1073 uint32_t cb_color_pitch
; // GFX6-GFX8
1074 uint32_t cb_mrt_epitch
; // GFX9+
1078 struct radv_ds_buffer_info
{
1079 uint64_t db_z_read_base
;
1080 uint64_t db_stencil_read_base
;
1081 uint64_t db_z_write_base
;
1082 uint64_t db_stencil_write_base
;
1083 uint64_t db_htile_data_base
;
1084 uint32_t db_depth_info
;
1086 uint32_t db_stencil_info
;
1087 uint32_t db_depth_view
;
1088 uint32_t db_depth_size
;
1089 uint32_t db_depth_slice
;
1090 uint32_t db_htile_surface
;
1091 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1092 uint32_t db_z_info2
; /* GFX9 only */
1093 uint32_t db_stencil_info2
; /* GFX9 only */
1098 radv_initialise_color_surface(struct radv_device
*device
,
1099 struct radv_color_buffer_info
*cb
,
1100 struct radv_image_view
*iview
);
1102 radv_initialise_ds_surface(struct radv_device
*device
,
1103 struct radv_ds_buffer_info
*ds
,
1104 struct radv_image_view
*iview
);
1107 * Attachment state when recording a renderpass instance.
1109 * The clear value is valid only if there exists a pending clear.
1111 struct radv_attachment_state
{
1112 VkImageAspectFlags pending_clear_aspects
;
1113 uint32_t cleared_views
;
1114 VkClearValue clear_value
;
1115 VkImageLayout current_layout
;
1116 bool current_in_render_loop
;
1117 struct radv_sample_locations_state sample_location
;
1120 struct radv_color_buffer_info cb
;
1121 struct radv_ds_buffer_info ds
;
1123 struct radv_image_view
*iview
;
1126 struct radv_descriptor_state
{
1127 struct radv_descriptor_set
*sets
[MAX_SETS
];
1130 struct radv_push_descriptor_set push_set
;
1132 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1135 struct radv_subpass_sample_locs_state
{
1136 uint32_t subpass_idx
;
1137 struct radv_sample_locations_state sample_location
;
1140 struct radv_cmd_state
{
1141 /* Vertex descriptors */
1148 uint32_t prefetch_L2_mask
;
1150 struct radv_pipeline
* pipeline
;
1151 struct radv_pipeline
* emitted_pipeline
;
1152 struct radv_pipeline
* compute_pipeline
;
1153 struct radv_pipeline
* emitted_compute_pipeline
;
1154 struct radv_framebuffer
* framebuffer
;
1155 struct radv_render_pass
* pass
;
1156 const struct radv_subpass
* subpass
;
1157 struct radv_dynamic_state dynamic
;
1158 struct radv_attachment_state
* attachments
;
1159 struct radv_streamout_state streamout
;
1160 VkRect2D render_area
;
1162 uint32_t num_subpass_sample_locs
;
1163 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1166 struct radv_buffer
*index_buffer
;
1167 uint64_t index_offset
;
1168 uint32_t index_type
;
1169 uint32_t max_index_count
;
1171 int32_t last_index_type
;
1173 int32_t last_primitive_reset_en
;
1174 uint32_t last_primitive_reset_index
;
1175 enum radv_cmd_flush_bits flush_bits
;
1176 unsigned active_occlusion_queries
;
1177 bool perfect_occlusion_queries_enabled
;
1178 unsigned active_pipeline_queries
;
1181 uint32_t last_ia_multi_vgt_param
;
1183 uint32_t last_num_instances
;
1184 uint32_t last_first_instance
;
1185 uint32_t last_vertex_offset
;
1187 /* Whether CP DMA is busy/idle. */
1190 /* Conditional rendering info. */
1191 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1192 uint64_t predication_va
;
1194 bool context_roll_without_scissor_emitted
;
1197 struct radv_cmd_pool
{
1198 VkAllocationCallbacks alloc
;
1199 struct list_head cmd_buffers
;
1200 struct list_head free_cmd_buffers
;
1201 uint32_t queue_family_index
;
1204 struct radv_cmd_buffer_upload
{
1208 struct radeon_winsys_bo
*upload_bo
;
1209 struct list_head list
;
1212 enum radv_cmd_buffer_status
{
1213 RADV_CMD_BUFFER_STATUS_INVALID
,
1214 RADV_CMD_BUFFER_STATUS_INITIAL
,
1215 RADV_CMD_BUFFER_STATUS_RECORDING
,
1216 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1217 RADV_CMD_BUFFER_STATUS_PENDING
,
1220 struct radv_cmd_buffer
{
1221 VK_LOADER_DATA _loader_data
;
1223 struct radv_device
* device
;
1225 struct radv_cmd_pool
* pool
;
1226 struct list_head pool_link
;
1228 VkCommandBufferUsageFlags usage_flags
;
1229 VkCommandBufferLevel level
;
1230 enum radv_cmd_buffer_status status
;
1231 struct radeon_cmdbuf
*cs
;
1232 struct radv_cmd_state state
;
1233 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1234 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1235 uint32_t queue_family_index
;
1237 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1238 VkShaderStageFlags push_constant_stages
;
1239 struct radv_descriptor_set meta_push_descriptors
;
1241 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1243 struct radv_cmd_buffer_upload upload
;
1245 uint32_t scratch_size_needed
;
1246 uint32_t compute_scratch_size_needed
;
1247 uint32_t esgs_ring_size_needed
;
1248 uint32_t gsvs_ring_size_needed
;
1249 bool tess_rings_needed
;
1250 bool gds_needed
; /* for GFX10 streamout */
1251 bool sample_positions_needed
;
1253 VkResult record_result
;
1255 uint64_t gfx9_fence_va
;
1256 uint32_t gfx9_fence_idx
;
1257 uint64_t gfx9_eop_bug_va
;
1260 * Whether a query pool has been resetted and we have to flush caches.
1262 bool pending_reset_query
;
1265 * Bitmask of pending active query flushes.
1267 enum radv_cmd_flush_bits active_query_flush_bits
;
1271 struct radv_image_view
;
1273 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1275 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1276 struct radeon_cmdbuf
*cs
);
1277 void si_emit_compute(struct radv_physical_device
*physical_device
,
1278 struct radeon_cmdbuf
*cs
);
1280 void cik_create_gfx_config(struct radv_device
*device
);
1282 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1283 int count
, const VkViewport
*viewports
);
1284 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1285 int count
, const VkRect2D
*scissors
,
1286 const VkViewport
*viewports
, bool can_use_guardband
);
1287 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1288 bool instanced_draw
, bool indirect_draw
,
1289 bool count_from_stream_output
,
1290 uint32_t draw_vertex_count
);
1291 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1292 enum chip_class chip_class
,
1294 unsigned event
, unsigned event_flags
,
1295 unsigned dst_sel
, unsigned data_sel
,
1298 uint64_t gfx9_eop_bug_va
);
1300 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1301 uint32_t ref
, uint32_t mask
);
1302 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1303 enum chip_class chip_class
,
1304 uint32_t *fence_ptr
, uint64_t va
,
1306 enum radv_cmd_flush_bits flush_bits
,
1307 uint64_t gfx9_eop_bug_va
);
1308 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1309 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1310 bool inverted
, uint64_t va
);
1311 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1312 uint64_t src_va
, uint64_t dest_va
,
1314 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1316 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1317 uint64_t size
, unsigned value
);
1318 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1320 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1322 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1325 unsigned *out_offset
,
1328 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1329 const struct radv_subpass
*subpass
);
1331 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1332 unsigned size
, unsigned alignmnet
,
1333 const void *data
, unsigned *out_offset
);
1335 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1336 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1337 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1338 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1339 VkImageAspectFlags aspects
,
1340 VkResolveModeFlagBitsKHR resolve_mode
);
1341 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1342 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1343 VkImageAspectFlags aspects
,
1344 VkResolveModeFlagBitsKHR resolve_mode
);
1345 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1346 unsigned radv_get_default_max_sample_dist(int log_samples
);
1347 void radv_device_init_msaa(struct radv_device
*device
);
1349 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1350 const struct radv_image_view
*iview
,
1351 VkClearDepthStencilValue ds_clear_value
,
1352 VkImageAspectFlags aspects
);
1354 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1355 const struct radv_image_view
*iview
,
1357 uint32_t color_values
[2]);
1359 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1360 struct radv_image
*image
,
1361 const VkImageSubresourceRange
*range
, bool value
);
1363 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1364 struct radv_image
*image
,
1365 const VkImageSubresourceRange
*range
, bool value
);
1367 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1368 struct radeon_winsys_bo
*bo
,
1369 uint64_t offset
, uint64_t size
, uint32_t value
);
1370 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1371 bool radv_get_memory_fd(struct radv_device
*device
,
1372 struct radv_device_memory
*memory
,
1376 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1377 unsigned sh_offset
, unsigned pointer_count
,
1378 bool use_32bit_pointers
)
1380 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1381 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1385 radv_emit_shader_pointer_body(struct radv_device
*device
,
1386 struct radeon_cmdbuf
*cs
,
1387 uint64_t va
, bool use_32bit_pointers
)
1389 radeon_emit(cs
, va
);
1391 if (use_32bit_pointers
) {
1393 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1395 radeon_emit(cs
, va
>> 32);
1400 radv_emit_shader_pointer(struct radv_device
*device
,
1401 struct radeon_cmdbuf
*cs
,
1402 uint32_t sh_offset
, uint64_t va
, bool global
)
1404 bool use_32bit_pointers
= !global
;
1406 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1407 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1410 static inline struct radv_descriptor_state
*
1411 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1412 VkPipelineBindPoint bind_point
)
1414 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1415 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1416 return &cmd_buffer
->descriptors
[bind_point
];
1420 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1422 * Limitations: Can't call normal dispatch functions without binding or rebinding
1423 * the compute pipeline.
1425 void radv_unaligned_dispatch(
1426 struct radv_cmd_buffer
*cmd_buffer
,
1432 struct radeon_winsys_bo
*bo
;
1436 struct radv_shader_module
;
1438 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1439 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1440 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1441 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1442 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
1443 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
1444 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
1445 #define RADV_HASH_SHADER_ACO (1 << 7)
1448 radv_hash_shaders(unsigned char *hash
,
1449 const VkPipelineShaderStageCreateInfo
**stages
,
1450 const struct radv_pipeline_layout
*layout
,
1451 const struct radv_pipeline_key
*key
,
1454 static inline gl_shader_stage
1455 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1457 assert(__builtin_popcount(vk_stage
) == 1);
1458 return ffs(vk_stage
) - 1;
1461 static inline VkShaderStageFlagBits
1462 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1464 return (1 << mesa_stage
);
1467 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1469 #define radv_foreach_stage(stage, stage_bits) \
1470 for (gl_shader_stage stage, \
1471 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1472 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1473 __tmp &= ~(1 << (stage)))
1475 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1476 unsigned radv_format_meta_fs_key(VkFormat format
);
1478 struct radv_multisample_state
{
1480 uint32_t pa_sc_line_cntl
;
1481 uint32_t pa_sc_mode_cntl_0
;
1482 uint32_t pa_sc_mode_cntl_1
;
1483 uint32_t pa_sc_aa_config
;
1484 uint32_t pa_sc_aa_mask
[2];
1485 unsigned num_samples
;
1488 struct radv_prim_vertex_count
{
1493 struct radv_vertex_elements_info
{
1494 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1497 struct radv_ia_multi_vgt_param_helpers
{
1499 bool partial_es_wave
;
1500 uint8_t primgroup_size
;
1501 bool wd_switch_on_eop
;
1502 bool ia_switch_on_eoi
;
1503 bool partial_vs_wave
;
1506 struct radv_binning_state
{
1507 uint32_t pa_sc_binner_cntl_0
;
1508 uint32_t db_dfsm_control
;
1511 #define SI_GS_PER_ES 128
1513 struct radv_pipeline
{
1514 struct radv_device
* device
;
1515 struct radv_dynamic_state dynamic_state
;
1517 struct radv_pipeline_layout
* layout
;
1519 bool need_indirect_descriptor_sets
;
1520 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1521 struct radv_shader_variant
*gs_copy_shader
;
1522 VkShaderStageFlags active_stages
;
1524 struct radeon_cmdbuf cs
;
1525 uint32_t ctx_cs_hash
;
1526 struct radeon_cmdbuf ctx_cs
;
1528 struct radv_vertex_elements_info vertex_elements
;
1530 uint32_t binding_stride
[MAX_VBS
];
1531 uint8_t num_vertex_bindings
;
1533 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1536 struct radv_multisample_state ms
;
1537 struct radv_binning_state binning
;
1538 uint32_t spi_baryc_cntl
;
1539 bool prim_restart_enable
;
1540 unsigned esgs_ring_size
;
1541 unsigned gsvs_ring_size
;
1542 uint32_t vtx_base_sgpr
;
1543 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1544 uint8_t vtx_emit_num
;
1545 struct radv_prim_vertex_count prim_vertex_count
;
1546 bool can_use_guardband
;
1547 uint32_t needed_dynamic_state
;
1548 bool disable_out_of_order_rast_for_occlusion
;
1550 /* Used for rbplus */
1551 uint32_t col_format
;
1552 uint32_t cb_target_mask
;
1557 unsigned scratch_bytes_per_wave
;
1559 /* Not NULL if graphics pipeline uses streamout. */
1560 struct radv_shader_variant
*streamout_shader
;
1563 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1565 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1568 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1570 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1573 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1575 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1577 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1578 gl_shader_stage stage
,
1581 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1582 gl_shader_stage stage
);
1584 struct radv_graphics_pipeline_create_info
{
1586 bool db_depth_clear
;
1587 bool db_stencil_clear
;
1588 bool db_depth_disable_expclear
;
1589 bool db_stencil_disable_expclear
;
1590 bool db_flush_depth_inplace
;
1591 bool db_flush_stencil_inplace
;
1592 bool db_resummarize
;
1593 uint32_t custom_blend_mode
;
1597 radv_graphics_pipeline_create(VkDevice device
,
1598 VkPipelineCache cache
,
1599 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1600 const struct radv_graphics_pipeline_create_info
*extra
,
1601 const VkAllocationCallbacks
*alloc
,
1602 VkPipeline
*pPipeline
);
1604 struct vk_format_description
;
1605 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1606 int first_non_void
);
1607 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1608 int first_non_void
);
1609 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1610 uint32_t radv_translate_colorformat(VkFormat format
);
1611 uint32_t radv_translate_color_numformat(VkFormat format
,
1612 const struct vk_format_description
*desc
,
1613 int first_non_void
);
1614 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1615 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1616 uint32_t radv_translate_dbformat(VkFormat format
);
1617 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1618 const struct vk_format_description
*desc
,
1619 int first_non_void
);
1620 uint32_t radv_translate_tex_numformat(VkFormat format
,
1621 const struct vk_format_description
*desc
,
1622 int first_non_void
);
1623 bool radv_format_pack_clear_color(VkFormat format
,
1624 uint32_t clear_vals
[2],
1625 VkClearColorValue
*value
);
1626 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1627 bool radv_dcc_formats_compatible(VkFormat format1
,
1629 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1631 struct radv_image_plane
{
1633 struct radeon_surf surface
;
1639 /* The original VkFormat provided by the client. This may not match any
1640 * of the actual surface formats.
1643 VkImageAspectFlags aspects
;
1644 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1645 struct ac_surf_info info
;
1646 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1647 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1652 unsigned queue_family_mask
;
1656 /* Set when bound */
1657 struct radeon_winsys_bo
*bo
;
1658 VkDeviceSize offset
;
1659 uint64_t dcc_offset
;
1660 uint64_t htile_offset
;
1661 bool tc_compatible_htile
;
1662 bool tc_compatible_cmask
;
1664 uint64_t cmask_offset
;
1665 uint64_t fmask_offset
;
1666 uint64_t clear_value_offset
;
1667 uint64_t fce_pred_offset
;
1668 uint64_t dcc_pred_offset
;
1671 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1672 * stored at this offset is UINT_MAX, the driver will emit
1673 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1674 * SET_CONTEXT_REG packet.
1676 uint64_t tc_compat_zrange_offset
;
1678 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1679 VkDeviceMemory owned_memory
;
1681 unsigned plane_count
;
1682 struct radv_image_plane planes
[0];
1685 /* Whether the image has a htile that is known consistent with the contents of
1687 bool radv_layout_has_htile(const struct radv_image
*image
,
1688 VkImageLayout layout
,
1689 bool in_render_loop
,
1690 unsigned queue_mask
);
1692 /* Whether the image has a htile that is known consistent with the contents of
1693 * the image and is allowed to be in compressed form.
1695 * If this is false reads that don't use the htile should be able to return
1698 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1699 VkImageLayout layout
,
1700 bool in_render_loop
,
1701 unsigned queue_mask
);
1703 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1704 VkImageLayout layout
,
1705 bool in_render_loop
,
1706 unsigned queue_mask
);
1708 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1709 const struct radv_image
*image
,
1710 VkImageLayout layout
,
1711 bool in_render_loop
,
1712 unsigned queue_mask
);
1715 * Return whether the image has CMASK metadata for color surfaces.
1718 radv_image_has_cmask(const struct radv_image
*image
)
1720 return image
->cmask_offset
;
1724 * Return whether the image has FMASK metadata for color surfaces.
1727 radv_image_has_fmask(const struct radv_image
*image
)
1729 return image
->fmask_offset
;
1733 * Return whether the image has DCC metadata for color surfaces.
1736 radv_image_has_dcc(const struct radv_image
*image
)
1738 return image
->planes
[0].surface
.dcc_size
;
1742 * Return whether the image is TC-compatible CMASK.
1745 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1747 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1751 * Return whether DCC metadata is enabled for a level.
1754 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1756 return radv_image_has_dcc(image
) &&
1757 level
< image
->planes
[0].surface
.num_dcc_levels
;
1761 * Return whether the image has CB metadata.
1764 radv_image_has_CB_metadata(const struct radv_image
*image
)
1766 return radv_image_has_cmask(image
) ||
1767 radv_image_has_fmask(image
) ||
1768 radv_image_has_dcc(image
);
1772 * Return whether the image has HTILE metadata for depth surfaces.
1775 radv_image_has_htile(const struct radv_image
*image
)
1777 return image
->planes
[0].surface
.htile_size
;
1781 * Return whether HTILE metadata is enabled for a level.
1784 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1786 return radv_image_has_htile(image
) && level
== 0;
1790 * Return whether the image is TC-compatible HTILE.
1793 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1795 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1798 static inline uint64_t
1799 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1800 uint32_t base_level
)
1802 uint64_t va
= radv_buffer_get_va(image
->bo
);
1803 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1807 static inline uint64_t
1808 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1809 uint32_t base_level
)
1811 uint64_t va
= radv_buffer_get_va(image
->bo
);
1812 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1816 static inline uint64_t
1817 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1818 uint32_t base_level
)
1820 uint64_t va
= radv_buffer_get_va(image
->bo
);
1821 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1825 static inline uint64_t
1826 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1827 uint32_t base_level
)
1829 uint64_t va
= radv_buffer_get_va(image
->bo
);
1830 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1834 static inline uint64_t
1835 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1836 uint32_t base_level
)
1838 uint64_t va
= radv_buffer_get_va(image
->bo
);
1839 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1843 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1845 static inline uint32_t
1846 radv_get_layerCount(const struct radv_image
*image
,
1847 const VkImageSubresourceRange
*range
)
1849 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1850 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1853 static inline uint32_t
1854 radv_get_levelCount(const struct radv_image
*image
,
1855 const VkImageSubresourceRange
*range
)
1857 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1858 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1861 struct radeon_bo_metadata
;
1863 radv_init_metadata(struct radv_device
*device
,
1864 struct radv_image
*image
,
1865 struct radeon_bo_metadata
*metadata
);
1868 radv_image_override_offset_stride(struct radv_device
*device
,
1869 struct radv_image
*image
,
1870 uint64_t offset
, uint32_t stride
);
1872 union radv_descriptor
{
1874 uint32_t plane0_descriptor
[8];
1875 uint32_t fmask_descriptor
[8];
1878 uint32_t plane_descriptors
[3][8];
1882 struct radv_image_view
{
1883 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1884 struct radeon_winsys_bo
*bo
;
1886 VkImageViewType type
;
1887 VkImageAspectFlags aspect_mask
;
1890 bool multiple_planes
;
1891 uint32_t base_layer
;
1892 uint32_t layer_count
;
1894 uint32_t level_count
;
1895 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1897 union radv_descriptor descriptor
;
1899 /* Descriptor for use as a storage image as opposed to a sampled image.
1900 * This has a few differences for cube maps (e.g. type).
1902 union radv_descriptor storage_descriptor
;
1905 struct radv_image_create_info
{
1906 const VkImageCreateInfo
*vk_info
;
1908 bool no_metadata_planes
;
1909 const struct radeon_bo_metadata
*bo_metadata
;
1912 VkResult
radv_image_create(VkDevice _device
,
1913 const struct radv_image_create_info
*info
,
1914 const VkAllocationCallbacks
* alloc
,
1918 radv_image_from_gralloc(VkDevice device_h
,
1919 const VkImageCreateInfo
*base_info
,
1920 const VkNativeBufferANDROID
*gralloc_info
,
1921 const VkAllocationCallbacks
*alloc
,
1922 VkImage
*out_image_h
);
1924 struct radv_image_view_extra_create_info
{
1925 bool disable_compression
;
1928 void radv_image_view_init(struct radv_image_view
*view
,
1929 struct radv_device
*device
,
1930 const VkImageViewCreateInfo
*pCreateInfo
,
1931 const struct radv_image_view_extra_create_info
* extra_create_info
);
1933 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
1935 struct radv_sampler_ycbcr_conversion
{
1937 VkSamplerYcbcrModelConversion ycbcr_model
;
1938 VkSamplerYcbcrRange ycbcr_range
;
1939 VkComponentMapping components
;
1940 VkChromaLocation chroma_offsets
[2];
1941 VkFilter chroma_filter
;
1944 struct radv_buffer_view
{
1945 struct radeon_winsys_bo
*bo
;
1947 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1950 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1951 struct radv_device
*device
,
1952 const VkBufferViewCreateInfo
* pCreateInfo
);
1954 static inline struct VkExtent3D
1955 radv_sanitize_image_extent(const VkImageType imageType
,
1956 const struct VkExtent3D imageExtent
)
1958 switch (imageType
) {
1959 case VK_IMAGE_TYPE_1D
:
1960 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1961 case VK_IMAGE_TYPE_2D
:
1962 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1963 case VK_IMAGE_TYPE_3D
:
1966 unreachable("invalid image type");
1970 static inline struct VkOffset3D
1971 radv_sanitize_image_offset(const VkImageType imageType
,
1972 const struct VkOffset3D imageOffset
)
1974 switch (imageType
) {
1975 case VK_IMAGE_TYPE_1D
:
1976 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1977 case VK_IMAGE_TYPE_2D
:
1978 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1979 case VK_IMAGE_TYPE_3D
:
1982 unreachable("invalid image type");
1987 radv_image_extent_compare(const struct radv_image
*image
,
1988 const VkExtent3D
*extent
)
1990 if (extent
->width
!= image
->info
.width
||
1991 extent
->height
!= image
->info
.height
||
1992 extent
->depth
!= image
->info
.depth
)
1997 struct radv_sampler
{
1999 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2002 struct radv_framebuffer
{
2007 uint32_t attachment_count
;
2008 struct radv_image_view
*attachments
[0];
2011 struct radv_subpass_barrier
{
2012 VkPipelineStageFlags src_stage_mask
;
2013 VkAccessFlags src_access_mask
;
2014 VkAccessFlags dst_access_mask
;
2017 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2018 const struct radv_subpass_barrier
*barrier
);
2020 struct radv_subpass_attachment
{
2021 uint32_t attachment
;
2022 VkImageLayout layout
;
2023 bool in_render_loop
;
2026 struct radv_subpass
{
2027 uint32_t attachment_count
;
2028 struct radv_subpass_attachment
* attachments
;
2030 uint32_t input_count
;
2031 uint32_t color_count
;
2032 struct radv_subpass_attachment
* input_attachments
;
2033 struct radv_subpass_attachment
* color_attachments
;
2034 struct radv_subpass_attachment
* resolve_attachments
;
2035 struct radv_subpass_attachment
* depth_stencil_attachment
;
2036 struct radv_subpass_attachment
* ds_resolve_attachment
;
2037 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2038 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2040 /** Subpass has at least one color resolve attachment */
2041 bool has_color_resolve
;
2043 /** Subpass has at least one color attachment */
2046 struct radv_subpass_barrier start_barrier
;
2049 VkSampleCountFlagBits max_sample_count
;
2053 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2055 struct radv_render_pass_attachment
{
2058 VkAttachmentLoadOp load_op
;
2059 VkAttachmentLoadOp stencil_load_op
;
2060 VkImageLayout initial_layout
;
2061 VkImageLayout final_layout
;
2063 /* The subpass id in which the attachment will be used first/last. */
2064 uint32_t first_subpass_idx
;
2065 uint32_t last_subpass_idx
;
2068 struct radv_render_pass
{
2069 uint32_t attachment_count
;
2070 uint32_t subpass_count
;
2071 struct radv_subpass_attachment
* subpass_attachments
;
2072 struct radv_render_pass_attachment
* attachments
;
2073 struct radv_subpass_barrier end_barrier
;
2074 struct radv_subpass subpasses
[0];
2077 VkResult
radv_device_init_meta(struct radv_device
*device
);
2078 void radv_device_finish_meta(struct radv_device
*device
);
2080 struct radv_query_pool
{
2081 struct radeon_winsys_bo
*bo
;
2083 uint32_t availability_offset
;
2087 uint32_t pipeline_stats_mask
;
2090 struct radv_semaphore
{
2091 /* use a winsys sem for non-exportable */
2092 struct radeon_winsys_sem
*sem
;
2094 uint32_t temp_syncobj
;
2097 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2098 VkPipelineBindPoint bind_point
,
2099 struct radv_descriptor_set
*set
,
2103 radv_update_descriptor_sets(struct radv_device
*device
,
2104 struct radv_cmd_buffer
*cmd_buffer
,
2105 VkDescriptorSet overrideSet
,
2106 uint32_t descriptorWriteCount
,
2107 const VkWriteDescriptorSet
*pDescriptorWrites
,
2108 uint32_t descriptorCopyCount
,
2109 const VkCopyDescriptorSet
*pDescriptorCopies
);
2112 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2113 struct radv_cmd_buffer
*cmd_buffer
,
2114 struct radv_descriptor_set
*set
,
2115 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2118 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2119 VkPipelineBindPoint pipelineBindPoint
,
2120 VkPipelineLayout _layout
,
2122 uint32_t descriptorWriteCount
,
2123 const VkWriteDescriptorSet
*pDescriptorWrites
);
2125 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2126 struct radv_image
*image
,
2127 const VkImageSubresourceRange
*range
, uint32_t value
);
2129 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2130 struct radv_image
*image
,
2131 const VkImageSubresourceRange
*range
);
2134 struct radeon_winsys_fence
*fence
;
2135 struct wsi_fence
*fence_wsi
;
2138 uint32_t temp_syncobj
;
2141 /* radv_nir_to_llvm.c */
2142 struct radv_shader_info
;
2143 struct radv_nir_compiler_options
;
2145 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2146 struct nir_shader
*geom_shader
,
2147 struct radv_shader_binary
**rbinary
,
2148 struct radv_shader_info
*info
,
2149 const struct radv_nir_compiler_options
*option
);
2151 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2152 struct radv_shader_binary
**rbinary
,
2153 struct radv_shader_info
*info
,
2154 struct nir_shader
*const *nir
,
2156 const struct radv_nir_compiler_options
*options
);
2158 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2159 gl_shader_stage stage
,
2160 const struct nir_shader
*nir
);
2162 /* radv_shader_info.h */
2163 struct radv_shader_info
;
2164 struct radv_shader_variant_key
;
2166 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2167 const struct radv_pipeline_layout
*layout
,
2168 const struct radv_shader_variant_key
*key
,
2169 struct radv_shader_info
*info
);
2171 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2173 struct radeon_winsys_sem
;
2175 uint64_t radv_get_current_time(void);
2177 static inline uint32_t
2178 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2181 case 0: /* GL_POINTS */
2183 case 1: /* GL_LINES */
2184 case 3: /* GL_LINE_STRIP */
2186 case 4: /* GL_TRIANGLES */
2187 case 5: /* GL_TRIANGLE_STRIP */
2189 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2191 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2193 case 7: /* GL_QUADS */
2194 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2201 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2203 static inline struct __radv_type * \
2204 __radv_type ## _from_handle(__VkType _handle) \
2206 return (struct __radv_type *) _handle; \
2209 static inline __VkType \
2210 __radv_type ## _to_handle(struct __radv_type *_obj) \
2212 return (__VkType) _obj; \
2215 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2217 static inline struct __radv_type * \
2218 __radv_type ## _from_handle(__VkType _handle) \
2220 return (struct __radv_type *)(uintptr_t) _handle; \
2223 static inline __VkType \
2224 __radv_type ## _to_handle(struct __radv_type *_obj) \
2226 return (__VkType)(uintptr_t) _obj; \
2229 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2230 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2232 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2233 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2234 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2235 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2236 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2238 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2239 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2240 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2241 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2242 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2243 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2244 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2245 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2246 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2247 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2248 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2249 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2250 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2251 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2252 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2253 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2254 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2255 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2256 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2257 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2258 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2259 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2261 #endif /* RADV_PRIVATE_H */