2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_debug.h"
57 #include "radv_descriptor_set.h"
59 #include <llvm-c/TargetMachine.h>
61 /* Pre-declarations needed for WSI entrypoints */
64 typedef struct xcb_connection_t xcb_connection_t
;
65 typedef uint32_t xcb_visualid_t
;
66 typedef uint32_t xcb_window_t
;
68 #include <vulkan/vulkan.h>
69 #include <vulkan/vulkan_intel.h>
70 #include <vulkan/vk_icd.h>
72 #include "radv_entrypoints.h"
74 #include "wsi_common.h"
77 #define MAX_VERTEX_ATTRIBS 32
79 #define MAX_VIEWPORTS 16
80 #define MAX_SCISSORS 16
81 #define MAX_PUSH_CONSTANTS_SIZE 128
82 #define MAX_DYNAMIC_BUFFERS 16
83 #define MAX_SAMPLES_LOG2 4
84 #define NUM_META_FS_KEYS 11
85 #define RADV_MAX_DRM_DEVICES 8
87 #define NUM_DEPTH_CLEAR_PIPELINES 3
91 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
98 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
99 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
100 RADV_MEM_TYPE_GTT_CACHED
,
104 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
106 static inline uint32_t
107 align_u32(uint32_t v
, uint32_t a
)
109 assert(a
!= 0 && a
== (a
& -a
));
110 return (v
+ a
- 1) & ~(a
- 1);
113 static inline uint32_t
114 align_u32_npot(uint32_t v
, uint32_t a
)
116 return (v
+ a
- 1) / a
* a
;
119 static inline uint64_t
120 align_u64(uint64_t v
, uint64_t a
)
122 assert(a
!= 0 && a
== (a
& -a
));
123 return (v
+ a
- 1) & ~(a
- 1);
126 static inline int32_t
127 align_i32(int32_t v
, int32_t a
)
129 assert(a
!= 0 && a
== (a
& -a
));
130 return (v
+ a
- 1) & ~(a
- 1);
133 /** Alignment must be a power of 2. */
135 radv_is_aligned(uintmax_t n
, uintmax_t a
)
137 assert(a
== (a
& -a
));
138 return (n
& (a
- 1)) == 0;
141 static inline uint32_t
142 round_up_u32(uint32_t v
, uint32_t a
)
144 return (v
+ a
- 1) / a
;
147 static inline uint64_t
148 round_up_u64(uint64_t v
, uint64_t a
)
150 return (v
+ a
- 1) / a
;
153 static inline uint32_t
154 radv_minify(uint32_t n
, uint32_t levels
)
156 if (unlikely(n
== 0))
159 return MAX2(n
>> levels
, 1);
162 radv_clamp_f(float f
, float min
, float max
)
175 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
177 if (*inout_mask
& clear_mask
) {
178 *inout_mask
&= ~clear_mask
;
185 #define for_each_bit(b, dword) \
186 for (uint32_t __dword = (dword); \
187 (b) = __builtin_ffs(__dword) - 1, __dword; \
188 __dword &= ~(1 << (b)))
190 #define typed_memcpy(dest, src, count) ({ \
191 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
192 memcpy((dest), (src), (count) * sizeof(*(src))); \
195 #define zero(x) (memset(&(x), 0, sizeof(x)))
197 /* Whenever we generate an error, pass it through this function. Useful for
198 * debugging, where we can break on it. Only call at error site, not when
199 * propagating errors. Might be useful to plug in a stack trace here.
202 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
205 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
206 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
212 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
213 radv_printflike(3, 4);
214 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
215 void radv_loge_v(const char *format
, va_list va
);
218 * Print a FINISHME message, including its source location.
220 #define radv_finishme(format, ...) \
222 static bool reported = false; \
224 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
229 /* A non-fatal assert. Useful for debugging. */
231 #define radv_assert(x) ({ \
232 if (unlikely(!(x))) \
233 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
236 #define radv_assert(x)
239 #define stub_return(v) \
241 radv_finishme("stub %s", __func__); \
247 radv_finishme("stub %s", __func__); \
251 void *radv_lookup_entrypoint(const char *name
);
253 struct radv_extensions
{
254 VkExtensionProperties
*ext_array
;
258 struct radv_physical_device
{
259 VK_LOADER_DATA _loader_data
;
261 struct radv_instance
* instance
;
263 struct radeon_winsys
*ws
;
264 struct radeon_info rad_info
;
267 uint8_t uuid
[VK_UUID_SIZE
];
270 struct wsi_device wsi_device
;
271 struct radv_extensions extensions
;
274 struct radv_instance
{
275 VK_LOADER_DATA _loader_data
;
277 VkAllocationCallbacks alloc
;
280 int physicalDeviceCount
;
281 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
283 uint64_t debug_flags
;
286 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
287 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
291 struct radv_pipeline_cache
{
292 struct radv_device
* device
;
293 pthread_mutex_t mutex
;
297 uint32_t kernel_count
;
298 struct cache_entry
** hash_table
;
301 VkAllocationCallbacks alloc
;
305 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
306 struct radv_device
*device
);
308 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
310 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
311 const void *data
, size_t size
);
313 struct radv_shader_variant
*
314 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
315 struct radv_pipeline_cache
*cache
,
316 const unsigned char *sha1
);
318 struct radv_shader_variant
*
319 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache
*cache
,
320 const unsigned char *sha1
,
321 struct radv_shader_variant
*variant
,
322 const void *code
, unsigned code_size
);
324 void radv_shader_variant_destroy(struct radv_device
*device
,
325 struct radv_shader_variant
*variant
);
327 struct radv_meta_state
{
328 VkAllocationCallbacks alloc
;
330 struct radv_pipeline_cache cache
;
333 * Use array element `i` for images with `2^i` samples.
336 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
337 struct radv_pipeline
*color_pipelines
[NUM_META_FS_KEYS
];
339 VkRenderPass depthstencil_rp
;
340 struct radv_pipeline
*depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
341 struct radv_pipeline
*stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
342 struct radv_pipeline
*depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
343 } clear
[1 + MAX_SAMPLES_LOG2
];
346 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
348 /** Pipeline that blits from a 1D image. */
349 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
351 /** Pipeline that blits from a 2D image. */
352 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
354 /** Pipeline that blits from a 3D image. */
355 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
357 VkRenderPass depth_only_rp
;
358 VkPipeline depth_only_1d_pipeline
;
359 VkPipeline depth_only_2d_pipeline
;
360 VkPipeline depth_only_3d_pipeline
;
362 VkRenderPass stencil_only_rp
;
363 VkPipeline stencil_only_1d_pipeline
;
364 VkPipeline stencil_only_2d_pipeline
;
365 VkPipeline stencil_only_3d_pipeline
;
366 VkPipelineLayout pipeline_layout
;
367 VkDescriptorSetLayout ds_layout
;
371 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
373 VkPipelineLayout p_layouts
[2];
374 VkDescriptorSetLayout ds_layouts
[2];
375 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
377 VkRenderPass depth_only_rp
;
378 VkPipeline depth_only_pipeline
[2];
380 VkRenderPass stencil_only_rp
;
381 VkPipeline stencil_only_pipeline
[2];
385 VkPipelineLayout img_p_layout
;
386 VkDescriptorSetLayout img_ds_layout
;
390 VkRenderPass render_pass
;
391 VkPipelineLayout img_p_layout
;
392 VkDescriptorSetLayout img_ds_layout
;
396 VkPipelineLayout img_p_layout
;
397 VkDescriptorSetLayout img_ds_layout
;
401 VkPipelineLayout img_p_layout
;
402 VkDescriptorSetLayout img_ds_layout
;
412 VkDescriptorSetLayout ds_layout
;
413 VkPipelineLayout p_layout
;
416 VkPipeline i_pipeline
;
417 } rc
[MAX_SAMPLES_LOG2
];
421 VkPipeline decompress_pipeline
;
422 VkPipeline resummarize_pipeline
;
427 VkPipeline cmask_eliminate_pipeline
;
428 VkPipeline fmask_decompress_pipeline
;
433 VkPipelineLayout fill_p_layout
;
434 VkPipelineLayout copy_p_layout
;
435 VkDescriptorSetLayout fill_ds_layout
;
436 VkDescriptorSetLayout copy_ds_layout
;
437 VkPipeline fill_pipeline
;
438 VkPipeline copy_pipeline
;
443 #define RADV_QUEUE_GENERAL 0
444 #define RADV_QUEUE_COMPUTE 1
445 #define RADV_QUEUE_TRANSFER 2
447 #define RADV_MAX_QUEUE_FAMILIES 3
449 enum ring_type
radv_queue_family_to_ring(int f
);
452 VK_LOADER_DATA _loader_data
;
453 struct radv_device
* device
;
454 struct radeon_winsys_ctx
*hw_ctx
;
455 int queue_family_index
;
458 uint32_t scratch_size
;
459 uint32_t compute_scratch_size
;
460 uint32_t esgs_ring_size
;
461 uint32_t gsvs_ring_size
;
463 struct radeon_winsys_bo
*scratch_bo
;
464 struct radeon_winsys_bo
*descriptor_bo
;
465 struct radeon_winsys_bo
*compute_scratch_bo
;
466 struct radeon_winsys_bo
*esgs_ring_bo
;
467 struct radeon_winsys_bo
*gsvs_ring_bo
;
468 struct radeon_winsys_cs
*initial_preamble_cs
;
469 struct radeon_winsys_cs
*continue_preamble_cs
;
473 VK_LOADER_DATA _loader_data
;
475 VkAllocationCallbacks alloc
;
477 struct radv_instance
* instance
;
478 struct radeon_winsys
*ws
;
480 struct radv_meta_state meta_state
;
482 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
483 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
484 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
485 struct radeon_winsys_cs
*flush_cs
[RADV_MAX_QUEUE_FAMILIES
];
487 uint64_t debug_flags
;
489 bool llvm_supports_spill
;
490 uint32_t scratch_waves
;
492 uint32_t gs_table_depth
;
494 /* MSAA sample locations.
495 * The first index is the sample index.
496 * The second index is the coordinate: X, Y. */
497 float sample_locations_1x
[1][2];
498 float sample_locations_2x
[2][2];
499 float sample_locations_4x
[4][2];
500 float sample_locations_8x
[8][2];
501 float sample_locations_16x
[16][2];
504 uint32_t gfx_init_size_dw
;
505 struct radeon_winsys_bo
*gfx_init
;
507 struct radeon_winsys_bo
*trace_bo
;
508 uint32_t *trace_id_ptr
;
510 struct radv_physical_device
*physical_device
;
512 /* Backup in-memory cache to be used if the app doesn't provide one */
513 struct radv_pipeline_cache
* mem_cache
;
516 struct radv_device_memory
{
517 struct radeon_winsys_bo
*bo
;
518 /* for dedicated allocations */
519 struct radv_image
*image
;
520 struct radv_buffer
*buffer
;
522 VkDeviceSize map_size
;
527 struct radv_descriptor_range
{
532 struct radv_descriptor_set
{
533 const struct radv_descriptor_set_layout
*layout
;
536 struct radeon_winsys_bo
*bo
;
538 uint32_t *mapped_ptr
;
539 struct radv_descriptor_range
*dynamic_descriptors
;
541 struct list_head vram_list
;
543 struct radeon_winsys_bo
*descriptors
[0];
546 struct radv_descriptor_pool
{
547 struct radeon_winsys_bo
*bo
;
549 uint64_t current_offset
;
552 struct list_head vram_list
;
556 struct radv_device
* device
;
559 VkBufferUsageFlags usage
;
560 VkBufferCreateFlags flags
;
563 struct radeon_winsys_bo
* bo
;
568 enum radv_cmd_dirty_bits
{
569 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
570 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
571 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
572 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
573 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
574 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
575 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
576 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
577 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
578 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
579 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
580 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
581 RADV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
583 typedef uint32_t radv_cmd_dirty_mask_t
;
585 enum radv_cmd_flush_bits
{
586 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
587 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
588 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
589 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
590 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
591 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
592 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
593 /* Same as above, but only writes back and doesn't invalidate */
594 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
595 /* Framebuffer caches */
596 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
597 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
598 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
599 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
600 /* Engine synchronization. */
601 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
602 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
603 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
604 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
606 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
607 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
608 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
609 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
612 struct radv_vertex_binding
{
613 struct radv_buffer
* buffer
;
617 struct radv_dynamic_state
{
620 VkViewport viewports
[MAX_VIEWPORTS
];
625 VkRect2D scissors
[MAX_SCISSORS
];
636 float blend_constants
[4];
646 } stencil_compare_mask
;
651 } stencil_write_mask
;
659 extern const struct radv_dynamic_state default_dynamic_state
;
661 void radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
662 const struct radv_dynamic_state
*src
,
665 * Attachment state when recording a renderpass instance.
667 * The clear value is valid only if there exists a pending clear.
669 struct radv_attachment_state
{
670 VkImageAspectFlags pending_clear_aspects
;
671 VkClearValue clear_value
;
672 VkImageLayout current_layout
;
675 struct radv_cmd_state
{
677 radv_cmd_dirty_mask_t dirty
;
678 bool vertex_descriptors_dirty
;
680 struct radv_pipeline
* pipeline
;
681 struct radv_pipeline
* emitted_pipeline
;
682 struct radv_pipeline
* compute_pipeline
;
683 struct radv_pipeline
* emitted_compute_pipeline
;
684 struct radv_framebuffer
* framebuffer
;
685 struct radv_render_pass
* pass
;
686 const struct radv_subpass
* subpass
;
687 struct radv_dynamic_state dynamic
;
688 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
689 struct radv_descriptor_set
* descriptors
[MAX_SETS
];
690 struct radv_attachment_state
* attachments
;
691 VkRect2D render_area
;
692 struct radv_buffer
* index_buffer
;
694 uint32_t index_offset
;
695 uint32_t last_primitive_reset_index
;
696 enum radv_cmd_flush_bits flush_bits
;
697 unsigned active_occlusion_queries
;
699 uint32_t descriptors_dirty
;
701 uint32_t last_ia_multi_vgt_param
;
704 struct radv_cmd_pool
{
705 VkAllocationCallbacks alloc
;
706 struct list_head cmd_buffers
;
707 struct list_head free_cmd_buffers
;
708 uint32_t queue_family_index
;
711 struct radv_cmd_buffer_upload
{
715 struct radeon_winsys_bo
*upload_bo
;
716 struct list_head list
;
719 struct radv_cmd_buffer
{
720 VK_LOADER_DATA _loader_data
;
722 struct radv_device
* device
;
724 struct radv_cmd_pool
* pool
;
725 struct list_head pool_link
;
727 VkCommandBufferUsageFlags usage_flags
;
728 VkCommandBufferLevel level
;
729 struct radeon_winsys_cs
*cs
;
730 struct radv_cmd_state state
;
731 uint32_t queue_family_index
;
733 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
734 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
735 VkShaderStageFlags push_constant_stages
;
737 struct radv_cmd_buffer_upload upload
;
741 uint32_t scratch_size_needed
;
742 uint32_t compute_scratch_size_needed
;
743 uint32_t esgs_ring_size_needed
;
744 uint32_t gsvs_ring_size_needed
;
746 int ring_offsets_idx
; /* just used for verification */
751 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
753 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
754 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
756 void cik_create_gfx_config(struct radv_device
*device
);
758 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
759 int count
, const VkViewport
*viewports
);
760 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
761 int count
, const VkRect2D
*scissors
);
762 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
763 bool instanced_draw
, bool indirect_draw
,
764 uint32_t draw_vertex_count
);
765 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
766 enum chip_class chip_class
,
768 enum radv_cmd_flush_bits flush_bits
);
769 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
770 enum chip_class chip_class
,
772 enum radv_cmd_flush_bits flush_bits
);
773 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
774 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
775 uint64_t src_va
, uint64_t dest_va
,
777 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
778 uint64_t size
, unsigned value
);
779 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
780 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
781 struct radv_descriptor_set
*set
,
784 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
787 unsigned *out_offset
,
790 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
791 const struct radv_subpass
*subpass
,
794 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
795 unsigned size
, unsigned alignmnet
,
796 const void *data
, unsigned *out_offset
);
798 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
799 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
800 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
801 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
802 unsigned radv_cayman_get_maxdist(int log_samples
);
803 void radv_device_init_msaa(struct radv_device
*device
);
804 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
805 struct radv_image
*image
,
806 VkClearDepthStencilValue ds_clear_value
,
807 VkImageAspectFlags aspects
);
808 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
809 struct radv_image
*image
,
811 uint32_t color_values
[2]);
812 void radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
813 struct radeon_winsys_bo
*bo
,
814 uint64_t offset
, uint64_t size
, uint32_t value
);
815 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
816 bool radv_get_memory_fd(struct radv_device
*device
,
817 struct radv_device_memory
*memory
,
820 * Takes x,y,z as exact numbers of invocations, instead of blocks.
822 * Limitations: Can't call normal dispatch functions without binding or rebinding
823 * the compute pipeline.
825 void radv_unaligned_dispatch(
826 struct radv_cmd_buffer
*cmd_buffer
,
832 struct radeon_winsys_bo
*bo
;
838 struct radv_shader_module
{
839 struct nir_shader
* nir
;
840 unsigned char sha1
[20];
845 union ac_shader_variant_key
;
848 radv_hash_shader(unsigned char *hash
, struct radv_shader_module
*module
,
849 const char *entrypoint
,
850 const VkSpecializationInfo
*spec_info
,
851 const struct radv_pipeline_layout
*layout
,
852 const union ac_shader_variant_key
*key
,
853 uint32_t is_geom_copy_shader
);
855 static inline gl_shader_stage
856 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
858 assert(__builtin_popcount(vk_stage
) == 1);
859 return ffs(vk_stage
) - 1;
862 static inline VkShaderStageFlagBits
863 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
865 return (1 << mesa_stage
);
868 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
870 #define radv_foreach_stage(stage, stage_bits) \
871 for (gl_shader_stage stage, \
872 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
873 stage = __builtin_ffs(__tmp) - 1, __tmp; \
874 __tmp &= ~(1 << (stage)))
876 struct radv_shader_variant
{
879 struct radeon_winsys_bo
*bo
;
880 struct ac_shader_config config
;
881 struct ac_shader_variant_info info
;
887 struct radv_depth_stencil_state
{
888 uint32_t db_depth_control
;
889 uint32_t db_stencil_control
;
890 uint32_t db_render_control
;
891 uint32_t db_render_override2
;
894 struct radv_blend_state
{
895 uint32_t cb_color_control
;
896 uint32_t cb_target_mask
;
897 uint32_t sx_mrt0_blend_opt
[8];
898 uint32_t cb_blend_control
[8];
900 uint32_t spi_shader_col_format
;
901 uint32_t cb_shader_mask
;
902 uint32_t db_alpha_to_mask
;
905 unsigned radv_format_meta_fs_key(VkFormat format
);
907 struct radv_raster_state
{
908 uint32_t pa_cl_clip_cntl
;
909 uint32_t spi_interp_control
;
910 uint32_t pa_su_point_size
;
911 uint32_t pa_su_point_minmax
;
912 uint32_t pa_su_line_cntl
;
913 uint32_t pa_su_vtx_cntl
;
914 uint32_t pa_su_sc_mode_cntl
;
917 struct radv_multisample_state
{
919 uint32_t pa_sc_line_cntl
;
920 uint32_t pa_sc_mode_cntl_0
;
921 uint32_t pa_sc_mode_cntl_1
;
922 uint32_t pa_sc_aa_config
;
923 uint32_t pa_sc_aa_mask
[2];
924 unsigned num_samples
;
927 struct radv_prim_vertex_count
{
932 struct radv_pipeline
{
933 struct radv_device
* device
;
934 uint32_t dynamic_state_mask
;
935 struct radv_dynamic_state dynamic_state
;
937 struct radv_pipeline_layout
* layout
;
939 bool needs_data_cache
;
941 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
942 struct radv_shader_variant
*gs_copy_shader
;
943 VkShaderStageFlags active_stages
;
945 uint32_t va_rsrc_word3
[MAX_VERTEX_ATTRIBS
];
946 uint32_t va_format_size
[MAX_VERTEX_ATTRIBS
];
947 uint32_t va_binding
[MAX_VERTEX_ATTRIBS
];
948 uint32_t va_offset
[MAX_VERTEX_ATTRIBS
];
949 uint32_t num_vertex_attribs
;
950 uint32_t binding_stride
[MAX_VBS
];
954 struct radv_blend_state blend
;
955 struct radv_depth_stencil_state ds
;
956 struct radv_raster_state raster
;
957 struct radv_multisample_state ms
;
958 uint32_t db_shader_control
;
959 uint32_t shader_z_format
;
962 uint32_t vgt_gs_mode
;
963 bool prim_restart_enable
;
964 unsigned esgs_ring_size
;
965 unsigned gsvs_ring_size
;
966 uint32_t ps_input_cntl
[32];
967 uint32_t ps_input_cntl_num
;
968 uint32_t pa_cl_vs_out_cntl
;
969 uint32_t vgt_shader_stages_en
;
970 struct radv_prim_vertex_count prim_vertex_count
;
975 unsigned scratch_bytes_per_wave
;
978 static inline bool radv_pipeline_has_gs(struct radv_pipeline
*pipeline
)
980 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
983 struct radv_graphics_pipeline_create_info
{
986 bool db_stencil_clear
;
987 bool db_depth_disable_expclear
;
988 bool db_stencil_disable_expclear
;
989 bool db_flush_depth_inplace
;
990 bool db_flush_stencil_inplace
;
992 uint32_t custom_blend_mode
;
996 radv_pipeline_init(struct radv_pipeline
*pipeline
, struct radv_device
*device
,
997 struct radv_pipeline_cache
*cache
,
998 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
999 const struct radv_graphics_pipeline_create_info
*extra
,
1000 const VkAllocationCallbacks
*alloc
);
1003 radv_graphics_pipeline_create(VkDevice device
,
1004 VkPipelineCache cache
,
1005 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1006 const struct radv_graphics_pipeline_create_info
*extra
,
1007 const VkAllocationCallbacks
*alloc
,
1008 VkPipeline
*pPipeline
);
1010 struct vk_format_description
;
1011 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1012 int first_non_void
);
1013 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1014 int first_non_void
);
1015 uint32_t radv_translate_colorformat(VkFormat format
);
1016 uint32_t radv_translate_color_numformat(VkFormat format
,
1017 const struct vk_format_description
*desc
,
1018 int first_non_void
);
1019 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1020 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1021 uint32_t radv_translate_dbformat(VkFormat format
);
1022 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1023 const struct vk_format_description
*desc
,
1024 int first_non_void
);
1025 uint32_t radv_translate_tex_numformat(VkFormat format
,
1026 const struct vk_format_description
*desc
,
1027 int first_non_void
);
1028 bool radv_format_pack_clear_color(VkFormat format
,
1029 uint32_t clear_vals
[2],
1030 VkClearColorValue
*value
);
1031 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1033 struct radv_fmask_info
{
1037 unsigned pitch_in_pixels
;
1038 unsigned bank_height
;
1039 unsigned slice_tile_max
;
1040 unsigned tile_mode_index
;
1043 struct radv_cmask_info
{
1047 unsigned slice_tile_max
;
1048 unsigned base_address_reg
;
1051 struct r600_htile_info
{
1062 /* The original VkFormat provided by the client. This may not match any
1063 * of the actual surface formats.
1066 VkImageAspectFlags aspects
;
1069 uint32_t array_size
;
1070 uint32_t samples
; /**< VkImageCreateInfo::samples */
1071 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1072 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1073 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1079 unsigned queue_family_mask
;
1081 /* Set when bound */
1082 struct radeon_winsys_bo
*bo
;
1083 VkDeviceSize offset
;
1084 uint32_t dcc_offset
;
1085 uint32_t htile_offset
;
1086 struct radeon_surf surface
;
1088 struct radv_fmask_info fmask
;
1089 struct radv_cmask_info cmask
;
1090 uint32_t clear_value_offset
;
1093 bool radv_layout_has_htile(const struct radv_image
*image
,
1094 VkImageLayout layout
);
1095 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1096 VkImageLayout layout
);
1097 bool radv_layout_can_expclear(const struct radv_image
*image
,
1098 VkImageLayout layout
);
1099 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1100 VkImageLayout layout
,
1101 unsigned queue_mask
);
1104 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1106 static inline uint32_t
1107 radv_get_layerCount(const struct radv_image
*image
,
1108 const VkImageSubresourceRange
*range
)
1110 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1111 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1114 static inline uint32_t
1115 radv_get_levelCount(const struct radv_image
*image
,
1116 const VkImageSubresourceRange
*range
)
1118 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1119 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1122 struct radeon_bo_metadata
;
1124 radv_init_metadata(struct radv_device
*device
,
1125 struct radv_image
*image
,
1126 struct radeon_bo_metadata
*metadata
);
1128 struct radv_image_view
{
1129 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1130 struct radeon_winsys_bo
*bo
;
1132 VkImageViewType type
;
1133 VkImageAspectFlags aspect_mask
;
1135 uint32_t base_layer
;
1136 uint32_t layer_count
;
1138 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1140 uint32_t descriptor
[8];
1141 uint32_t fmask_descriptor
[8];
1144 struct radv_image_create_info
{
1145 const VkImageCreateInfo
*vk_info
;
1150 VkResult
radv_image_create(VkDevice _device
,
1151 const struct radv_image_create_info
*info
,
1152 const VkAllocationCallbacks
* alloc
,
1155 void radv_image_view_init(struct radv_image_view
*view
,
1156 struct radv_device
*device
,
1157 const VkImageViewCreateInfo
* pCreateInfo
,
1158 struct radv_cmd_buffer
*cmd_buffer
,
1159 VkImageUsageFlags usage_mask
);
1160 void radv_image_set_optimal_micro_tile_mode(struct radv_device
*device
,
1161 struct radv_image
*image
, uint32_t micro_tile_mode
);
1162 struct radv_buffer_view
{
1163 struct radeon_winsys_bo
*bo
;
1165 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1168 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1169 struct radv_device
*device
,
1170 const VkBufferViewCreateInfo
* pCreateInfo
,
1171 struct radv_cmd_buffer
*cmd_buffer
);
1173 static inline struct VkExtent3D
1174 radv_sanitize_image_extent(const VkImageType imageType
,
1175 const struct VkExtent3D imageExtent
)
1177 switch (imageType
) {
1178 case VK_IMAGE_TYPE_1D
:
1179 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1180 case VK_IMAGE_TYPE_2D
:
1181 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1182 case VK_IMAGE_TYPE_3D
:
1185 unreachable("invalid image type");
1189 static inline struct VkOffset3D
1190 radv_sanitize_image_offset(const VkImageType imageType
,
1191 const struct VkOffset3D imageOffset
)
1193 switch (imageType
) {
1194 case VK_IMAGE_TYPE_1D
:
1195 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1196 case VK_IMAGE_TYPE_2D
:
1197 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1198 case VK_IMAGE_TYPE_3D
:
1201 unreachable("invalid image type");
1205 struct radv_sampler
{
1209 struct radv_color_buffer_info
{
1210 uint32_t cb_color_base
;
1211 uint32_t cb_color_pitch
;
1212 uint32_t cb_color_slice
;
1213 uint32_t cb_color_view
;
1214 uint32_t cb_color_info
;
1215 uint32_t cb_color_attrib
;
1216 uint32_t cb_dcc_control
;
1217 uint32_t cb_color_cmask
;
1218 uint32_t cb_color_cmask_slice
;
1219 uint32_t cb_color_fmask
;
1220 uint32_t cb_color_fmask_slice
;
1221 uint32_t cb_clear_value0
;
1222 uint32_t cb_clear_value1
;
1223 uint32_t cb_dcc_base
;
1224 uint32_t micro_tile_mode
;
1227 struct radv_ds_buffer_info
{
1228 uint32_t db_depth_info
;
1230 uint32_t db_stencil_info
;
1231 uint32_t db_z_read_base
;
1232 uint32_t db_stencil_read_base
;
1233 uint32_t db_z_write_base
;
1234 uint32_t db_stencil_write_base
;
1235 uint32_t db_depth_view
;
1236 uint32_t db_depth_size
;
1237 uint32_t db_depth_slice
;
1238 uint32_t db_htile_surface
;
1239 uint32_t db_htile_data_base
;
1240 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1244 struct radv_attachment_info
{
1246 struct radv_color_buffer_info cb
;
1247 struct radv_ds_buffer_info ds
;
1249 struct radv_image_view
*attachment
;
1252 struct radv_framebuffer
{
1257 uint32_t attachment_count
;
1258 struct radv_attachment_info attachments
[0];
1261 struct radv_subpass_barrier
{
1262 VkPipelineStageFlags src_stage_mask
;
1263 VkAccessFlags src_access_mask
;
1264 VkAccessFlags dst_access_mask
;
1267 struct radv_subpass
{
1268 uint32_t input_count
;
1269 VkAttachmentReference
* input_attachments
;
1270 uint32_t color_count
;
1271 VkAttachmentReference
* color_attachments
;
1272 VkAttachmentReference
* resolve_attachments
;
1273 VkAttachmentReference depth_stencil_attachment
;
1275 /** Subpass has at least one resolve attachment */
1278 struct radv_subpass_barrier start_barrier
;
1281 struct radv_render_pass_attachment
{
1284 VkAttachmentLoadOp load_op
;
1285 VkAttachmentLoadOp stencil_load_op
;
1286 VkImageLayout initial_layout
;
1287 VkImageLayout final_layout
;
1290 struct radv_render_pass
{
1291 uint32_t attachment_count
;
1292 uint32_t subpass_count
;
1293 VkAttachmentReference
* subpass_attachments
;
1294 struct radv_render_pass_attachment
* attachments
;
1295 struct radv_subpass_barrier end_barrier
;
1296 struct radv_subpass subpasses
[0];
1299 VkResult
radv_device_init_meta(struct radv_device
*device
);
1300 void radv_device_finish_meta(struct radv_device
*device
);
1302 struct radv_query_pool
{
1303 struct radeon_winsys_bo
*bo
;
1305 uint32_t availability_offset
;
1311 radv_temp_descriptor_set_create(struct radv_device
*device
,
1312 struct radv_cmd_buffer
*cmd_buffer
,
1313 VkDescriptorSetLayout _layout
,
1314 VkDescriptorSet
*_set
);
1317 radv_temp_descriptor_set_destroy(struct radv_device
*device
,
1318 VkDescriptorSet _set
);
1319 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1320 struct radv_image
*image
, uint32_t value
);
1321 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1322 struct radv_image
*image
, uint32_t value
);
1325 struct radeon_winsys_fence
*fence
;
1330 struct radeon_winsys_sem
;
1332 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1334 static inline struct __radv_type * \
1335 __radv_type ## _from_handle(__VkType _handle) \
1337 return (struct __radv_type *) _handle; \
1340 static inline __VkType \
1341 __radv_type ## _to_handle(struct __radv_type *_obj) \
1343 return (__VkType) _obj; \
1346 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1348 static inline struct __radv_type * \
1349 __radv_type ## _from_handle(__VkType _handle) \
1351 return (struct __radv_type *)(uintptr_t) _handle; \
1354 static inline __VkType \
1355 __radv_type ## _to_handle(struct __radv_type *_obj) \
1357 return (__VkType)(uintptr_t) _obj; \
1360 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1361 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1363 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1364 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1365 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1366 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1367 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1369 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1370 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1371 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1372 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1373 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1374 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1375 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1376 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1377 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1378 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1379 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1380 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1381 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1382 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1383 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1384 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1385 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1386 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1387 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1388 RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem
, VkSemaphore
)
1390 #endif /* RADV_PRIVATE_H */