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ac: add ac_build_{struct,raw}_tbuffer_load() helpers
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102 #define MAX_SO_STREAMS 4
103 #define MAX_SO_BUFFERS 4
104 #define MAX_SO_OUTPUTS 64
105
106 #define NUM_DEPTH_CLEAR_PIPELINES 3
107
108 /*
109 * This is the point we switch from using CP to compute shader
110 * for certain buffer operations.
111 */
112 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113
114 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
115
116 enum radv_mem_heap {
117 RADV_MEM_HEAP_VRAM,
118 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
119 RADV_MEM_HEAP_GTT,
120 RADV_MEM_HEAP_COUNT
121 };
122
123 enum radv_mem_type {
124 RADV_MEM_TYPE_VRAM,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
127 RADV_MEM_TYPE_GTT_CACHED,
128 RADV_MEM_TYPE_COUNT
129 };
130
131 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
132
133 static inline uint32_t
134 align_u32(uint32_t v, uint32_t a)
135 {
136 assert(a != 0 && a == (a & -a));
137 return (v + a - 1) & ~(a - 1);
138 }
139
140 static inline uint32_t
141 align_u32_npot(uint32_t v, uint32_t a)
142 {
143 return (v + a - 1) / a * a;
144 }
145
146 static inline uint64_t
147 align_u64(uint64_t v, uint64_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 static inline int32_t
154 align_i32(int32_t v, int32_t a)
155 {
156 assert(a != 0 && a == (a & -a));
157 return (v + a - 1) & ~(a - 1);
158 }
159
160 /** Alignment must be a power of 2. */
161 static inline bool
162 radv_is_aligned(uintmax_t n, uintmax_t a)
163 {
164 assert(a == (a & -a));
165 return (n & (a - 1)) == 0;
166 }
167
168 static inline uint32_t
169 round_up_u32(uint32_t v, uint32_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint64_t
175 round_up_u64(uint64_t v, uint64_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint32_t
181 radv_minify(uint32_t n, uint32_t levels)
182 {
183 if (unlikely(n == 0))
184 return 0;
185 else
186 return MAX2(n >> levels, 1);
187 }
188 static inline float
189 radv_clamp_f(float f, float min, float max)
190 {
191 assert(min < max);
192
193 if (f > max)
194 return max;
195 else if (f < min)
196 return min;
197 else
198 return f;
199 }
200
201 static inline bool
202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
203 {
204 if (*inout_mask & clear_mask) {
205 *inout_mask &= ~clear_mask;
206 return true;
207 } else {
208 return false;
209 }
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Whenever we generate an error, pass it through this function. Useful for
223 * debugging, where we can break on it. Only call at error site, not when
224 * propagating errors. Might be useful to plug in a stack trace here.
225 */
226
227 struct radv_instance;
228
229 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
230
231 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
232 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
233
234 void __radv_finishme(const char *file, int line, const char *format, ...)
235 radv_printflike(3, 4);
236 void radv_loge(const char *format, ...) radv_printflike(1, 2);
237 void radv_loge_v(const char *format, va_list va);
238 void radv_logi(const char *format, ...) radv_printflike(1, 2);
239 void radv_logi_v(const char *format, va_list va);
240
241 /**
242 * Print a FINISHME message, including its source location.
243 */
244 #define radv_finishme(format, ...) \
245 do { \
246 static bool reported = false; \
247 if (!reported) { \
248 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 reported = true; \
250 } \
251 } while (0)
252
253 /* A non-fatal assert. Useful for debugging. */
254 #ifdef DEBUG
255 #define radv_assert(x) ({ \
256 if (unlikely(!(x))) \
257 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
258 })
259 #else
260 #define radv_assert(x)
261 #endif
262
263 #define stub_return(v) \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return (v); \
267 } while (0)
268
269 #define stub() \
270 do { \
271 radv_finishme("stub %s", __func__); \
272 return; \
273 } while (0)
274
275 void *radv_lookup_entrypoint_unchecked(const char *name);
276 void *radv_lookup_entrypoint_checked(const char *name,
277 uint32_t core_version,
278 const struct radv_instance_extension_table *instance,
279 const struct radv_device_extension_table *device);
280
281 struct radv_physical_device {
282 VK_LOADER_DATA _loader_data;
283
284 struct radv_instance * instance;
285
286 struct radeon_winsys *ws;
287 struct radeon_info rad_info;
288 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
289 uint8_t driver_uuid[VK_UUID_SIZE];
290 uint8_t device_uuid[VK_UUID_SIZE];
291 uint8_t cache_uuid[VK_UUID_SIZE];
292
293 int local_fd;
294 int master_fd;
295 struct wsi_device wsi_device;
296
297 bool has_rbplus; /* if RB+ register exist */
298 bool rbplus_allowed; /* if RB+ is allowed */
299 bool has_clear_state;
300 bool cpdma_prefetch_writes_memory;
301 bool has_scissor_bug;
302
303 bool has_out_of_order_rast;
304 bool out_of_order_rast_allowed;
305
306 /* Whether DCC should be enabled for MSAA textures. */
307 bool dcc_msaa_allowed;
308
309 /* Whether LOAD_CONTEXT_REG packets are supported. */
310 bool has_load_ctx_reg_pkt;
311
312 /* This is the drivers on-disk cache used as a fallback as opposed to
313 * the pipeline cache defined by apps.
314 */
315 struct disk_cache * disk_cache;
316
317 VkPhysicalDeviceMemoryProperties memory_properties;
318 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
319
320 drmPciBusInfo bus_info;
321
322 struct radv_device_extension_table supported_extensions;
323 };
324
325 struct radv_instance {
326 VK_LOADER_DATA _loader_data;
327
328 VkAllocationCallbacks alloc;
329
330 uint32_t apiVersion;
331 int physicalDeviceCount;
332 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
333
334 uint64_t debug_flags;
335 uint64_t perftest_flags;
336
337 struct vk_debug_report_instance debug_report_callbacks;
338
339 struct radv_instance_extension_table enabled_extensions;
340 };
341
342 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
343 void radv_finish_wsi(struct radv_physical_device *physical_device);
344
345 bool radv_instance_extension_supported(const char *name);
346 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
347 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
348 const char *name);
349
350 struct cache_entry;
351
352 struct radv_pipeline_cache {
353 struct radv_device * device;
354 pthread_mutex_t mutex;
355
356 uint32_t total_size;
357 uint32_t table_size;
358 uint32_t kernel_count;
359 struct cache_entry ** hash_table;
360 bool modified;
361
362 VkAllocationCallbacks alloc;
363 };
364
365 struct radv_pipeline_key {
366 uint32_t instance_rate_inputs;
367 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
368 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
369 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
370 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
371 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
372 uint64_t vertex_alpha_adjust;
373 uint32_t vertex_post_shuffle;
374 unsigned tess_input_vertices;
375 uint32_t col_format;
376 uint32_t is_int8;
377 uint32_t is_int10;
378 uint8_t log2_ps_iter_samples;
379 uint8_t num_samples;
380 uint32_t has_multiview_view_index : 1;
381 uint32_t optimisations_disabled : 1;
382 };
383
384 void
385 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
386 struct radv_device *device);
387 void
388 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
389 bool
390 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
391 const void *data, size_t size);
392
393 struct radv_shader_variant;
394
395 bool
396 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
397 struct radv_pipeline_cache *cache,
398 const unsigned char *sha1,
399 struct radv_shader_variant **variants);
400
401 void
402 radv_pipeline_cache_insert_shaders(struct radv_device *device,
403 struct radv_pipeline_cache *cache,
404 const unsigned char *sha1,
405 struct radv_shader_variant **variants,
406 const void *const *codes,
407 const unsigned *code_sizes);
408
409 enum radv_blit_ds_layout {
410 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
411 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
412 RADV_BLIT_DS_LAYOUT_COUNT,
413 };
414
415 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
416 {
417 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
418 }
419
420 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
421 {
422 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
423 }
424
425 enum radv_meta_dst_layout {
426 RADV_META_DST_LAYOUT_GENERAL,
427 RADV_META_DST_LAYOUT_OPTIMAL,
428 RADV_META_DST_LAYOUT_COUNT,
429 };
430
431 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
432 {
433 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
434 }
435
436 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
437 {
438 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
439 }
440
441 struct radv_meta_state {
442 VkAllocationCallbacks alloc;
443
444 struct radv_pipeline_cache cache;
445
446 /*
447 * For on-demand pipeline creation, makes sure that
448 * only one thread tries to build a pipeline at the same time.
449 */
450 mtx_t mtx;
451
452 /**
453 * Use array element `i` for images with `2^i` samples.
454 */
455 struct {
456 VkRenderPass render_pass[NUM_META_FS_KEYS];
457 VkPipeline color_pipelines[NUM_META_FS_KEYS];
458
459 VkRenderPass depthstencil_rp;
460 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
461 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
462 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
463 } clear[1 + MAX_SAMPLES_LOG2];
464
465 VkPipelineLayout clear_color_p_layout;
466 VkPipelineLayout clear_depth_p_layout;
467
468 /* Optimized compute fast HTILE clear for stencil or depth only. */
469 VkPipeline clear_htile_mask_pipeline;
470 VkPipelineLayout clear_htile_mask_p_layout;
471 VkDescriptorSetLayout clear_htile_mask_ds_layout;
472
473 struct {
474 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
475
476 /** Pipeline that blits from a 1D image. */
477 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
478
479 /** Pipeline that blits from a 2D image. */
480 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
481
482 /** Pipeline that blits from a 3D image. */
483 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
484
485 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
486 VkPipeline depth_only_1d_pipeline;
487 VkPipeline depth_only_2d_pipeline;
488 VkPipeline depth_only_3d_pipeline;
489
490 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
491 VkPipeline stencil_only_1d_pipeline;
492 VkPipeline stencil_only_2d_pipeline;
493 VkPipeline stencil_only_3d_pipeline;
494 VkPipelineLayout pipeline_layout;
495 VkDescriptorSetLayout ds_layout;
496 } blit;
497
498 struct {
499 VkPipelineLayout p_layouts[5];
500 VkDescriptorSetLayout ds_layouts[5];
501 VkPipeline pipelines[5][NUM_META_FS_KEYS];
502
503 VkPipeline depth_only_pipeline[5];
504
505 VkPipeline stencil_only_pipeline[5];
506 } blit2d[1 + MAX_SAMPLES_LOG2];
507
508 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
509 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
510 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
511
512 struct {
513 VkPipelineLayout img_p_layout;
514 VkDescriptorSetLayout img_ds_layout;
515 VkPipeline pipeline;
516 VkPipeline pipeline_3d;
517 } itob;
518 struct {
519 VkPipelineLayout img_p_layout;
520 VkDescriptorSetLayout img_ds_layout;
521 VkPipeline pipeline;
522 VkPipeline pipeline_3d;
523 } btoi;
524 struct {
525 VkPipelineLayout img_p_layout;
526 VkDescriptorSetLayout img_ds_layout;
527 VkPipeline pipeline;
528 } btoi_r32g32b32;
529 struct {
530 VkPipelineLayout img_p_layout;
531 VkDescriptorSetLayout img_ds_layout;
532 VkPipeline pipeline;
533 VkPipeline pipeline_3d;
534 } itoi;
535 struct {
536 VkPipelineLayout img_p_layout;
537 VkDescriptorSetLayout img_ds_layout;
538 VkPipeline pipeline;
539 } itoi_r32g32b32;
540 struct {
541 VkPipelineLayout img_p_layout;
542 VkDescriptorSetLayout img_ds_layout;
543 VkPipeline pipeline;
544 VkPipeline pipeline_3d;
545 } cleari;
546 struct {
547 VkPipelineLayout img_p_layout;
548 VkDescriptorSetLayout img_ds_layout;
549 VkPipeline pipeline;
550 } cleari_r32g32b32;
551
552 struct {
553 VkPipelineLayout p_layout;
554 VkPipeline pipeline[NUM_META_FS_KEYS];
555 VkRenderPass pass[NUM_META_FS_KEYS];
556 } resolve;
557
558 struct {
559 VkDescriptorSetLayout ds_layout;
560 VkPipelineLayout p_layout;
561 struct {
562 VkPipeline pipeline;
563 VkPipeline i_pipeline;
564 VkPipeline srgb_pipeline;
565 } rc[MAX_SAMPLES_LOG2];
566 } resolve_compute;
567
568 struct {
569 VkDescriptorSetLayout ds_layout;
570 VkPipelineLayout p_layout;
571
572 struct {
573 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
574 VkPipeline pipeline[NUM_META_FS_KEYS];
575 } rc[MAX_SAMPLES_LOG2];
576 } resolve_fragment;
577
578 struct {
579 VkPipelineLayout p_layout;
580 VkPipeline decompress_pipeline;
581 VkPipeline resummarize_pipeline;
582 VkRenderPass pass;
583 } depth_decomp[1 + MAX_SAMPLES_LOG2];
584
585 struct {
586 VkPipelineLayout p_layout;
587 VkPipeline cmask_eliminate_pipeline;
588 VkPipeline fmask_decompress_pipeline;
589 VkPipeline dcc_decompress_pipeline;
590 VkRenderPass pass;
591
592 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
593 VkPipelineLayout dcc_decompress_compute_p_layout;
594 VkPipeline dcc_decompress_compute_pipeline;
595 } fast_clear_flush;
596
597 struct {
598 VkPipelineLayout fill_p_layout;
599 VkPipelineLayout copy_p_layout;
600 VkDescriptorSetLayout fill_ds_layout;
601 VkDescriptorSetLayout copy_ds_layout;
602 VkPipeline fill_pipeline;
603 VkPipeline copy_pipeline;
604 } buffer;
605
606 struct {
607 VkDescriptorSetLayout ds_layout;
608 VkPipelineLayout p_layout;
609 VkPipeline occlusion_query_pipeline;
610 VkPipeline pipeline_statistics_query_pipeline;
611 VkPipeline tfb_query_pipeline;
612 } query;
613
614 struct {
615 VkDescriptorSetLayout ds_layout;
616 VkPipelineLayout p_layout;
617 VkPipeline pipeline[MAX_SAMPLES_LOG2];
618 } fmask_expand;
619 };
620
621 /* queue types */
622 #define RADV_QUEUE_GENERAL 0
623 #define RADV_QUEUE_COMPUTE 1
624 #define RADV_QUEUE_TRANSFER 2
625
626 #define RADV_MAX_QUEUE_FAMILIES 3
627
628 enum ring_type radv_queue_family_to_ring(int f);
629
630 struct radv_queue {
631 VK_LOADER_DATA _loader_data;
632 struct radv_device * device;
633 struct radeon_winsys_ctx *hw_ctx;
634 enum radeon_ctx_priority priority;
635 uint32_t queue_family_index;
636 int queue_idx;
637 VkDeviceQueueCreateFlags flags;
638
639 uint32_t scratch_size;
640 uint32_t compute_scratch_size;
641 uint32_t esgs_ring_size;
642 uint32_t gsvs_ring_size;
643 bool has_tess_rings;
644 bool has_sample_positions;
645
646 struct radeon_winsys_bo *scratch_bo;
647 struct radeon_winsys_bo *descriptor_bo;
648 struct radeon_winsys_bo *compute_scratch_bo;
649 struct radeon_winsys_bo *esgs_ring_bo;
650 struct radeon_winsys_bo *gsvs_ring_bo;
651 struct radeon_winsys_bo *tess_rings_bo;
652 struct radeon_cmdbuf *initial_preamble_cs;
653 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
654 struct radeon_cmdbuf *continue_preamble_cs;
655 };
656
657 struct radv_bo_list {
658 struct radv_winsys_bo_list list;
659 unsigned capacity;
660 pthread_mutex_t mutex;
661 };
662
663 struct radv_device {
664 VK_LOADER_DATA _loader_data;
665
666 VkAllocationCallbacks alloc;
667
668 struct radv_instance * instance;
669 struct radeon_winsys *ws;
670
671 struct radv_meta_state meta_state;
672
673 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
674 int queue_count[RADV_MAX_QUEUE_FAMILIES];
675 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
676
677 bool always_use_syncobj;
678 bool has_distributed_tess;
679 bool pbb_allowed;
680 bool dfsm_allowed;
681 uint32_t tess_offchip_block_dw_size;
682 uint32_t scratch_waves;
683 uint32_t dispatch_initiator;
684
685 uint32_t gs_table_depth;
686
687 /* MSAA sample locations.
688 * The first index is the sample index.
689 * The second index is the coordinate: X, Y. */
690 float sample_locations_1x[1][2];
691 float sample_locations_2x[2][2];
692 float sample_locations_4x[4][2];
693 float sample_locations_8x[8][2];
694 float sample_locations_16x[16][2];
695
696 /* CIK and later */
697 uint32_t gfx_init_size_dw;
698 struct radeon_winsys_bo *gfx_init;
699
700 struct radeon_winsys_bo *trace_bo;
701 uint32_t *trace_id_ptr;
702
703 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
704 bool keep_shader_info;
705
706 struct radv_physical_device *physical_device;
707
708 /* Backup in-memory cache to be used if the app doesn't provide one */
709 struct radv_pipeline_cache * mem_cache;
710
711 /*
712 * use different counters so MSAA MRTs get consecutive surface indices,
713 * even if MASK is allocated in between.
714 */
715 uint32_t image_mrt_offset_counter;
716 uint32_t fmask_mrt_offset_counter;
717 struct list_head shader_slabs;
718 mtx_t shader_slab_mutex;
719
720 /* For detecting VM faults reported by dmesg. */
721 uint64_t dmesg_timestamp;
722
723 struct radv_device_extension_table enabled_extensions;
724
725 /* Whether the driver uses a global BO list. */
726 bool use_global_bo_list;
727
728 struct radv_bo_list bo_list;
729
730 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
731 int force_aniso;
732 };
733
734 struct radv_device_memory {
735 struct radeon_winsys_bo *bo;
736 /* for dedicated allocations */
737 struct radv_image *image;
738 struct radv_buffer *buffer;
739 uint32_t type_index;
740 VkDeviceSize map_size;
741 void * map;
742 void * user_ptr;
743 };
744
745
746 struct radv_descriptor_range {
747 uint64_t va;
748 uint32_t size;
749 };
750
751 struct radv_descriptor_set {
752 const struct radv_descriptor_set_layout *layout;
753 uint32_t size;
754
755 struct radeon_winsys_bo *bo;
756 uint64_t va;
757 uint32_t *mapped_ptr;
758 struct radv_descriptor_range *dynamic_descriptors;
759
760 struct radeon_winsys_bo *descriptors[0];
761 };
762
763 struct radv_push_descriptor_set
764 {
765 struct radv_descriptor_set set;
766 uint32_t capacity;
767 };
768
769 struct radv_descriptor_pool_entry {
770 uint32_t offset;
771 uint32_t size;
772 struct radv_descriptor_set *set;
773 };
774
775 struct radv_descriptor_pool {
776 struct radeon_winsys_bo *bo;
777 uint8_t *mapped_ptr;
778 uint64_t current_offset;
779 uint64_t size;
780
781 uint8_t *host_memory_base;
782 uint8_t *host_memory_ptr;
783 uint8_t *host_memory_end;
784
785 uint32_t entry_count;
786 uint32_t max_entry_count;
787 struct radv_descriptor_pool_entry entries[0];
788 };
789
790 struct radv_descriptor_update_template_entry {
791 VkDescriptorType descriptor_type;
792
793 /* The number of descriptors to update */
794 uint32_t descriptor_count;
795
796 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
797 uint32_t dst_offset;
798
799 /* In dwords. Not valid/used for dynamic descriptors */
800 uint32_t dst_stride;
801
802 uint32_t buffer_offset;
803
804 /* Only valid for combined image samplers and samplers */
805 uint16_t has_sampler;
806
807 /* In bytes */
808 size_t src_offset;
809 size_t src_stride;
810
811 /* For push descriptors */
812 const uint32_t *immutable_samplers;
813 };
814
815 struct radv_descriptor_update_template {
816 uint32_t entry_count;
817 VkPipelineBindPoint bind_point;
818 struct radv_descriptor_update_template_entry entry[0];
819 };
820
821 struct radv_buffer {
822 VkDeviceSize size;
823
824 VkBufferUsageFlags usage;
825 VkBufferCreateFlags flags;
826
827 /* Set when bound */
828 struct radeon_winsys_bo * bo;
829 VkDeviceSize offset;
830
831 bool shareable;
832 };
833
834 enum radv_dynamic_state_bits {
835 RADV_DYNAMIC_VIEWPORT = 1 << 0,
836 RADV_DYNAMIC_SCISSOR = 1 << 1,
837 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
838 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
839 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
840 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
841 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
842 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
843 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
844 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
845 RADV_DYNAMIC_ALL = (1 << 10) - 1,
846 };
847
848 enum radv_cmd_dirty_bits {
849 /* Keep the dynamic state dirty bits in sync with
850 * enum radv_dynamic_state_bits */
851 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
852 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
853 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
854 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
855 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
856 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
857 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
858 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
859 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
860 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
861 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
862 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
863 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
864 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
865 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
866 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
867 };
868
869 enum radv_cmd_flush_bits {
870 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
871 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
872 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
873 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
874 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
875 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
876 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
877 /* Same as above, but only writes back and doesn't invalidate */
878 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
879 /* Framebuffer caches */
880 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
881 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
882 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
883 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
884 /* Engine synchronization. */
885 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
886 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
887 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
888 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
889 /* Pipeline query controls. */
890 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
891 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
892 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
893
894 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
895 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
896 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
897 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
898 };
899
900 struct radv_vertex_binding {
901 struct radv_buffer * buffer;
902 VkDeviceSize offset;
903 };
904
905 struct radv_streamout_binding {
906 struct radv_buffer *buffer;
907 VkDeviceSize offset;
908 VkDeviceSize size;
909 };
910
911 struct radv_streamout_state {
912 /* Mask of bound streamout buffers. */
913 uint8_t enabled_mask;
914
915 /* External state that comes from the last vertex stage, it must be
916 * set explicitely when binding a new graphics pipeline.
917 */
918 uint16_t stride_in_dw[MAX_SO_BUFFERS];
919 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
920
921 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
922 uint32_t hw_enabled_mask;
923
924 /* State of VGT_STRMOUT_(CONFIG|EN) */
925 bool streamout_enabled;
926 };
927
928 struct radv_viewport_state {
929 uint32_t count;
930 VkViewport viewports[MAX_VIEWPORTS];
931 };
932
933 struct radv_scissor_state {
934 uint32_t count;
935 VkRect2D scissors[MAX_SCISSORS];
936 };
937
938 struct radv_discard_rectangle_state {
939 uint32_t count;
940 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
941 };
942
943 struct radv_dynamic_state {
944 /**
945 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
946 * Defines the set of saved dynamic state.
947 */
948 uint32_t mask;
949
950 struct radv_viewport_state viewport;
951
952 struct radv_scissor_state scissor;
953
954 float line_width;
955
956 struct {
957 float bias;
958 float clamp;
959 float slope;
960 } depth_bias;
961
962 float blend_constants[4];
963
964 struct {
965 float min;
966 float max;
967 } depth_bounds;
968
969 struct {
970 uint32_t front;
971 uint32_t back;
972 } stencil_compare_mask;
973
974 struct {
975 uint32_t front;
976 uint32_t back;
977 } stencil_write_mask;
978
979 struct {
980 uint32_t front;
981 uint32_t back;
982 } stencil_reference;
983
984 struct radv_discard_rectangle_state discard_rectangle;
985 };
986
987 extern const struct radv_dynamic_state default_dynamic_state;
988
989 const char *
990 radv_get_debug_option_name(int id);
991
992 const char *
993 radv_get_perftest_option_name(int id);
994
995 /**
996 * Attachment state when recording a renderpass instance.
997 *
998 * The clear value is valid only if there exists a pending clear.
999 */
1000 struct radv_attachment_state {
1001 VkImageAspectFlags pending_clear_aspects;
1002 uint32_t cleared_views;
1003 VkClearValue clear_value;
1004 VkImageLayout current_layout;
1005 };
1006
1007 struct radv_descriptor_state {
1008 struct radv_descriptor_set *sets[MAX_SETS];
1009 uint32_t dirty;
1010 uint32_t valid;
1011 struct radv_push_descriptor_set push_set;
1012 bool push_dirty;
1013 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1014 };
1015
1016 struct radv_cmd_state {
1017 /* Vertex descriptors */
1018 uint64_t vb_va;
1019 unsigned vb_size;
1020
1021 bool predicating;
1022 uint32_t dirty;
1023
1024 uint32_t prefetch_L2_mask;
1025
1026 struct radv_pipeline * pipeline;
1027 struct radv_pipeline * emitted_pipeline;
1028 struct radv_pipeline * compute_pipeline;
1029 struct radv_pipeline * emitted_compute_pipeline;
1030 struct radv_framebuffer * framebuffer;
1031 struct radv_render_pass * pass;
1032 const struct radv_subpass * subpass;
1033 struct radv_dynamic_state dynamic;
1034 struct radv_attachment_state * attachments;
1035 struct radv_streamout_state streamout;
1036 VkRect2D render_area;
1037
1038 /* Index buffer */
1039 struct radv_buffer *index_buffer;
1040 uint64_t index_offset;
1041 uint32_t index_type;
1042 uint32_t max_index_count;
1043 uint64_t index_va;
1044 int32_t last_index_type;
1045
1046 int32_t last_primitive_reset_en;
1047 uint32_t last_primitive_reset_index;
1048 enum radv_cmd_flush_bits flush_bits;
1049 unsigned active_occlusion_queries;
1050 bool perfect_occlusion_queries_enabled;
1051 unsigned active_pipeline_queries;
1052 float offset_scale;
1053 uint32_t trace_id;
1054 uint32_t last_ia_multi_vgt_param;
1055
1056 uint32_t last_num_instances;
1057 uint32_t last_first_instance;
1058 uint32_t last_vertex_offset;
1059
1060 /* Whether CP DMA is busy/idle. */
1061 bool dma_is_busy;
1062
1063 /* Conditional rendering info. */
1064 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1065 uint64_t predication_va;
1066
1067 bool context_roll_without_scissor_emitted;
1068 };
1069
1070 struct radv_cmd_pool {
1071 VkAllocationCallbacks alloc;
1072 struct list_head cmd_buffers;
1073 struct list_head free_cmd_buffers;
1074 uint32_t queue_family_index;
1075 };
1076
1077 struct radv_cmd_buffer_upload {
1078 uint8_t *map;
1079 unsigned offset;
1080 uint64_t size;
1081 struct radeon_winsys_bo *upload_bo;
1082 struct list_head list;
1083 };
1084
1085 enum radv_cmd_buffer_status {
1086 RADV_CMD_BUFFER_STATUS_INVALID,
1087 RADV_CMD_BUFFER_STATUS_INITIAL,
1088 RADV_CMD_BUFFER_STATUS_RECORDING,
1089 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1090 RADV_CMD_BUFFER_STATUS_PENDING,
1091 };
1092
1093 struct radv_cmd_buffer {
1094 VK_LOADER_DATA _loader_data;
1095
1096 struct radv_device * device;
1097
1098 struct radv_cmd_pool * pool;
1099 struct list_head pool_link;
1100
1101 VkCommandBufferUsageFlags usage_flags;
1102 VkCommandBufferLevel level;
1103 enum radv_cmd_buffer_status status;
1104 struct radeon_cmdbuf *cs;
1105 struct radv_cmd_state state;
1106 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1107 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1108 uint32_t queue_family_index;
1109
1110 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1111 VkShaderStageFlags push_constant_stages;
1112 struct radv_descriptor_set meta_push_descriptors;
1113
1114 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1115
1116 struct radv_cmd_buffer_upload upload;
1117
1118 uint32_t scratch_size_needed;
1119 uint32_t compute_scratch_size_needed;
1120 uint32_t esgs_ring_size_needed;
1121 uint32_t gsvs_ring_size_needed;
1122 bool tess_rings_needed;
1123 bool sample_positions_needed;
1124
1125 VkResult record_result;
1126
1127 uint64_t gfx9_fence_va;
1128 uint32_t gfx9_fence_idx;
1129 uint64_t gfx9_eop_bug_va;
1130
1131 /**
1132 * Whether a query pool has been resetted and we have to flush caches.
1133 */
1134 bool pending_reset_query;
1135 };
1136
1137 struct radv_image;
1138
1139 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1140
1141 void si_emit_graphics(struct radv_physical_device *physical_device,
1142 struct radeon_cmdbuf *cs);
1143 void si_emit_compute(struct radv_physical_device *physical_device,
1144 struct radeon_cmdbuf *cs);
1145
1146 void cik_create_gfx_config(struct radv_device *device);
1147
1148 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1149 int count, const VkViewport *viewports);
1150 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1151 int count, const VkRect2D *scissors,
1152 const VkViewport *viewports, bool can_use_guardband);
1153 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1154 bool instanced_draw, bool indirect_draw,
1155 uint32_t draw_vertex_count);
1156 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1157 enum chip_class chip_class,
1158 bool is_mec,
1159 unsigned event, unsigned event_flags,
1160 unsigned data_sel,
1161 uint64_t va,
1162 uint32_t new_fence,
1163 uint64_t gfx9_eop_bug_va);
1164
1165 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1166 uint32_t ref, uint32_t mask);
1167 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1168 enum chip_class chip_class,
1169 uint32_t *fence_ptr, uint64_t va,
1170 bool is_mec,
1171 enum radv_cmd_flush_bits flush_bits,
1172 uint64_t gfx9_eop_bug_va);
1173 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1174 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1175 bool inverted, uint64_t va);
1176 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1177 uint64_t src_va, uint64_t dest_va,
1178 uint64_t size);
1179 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1180 unsigned size);
1181 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1182 uint64_t size, unsigned value);
1183 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1184
1185 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1186 bool
1187 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1188 unsigned size,
1189 unsigned alignment,
1190 unsigned *out_offset,
1191 void **ptr);
1192 void
1193 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1194 const struct radv_subpass *subpass);
1195 bool
1196 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1197 unsigned size, unsigned alignmnet,
1198 const void *data, unsigned *out_offset);
1199
1200 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1201 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1202 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1203 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1204 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1205 unsigned radv_cayman_get_maxdist(int log_samples);
1206 void radv_device_init_msaa(struct radv_device *device);
1207
1208 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1209 struct radv_image *image,
1210 VkClearDepthStencilValue ds_clear_value,
1211 VkImageAspectFlags aspects);
1212
1213 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1214 struct radv_image *image,
1215 int cb_idx,
1216 uint32_t color_values[2]);
1217
1218 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1219 struct radv_image *image, bool value);
1220
1221 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1222 struct radv_image *image, bool value);
1223
1224 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1225 struct radeon_winsys_bo *bo,
1226 uint64_t offset, uint64_t size, uint32_t value);
1227 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1228 bool radv_get_memory_fd(struct radv_device *device,
1229 struct radv_device_memory *memory,
1230 int *pFD);
1231
1232 static inline void
1233 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1234 unsigned sh_offset, unsigned pointer_count,
1235 bool use_32bit_pointers)
1236 {
1237 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1238 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1239 }
1240
1241 static inline void
1242 radv_emit_shader_pointer_body(struct radv_device *device,
1243 struct radeon_cmdbuf *cs,
1244 uint64_t va, bool use_32bit_pointers)
1245 {
1246 radeon_emit(cs, va);
1247
1248 if (use_32bit_pointers) {
1249 assert(va == 0 ||
1250 (va >> 32) == device->physical_device->rad_info.address32_hi);
1251 } else {
1252 radeon_emit(cs, va >> 32);
1253 }
1254 }
1255
1256 static inline void
1257 radv_emit_shader_pointer(struct radv_device *device,
1258 struct radeon_cmdbuf *cs,
1259 uint32_t sh_offset, uint64_t va, bool global)
1260 {
1261 bool use_32bit_pointers = !global;
1262
1263 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1264 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1265 }
1266
1267 static inline struct radv_descriptor_state *
1268 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1269 VkPipelineBindPoint bind_point)
1270 {
1271 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1272 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1273 return &cmd_buffer->descriptors[bind_point];
1274 }
1275
1276 /*
1277 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1278 *
1279 * Limitations: Can't call normal dispatch functions without binding or rebinding
1280 * the compute pipeline.
1281 */
1282 void radv_unaligned_dispatch(
1283 struct radv_cmd_buffer *cmd_buffer,
1284 uint32_t x,
1285 uint32_t y,
1286 uint32_t z);
1287
1288 struct radv_event {
1289 struct radeon_winsys_bo *bo;
1290 uint64_t *map;
1291 };
1292
1293 struct radv_shader_module;
1294
1295 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1296 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1297 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1298 void
1299 radv_hash_shaders(unsigned char *hash,
1300 const VkPipelineShaderStageCreateInfo **stages,
1301 const struct radv_pipeline_layout *layout,
1302 const struct radv_pipeline_key *key,
1303 uint32_t flags);
1304
1305 static inline gl_shader_stage
1306 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1307 {
1308 assert(__builtin_popcount(vk_stage) == 1);
1309 return ffs(vk_stage) - 1;
1310 }
1311
1312 static inline VkShaderStageFlagBits
1313 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1314 {
1315 return (1 << mesa_stage);
1316 }
1317
1318 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1319
1320 #define radv_foreach_stage(stage, stage_bits) \
1321 for (gl_shader_stage stage, \
1322 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1323 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1324 __tmp &= ~(1 << (stage)))
1325
1326 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1327 unsigned radv_format_meta_fs_key(VkFormat format);
1328
1329 struct radv_multisample_state {
1330 uint32_t db_eqaa;
1331 uint32_t pa_sc_line_cntl;
1332 uint32_t pa_sc_mode_cntl_0;
1333 uint32_t pa_sc_mode_cntl_1;
1334 uint32_t pa_sc_aa_config;
1335 uint32_t pa_sc_aa_mask[2];
1336 unsigned num_samples;
1337 };
1338
1339 struct radv_prim_vertex_count {
1340 uint8_t min;
1341 uint8_t incr;
1342 };
1343
1344 struct radv_vertex_elements_info {
1345 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1346 };
1347
1348 struct radv_ia_multi_vgt_param_helpers {
1349 uint32_t base;
1350 bool partial_es_wave;
1351 uint8_t primgroup_size;
1352 bool wd_switch_on_eop;
1353 bool ia_switch_on_eoi;
1354 bool partial_vs_wave;
1355 };
1356
1357 #define SI_GS_PER_ES 128
1358
1359 struct radv_pipeline {
1360 struct radv_device * device;
1361 struct radv_dynamic_state dynamic_state;
1362
1363 struct radv_pipeline_layout * layout;
1364
1365 bool need_indirect_descriptor_sets;
1366 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1367 struct radv_shader_variant *gs_copy_shader;
1368 VkShaderStageFlags active_stages;
1369
1370 struct radeon_cmdbuf cs;
1371 uint32_t ctx_cs_hash;
1372 struct radeon_cmdbuf ctx_cs;
1373
1374 struct radv_vertex_elements_info vertex_elements;
1375
1376 uint32_t binding_stride[MAX_VBS];
1377 uint8_t num_vertex_bindings;
1378
1379 uint32_t user_data_0[MESA_SHADER_STAGES];
1380 union {
1381 struct {
1382 struct radv_multisample_state ms;
1383 uint32_t spi_baryc_cntl;
1384 bool prim_restart_enable;
1385 unsigned esgs_ring_size;
1386 unsigned gsvs_ring_size;
1387 uint32_t vtx_base_sgpr;
1388 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1389 uint8_t vtx_emit_num;
1390 struct radv_prim_vertex_count prim_vertex_count;
1391 bool can_use_guardband;
1392 uint32_t needed_dynamic_state;
1393 bool disable_out_of_order_rast_for_occlusion;
1394
1395 /* Used for rbplus */
1396 uint32_t col_format;
1397 uint32_t cb_target_mask;
1398 } graphics;
1399 };
1400
1401 unsigned max_waves;
1402 unsigned scratch_bytes_per_wave;
1403
1404 /* Not NULL if graphics pipeline uses streamout. */
1405 struct radv_shader_variant *streamout_shader;
1406 };
1407
1408 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1409 {
1410 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1411 }
1412
1413 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1414 {
1415 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1416 }
1417
1418 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1419 gl_shader_stage stage,
1420 int idx);
1421
1422 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1423 gl_shader_stage stage);
1424
1425 struct radv_graphics_pipeline_create_info {
1426 bool use_rectlist;
1427 bool db_depth_clear;
1428 bool db_stencil_clear;
1429 bool db_depth_disable_expclear;
1430 bool db_stencil_disable_expclear;
1431 bool db_flush_depth_inplace;
1432 bool db_flush_stencil_inplace;
1433 bool db_resummarize;
1434 uint32_t custom_blend_mode;
1435 };
1436
1437 VkResult
1438 radv_graphics_pipeline_create(VkDevice device,
1439 VkPipelineCache cache,
1440 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1441 const struct radv_graphics_pipeline_create_info *extra,
1442 const VkAllocationCallbacks *alloc,
1443 VkPipeline *pPipeline);
1444
1445 struct vk_format_description;
1446 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1447 int first_non_void);
1448 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1449 int first_non_void);
1450 uint32_t radv_translate_colorformat(VkFormat format);
1451 uint32_t radv_translate_color_numformat(VkFormat format,
1452 const struct vk_format_description *desc,
1453 int first_non_void);
1454 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1455 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1456 uint32_t radv_translate_dbformat(VkFormat format);
1457 uint32_t radv_translate_tex_dataformat(VkFormat format,
1458 const struct vk_format_description *desc,
1459 int first_non_void);
1460 uint32_t radv_translate_tex_numformat(VkFormat format,
1461 const struct vk_format_description *desc,
1462 int first_non_void);
1463 bool radv_format_pack_clear_color(VkFormat format,
1464 uint32_t clear_vals[2],
1465 VkClearColorValue *value);
1466 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1467 bool radv_dcc_formats_compatible(VkFormat format1,
1468 VkFormat format2);
1469 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1470
1471 struct radv_fmask_info {
1472 uint64_t offset;
1473 uint64_t size;
1474 unsigned alignment;
1475 unsigned pitch_in_pixels;
1476 unsigned bank_height;
1477 unsigned slice_tile_max;
1478 unsigned tile_mode_index;
1479 unsigned tile_swizzle;
1480 };
1481
1482 struct radv_cmask_info {
1483 uint64_t offset;
1484 uint64_t size;
1485 unsigned alignment;
1486 unsigned slice_tile_max;
1487 };
1488
1489 struct radv_image {
1490 VkImageType type;
1491 /* The original VkFormat provided by the client. This may not match any
1492 * of the actual surface formats.
1493 */
1494 VkFormat vk_format;
1495 VkImageAspectFlags aspects;
1496 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1497 struct ac_surf_info info;
1498 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1499 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1500
1501 VkDeviceSize size;
1502 uint32_t alignment;
1503
1504 unsigned queue_family_mask;
1505 bool exclusive;
1506 bool shareable;
1507
1508 /* Set when bound */
1509 struct radeon_winsys_bo *bo;
1510 VkDeviceSize offset;
1511 uint64_t dcc_offset;
1512 uint64_t htile_offset;
1513 bool tc_compatible_htile;
1514 struct radeon_surf surface;
1515
1516 struct radv_fmask_info fmask;
1517 struct radv_cmask_info cmask;
1518 uint64_t clear_value_offset;
1519 uint64_t fce_pred_offset;
1520 uint64_t dcc_pred_offset;
1521
1522 /*
1523 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1524 * stored at this offset is UINT_MAX, the driver will emit
1525 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1526 * SET_CONTEXT_REG packet.
1527 */
1528 uint64_t tc_compat_zrange_offset;
1529
1530 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1531 VkDeviceMemory owned_memory;
1532 };
1533
1534 /* Whether the image has a htile that is known consistent with the contents of
1535 * the image. */
1536 bool radv_layout_has_htile(const struct radv_image *image,
1537 VkImageLayout layout,
1538 unsigned queue_mask);
1539
1540 /* Whether the image has a htile that is known consistent with the contents of
1541 * the image and is allowed to be in compressed form.
1542 *
1543 * If this is false reads that don't use the htile should be able to return
1544 * correct results.
1545 */
1546 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1547 VkImageLayout layout,
1548 unsigned queue_mask);
1549
1550 bool radv_layout_can_fast_clear(const struct radv_image *image,
1551 VkImageLayout layout,
1552 unsigned queue_mask);
1553
1554 bool radv_layout_dcc_compressed(const struct radv_image *image,
1555 VkImageLayout layout,
1556 unsigned queue_mask);
1557
1558 /**
1559 * Return whether the image has CMASK metadata for color surfaces.
1560 */
1561 static inline bool
1562 radv_image_has_cmask(const struct radv_image *image)
1563 {
1564 return image->cmask.size;
1565 }
1566
1567 /**
1568 * Return whether the image has FMASK metadata for color surfaces.
1569 */
1570 static inline bool
1571 radv_image_has_fmask(const struct radv_image *image)
1572 {
1573 return image->fmask.size;
1574 }
1575
1576 /**
1577 * Return whether the image has DCC metadata for color surfaces.
1578 */
1579 static inline bool
1580 radv_image_has_dcc(const struct radv_image *image)
1581 {
1582 return image->surface.dcc_size;
1583 }
1584
1585 /**
1586 * Return whether DCC metadata is enabled for a level.
1587 */
1588 static inline bool
1589 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1590 {
1591 return radv_image_has_dcc(image) &&
1592 level < image->surface.num_dcc_levels;
1593 }
1594
1595 /**
1596 * Return whether the image has CB metadata.
1597 */
1598 static inline bool
1599 radv_image_has_CB_metadata(const struct radv_image *image)
1600 {
1601 return radv_image_has_cmask(image) ||
1602 radv_image_has_fmask(image) ||
1603 radv_image_has_dcc(image);
1604 }
1605
1606 /**
1607 * Return whether the image has HTILE metadata for depth surfaces.
1608 */
1609 static inline bool
1610 radv_image_has_htile(const struct radv_image *image)
1611 {
1612 return image->surface.htile_size;
1613 }
1614
1615 /**
1616 * Return whether HTILE metadata is enabled for a level.
1617 */
1618 static inline bool
1619 radv_htile_enabled(const struct radv_image *image, unsigned level)
1620 {
1621 return radv_image_has_htile(image) && level == 0;
1622 }
1623
1624 /**
1625 * Return whether the image is TC-compatible HTILE.
1626 */
1627 static inline bool
1628 radv_image_is_tc_compat_htile(const struct radv_image *image)
1629 {
1630 return radv_image_has_htile(image) && image->tc_compatible_htile;
1631 }
1632
1633 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1634
1635 static inline uint32_t
1636 radv_get_layerCount(const struct radv_image *image,
1637 const VkImageSubresourceRange *range)
1638 {
1639 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1640 image->info.array_size - range->baseArrayLayer : range->layerCount;
1641 }
1642
1643 static inline uint32_t
1644 radv_get_levelCount(const struct radv_image *image,
1645 const VkImageSubresourceRange *range)
1646 {
1647 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1648 image->info.levels - range->baseMipLevel : range->levelCount;
1649 }
1650
1651 struct radeon_bo_metadata;
1652 void
1653 radv_init_metadata(struct radv_device *device,
1654 struct radv_image *image,
1655 struct radeon_bo_metadata *metadata);
1656
1657 struct radv_image_view {
1658 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1659 struct radeon_winsys_bo *bo;
1660
1661 VkImageViewType type;
1662 VkImageAspectFlags aspect_mask;
1663 VkFormat vk_format;
1664 uint32_t base_layer;
1665 uint32_t layer_count;
1666 uint32_t base_mip;
1667 uint32_t level_count;
1668 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1669
1670 uint32_t descriptor[16];
1671
1672 /* Descriptor for use as a storage image as opposed to a sampled image.
1673 * This has a few differences for cube maps (e.g. type).
1674 */
1675 uint32_t storage_descriptor[16];
1676 };
1677
1678 struct radv_image_create_info {
1679 const VkImageCreateInfo *vk_info;
1680 bool scanout;
1681 bool no_metadata_planes;
1682 };
1683
1684 VkResult radv_image_create(VkDevice _device,
1685 const struct radv_image_create_info *info,
1686 const VkAllocationCallbacks* alloc,
1687 VkImage *pImage);
1688
1689 VkResult
1690 radv_image_from_gralloc(VkDevice device_h,
1691 const VkImageCreateInfo *base_info,
1692 const VkNativeBufferANDROID *gralloc_info,
1693 const VkAllocationCallbacks *alloc,
1694 VkImage *out_image_h);
1695
1696 void radv_image_view_init(struct radv_image_view *view,
1697 struct radv_device *device,
1698 const VkImageViewCreateInfo* pCreateInfo);
1699
1700 struct radv_buffer_view {
1701 struct radeon_winsys_bo *bo;
1702 VkFormat vk_format;
1703 uint64_t range; /**< VkBufferViewCreateInfo::range */
1704 uint32_t state[4];
1705 };
1706 void radv_buffer_view_init(struct radv_buffer_view *view,
1707 struct radv_device *device,
1708 const VkBufferViewCreateInfo* pCreateInfo);
1709
1710 static inline struct VkExtent3D
1711 radv_sanitize_image_extent(const VkImageType imageType,
1712 const struct VkExtent3D imageExtent)
1713 {
1714 switch (imageType) {
1715 case VK_IMAGE_TYPE_1D:
1716 return (VkExtent3D) { imageExtent.width, 1, 1 };
1717 case VK_IMAGE_TYPE_2D:
1718 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1719 case VK_IMAGE_TYPE_3D:
1720 return imageExtent;
1721 default:
1722 unreachable("invalid image type");
1723 }
1724 }
1725
1726 static inline struct VkOffset3D
1727 radv_sanitize_image_offset(const VkImageType imageType,
1728 const struct VkOffset3D imageOffset)
1729 {
1730 switch (imageType) {
1731 case VK_IMAGE_TYPE_1D:
1732 return (VkOffset3D) { imageOffset.x, 0, 0 };
1733 case VK_IMAGE_TYPE_2D:
1734 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1735 case VK_IMAGE_TYPE_3D:
1736 return imageOffset;
1737 default:
1738 unreachable("invalid image type");
1739 }
1740 }
1741
1742 static inline bool
1743 radv_image_extent_compare(const struct radv_image *image,
1744 const VkExtent3D *extent)
1745 {
1746 if (extent->width != image->info.width ||
1747 extent->height != image->info.height ||
1748 extent->depth != image->info.depth)
1749 return false;
1750 return true;
1751 }
1752
1753 struct radv_sampler {
1754 uint32_t state[4];
1755 };
1756
1757 struct radv_color_buffer_info {
1758 uint64_t cb_color_base;
1759 uint64_t cb_color_cmask;
1760 uint64_t cb_color_fmask;
1761 uint64_t cb_dcc_base;
1762 uint32_t cb_color_pitch;
1763 uint32_t cb_color_slice;
1764 uint32_t cb_color_view;
1765 uint32_t cb_color_info;
1766 uint32_t cb_color_attrib;
1767 uint32_t cb_color_attrib2;
1768 uint32_t cb_dcc_control;
1769 uint32_t cb_color_cmask_slice;
1770 uint32_t cb_color_fmask_slice;
1771 };
1772
1773 struct radv_ds_buffer_info {
1774 uint64_t db_z_read_base;
1775 uint64_t db_stencil_read_base;
1776 uint64_t db_z_write_base;
1777 uint64_t db_stencil_write_base;
1778 uint64_t db_htile_data_base;
1779 uint32_t db_depth_info;
1780 uint32_t db_z_info;
1781 uint32_t db_stencil_info;
1782 uint32_t db_depth_view;
1783 uint32_t db_depth_size;
1784 uint32_t db_depth_slice;
1785 uint32_t db_htile_surface;
1786 uint32_t pa_su_poly_offset_db_fmt_cntl;
1787 uint32_t db_z_info2;
1788 uint32_t db_stencil_info2;
1789 float offset_scale;
1790 };
1791
1792 struct radv_attachment_info {
1793 union {
1794 struct radv_color_buffer_info cb;
1795 struct radv_ds_buffer_info ds;
1796 };
1797 struct radv_image_view *attachment;
1798 };
1799
1800 struct radv_framebuffer {
1801 uint32_t width;
1802 uint32_t height;
1803 uint32_t layers;
1804
1805 uint32_t attachment_count;
1806 struct radv_attachment_info attachments[0];
1807 };
1808
1809 struct radv_subpass_barrier {
1810 VkPipelineStageFlags src_stage_mask;
1811 VkAccessFlags src_access_mask;
1812 VkAccessFlags dst_access_mask;
1813 };
1814
1815 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1816 const struct radv_subpass_barrier *barrier);
1817
1818 struct radv_subpass_attachment {
1819 uint32_t attachment;
1820 VkImageLayout layout;
1821 };
1822
1823 struct radv_subpass {
1824 uint32_t attachment_count;
1825 struct radv_subpass_attachment * attachments;
1826
1827 uint32_t input_count;
1828 uint32_t color_count;
1829 struct radv_subpass_attachment * input_attachments;
1830 struct radv_subpass_attachment * color_attachments;
1831 struct radv_subpass_attachment * resolve_attachments;
1832 struct radv_subpass_attachment * depth_stencil_attachment;
1833
1834 /** Subpass has at least one resolve attachment */
1835 bool has_resolve;
1836
1837 /** Subpass has at least one color attachment */
1838 bool has_color_att;
1839
1840 struct radv_subpass_barrier start_barrier;
1841
1842 uint32_t view_mask;
1843 VkSampleCountFlagBits max_sample_count;
1844 };
1845
1846 struct radv_render_pass_attachment {
1847 VkFormat format;
1848 uint32_t samples;
1849 VkAttachmentLoadOp load_op;
1850 VkAttachmentLoadOp stencil_load_op;
1851 VkImageLayout initial_layout;
1852 VkImageLayout final_layout;
1853
1854 /* The subpass id in which the attachment will be used last. */
1855 uint32_t last_subpass_idx;
1856 };
1857
1858 struct radv_render_pass {
1859 uint32_t attachment_count;
1860 uint32_t subpass_count;
1861 struct radv_subpass_attachment * subpass_attachments;
1862 struct radv_render_pass_attachment * attachments;
1863 struct radv_subpass_barrier end_barrier;
1864 struct radv_subpass subpasses[0];
1865 };
1866
1867 VkResult radv_device_init_meta(struct radv_device *device);
1868 void radv_device_finish_meta(struct radv_device *device);
1869
1870 struct radv_query_pool {
1871 struct radeon_winsys_bo *bo;
1872 uint32_t stride;
1873 uint32_t availability_offset;
1874 uint64_t size;
1875 char *ptr;
1876 VkQueryType type;
1877 uint32_t pipeline_stats_mask;
1878 };
1879
1880 struct radv_semaphore {
1881 /* use a winsys sem for non-exportable */
1882 struct radeon_winsys_sem *sem;
1883 uint32_t syncobj;
1884 uint32_t temp_syncobj;
1885 };
1886
1887 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1888 VkPipelineBindPoint bind_point,
1889 struct radv_descriptor_set *set,
1890 unsigned idx);
1891
1892 void
1893 radv_update_descriptor_sets(struct radv_device *device,
1894 struct radv_cmd_buffer *cmd_buffer,
1895 VkDescriptorSet overrideSet,
1896 uint32_t descriptorWriteCount,
1897 const VkWriteDescriptorSet *pDescriptorWrites,
1898 uint32_t descriptorCopyCount,
1899 const VkCopyDescriptorSet *pDescriptorCopies);
1900
1901 void
1902 radv_update_descriptor_set_with_template(struct radv_device *device,
1903 struct radv_cmd_buffer *cmd_buffer,
1904 struct radv_descriptor_set *set,
1905 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1906 const void *pData);
1907
1908 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1909 VkPipelineBindPoint pipelineBindPoint,
1910 VkPipelineLayout _layout,
1911 uint32_t set,
1912 uint32_t descriptorWriteCount,
1913 const VkWriteDescriptorSet *pDescriptorWrites);
1914
1915 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1916 struct radv_image *image, uint32_t value);
1917
1918 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
1919 struct radv_image *image);
1920
1921 struct radv_fence {
1922 struct radeon_winsys_fence *fence;
1923 struct wsi_fence *fence_wsi;
1924 bool submitted;
1925 bool signalled;
1926
1927 uint32_t syncobj;
1928 uint32_t temp_syncobj;
1929 };
1930
1931 /* radv_nir_to_llvm.c */
1932 struct radv_shader_variant_info;
1933 struct radv_nir_compiler_options;
1934
1935 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1936 struct nir_shader *geom_shader,
1937 struct ac_shader_binary *binary,
1938 struct ac_shader_config *config,
1939 struct radv_shader_variant_info *shader_info,
1940 const struct radv_nir_compiler_options *option);
1941
1942 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1943 struct ac_shader_binary *binary,
1944 struct ac_shader_config *config,
1945 struct radv_shader_variant_info *shader_info,
1946 struct nir_shader *const *nir,
1947 int nir_count,
1948 const struct radv_nir_compiler_options *options);
1949
1950 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
1951 const struct nir_shader *nir);
1952
1953 /* radv_shader_info.h */
1954 struct radv_shader_info;
1955
1956 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1957 const struct radv_nir_compiler_options *options,
1958 struct radv_shader_info *info);
1959
1960 void radv_nir_shader_info_init(struct radv_shader_info *info);
1961
1962 struct radeon_winsys_sem;
1963
1964 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1965 \
1966 static inline struct __radv_type * \
1967 __radv_type ## _from_handle(__VkType _handle) \
1968 { \
1969 return (struct __radv_type *) _handle; \
1970 } \
1971 \
1972 static inline __VkType \
1973 __radv_type ## _to_handle(struct __radv_type *_obj) \
1974 { \
1975 return (__VkType) _obj; \
1976 }
1977
1978 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1979 \
1980 static inline struct __radv_type * \
1981 __radv_type ## _from_handle(__VkType _handle) \
1982 { \
1983 return (struct __radv_type *)(uintptr_t) _handle; \
1984 } \
1985 \
1986 static inline __VkType \
1987 __radv_type ## _to_handle(struct __radv_type *_obj) \
1988 { \
1989 return (__VkType)(uintptr_t) _obj; \
1990 }
1991
1992 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1993 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1994
1995 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1996 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1997 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1998 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1999 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2000
2001 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2002 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2003 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2004 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2005 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2006 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2007 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2008 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2009 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2010 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2011 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2012 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2013 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2014 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2015 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2016 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2017 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2018 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2019 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2020 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2021 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2022
2023 #endif /* RADV_PRIVATE_H */