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3c99bc679a249600afffdbcf16beb705c7a2974a
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73
74 #define MAX_VBS 32
75 #define MAX_VERTEX_ATTRIBS 32
76 #define MAX_RTS 8
77 #define MAX_VIEWPORTS 16
78 #define MAX_SCISSORS 16
79 #define MAX_PUSH_CONSTANTS_SIZE 128
80 #define MAX_DYNAMIC_BUFFERS 16
81 #define MAX_IMAGES 8
82 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
83 #define NUM_META_FS_KEYS 11
84
85 #define NUM_DEPTH_CLEAR_PIPELINES 3
86
87 #define radv_noreturn __attribute__((__noreturn__))
88 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
89
90 static inline uint32_t
91 align_u32(uint32_t v, uint32_t a)
92 {
93 assert(a != 0 && a == (a & -a));
94 return (v + a - 1) & ~(a - 1);
95 }
96
97 static inline uint32_t
98 align_u32_npot(uint32_t v, uint32_t a)
99 {
100 return (v + a - 1) / a * a;
101 }
102
103 static inline uint64_t
104 align_u64(uint64_t v, uint64_t a)
105 {
106 assert(a != 0 && a == (a & -a));
107 return (v + a - 1) & ~(a - 1);
108 }
109
110 static inline int32_t
111 align_i32(int32_t v, int32_t a)
112 {
113 assert(a != 0 && a == (a & -a));
114 return (v + a - 1) & ~(a - 1);
115 }
116
117 /** Alignment must be a power of 2. */
118 static inline bool
119 radv_is_aligned(uintmax_t n, uintmax_t a)
120 {
121 assert(a == (a & -a));
122 return (n & (a - 1)) == 0;
123 }
124
125 static inline uint32_t
126 round_up_u32(uint32_t v, uint32_t a)
127 {
128 return (v + a - 1) / a;
129 }
130
131 static inline uint64_t
132 round_up_u64(uint64_t v, uint64_t a)
133 {
134 return (v + a - 1) / a;
135 }
136
137 static inline uint32_t
138 radv_minify(uint32_t n, uint32_t levels)
139 {
140 if (unlikely(n == 0))
141 return 0;
142 else
143 return MAX2(n >> levels, 1);
144 }
145 static inline float
146 radv_clamp_f(float f, float min, float max)
147 {
148 assert(min < max);
149
150 if (f > max)
151 return max;
152 else if (f < min)
153 return min;
154 else
155 return f;
156 }
157
158 static inline bool
159 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
160 {
161 if (*inout_mask & clear_mask) {
162 *inout_mask &= ~clear_mask;
163 return true;
164 } else {
165 return false;
166 }
167 }
168
169 #define for_each_bit(b, dword) \
170 for (uint32_t __dword = (dword); \
171 (b) = __builtin_ffs(__dword) - 1, __dword; \
172 __dword &= ~(1 << (b)))
173
174 #define typed_memcpy(dest, src, count) ({ \
175 static_assert(sizeof(*src) == sizeof(*dest), ""); \
176 memcpy((dest), (src), (count) * sizeof(*(src))); \
177 })
178
179 #define zero(x) (memset(&(x), 0, sizeof(x)))
180
181 /* Define no kernel as 1, since that's an illegal offset for a kernel */
182 #define NO_KERNEL 1
183
184 struct radv_common {
185 VkStructureType sType;
186 const void* pNext;
187 };
188
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
192 */
193
194 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
195
196 #ifdef DEBUG
197 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
198 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
199 #else
200 #define vk_error(error) error
201 #define vk_errorf(error, format, ...) error
202 #endif
203
204 void __radv_finishme(const char *file, int line, const char *format, ...)
205 radv_printflike(3, 4);
206 void radv_loge(const char *format, ...) radv_printflike(1, 2);
207 void radv_loge_v(const char *format, va_list va);
208
209 /**
210 * Print a FINISHME message, including its source location.
211 */
212 #define radv_finishme(format, ...) \
213 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
214
215 /* A non-fatal assert. Useful for debugging. */
216 #ifdef DEBUG
217 #define radv_assert(x) ({ \
218 if (unlikely(!(x))) \
219 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
220 })
221 #else
222 #define radv_assert(x)
223 #endif
224
225 void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
226 void radv_abortfv(const char *format, va_list va) radv_noreturn;
227
228 #define stub_return(v) \
229 do { \
230 radv_finishme("stub %s", __func__); \
231 return (v); \
232 } while (0)
233
234 #define stub() \
235 do { \
236 radv_finishme("stub %s", __func__); \
237 return; \
238 } while (0)
239
240 void *radv_resolve_entrypoint(uint32_t index);
241 void *radv_lookup_entrypoint(const char *name);
242
243 extern struct radv_dispatch_table dtable;
244
245 struct radv_wsi_interaface;
246
247 #define VK_ICD_WSI_PLATFORM_MAX 5
248
249 struct radv_physical_device {
250 VK_LOADER_DATA _loader_data;
251
252 struct radv_instance * instance;
253
254 struct radeon_winsys *ws;
255 struct radeon_info rad_info;
256 uint32_t chipset_id;
257 char path[20];
258 const char * name;
259 uint64_t aperture_size;
260 int cmd_parser_version;
261 uint32_t pci_vendor_id;
262 uint32_t pci_device_id;
263
264 struct radv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
265 };
266
267 struct radv_instance {
268 VK_LOADER_DATA _loader_data;
269
270 VkAllocationCallbacks alloc;
271
272 uint32_t apiVersion;
273 int physicalDeviceCount;
274 struct radv_physical_device physicalDevice;
275 };
276
277 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
278 void radv_finish_wsi(struct radv_physical_device *physical_device);
279
280 struct cache_entry;
281
282 struct radv_pipeline_cache {
283 struct radv_device * device;
284 pthread_mutex_t mutex;
285
286 uint32_t total_size;
287 uint32_t table_size;
288 uint32_t kernel_count;
289 struct cache_entry ** hash_table;
290 bool modified;
291
292 VkAllocationCallbacks alloc;
293 };
294
295 void
296 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
297 struct radv_device *device);
298 void
299 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
300 void
301 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
302 const void *data, size_t size);
303
304 struct radv_shader_variant *
305 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
306 struct radv_pipeline_cache *cache,
307 const unsigned char *sha1);
308
309 struct radv_shader_variant *
310 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
311 const unsigned char *sha1,
312 struct radv_shader_variant *variant,
313 const void *code, unsigned code_size);
314
315 void radv_shader_variant_destroy(struct radv_device *device,
316 struct radv_shader_variant *variant);
317
318 struct radv_meta_state {
319 VkAllocationCallbacks alloc;
320
321 struct radv_pipeline_cache cache;
322
323 /**
324 * Use array element `i` for images with `2^i` samples.
325 */
326 struct {
327 VkRenderPass render_pass[NUM_META_FS_KEYS];
328 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
329
330 VkRenderPass depth_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
331 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
332 VkRenderPass stencil_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
333 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
334 VkRenderPass depthstencil_rp[NUM_DEPTH_CLEAR_PIPELINES];
335 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
336 } clear[1 + MAX_SAMPLES_LOG2];
337
338 struct {
339 VkRenderPass render_pass[NUM_META_FS_KEYS];
340
341 /** Pipeline that blits from a 1D image. */
342 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
343
344 /** Pipeline that blits from a 2D image. */
345 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
346
347 /** Pipeline that blits from a 3D image. */
348 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
349
350 VkRenderPass depth_only_rp;
351 VkPipeline depth_only_1d_pipeline;
352 VkPipeline depth_only_2d_pipeline;
353 VkPipeline depth_only_3d_pipeline;
354
355 VkRenderPass stencil_only_rp;
356 VkPipeline stencil_only_1d_pipeline;
357 VkPipeline stencil_only_2d_pipeline;
358 VkPipeline stencil_only_3d_pipeline;
359 VkPipelineLayout pipeline_layout;
360 VkDescriptorSetLayout ds_layout;
361 } blit;
362
363 struct {
364 VkRenderPass render_passes[NUM_META_FS_KEYS];
365
366 VkPipelineLayout p_layouts[2];
367 VkDescriptorSetLayout ds_layouts[2];
368 VkPipeline pipelines[2][NUM_META_FS_KEYS];
369
370 VkRenderPass depth_only_rp;
371 VkPipeline depth_only_pipeline[2];
372
373 VkRenderPass stencil_only_rp;
374 VkPipeline stencil_only_pipeline[2];
375 } blit2d;
376
377 struct {
378 VkPipelineLayout img_p_layout;
379 VkDescriptorSetLayout img_ds_layout;
380 VkPipeline pipeline;
381 } itob;
382 struct {
383 VkRenderPass render_pass;
384 VkPipelineLayout img_p_layout;
385 VkDescriptorSetLayout img_ds_layout;
386 VkPipeline pipeline;
387 } btoi;
388
389 struct {
390 VkPipeline pipeline;
391 VkRenderPass pass;
392 } resolve;
393
394 struct {
395 VkDescriptorSetLayout ds_layout;
396 VkPipelineLayout p_layout;
397 struct {
398 VkPipeline pipeline;
399 VkPipeline i_pipeline;
400 } rc[MAX_SAMPLES_LOG2];
401 } resolve_compute;
402
403 struct {
404 VkPipeline decompress_pipeline;
405 VkPipeline resummarize_pipeline;
406 VkRenderPass pass;
407 } depth_decomp;
408
409 struct {
410 VkPipeline cmask_eliminate_pipeline;
411 VkPipeline fmask_decompress_pipeline;
412 VkRenderPass pass;
413 } fast_clear_flush;
414
415 struct {
416 VkPipelineLayout fill_p_layout;
417 VkPipelineLayout copy_p_layout;
418 VkDescriptorSetLayout fill_ds_layout;
419 VkDescriptorSetLayout copy_ds_layout;
420 VkPipeline fill_pipeline;
421 VkPipeline copy_pipeline;
422 } buffer;
423 };
424
425 struct radv_queue {
426 VK_LOADER_DATA _loader_data;
427
428 struct radv_device * device;
429
430 struct radv_state_pool * pool;
431 };
432
433 struct radv_device {
434 VK_LOADER_DATA _loader_data;
435
436 VkAllocationCallbacks alloc;
437
438 struct radv_instance * instance;
439 struct radeon_winsys *ws;
440 struct radeon_winsys_ctx *hw_ctx;
441
442 struct radv_meta_state meta_state;
443 struct radv_queue queue;
444 struct radeon_winsys_cs *empty_cs;
445
446 bool allow_fast_clears;
447 bool allow_dcc;
448
449 /* MSAA sample locations.
450 * The first index is the sample index.
451 * The second index is the coordinate: X, Y. */
452 float sample_locations_1x[1][2];
453 float sample_locations_2x[2][2];
454 float sample_locations_4x[4][2];
455 float sample_locations_8x[8][2];
456 float sample_locations_16x[16][2];
457 };
458
459 void radv_device_get_cache_uuid(void *uuid);
460
461 struct radv_device_memory {
462 struct radeon_winsys_bo *bo;
463 uint32_t type_index;
464 VkDeviceSize map_size;
465 void * map;
466 };
467
468
469 struct radv_descriptor_range {
470 uint64_t va;
471 uint32_t size;
472 };
473
474 struct radv_descriptor_set {
475 const struct radv_descriptor_set_layout *layout;
476 struct list_head descriptor_pool;
477 uint32_t size;
478
479 struct radv_buffer_view *buffer_views;
480 struct radeon_winsys_bo *bo;
481 uint64_t va;
482 uint32_t *mapped_ptr;
483 struct radv_descriptor_range *dynamic_descriptors;
484 struct radeon_winsys_bo *descriptors[0];
485 };
486
487 struct radv_descriptor_pool_free_node {
488 int next;
489 uint32_t offset;
490 uint32_t size;
491 };
492
493 struct radv_descriptor_pool {
494 struct list_head descriptor_sets;
495
496 struct radeon_winsys_bo *bo;
497 uint8_t *mapped_ptr;
498 uint64_t current_offset;
499 uint64_t size;
500
501 int free_list;
502 int full_list;
503 uint32_t max_sets;
504 struct radv_descriptor_pool_free_node free_nodes[];
505 };
506
507 struct radv_buffer {
508 struct radv_device * device;
509 VkDeviceSize size;
510
511 VkBufferUsageFlags usage;
512
513 /* Set when bound */
514 struct radeon_winsys_bo * bo;
515 VkDeviceSize offset;
516 };
517
518
519 enum radv_cmd_dirty_bits {
520 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
521 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
522 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
523 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
524 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
525 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
526 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
527 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
528 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
529 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
530 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
531 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
532 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
533 };
534 typedef uint32_t radv_cmd_dirty_mask_t;
535
536 enum radv_cmd_flush_bits {
537 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
538 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
539 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
540 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
541 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
542 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
543 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
544 /* Framebuffer caches */
545 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
546 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
547 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
548 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
549 /* Engine synchronization. */
550 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
551 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
552 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
553 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
554
555 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
556 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
557 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
558 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
559 };
560
561 struct radv_vertex_binding {
562 struct radv_buffer * buffer;
563 VkDeviceSize offset;
564 };
565
566 struct radv_dynamic_state {
567 struct {
568 uint32_t count;
569 VkViewport viewports[MAX_VIEWPORTS];
570 } viewport;
571
572 struct {
573 uint32_t count;
574 VkRect2D scissors[MAX_SCISSORS];
575 } scissor;
576
577 float line_width;
578
579 struct {
580 float bias;
581 float clamp;
582 float slope;
583 } depth_bias;
584
585 float blend_constants[4];
586
587 struct {
588 float min;
589 float max;
590 } depth_bounds;
591
592 struct {
593 uint32_t front;
594 uint32_t back;
595 } stencil_compare_mask;
596
597 struct {
598 uint32_t front;
599 uint32_t back;
600 } stencil_write_mask;
601
602 struct {
603 uint32_t front;
604 uint32_t back;
605 } stencil_reference;
606 };
607
608 extern const struct radv_dynamic_state default_dynamic_state;
609
610 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
611 const struct radv_dynamic_state *src,
612 uint32_t copy_mask);
613 /**
614 * Attachment state when recording a renderpass instance.
615 *
616 * The clear value is valid only if there exists a pending clear.
617 */
618 struct radv_attachment_state {
619 VkImageAspectFlags pending_clear_aspects;
620 VkClearValue clear_value;
621 VkImageLayout current_layout;
622 };
623
624 struct radv_cmd_state {
625 uint32_t vb_dirty;
626 bool vertex_descriptors_dirty;
627 radv_cmd_dirty_mask_t dirty;
628
629 struct radv_pipeline * pipeline;
630 struct radv_pipeline * emitted_pipeline;
631 struct radv_pipeline * compute_pipeline;
632 struct radv_pipeline * emitted_compute_pipeline;
633 struct radv_framebuffer * framebuffer;
634 struct radv_render_pass * pass;
635 const struct radv_subpass * subpass;
636 struct radv_dynamic_state dynamic;
637 struct radv_vertex_binding vertex_bindings[MAX_VBS];
638 struct radv_descriptor_set * descriptors[MAX_SETS];
639 struct radv_attachment_state * attachments;
640 VkRect2D render_area;
641 struct radv_buffer * index_buffer;
642 uint32_t index_type;
643 uint32_t index_offset;
644 uint32_t last_primitive_reset_index;
645 enum radv_cmd_flush_bits flush_bits;
646 unsigned active_occlusion_queries;
647 float offset_scale;
648 };
649 struct radv_cmd_pool {
650 VkAllocationCallbacks alloc;
651 struct list_head cmd_buffers;
652 };
653
654 struct radv_cmd_buffer_upload {
655 uint8_t *map;
656 unsigned offset;
657 uint64_t size;
658 struct radeon_winsys_bo *upload_bo;
659 struct list_head list;
660 };
661
662 struct radv_cmd_buffer {
663 VK_LOADER_DATA _loader_data;
664
665 struct radv_device * device;
666
667 struct radv_cmd_pool * pool;
668 struct list_head pool_link;
669
670 VkCommandBufferUsageFlags usage_flags;
671 VkCommandBufferLevel level;
672 struct radeon_winsys_cs *cs;
673 struct radv_cmd_state state;
674
675 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
676 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
677 VkShaderStageFlags push_constant_stages;
678
679 struct radv_cmd_buffer_upload upload;
680
681 bool record_fail;
682 };
683
684 struct radv_image;
685
686 void si_init_config(struct radv_physical_device *physical_device,
687 struct radv_cmd_buffer *cmd_buffer);
688 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
689 int count, const VkViewport *viewports);
690 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
691 int count, const VkRect2D *scissors);
692 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
693 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
694 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
695 uint64_t src_va, uint64_t dest_va,
696 uint64_t size);
697 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
698 uint64_t size, unsigned value);
699 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
700 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
701 struct radv_descriptor_set *set,
702 unsigned idx);
703 bool
704 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
705 unsigned size,
706 unsigned alignment,
707 unsigned *out_offset,
708 void **ptr);
709 void
710 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
711 const struct radv_subpass *subpass,
712 bool transitions);
713 bool
714 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
715 unsigned size, unsigned alignmnet,
716 const void *data, unsigned *out_offset);
717 void
718 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
719 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
720 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
721 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
722 unsigned radv_cayman_get_maxdist(int log_samples);
723 void radv_device_init_msaa(struct radv_device *device);
724 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
725 struct radv_image *image,
726 VkClearDepthStencilValue ds_clear_value,
727 VkImageAspectFlags aspects);
728 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
729 struct radv_image *image,
730 int idx,
731 uint32_t color_values[2]);
732 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
733 struct radeon_winsys_bo *bo,
734 uint64_t offset, uint64_t size, uint32_t value);
735
736 /*
737 * Takes x,y,z as exact numbers of invocations, instead of blocks.
738 *
739 * Limitations: Can't call normal dispatch functions without binding or rebinding
740 * the compute pipeline.
741 */
742 void radv_unaligned_dispatch(
743 struct radv_cmd_buffer *cmd_buffer,
744 uint32_t x,
745 uint32_t y,
746 uint32_t z);
747
748 struct radv_event {
749 struct radeon_winsys_bo *bo;
750 uint64_t *map;
751 };
752
753 struct nir_shader;
754
755 struct radv_shader_module {
756 struct nir_shader * nir;
757 unsigned char sha1[20];
758 uint32_t size;
759 char data[0];
760 };
761
762 union ac_shader_variant_key;
763
764 void
765 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
766 const char *entrypoint,
767 const VkSpecializationInfo *spec_info,
768 const struct radv_pipeline_layout *layout,
769 const union ac_shader_variant_key *key);
770
771 static inline gl_shader_stage
772 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
773 {
774 assert(__builtin_popcount(vk_stage) == 1);
775 return ffs(vk_stage) - 1;
776 }
777
778 static inline VkShaderStageFlagBits
779 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
780 {
781 return (1 << mesa_stage);
782 }
783
784 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
785
786 #define radv_foreach_stage(stage, stage_bits) \
787 for (gl_shader_stage stage, \
788 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
789 stage = __builtin_ffs(__tmp) - 1, __tmp; \
790 __tmp &= ~(1 << (stage)))
791
792 struct radv_shader_variant {
793 uint32_t ref_count;
794
795 struct radeon_winsys_bo *bo;
796 struct ac_shader_config config;
797 struct ac_shader_variant_info info;
798 unsigned rsrc1;
799 unsigned rsrc2;
800 };
801
802 struct radv_depth_stencil_state {
803 uint32_t db_depth_control;
804 uint32_t db_stencil_control;
805 uint32_t db_render_control;
806 uint32_t db_render_override2;
807 };
808
809 struct radv_blend_state {
810 uint32_t cb_color_control;
811 uint32_t cb_target_mask;
812 uint32_t sx_mrt0_blend_opt[8];
813 uint32_t cb_blend_control[8];
814
815 uint32_t spi_shader_col_format;
816 uint32_t cb_shader_mask;
817 uint32_t db_alpha_to_mask;
818 };
819
820 unsigned radv_format_meta_fs_key(VkFormat format);
821
822 struct radv_raster_state {
823 uint32_t pa_cl_clip_cntl;
824 uint32_t pa_cl_vs_out_cntl;
825 uint32_t spi_interp_control;
826 uint32_t pa_su_point_size;
827 uint32_t pa_su_point_minmax;
828 uint32_t pa_su_line_cntl;
829 uint32_t pa_su_vtx_cntl;
830 uint32_t pa_su_sc_mode_cntl;
831 };
832
833 struct radv_multisample_state {
834 uint32_t db_eqaa;
835 uint32_t pa_sc_line_cntl;
836 uint32_t pa_sc_mode_cntl_0;
837 uint32_t pa_sc_mode_cntl_1;
838 uint32_t pa_sc_aa_config;
839 uint32_t pa_sc_aa_mask[2];
840 unsigned num_samples;
841 };
842
843 struct radv_pipeline {
844 struct radv_device * device;
845 uint32_t dynamic_state_mask;
846 struct radv_dynamic_state dynamic_state;
847
848 struct radv_pipeline_layout * layout;
849
850 bool needs_data_cache;
851
852 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
853 VkShaderStageFlags active_stages;
854
855 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
856 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
857 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
858 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
859 uint32_t num_vertex_attribs;
860 uint32_t binding_stride[MAX_VBS];
861
862 union {
863 struct {
864 struct radv_blend_state blend;
865 struct radv_depth_stencil_state ds;
866 struct radv_raster_state raster;
867 struct radv_multisample_state ms;
868 unsigned prim;
869 unsigned gs_out;
870 bool prim_restart_enable;
871 } graphics;
872 };
873 };
874
875 struct radv_graphics_pipeline_create_info {
876 bool use_rectlist;
877 bool db_depth_clear;
878 bool db_stencil_clear;
879 bool db_depth_disable_expclear;
880 bool db_stencil_disable_expclear;
881 bool db_flush_depth_inplace;
882 bool db_flush_stencil_inplace;
883 bool db_resummarize;
884 uint32_t custom_blend_mode;
885 };
886
887 VkResult
888 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
889 struct radv_pipeline_cache *cache,
890 const VkGraphicsPipelineCreateInfo *pCreateInfo,
891 const struct radv_graphics_pipeline_create_info *extra,
892 const VkAllocationCallbacks *alloc);
893
894 VkResult
895 radv_graphics_pipeline_create(VkDevice device,
896 VkPipelineCache cache,
897 const VkGraphicsPipelineCreateInfo *pCreateInfo,
898 const struct radv_graphics_pipeline_create_info *extra,
899 const VkAllocationCallbacks *alloc,
900 VkPipeline *pPipeline);
901
902 struct vk_format_description;
903 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
904 int first_non_void);
905 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
906 int first_non_void);
907 uint32_t radv_translate_colorformat(VkFormat format);
908 uint32_t radv_translate_color_numformat(VkFormat format,
909 const struct vk_format_description *desc,
910 int first_non_void);
911 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
912 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
913 uint32_t radv_translate_dbformat(VkFormat format);
914 uint32_t radv_translate_tex_dataformat(VkFormat format,
915 const struct vk_format_description *desc,
916 int first_non_void);
917 uint32_t radv_translate_tex_numformat(VkFormat format,
918 const struct vk_format_description *desc,
919 int first_non_void);
920 bool radv_format_pack_clear_color(VkFormat format,
921 uint32_t clear_vals[2],
922 VkClearColorValue *value);
923 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
924
925 struct radv_fmask_info {
926 uint64_t offset;
927 uint64_t size;
928 unsigned alignment;
929 unsigned pitch_in_pixels;
930 unsigned bank_height;
931 unsigned slice_tile_max;
932 unsigned tile_mode_index;
933 };
934
935 struct radv_cmask_info {
936 uint64_t offset;
937 uint64_t size;
938 unsigned alignment;
939 unsigned pitch;
940 unsigned height;
941 unsigned xalign;
942 unsigned yalign;
943 unsigned slice_tile_max;
944 unsigned base_address_reg;
945 };
946
947 struct r600_htile_info {
948 uint64_t offset;
949 uint64_t size;
950 unsigned pitch;
951 unsigned height;
952 unsigned xalign;
953 unsigned yalign;
954 };
955
956 struct radv_image {
957 VkImageType type;
958 /* The original VkFormat provided by the client. This may not match any
959 * of the actual surface formats.
960 */
961 VkFormat vk_format;
962 VkImageAspectFlags aspects;
963 VkExtent3D extent;
964 uint32_t levels;
965 uint32_t array_size;
966 uint32_t samples; /**< VkImageCreateInfo::samples */
967 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
968 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
969
970 VkDeviceSize size;
971 uint32_t alignment;
972
973 /* Set when bound */
974 struct radeon_winsys_bo *bo;
975 VkDeviceSize offset;
976 uint32_t dcc_offset;
977 struct radeon_surf surface;
978
979 struct radv_fmask_info fmask;
980 struct radv_cmask_info cmask;
981 uint32_t clear_value_offset;
982
983 /* Depth buffer compression and fast clear. */
984 struct r600_htile_info htile;
985 };
986
987 bool radv_layout_has_htile(const struct radv_image *image,
988 VkImageLayout layout);
989 bool radv_layout_is_htile_compressed(const struct radv_image *image,
990 VkImageLayout layout);
991 bool radv_layout_can_expclear(const struct radv_image *image,
992 VkImageLayout layout);
993 bool radv_layout_has_cmask(const struct radv_image *image,
994 VkImageLayout layout);
995 static inline uint32_t
996 radv_get_layerCount(const struct radv_image *image,
997 const VkImageSubresourceRange *range)
998 {
999 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1000 image->array_size - range->baseArrayLayer : range->layerCount;
1001 }
1002
1003 static inline uint32_t
1004 radv_get_levelCount(const struct radv_image *image,
1005 const VkImageSubresourceRange *range)
1006 {
1007 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1008 image->levels - range->baseMipLevel : range->levelCount;
1009 }
1010
1011 struct radeon_bo_metadata;
1012 void
1013 radv_init_metadata(struct radv_device *device,
1014 struct radv_image *image,
1015 struct radeon_bo_metadata *metadata);
1016
1017 struct radv_image_view {
1018 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1019 struct radeon_winsys_bo *bo;
1020
1021 VkImageViewType type;
1022 VkImageAspectFlags aspect_mask;
1023 VkFormat vk_format;
1024 uint32_t base_layer;
1025 uint32_t layer_count;
1026 uint32_t base_mip;
1027 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1028
1029 uint32_t descriptor[8];
1030 uint32_t fmask_descriptor[8];
1031 };
1032
1033 struct radv_image_create_info {
1034 const VkImageCreateInfo *vk_info;
1035 uint32_t stride;
1036 bool scanout;
1037 };
1038
1039 VkResult radv_image_create(VkDevice _device,
1040 const struct radv_image_create_info *info,
1041 const VkAllocationCallbacks* alloc,
1042 VkImage *pImage);
1043
1044 void radv_image_view_init(struct radv_image_view *view,
1045 struct radv_device *device,
1046 const VkImageViewCreateInfo* pCreateInfo,
1047 struct radv_cmd_buffer *cmd_buffer,
1048 VkImageUsageFlags usage_mask);
1049 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1050 struct radv_image *image, uint32_t micro_tile_mode);
1051 struct radv_buffer_view {
1052 struct radeon_winsys_bo *bo;
1053 VkFormat vk_format;
1054 uint64_t range; /**< VkBufferViewCreateInfo::range */
1055 uint32_t state[4];
1056 };
1057 void radv_buffer_view_init(struct radv_buffer_view *view,
1058 struct radv_device *device,
1059 const VkBufferViewCreateInfo* pCreateInfo,
1060 struct radv_cmd_buffer *cmd_buffer);
1061
1062 static inline struct VkExtent3D
1063 radv_sanitize_image_extent(const VkImageType imageType,
1064 const struct VkExtent3D imageExtent)
1065 {
1066 switch (imageType) {
1067 case VK_IMAGE_TYPE_1D:
1068 return (VkExtent3D) { imageExtent.width, 1, 1 };
1069 case VK_IMAGE_TYPE_2D:
1070 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1071 case VK_IMAGE_TYPE_3D:
1072 return imageExtent;
1073 default:
1074 unreachable("invalid image type");
1075 }
1076 }
1077
1078 static inline struct VkOffset3D
1079 radv_sanitize_image_offset(const VkImageType imageType,
1080 const struct VkOffset3D imageOffset)
1081 {
1082 switch (imageType) {
1083 case VK_IMAGE_TYPE_1D:
1084 return (VkOffset3D) { imageOffset.x, 0, 0 };
1085 case VK_IMAGE_TYPE_2D:
1086 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1087 case VK_IMAGE_TYPE_3D:
1088 return imageOffset;
1089 default:
1090 unreachable("invalid image type");
1091 }
1092 }
1093
1094 struct radv_sampler {
1095 uint32_t state[4];
1096 };
1097
1098 struct radv_color_buffer_info {
1099 uint32_t cb_color_base;
1100 uint32_t cb_color_pitch;
1101 uint32_t cb_color_slice;
1102 uint32_t cb_color_view;
1103 uint32_t cb_color_info;
1104 uint32_t cb_color_attrib;
1105 uint32_t cb_dcc_control;
1106 uint32_t cb_color_cmask;
1107 uint32_t cb_color_cmask_slice;
1108 uint32_t cb_color_fmask;
1109 uint32_t cb_color_fmask_slice;
1110 uint32_t cb_clear_value0;
1111 uint32_t cb_clear_value1;
1112 uint32_t cb_dcc_base;
1113 uint32_t micro_tile_mode;
1114 };
1115
1116 struct radv_ds_buffer_info {
1117 uint32_t db_depth_info;
1118 uint32_t db_z_info;
1119 uint32_t db_stencil_info;
1120 uint32_t db_z_read_base;
1121 uint32_t db_stencil_read_base;
1122 uint32_t db_z_write_base;
1123 uint32_t db_stencil_write_base;
1124 uint32_t db_depth_view;
1125 uint32_t db_depth_size;
1126 uint32_t db_depth_slice;
1127 uint32_t db_htile_surface;
1128 uint32_t db_htile_data_base;
1129 uint32_t pa_su_poly_offset_db_fmt_cntl;
1130 float offset_scale;
1131 };
1132
1133 struct radv_attachment_info {
1134 union {
1135 struct radv_color_buffer_info cb;
1136 struct radv_ds_buffer_info ds;
1137 };
1138 struct radv_image_view *attachment;
1139 };
1140
1141 struct radv_framebuffer {
1142 uint32_t width;
1143 uint32_t height;
1144 uint32_t layers;
1145
1146 uint32_t attachment_count;
1147 struct radv_attachment_info attachments[0];
1148 };
1149
1150 struct radv_subpass_barrier {
1151 VkPipelineStageFlags src_stage_mask;
1152 VkAccessFlags src_access_mask;
1153 VkAccessFlags dst_access_mask;
1154 };
1155
1156 struct radv_subpass {
1157 uint32_t input_count;
1158 VkAttachmentReference * input_attachments;
1159 uint32_t color_count;
1160 VkAttachmentReference * color_attachments;
1161 VkAttachmentReference * resolve_attachments;
1162 VkAttachmentReference depth_stencil_attachment;
1163
1164 /** Subpass has at least one resolve attachment */
1165 bool has_resolve;
1166
1167 struct radv_subpass_barrier start_barrier;
1168 };
1169
1170 struct radv_render_pass_attachment {
1171 VkFormat format;
1172 uint32_t samples;
1173 VkAttachmentLoadOp load_op;
1174 VkAttachmentLoadOp stencil_load_op;
1175 VkImageLayout initial_layout;
1176 VkImageLayout final_layout;
1177 };
1178
1179 struct radv_render_pass {
1180 uint32_t attachment_count;
1181 uint32_t subpass_count;
1182 VkAttachmentReference * subpass_attachments;
1183 struct radv_render_pass_attachment * attachments;
1184 struct radv_subpass_barrier end_barrier;
1185 struct radv_subpass subpasses[0];
1186 };
1187
1188 VkResult radv_device_init_meta(struct radv_device *device);
1189 void radv_device_finish_meta(struct radv_device *device);
1190
1191 struct radv_query_pool {
1192 struct radeon_winsys_bo *bo;
1193 uint32_t stride;
1194 uint32_t availability_offset;
1195 char *ptr;
1196 VkQueryType type;
1197 };
1198
1199 VkResult
1200 radv_temp_descriptor_set_create(struct radv_device *device,
1201 struct radv_cmd_buffer *cmd_buffer,
1202 VkDescriptorSetLayout _layout,
1203 VkDescriptorSet *_set);
1204
1205 void
1206 radv_temp_descriptor_set_destroy(struct radv_device *device,
1207 VkDescriptorSet _set);
1208 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1209 struct radv_image *image, uint32_t value);
1210 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1211 struct radv_image *image, uint32_t value);
1212 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1213 \
1214 static inline struct __radv_type * \
1215 __radv_type ## _from_handle(__VkType _handle) \
1216 { \
1217 return (struct __radv_type *) _handle; \
1218 } \
1219 \
1220 static inline __VkType \
1221 __radv_type ## _to_handle(struct __radv_type *_obj) \
1222 { \
1223 return (__VkType) _obj; \
1224 }
1225
1226 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1227 \
1228 static inline struct __radv_type * \
1229 __radv_type ## _from_handle(__VkType _handle) \
1230 { \
1231 return (struct __radv_type *)(uintptr_t) _handle; \
1232 } \
1233 \
1234 static inline __VkType \
1235 __radv_type ## _to_handle(struct __radv_type *_obj) \
1236 { \
1237 return (__VkType)(uintptr_t) _obj; \
1238 }
1239
1240 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1241 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1242
1243 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1244 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1245 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1246 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1247 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1248
1249 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1250 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1251 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1252 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1253 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1254 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1255 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1256 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1257 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1258 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1259 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1260 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1261 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1262 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1263 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1264 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1265 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1266 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1267 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1268
1269 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1270 \
1271 static inline const __VkType * \
1272 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1273 { \
1274 return (const __VkType *) __radv_obj; \
1275 }
1276
1277 #define RADV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1278 const __VkType *__vk_name = radv_common_to_ ## __VkType(__common_name)
1279
1280 RADV_DEFINE_STRUCT_CASTS(radv_common, VkMemoryBarrier)
1281 RADV_DEFINE_STRUCT_CASTS(radv_common, VkBufferMemoryBarrier)
1282 RADV_DEFINE_STRUCT_CASTS(radv_common, VkImageMemoryBarrier)
1283
1284
1285 #endif /* RADV_PRIVATE_H */