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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_IMAGES 8
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
84 #define NUM_META_FS_KEYS 11
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 enum radv_mem_heap {
89 RADV_MEM_HEAP_VRAM,
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
91 RADV_MEM_HEAP_GTT,
92 RADV_MEM_HEAP_COUNT
93 };
94
95 enum radv_mem_type {
96 RADV_MEM_TYPE_VRAM,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
99 RADV_MEM_TYPE_GTT_CACHED,
100 RADV_MEM_TYPE_COUNT
101 };
102
103 #define radv_noreturn __attribute__((__noreturn__))
104 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105
106 static inline uint32_t
107 align_u32(uint32_t v, uint32_t a)
108 {
109 assert(a != 0 && a == (a & -a));
110 return (v + a - 1) & ~(a - 1);
111 }
112
113 static inline uint32_t
114 align_u32_npot(uint32_t v, uint32_t a)
115 {
116 return (v + a - 1) / a * a;
117 }
118
119 static inline uint64_t
120 align_u64(uint64_t v, uint64_t a)
121 {
122 assert(a != 0 && a == (a & -a));
123 return (v + a - 1) & ~(a - 1);
124 }
125
126 static inline int32_t
127 align_i32(int32_t v, int32_t a)
128 {
129 assert(a != 0 && a == (a & -a));
130 return (v + a - 1) & ~(a - 1);
131 }
132
133 /** Alignment must be a power of 2. */
134 static inline bool
135 radv_is_aligned(uintmax_t n, uintmax_t a)
136 {
137 assert(a == (a & -a));
138 return (n & (a - 1)) == 0;
139 }
140
141 static inline uint32_t
142 round_up_u32(uint32_t v, uint32_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint64_t
148 round_up_u64(uint64_t v, uint64_t a)
149 {
150 return (v + a - 1) / a;
151 }
152
153 static inline uint32_t
154 radv_minify(uint32_t n, uint32_t levels)
155 {
156 if (unlikely(n == 0))
157 return 0;
158 else
159 return MAX2(n >> levels, 1);
160 }
161 static inline float
162 radv_clamp_f(float f, float min, float max)
163 {
164 assert(min < max);
165
166 if (f > max)
167 return max;
168 else if (f < min)
169 return min;
170 else
171 return f;
172 }
173
174 static inline bool
175 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
176 {
177 if (*inout_mask & clear_mask) {
178 *inout_mask &= ~clear_mask;
179 return true;
180 } else {
181 return false;
182 }
183 }
184
185 #define for_each_bit(b, dword) \
186 for (uint32_t __dword = (dword); \
187 (b) = __builtin_ffs(__dword) - 1, __dword; \
188 __dword &= ~(1 << (b)))
189
190 #define typed_memcpy(dest, src, count) ({ \
191 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
192 memcpy((dest), (src), (count) * sizeof(*(src))); \
193 })
194
195 #define zero(x) (memset(&(x), 0, sizeof(x)))
196
197 /* Whenever we generate an error, pass it through this function. Useful for
198 * debugging, where we can break on it. Only call at error site, not when
199 * propagating errors. Might be useful to plug in a stack trace here.
200 */
201
202 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
203
204 #ifdef DEBUG
205 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
206 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
207 #else
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #endif
211
212 void __radv_finishme(const char *file, int line, const char *format, ...)
213 radv_printflike(3, 4);
214 void radv_loge(const char *format, ...) radv_printflike(1, 2);
215 void radv_loge_v(const char *format, va_list va);
216
217 /**
218 * Print a FINISHME message, including its source location.
219 */
220 #define radv_finishme(format, ...) \
221 do { \
222 static bool reported = false; \
223 if (!reported) { \
224 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
225 reported = true; \
226 } \
227 } while (0)
228
229 /* A non-fatal assert. Useful for debugging. */
230 #ifdef DEBUG
231 #define radv_assert(x) ({ \
232 if (unlikely(!(x))) \
233 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
234 })
235 #else
236 #define radv_assert(x)
237 #endif
238
239 void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
240 void radv_abortfv(const char *format, va_list va) radv_noreturn;
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_resolve_entrypoint(uint32_t index);
255 void *radv_lookup_entrypoint(const char *name);
256
257 extern struct radv_dispatch_table dtable;
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 uint32_t chipset_id;
267 char path[20];
268 const char * name;
269 uint64_t aperture_size;
270 int cmd_parser_version;
271 uint32_t pci_vendor_id;
272 uint32_t pci_device_id;
273
274 uint8_t uuid[VK_UUID_SIZE];
275
276 struct wsi_device wsi_device;
277 };
278
279 struct radv_instance {
280 VK_LOADER_DATA _loader_data;
281
282 VkAllocationCallbacks alloc;
283
284 uint32_t apiVersion;
285 int physicalDeviceCount;
286 struct radv_physical_device physicalDevice;
287 };
288
289 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
290 void radv_finish_wsi(struct radv_physical_device *physical_device);
291
292 struct cache_entry;
293
294 struct radv_pipeline_cache {
295 struct radv_device * device;
296 pthread_mutex_t mutex;
297
298 uint32_t total_size;
299 uint32_t table_size;
300 uint32_t kernel_count;
301 struct cache_entry ** hash_table;
302 bool modified;
303
304 VkAllocationCallbacks alloc;
305 };
306
307 void
308 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
309 struct radv_device *device);
310 void
311 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
312 void
313 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
314 const void *data, size_t size);
315
316 struct radv_shader_variant *
317 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
318 struct radv_pipeline_cache *cache,
319 const unsigned char *sha1);
320
321 struct radv_shader_variant *
322 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
323 const unsigned char *sha1,
324 struct radv_shader_variant *variant,
325 const void *code, unsigned code_size);
326
327 void radv_shader_variant_destroy(struct radv_device *device,
328 struct radv_shader_variant *variant);
329
330 struct radv_meta_state {
331 VkAllocationCallbacks alloc;
332
333 struct radv_pipeline_cache cache;
334
335 /**
336 * Use array element `i` for images with `2^i` samples.
337 */
338 struct {
339 VkRenderPass render_pass[NUM_META_FS_KEYS];
340 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
341
342 VkRenderPass depth_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
343 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
344 VkRenderPass stencil_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
345 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
346 VkRenderPass depthstencil_rp[NUM_DEPTH_CLEAR_PIPELINES];
347 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
348 } clear[1 + MAX_SAMPLES_LOG2];
349
350 struct {
351 VkRenderPass render_pass[NUM_META_FS_KEYS];
352
353 /** Pipeline that blits from a 1D image. */
354 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
355
356 /** Pipeline that blits from a 2D image. */
357 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
358
359 /** Pipeline that blits from a 3D image. */
360 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
361
362 VkRenderPass depth_only_rp;
363 VkPipeline depth_only_1d_pipeline;
364 VkPipeline depth_only_2d_pipeline;
365 VkPipeline depth_only_3d_pipeline;
366
367 VkRenderPass stencil_only_rp;
368 VkPipeline stencil_only_1d_pipeline;
369 VkPipeline stencil_only_2d_pipeline;
370 VkPipeline stencil_only_3d_pipeline;
371 VkPipelineLayout pipeline_layout;
372 VkDescriptorSetLayout ds_layout;
373 } blit;
374
375 struct {
376 VkRenderPass render_passes[NUM_META_FS_KEYS];
377
378 VkPipelineLayout p_layouts[2];
379 VkDescriptorSetLayout ds_layouts[2];
380 VkPipeline pipelines[2][NUM_META_FS_KEYS];
381
382 VkRenderPass depth_only_rp;
383 VkPipeline depth_only_pipeline[2];
384
385 VkRenderPass stencil_only_rp;
386 VkPipeline stencil_only_pipeline[2];
387 } blit2d;
388
389 struct {
390 VkPipelineLayout img_p_layout;
391 VkDescriptorSetLayout img_ds_layout;
392 VkPipeline pipeline;
393 } itob;
394 struct {
395 VkRenderPass render_pass;
396 VkPipelineLayout img_p_layout;
397 VkDescriptorSetLayout img_ds_layout;
398 VkPipeline pipeline;
399 } btoi;
400
401 struct {
402 VkPipeline pipeline;
403 VkRenderPass pass;
404 } resolve;
405
406 struct {
407 VkDescriptorSetLayout ds_layout;
408 VkPipelineLayout p_layout;
409 struct {
410 VkPipeline pipeline;
411 VkPipeline i_pipeline;
412 } rc[MAX_SAMPLES_LOG2];
413 } resolve_compute;
414
415 struct {
416 VkPipeline decompress_pipeline;
417 VkPipeline resummarize_pipeline;
418 VkRenderPass pass;
419 } depth_decomp;
420
421 struct {
422 VkPipeline cmask_eliminate_pipeline;
423 VkPipeline fmask_decompress_pipeline;
424 VkRenderPass pass;
425 } fast_clear_flush;
426
427 struct {
428 VkPipelineLayout fill_p_layout;
429 VkPipelineLayout copy_p_layout;
430 VkDescriptorSetLayout fill_ds_layout;
431 VkDescriptorSetLayout copy_ds_layout;
432 VkPipeline fill_pipeline;
433 VkPipeline copy_pipeline;
434 } buffer;
435 };
436
437 struct radv_queue {
438 VK_LOADER_DATA _loader_data;
439
440 struct radv_device * device;
441
442 struct radv_state_pool * pool;
443 };
444
445 struct radv_device {
446 VK_LOADER_DATA _loader_data;
447
448 VkAllocationCallbacks alloc;
449
450 struct radv_instance * instance;
451 struct radeon_winsys *ws;
452 struct radeon_winsys_ctx *hw_ctx;
453
454 struct radv_meta_state meta_state;
455 struct radv_queue queue;
456 struct radeon_winsys_cs *empty_cs;
457
458 bool allow_fast_clears;
459 bool allow_dcc;
460 bool shader_stats_dump;
461
462 /* MSAA sample locations.
463 * The first index is the sample index.
464 * The second index is the coordinate: X, Y. */
465 float sample_locations_1x[1][2];
466 float sample_locations_2x[2][2];
467 float sample_locations_4x[4][2];
468 float sample_locations_8x[8][2];
469 float sample_locations_16x[16][2];
470 };
471
472 struct radv_device_memory {
473 struct radeon_winsys_bo *bo;
474 uint32_t type_index;
475 VkDeviceSize map_size;
476 void * map;
477 };
478
479
480 struct radv_descriptor_range {
481 uint64_t va;
482 uint32_t size;
483 };
484
485 struct radv_descriptor_set {
486 const struct radv_descriptor_set_layout *layout;
487 struct list_head descriptor_pool;
488 uint32_t size;
489
490 struct radv_buffer_view *buffer_views;
491 struct radeon_winsys_bo *bo;
492 uint64_t va;
493 uint32_t *mapped_ptr;
494 struct radv_descriptor_range *dynamic_descriptors;
495 struct radeon_winsys_bo *descriptors[0];
496 };
497
498 struct radv_descriptor_pool_free_node {
499 int next;
500 uint32_t offset;
501 uint32_t size;
502 };
503
504 struct radv_descriptor_pool {
505 struct list_head descriptor_sets;
506
507 struct radeon_winsys_bo *bo;
508 uint8_t *mapped_ptr;
509 uint64_t current_offset;
510 uint64_t size;
511
512 int free_list;
513 int full_list;
514 uint32_t max_sets;
515 struct radv_descriptor_pool_free_node free_nodes[];
516 };
517
518 struct radv_buffer {
519 struct radv_device * device;
520 VkDeviceSize size;
521
522 VkBufferUsageFlags usage;
523
524 /* Set when bound */
525 struct radeon_winsys_bo * bo;
526 VkDeviceSize offset;
527 };
528
529
530 enum radv_cmd_dirty_bits {
531 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
532 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
533 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
534 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
535 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
536 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
537 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
538 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
539 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
540 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
541 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
542 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
543 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
544 };
545 typedef uint32_t radv_cmd_dirty_mask_t;
546
547 enum radv_cmd_flush_bits {
548 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
549 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
550 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
551 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
552 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
553 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
554 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
555 /* Framebuffer caches */
556 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
557 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
558 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
559 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
560 /* Engine synchronization. */
561 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
562 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
563 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
564 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
565
566 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
567 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
568 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
569 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
570 };
571
572 struct radv_vertex_binding {
573 struct radv_buffer * buffer;
574 VkDeviceSize offset;
575 };
576
577 struct radv_dynamic_state {
578 struct {
579 uint32_t count;
580 VkViewport viewports[MAX_VIEWPORTS];
581 } viewport;
582
583 struct {
584 uint32_t count;
585 VkRect2D scissors[MAX_SCISSORS];
586 } scissor;
587
588 float line_width;
589
590 struct {
591 float bias;
592 float clamp;
593 float slope;
594 } depth_bias;
595
596 float blend_constants[4];
597
598 struct {
599 float min;
600 float max;
601 } depth_bounds;
602
603 struct {
604 uint32_t front;
605 uint32_t back;
606 } stencil_compare_mask;
607
608 struct {
609 uint32_t front;
610 uint32_t back;
611 } stencil_write_mask;
612
613 struct {
614 uint32_t front;
615 uint32_t back;
616 } stencil_reference;
617 };
618
619 extern const struct radv_dynamic_state default_dynamic_state;
620
621 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
622 const struct radv_dynamic_state *src,
623 uint32_t copy_mask);
624 /**
625 * Attachment state when recording a renderpass instance.
626 *
627 * The clear value is valid only if there exists a pending clear.
628 */
629 struct radv_attachment_state {
630 VkImageAspectFlags pending_clear_aspects;
631 VkClearValue clear_value;
632 VkImageLayout current_layout;
633 };
634
635 struct radv_cmd_state {
636 uint32_t vb_dirty;
637 bool vertex_descriptors_dirty;
638 radv_cmd_dirty_mask_t dirty;
639
640 struct radv_pipeline * pipeline;
641 struct radv_pipeline * emitted_pipeline;
642 struct radv_pipeline * compute_pipeline;
643 struct radv_pipeline * emitted_compute_pipeline;
644 struct radv_framebuffer * framebuffer;
645 struct radv_render_pass * pass;
646 const struct radv_subpass * subpass;
647 struct radv_dynamic_state dynamic;
648 struct radv_vertex_binding vertex_bindings[MAX_VBS];
649 struct radv_descriptor_set * descriptors[MAX_SETS];
650 struct radv_attachment_state * attachments;
651 VkRect2D render_area;
652 struct radv_buffer * index_buffer;
653 uint32_t index_type;
654 uint32_t index_offset;
655 uint32_t last_primitive_reset_index;
656 enum radv_cmd_flush_bits flush_bits;
657 unsigned active_occlusion_queries;
658 float offset_scale;
659 uint32_t descriptors_dirty;
660 };
661 struct radv_cmd_pool {
662 VkAllocationCallbacks alloc;
663 struct list_head cmd_buffers;
664 };
665
666 struct radv_cmd_buffer_upload {
667 uint8_t *map;
668 unsigned offset;
669 uint64_t size;
670 struct radeon_winsys_bo *upload_bo;
671 struct list_head list;
672 };
673
674 struct radv_cmd_buffer {
675 VK_LOADER_DATA _loader_data;
676
677 struct radv_device * device;
678
679 struct radv_cmd_pool * pool;
680 struct list_head pool_link;
681
682 VkCommandBufferUsageFlags usage_flags;
683 VkCommandBufferLevel level;
684 struct radeon_winsys_cs *cs;
685 struct radv_cmd_state state;
686
687 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
688 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
689 VkShaderStageFlags push_constant_stages;
690
691 struct radv_cmd_buffer_upload upload;
692
693 bool record_fail;
694 };
695
696 struct radv_image;
697
698 void si_init_config(struct radv_physical_device *physical_device,
699 struct radv_cmd_buffer *cmd_buffer);
700 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
701 int count, const VkViewport *viewports);
702 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
703 int count, const VkRect2D *scissors);
704 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
705 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
706 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
707 uint64_t src_va, uint64_t dest_va,
708 uint64_t size);
709 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
710 uint64_t size, unsigned value);
711 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
712 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
713 struct radv_descriptor_set *set,
714 unsigned idx);
715 bool
716 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
717 unsigned size,
718 unsigned alignment,
719 unsigned *out_offset,
720 void **ptr);
721 void
722 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
723 const struct radv_subpass *subpass,
724 bool transitions);
725 bool
726 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
727 unsigned size, unsigned alignmnet,
728 const void *data, unsigned *out_offset);
729 void
730 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
731 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
732 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
733 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
734 unsigned radv_cayman_get_maxdist(int log_samples);
735 void radv_device_init_msaa(struct radv_device *device);
736 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
737 struct radv_image *image,
738 VkClearDepthStencilValue ds_clear_value,
739 VkImageAspectFlags aspects);
740 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
741 struct radv_image *image,
742 int idx,
743 uint32_t color_values[2]);
744 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
745 struct radeon_winsys_bo *bo,
746 uint64_t offset, uint64_t size, uint32_t value);
747
748 /*
749 * Takes x,y,z as exact numbers of invocations, instead of blocks.
750 *
751 * Limitations: Can't call normal dispatch functions without binding or rebinding
752 * the compute pipeline.
753 */
754 void radv_unaligned_dispatch(
755 struct radv_cmd_buffer *cmd_buffer,
756 uint32_t x,
757 uint32_t y,
758 uint32_t z);
759
760 struct radv_event {
761 struct radeon_winsys_bo *bo;
762 uint64_t *map;
763 };
764
765 struct nir_shader;
766
767 struct radv_shader_module {
768 struct nir_shader * nir;
769 unsigned char sha1[20];
770 uint32_t size;
771 char data[0];
772 };
773
774 union ac_shader_variant_key;
775
776 void
777 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
778 const char *entrypoint,
779 const VkSpecializationInfo *spec_info,
780 const struct radv_pipeline_layout *layout,
781 const union ac_shader_variant_key *key);
782
783 static inline gl_shader_stage
784 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
785 {
786 assert(__builtin_popcount(vk_stage) == 1);
787 return ffs(vk_stage) - 1;
788 }
789
790 static inline VkShaderStageFlagBits
791 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
792 {
793 return (1 << mesa_stage);
794 }
795
796 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
797
798 #define radv_foreach_stage(stage, stage_bits) \
799 for (gl_shader_stage stage, \
800 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
801 stage = __builtin_ffs(__tmp) - 1, __tmp; \
802 __tmp &= ~(1 << (stage)))
803
804 struct radv_shader_variant {
805 uint32_t ref_count;
806
807 struct radeon_winsys_bo *bo;
808 struct ac_shader_config config;
809 struct ac_shader_variant_info info;
810 unsigned rsrc1;
811 unsigned rsrc2;
812 uint32_t code_size;
813 };
814
815 struct radv_depth_stencil_state {
816 uint32_t db_depth_control;
817 uint32_t db_stencil_control;
818 uint32_t db_render_control;
819 uint32_t db_render_override2;
820 };
821
822 struct radv_blend_state {
823 uint32_t cb_color_control;
824 uint32_t cb_target_mask;
825 uint32_t sx_mrt0_blend_opt[8];
826 uint32_t cb_blend_control[8];
827
828 uint32_t spi_shader_col_format;
829 uint32_t cb_shader_mask;
830 uint32_t db_alpha_to_mask;
831 };
832
833 unsigned radv_format_meta_fs_key(VkFormat format);
834
835 struct radv_raster_state {
836 uint32_t pa_cl_clip_cntl;
837 uint32_t pa_cl_vs_out_cntl;
838 uint32_t spi_interp_control;
839 uint32_t pa_su_point_size;
840 uint32_t pa_su_point_minmax;
841 uint32_t pa_su_line_cntl;
842 uint32_t pa_su_vtx_cntl;
843 uint32_t pa_su_sc_mode_cntl;
844 };
845
846 struct radv_multisample_state {
847 uint32_t db_eqaa;
848 uint32_t pa_sc_line_cntl;
849 uint32_t pa_sc_mode_cntl_0;
850 uint32_t pa_sc_mode_cntl_1;
851 uint32_t pa_sc_aa_config;
852 uint32_t pa_sc_aa_mask[2];
853 unsigned num_samples;
854 };
855
856 struct radv_pipeline {
857 struct radv_device * device;
858 uint32_t dynamic_state_mask;
859 struct radv_dynamic_state dynamic_state;
860
861 struct radv_pipeline_layout * layout;
862
863 bool needs_data_cache;
864
865 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
866 VkShaderStageFlags active_stages;
867
868 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
869 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
870 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
871 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
872 uint32_t num_vertex_attribs;
873 uint32_t binding_stride[MAX_VBS];
874
875 union {
876 struct {
877 struct radv_blend_state blend;
878 struct radv_depth_stencil_state ds;
879 struct radv_raster_state raster;
880 struct radv_multisample_state ms;
881 unsigned prim;
882 unsigned gs_out;
883 bool prim_restart_enable;
884 } graphics;
885 };
886 };
887
888 struct radv_graphics_pipeline_create_info {
889 bool use_rectlist;
890 bool db_depth_clear;
891 bool db_stencil_clear;
892 bool db_depth_disable_expclear;
893 bool db_stencil_disable_expclear;
894 bool db_flush_depth_inplace;
895 bool db_flush_stencil_inplace;
896 bool db_resummarize;
897 uint32_t custom_blend_mode;
898 };
899
900 VkResult
901 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
902 struct radv_pipeline_cache *cache,
903 const VkGraphicsPipelineCreateInfo *pCreateInfo,
904 const struct radv_graphics_pipeline_create_info *extra,
905 const VkAllocationCallbacks *alloc);
906
907 VkResult
908 radv_graphics_pipeline_create(VkDevice device,
909 VkPipelineCache cache,
910 const VkGraphicsPipelineCreateInfo *pCreateInfo,
911 const struct radv_graphics_pipeline_create_info *extra,
912 const VkAllocationCallbacks *alloc,
913 VkPipeline *pPipeline);
914
915 struct vk_format_description;
916 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
917 int first_non_void);
918 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
919 int first_non_void);
920 uint32_t radv_translate_colorformat(VkFormat format);
921 uint32_t radv_translate_color_numformat(VkFormat format,
922 const struct vk_format_description *desc,
923 int first_non_void);
924 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
925 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
926 uint32_t radv_translate_dbformat(VkFormat format);
927 uint32_t radv_translate_tex_dataformat(VkFormat format,
928 const struct vk_format_description *desc,
929 int first_non_void);
930 uint32_t radv_translate_tex_numformat(VkFormat format,
931 const struct vk_format_description *desc,
932 int first_non_void);
933 bool radv_format_pack_clear_color(VkFormat format,
934 uint32_t clear_vals[2],
935 VkClearColorValue *value);
936 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
937
938 struct radv_fmask_info {
939 uint64_t offset;
940 uint64_t size;
941 unsigned alignment;
942 unsigned pitch_in_pixels;
943 unsigned bank_height;
944 unsigned slice_tile_max;
945 unsigned tile_mode_index;
946 };
947
948 struct radv_cmask_info {
949 uint64_t offset;
950 uint64_t size;
951 unsigned alignment;
952 unsigned slice_tile_max;
953 unsigned base_address_reg;
954 };
955
956 struct r600_htile_info {
957 uint64_t offset;
958 uint64_t size;
959 unsigned pitch;
960 unsigned height;
961 unsigned xalign;
962 unsigned yalign;
963 };
964
965 struct radv_image {
966 VkImageType type;
967 /* The original VkFormat provided by the client. This may not match any
968 * of the actual surface formats.
969 */
970 VkFormat vk_format;
971 VkImageAspectFlags aspects;
972 VkExtent3D extent;
973 uint32_t levels;
974 uint32_t array_size;
975 uint32_t samples; /**< VkImageCreateInfo::samples */
976 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
977 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
978
979 VkDeviceSize size;
980 uint32_t alignment;
981
982 /* Set when bound */
983 struct radeon_winsys_bo *bo;
984 VkDeviceSize offset;
985 uint32_t dcc_offset;
986 struct radeon_surf surface;
987
988 struct radv_fmask_info fmask;
989 struct radv_cmask_info cmask;
990 uint32_t clear_value_offset;
991
992 /* Depth buffer compression and fast clear. */
993 struct r600_htile_info htile;
994 };
995
996 bool radv_layout_has_htile(const struct radv_image *image,
997 VkImageLayout layout);
998 bool radv_layout_is_htile_compressed(const struct radv_image *image,
999 VkImageLayout layout);
1000 bool radv_layout_can_expclear(const struct radv_image *image,
1001 VkImageLayout layout);
1002 bool radv_layout_has_cmask(const struct radv_image *image,
1003 VkImageLayout layout);
1004 static inline uint32_t
1005 radv_get_layerCount(const struct radv_image *image,
1006 const VkImageSubresourceRange *range)
1007 {
1008 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1009 image->array_size - range->baseArrayLayer : range->layerCount;
1010 }
1011
1012 static inline uint32_t
1013 radv_get_levelCount(const struct radv_image *image,
1014 const VkImageSubresourceRange *range)
1015 {
1016 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1017 image->levels - range->baseMipLevel : range->levelCount;
1018 }
1019
1020 struct radeon_bo_metadata;
1021 void
1022 radv_init_metadata(struct radv_device *device,
1023 struct radv_image *image,
1024 struct radeon_bo_metadata *metadata);
1025
1026 struct radv_image_view {
1027 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1028 struct radeon_winsys_bo *bo;
1029
1030 VkImageViewType type;
1031 VkImageAspectFlags aspect_mask;
1032 VkFormat vk_format;
1033 uint32_t base_layer;
1034 uint32_t layer_count;
1035 uint32_t base_mip;
1036 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1037
1038 uint32_t descriptor[8];
1039 uint32_t fmask_descriptor[8];
1040 };
1041
1042 struct radv_image_create_info {
1043 const VkImageCreateInfo *vk_info;
1044 uint32_t stride;
1045 bool scanout;
1046 };
1047
1048 VkResult radv_image_create(VkDevice _device,
1049 const struct radv_image_create_info *info,
1050 const VkAllocationCallbacks* alloc,
1051 VkImage *pImage);
1052
1053 void radv_image_view_init(struct radv_image_view *view,
1054 struct radv_device *device,
1055 const VkImageViewCreateInfo* pCreateInfo,
1056 struct radv_cmd_buffer *cmd_buffer,
1057 VkImageUsageFlags usage_mask);
1058 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1059 struct radv_image *image, uint32_t micro_tile_mode);
1060 struct radv_buffer_view {
1061 struct radeon_winsys_bo *bo;
1062 VkFormat vk_format;
1063 uint64_t range; /**< VkBufferViewCreateInfo::range */
1064 uint32_t state[4];
1065 };
1066 void radv_buffer_view_init(struct radv_buffer_view *view,
1067 struct radv_device *device,
1068 const VkBufferViewCreateInfo* pCreateInfo,
1069 struct radv_cmd_buffer *cmd_buffer);
1070
1071 static inline struct VkExtent3D
1072 radv_sanitize_image_extent(const VkImageType imageType,
1073 const struct VkExtent3D imageExtent)
1074 {
1075 switch (imageType) {
1076 case VK_IMAGE_TYPE_1D:
1077 return (VkExtent3D) { imageExtent.width, 1, 1 };
1078 case VK_IMAGE_TYPE_2D:
1079 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1080 case VK_IMAGE_TYPE_3D:
1081 return imageExtent;
1082 default:
1083 unreachable("invalid image type");
1084 }
1085 }
1086
1087 static inline struct VkOffset3D
1088 radv_sanitize_image_offset(const VkImageType imageType,
1089 const struct VkOffset3D imageOffset)
1090 {
1091 switch (imageType) {
1092 case VK_IMAGE_TYPE_1D:
1093 return (VkOffset3D) { imageOffset.x, 0, 0 };
1094 case VK_IMAGE_TYPE_2D:
1095 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1096 case VK_IMAGE_TYPE_3D:
1097 return imageOffset;
1098 default:
1099 unreachable("invalid image type");
1100 }
1101 }
1102
1103 struct radv_sampler {
1104 uint32_t state[4];
1105 };
1106
1107 struct radv_color_buffer_info {
1108 uint32_t cb_color_base;
1109 uint32_t cb_color_pitch;
1110 uint32_t cb_color_slice;
1111 uint32_t cb_color_view;
1112 uint32_t cb_color_info;
1113 uint32_t cb_color_attrib;
1114 uint32_t cb_dcc_control;
1115 uint32_t cb_color_cmask;
1116 uint32_t cb_color_cmask_slice;
1117 uint32_t cb_color_fmask;
1118 uint32_t cb_color_fmask_slice;
1119 uint32_t cb_clear_value0;
1120 uint32_t cb_clear_value1;
1121 uint32_t cb_dcc_base;
1122 uint32_t micro_tile_mode;
1123 };
1124
1125 struct radv_ds_buffer_info {
1126 uint32_t db_depth_info;
1127 uint32_t db_z_info;
1128 uint32_t db_stencil_info;
1129 uint32_t db_z_read_base;
1130 uint32_t db_stencil_read_base;
1131 uint32_t db_z_write_base;
1132 uint32_t db_stencil_write_base;
1133 uint32_t db_depth_view;
1134 uint32_t db_depth_size;
1135 uint32_t db_depth_slice;
1136 uint32_t db_htile_surface;
1137 uint32_t db_htile_data_base;
1138 uint32_t pa_su_poly_offset_db_fmt_cntl;
1139 float offset_scale;
1140 };
1141
1142 struct radv_attachment_info {
1143 union {
1144 struct radv_color_buffer_info cb;
1145 struct radv_ds_buffer_info ds;
1146 };
1147 struct radv_image_view *attachment;
1148 };
1149
1150 struct radv_framebuffer {
1151 uint32_t width;
1152 uint32_t height;
1153 uint32_t layers;
1154
1155 uint32_t attachment_count;
1156 struct radv_attachment_info attachments[0];
1157 };
1158
1159 struct radv_subpass_barrier {
1160 VkPipelineStageFlags src_stage_mask;
1161 VkAccessFlags src_access_mask;
1162 VkAccessFlags dst_access_mask;
1163 };
1164
1165 struct radv_subpass {
1166 uint32_t input_count;
1167 VkAttachmentReference * input_attachments;
1168 uint32_t color_count;
1169 VkAttachmentReference * color_attachments;
1170 VkAttachmentReference * resolve_attachments;
1171 VkAttachmentReference depth_stencil_attachment;
1172
1173 /** Subpass has at least one resolve attachment */
1174 bool has_resolve;
1175
1176 struct radv_subpass_barrier start_barrier;
1177 };
1178
1179 struct radv_render_pass_attachment {
1180 VkFormat format;
1181 uint32_t samples;
1182 VkAttachmentLoadOp load_op;
1183 VkAttachmentLoadOp stencil_load_op;
1184 VkImageLayout initial_layout;
1185 VkImageLayout final_layout;
1186 };
1187
1188 struct radv_render_pass {
1189 uint32_t attachment_count;
1190 uint32_t subpass_count;
1191 VkAttachmentReference * subpass_attachments;
1192 struct radv_render_pass_attachment * attachments;
1193 struct radv_subpass_barrier end_barrier;
1194 struct radv_subpass subpasses[0];
1195 };
1196
1197 VkResult radv_device_init_meta(struct radv_device *device);
1198 void radv_device_finish_meta(struct radv_device *device);
1199
1200 struct radv_query_pool {
1201 struct radeon_winsys_bo *bo;
1202 uint32_t stride;
1203 uint32_t availability_offset;
1204 char *ptr;
1205 VkQueryType type;
1206 };
1207
1208 VkResult
1209 radv_temp_descriptor_set_create(struct radv_device *device,
1210 struct radv_cmd_buffer *cmd_buffer,
1211 VkDescriptorSetLayout _layout,
1212 VkDescriptorSet *_set);
1213
1214 void
1215 radv_temp_descriptor_set_destroy(struct radv_device *device,
1216 VkDescriptorSet _set);
1217 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1218 struct radv_image *image, uint32_t value);
1219 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1220 struct radv_image *image, uint32_t value);
1221
1222 struct radv_fence {
1223 struct radeon_winsys_fence *fence;
1224 bool submitted;
1225 bool signalled;
1226 };
1227
1228 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1229 \
1230 static inline struct __radv_type * \
1231 __radv_type ## _from_handle(__VkType _handle) \
1232 { \
1233 return (struct __radv_type *) _handle; \
1234 } \
1235 \
1236 static inline __VkType \
1237 __radv_type ## _to_handle(struct __radv_type *_obj) \
1238 { \
1239 return (__VkType) _obj; \
1240 }
1241
1242 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1243 \
1244 static inline struct __radv_type * \
1245 __radv_type ## _from_handle(__VkType _handle) \
1246 { \
1247 return (struct __radv_type *)(uintptr_t) _handle; \
1248 } \
1249 \
1250 static inline __VkType \
1251 __radv_type ## _to_handle(struct __radv_type *_obj) \
1252 { \
1253 return (__VkType)(uintptr_t) _obj; \
1254 }
1255
1256 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1257 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1258
1259 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1260 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1261 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1262 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1263 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1264
1265 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1266 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1267 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1268 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1269 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1270 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1271 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1272 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1273 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1274 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1275 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1276 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1277 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1278 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1279 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1280 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1281 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1282 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1283 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1284
1285 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1286 \
1287 static inline const __VkType * \
1288 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1289 { \
1290 return (const __VkType *) __radv_obj; \
1291 }
1292
1293 #endif /* RADV_PRIVATE_H */