2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
42 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "radv_radeon_winsys.h"
53 #include "ac_binary.h"
54 #include "ac_nir_to_llvm.h"
55 #include "radv_descriptor_set.h"
57 #include <llvm-c/TargetMachine.h>
59 /* Pre-declarations needed for WSI entrypoints */
62 typedef struct xcb_connection_t xcb_connection_t
;
63 typedef uint32_t xcb_visualid_t
;
64 typedef uint32_t xcb_window_t
;
66 #include <vulkan/vulkan.h>
67 #include <vulkan/vulkan_intel.h>
68 #include <vulkan/vk_icd.h>
70 #include "radv_entrypoints.h"
74 #define MAX_VERTEX_ATTRIBS 32
76 #define MAX_VIEWPORTS 16
77 #define MAX_SCISSORS 16
78 #define MAX_PUSH_CONSTANTS_SIZE 128
79 #define MAX_DYNAMIC_BUFFERS 16
81 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
82 #define NUM_META_FS_KEYS 11
84 #define NUM_DEPTH_CLEAR_PIPELINES 3
86 #define radv_noreturn __attribute__((__noreturn__))
87 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
89 #define MIN(a, b) ((a) < (b) ? (a) : (b))
90 #define MAX(a, b) ((a) > (b) ? (a) : (b))
92 static inline uint32_t
93 align_u32(uint32_t v
, uint32_t a
)
95 assert(a
!= 0 && a
== (a
& -a
));
96 return (v
+ a
- 1) & ~(a
- 1);
99 static inline uint32_t
100 align_u32_npot(uint32_t v
, uint32_t a
)
102 return (v
+ a
- 1) / a
* a
;
105 static inline uint64_t
106 align_u64(uint64_t v
, uint64_t a
)
108 assert(a
!= 0 && a
== (a
& -a
));
109 return (v
+ a
- 1) & ~(a
- 1);
112 static inline int32_t
113 align_i32(int32_t v
, int32_t a
)
115 assert(a
!= 0 && a
== (a
& -a
));
116 return (v
+ a
- 1) & ~(a
- 1);
119 /** Alignment must be a power of 2. */
121 radv_is_aligned(uintmax_t n
, uintmax_t a
)
123 assert(a
== (a
& -a
));
124 return (n
& (a
- 1)) == 0;
127 static inline uint32_t
128 round_up_u32(uint32_t v
, uint32_t a
)
130 return (v
+ a
- 1) / a
;
133 static inline uint64_t
134 round_up_u64(uint64_t v
, uint64_t a
)
136 return (v
+ a
- 1) / a
;
139 static inline uint32_t
140 radv_minify(uint32_t n
, uint32_t levels
)
142 if (unlikely(n
== 0))
145 return MAX(n
>> levels
, 1);
148 radv_clamp_f(float f
, float min
, float max
)
161 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
163 if (*inout_mask
& clear_mask
) {
164 *inout_mask
&= ~clear_mask
;
171 #define for_each_bit(b, dword) \
172 for (uint32_t __dword = (dword); \
173 (b) = __builtin_ffs(__dword) - 1, __dword; \
174 __dword &= ~(1 << (b)))
176 #define typed_memcpy(dest, src, count) ({ \
177 static_assert(sizeof(*src) == sizeof(*dest), ""); \
178 memcpy((dest), (src), (count) * sizeof(*(src))); \
181 #define zero(x) (memset(&(x), 0, sizeof(x)))
183 /* Define no kernel as 1, since that's an illegal offset for a kernel */
187 VkStructureType sType
;
191 /* Whenever we generate an error, pass it through this function. Useful for
192 * debugging, where we can break on it. Only call at error site, not when
193 * propagating errors. Might be useful to plug in a stack trace here.
196 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
199 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
200 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
202 #define vk_error(error) error
203 #define vk_errorf(error, format, ...) error
206 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
207 radv_printflike(3, 4);
208 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
209 void radv_loge_v(const char *format
, va_list va
);
212 * Print a FINISHME message, including its source location.
214 #define radv_finishme(format, ...) \
215 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
217 /* A non-fatal assert. Useful for debugging. */
219 #define radv_assert(x) ({ \
220 if (unlikely(!(x))) \
221 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
224 #define radv_assert(x)
228 * If a block of code is annotated with radv_validate, then the block runs only
232 #define radv_validate if (1)
234 #define radv_validate if (0)
237 void radv_abortf(const char *format
, ...) radv_noreturn
radv_printflike(1, 2);
238 void radv_abortfv(const char *format
, va_list va
) radv_noreturn
;
240 #define stub_return(v) \
242 radv_finishme("stub %s", __func__); \
248 radv_finishme("stub %s", __func__); \
253 * A dynamically growable, circular buffer. Elements are added at head and
254 * removed from tail. head and tail are free-running uint32_t indices and we
255 * only compute the modulo with size when accessing the array. This way,
256 * number of bytes in the queue is always head - tail, even in case of
263 uint32_t element_size
;
268 int radv_vector_init(struct radv_vector
*queue
, uint32_t element_size
, uint32_t size
);
269 void *radv_vector_add(struct radv_vector
*queue
);
270 void *radv_vector_remove(struct radv_vector
*queue
);
273 radv_vector_length(struct radv_vector
*queue
)
275 return (queue
->head
- queue
->tail
) / queue
->element_size
;
279 radv_vector_head(struct radv_vector
*vector
)
281 assert(vector
->tail
< vector
->head
);
282 return (void *)((char *)vector
->data
+
283 ((vector
->head
- vector
->element_size
) &
284 (vector
->size
- 1)));
288 radv_vector_tail(struct radv_vector
*vector
)
290 return (void *)((char *)vector
->data
+ (vector
->tail
& (vector
->size
- 1)));
294 radv_vector_finish(struct radv_vector
*queue
)
299 #define radv_vector_foreach(elem, queue) \
300 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct radv_vector *), ""); \
301 for (uint32_t __radv_vector_offset = (queue)->tail; \
302 elem = (queue)->data + (__radv_vector_offset & ((queue)->size - 1)), __radv_vector_offset < (queue)->head; \
303 __radv_vector_offset += (queue)->element_size)
305 void *radv_resolve_entrypoint(uint32_t index
);
306 void *radv_lookup_entrypoint(const char *name
);
308 extern struct radv_dispatch_table dtable
;
311 radv_alloc(const VkAllocationCallbacks
*alloc
,
312 size_t size
, size_t align
,
313 VkSystemAllocationScope scope
)
315 return alloc
->pfnAllocation(alloc
->pUserData
, size
, align
, scope
);
319 radv_realloc(const VkAllocationCallbacks
*alloc
,
320 void *ptr
, size_t size
, size_t align
,
321 VkSystemAllocationScope scope
)
323 return alloc
->pfnReallocation(alloc
->pUserData
, ptr
, size
, align
, scope
);
327 radv_free(const VkAllocationCallbacks
*alloc
, void *data
)
329 alloc
->pfnFree(alloc
->pUserData
, data
);
333 radv_alloc2(const VkAllocationCallbacks
*parent_alloc
,
334 const VkAllocationCallbacks
*alloc
,
335 size_t size
, size_t align
,
336 VkSystemAllocationScope scope
)
339 return radv_alloc(alloc
, size
, align
, scope
);
341 return radv_alloc(parent_alloc
, size
, align
, scope
);
345 radv_free2(const VkAllocationCallbacks
*parent_alloc
,
346 const VkAllocationCallbacks
*alloc
,
350 radv_free(alloc
, data
);
352 radv_free(parent_alloc
, data
);
355 struct radv_wsi_interaface
;
357 #define VK_ICD_WSI_PLATFORM_MAX 5
359 struct radv_physical_device
{
360 VK_LOADER_DATA _loader_data
;
362 struct radv_instance
* instance
;
364 struct radeon_winsys
*ws
;
365 struct radeon_info rad_info
;
369 uint64_t aperture_size
;
370 int cmd_parser_version
;
371 uint32_t pci_vendor_id
;
372 uint32_t pci_device_id
;
374 struct radv_wsi_interface
* wsi
[VK_ICD_WSI_PLATFORM_MAX
];
377 struct radv_instance
{
378 VK_LOADER_DATA _loader_data
;
380 VkAllocationCallbacks alloc
;
383 int physicalDeviceCount
;
384 struct radv_physical_device physicalDevice
;
387 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
388 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
392 struct radv_pipeline_cache
{
393 struct radv_device
* device
;
394 pthread_mutex_t mutex
;
398 uint32_t kernel_count
;
399 struct cache_entry
** hash_table
;
402 VkAllocationCallbacks alloc
;
406 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
407 struct radv_device
*device
);
409 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
411 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
412 const void *data
, size_t size
);
414 struct radv_shader_variant
*
415 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
416 struct radv_pipeline_cache
*cache
,
417 const unsigned char *sha1
);
419 struct radv_shader_variant
*
420 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache
*cache
,
421 const unsigned char *sha1
,
422 struct radv_shader_variant
*variant
,
423 const void *code
, unsigned code_size
);
425 void radv_shader_variant_destroy(struct radv_device
*device
,
426 struct radv_shader_variant
*variant
);
428 struct radv_meta_state
{
429 VkAllocationCallbacks alloc
;
431 struct radv_pipeline_cache cache
;
434 * Use array element `i` for images with `2^i` samples.
437 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
438 struct radv_pipeline
*color_pipelines
[NUM_META_FS_KEYS
];
440 VkRenderPass depth_only_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
441 struct radv_pipeline
*depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
442 VkRenderPass stencil_only_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
443 struct radv_pipeline
*stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
444 VkRenderPass depthstencil_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
445 struct radv_pipeline
*depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
446 } clear
[1 + MAX_SAMPLES_LOG2
];
449 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
451 /** Pipeline that blits from a 1D image. */
452 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
454 /** Pipeline that blits from a 2D image. */
455 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
457 /** Pipeline that blits from a 3D image. */
458 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
460 VkRenderPass depth_only_rp
;
461 VkPipeline depth_only_1d_pipeline
;
462 VkPipeline depth_only_2d_pipeline
;
463 VkPipeline depth_only_3d_pipeline
;
465 VkRenderPass stencil_only_rp
;
466 VkPipeline stencil_only_1d_pipeline
;
467 VkPipeline stencil_only_2d_pipeline
;
468 VkPipeline stencil_only_3d_pipeline
;
469 VkPipelineLayout pipeline_layout
;
470 VkDescriptorSetLayout ds_layout
;
474 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
476 VkPipelineLayout p_layouts
[2];
477 VkDescriptorSetLayout ds_layouts
[2];
478 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
480 VkRenderPass depth_only_rp
;
481 VkPipeline depth_only_pipeline
[2];
483 VkRenderPass stencil_only_rp
;
484 VkPipeline stencil_only_pipeline
[2];
488 VkPipelineLayout img_p_layout
;
489 VkDescriptorSetLayout img_ds_layout
;
493 VkRenderPass render_pass
;
494 VkPipelineLayout img_p_layout
;
495 VkDescriptorSetLayout img_ds_layout
;
505 VkDescriptorSetLayout ds_layout
;
506 VkPipelineLayout p_layout
;
509 VkPipeline i_pipeline
;
510 } rc
[MAX_SAMPLES_LOG2
];
514 VkPipeline decompress_pipeline
;
515 VkPipeline resummarize_pipeline
;
520 VkPipeline cmask_eliminate_pipeline
;
521 VkPipeline fmask_decompress_pipeline
;
526 VkPipelineLayout fill_p_layout
;
527 VkPipelineLayout copy_p_layout
;
528 VkDescriptorSetLayout fill_ds_layout
;
529 VkDescriptorSetLayout copy_ds_layout
;
530 VkPipeline fill_pipeline
;
531 VkPipeline copy_pipeline
;
536 VK_LOADER_DATA _loader_data
;
538 struct radv_device
* device
;
540 struct radv_state_pool
* pool
;
544 VK_LOADER_DATA _loader_data
;
546 VkAllocationCallbacks alloc
;
548 struct radv_instance
* instance
;
549 struct radeon_winsys
*ws
;
550 struct radeon_winsys_ctx
*hw_ctx
;
552 struct radv_meta_state meta_state
;
553 struct radv_queue queue
;
554 struct radeon_winsys_cs
*empty_cs
;
556 bool allow_fast_clears
;
559 /* MSAA sample locations.
560 * The first index is the sample index.
561 * The second index is the coordinate: X, Y. */
562 float sample_locations_1x
[1][2];
563 float sample_locations_2x
[2][2];
564 float sample_locations_4x
[4][2];
565 float sample_locations_8x
[8][2];
566 float sample_locations_16x
[16][2];
569 void radv_device_get_cache_uuid(void *uuid
);
571 struct radv_device_memory
{
572 struct radeon_winsys_bo
*bo
;
574 VkDeviceSize map_size
;
579 struct radv_descriptor_range
{
584 struct radv_descriptor_set
{
585 const struct radv_descriptor_set_layout
*layout
;
586 struct list_head descriptor_pool
;
589 struct radv_buffer_view
*buffer_views
;
590 struct radeon_winsys_bo
*bo
;
592 uint32_t *mapped_ptr
;
593 struct radv_descriptor_range
*dynamic_descriptors
;
594 struct radeon_winsys_bo
*descriptors
[0];
597 struct radv_descriptor_pool_free_node
{
603 struct radv_descriptor_pool
{
604 struct list_head descriptor_sets
;
606 struct radeon_winsys_bo
*bo
;
608 uint64_t current_offset
;
614 struct radv_descriptor_pool_free_node free_nodes
[];
618 struct radv_device
* device
;
621 VkBufferUsageFlags usage
;
624 struct radeon_winsys_bo
* bo
;
629 enum radv_cmd_dirty_bits
{
630 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
631 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
632 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
633 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
634 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
635 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
636 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
637 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
638 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
639 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
640 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
641 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
642 RADV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
644 typedef uint32_t radv_cmd_dirty_mask_t
;
646 enum radv_cmd_flush_bits
{
647 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
648 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
649 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
650 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
651 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
652 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
653 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
654 /* Framebuffer caches */
655 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 4,
656 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 5,
657 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 6,
658 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 7,
659 /* Engine synchronization. */
660 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 8,
661 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 9,
662 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 10,
663 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 11,
665 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
666 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
667 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
668 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
671 struct radv_vertex_binding
{
672 struct radv_buffer
* buffer
;
676 struct radv_dynamic_state
{
679 VkViewport viewports
[MAX_VIEWPORTS
];
684 VkRect2D scissors
[MAX_SCISSORS
];
695 float blend_constants
[4];
705 } stencil_compare_mask
;
710 } stencil_write_mask
;
718 extern const struct radv_dynamic_state default_dynamic_state
;
720 void radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
721 const struct radv_dynamic_state
*src
,
724 * Attachment state when recording a renderpass instance.
726 * The clear value is valid only if there exists a pending clear.
728 struct radv_attachment_state
{
729 VkImageAspectFlags pending_clear_aspects
;
730 VkClearValue clear_value
;
731 VkImageLayout current_layout
;
734 struct radv_cmd_state
{
736 bool vertex_descriptors_dirty
;
737 radv_cmd_dirty_mask_t dirty
;
739 struct radv_pipeline
* pipeline
;
740 struct radv_pipeline
* emitted_pipeline
;
741 struct radv_pipeline
* compute_pipeline
;
742 struct radv_pipeline
* emitted_compute_pipeline
;
743 struct radv_framebuffer
* framebuffer
;
744 struct radv_render_pass
* pass
;
745 const struct radv_subpass
* subpass
;
746 struct radv_dynamic_state dynamic
;
747 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
748 struct radv_descriptor_set
* descriptors
[MAX_SETS
];
749 struct radv_attachment_state
* attachments
;
750 VkRect2D render_area
;
751 struct radv_buffer
* index_buffer
;
753 uint32_t index_offset
;
754 uint32_t last_primitive_reset_index
;
755 enum radv_cmd_flush_bits flush_bits
;
756 unsigned active_occlusion_queries
;
759 struct radv_cmd_pool
{
760 VkAllocationCallbacks alloc
;
761 struct list_head cmd_buffers
;
764 struct radv_cmd_buffer_upload
{
768 struct radeon_winsys_bo
*upload_bo
;
769 struct list_head list
;
772 struct radv_cmd_buffer
{
773 VK_LOADER_DATA _loader_data
;
775 struct radv_device
* device
;
777 struct radv_cmd_pool
* pool
;
778 struct list_head pool_link
;
780 VkCommandBufferUsageFlags usage_flags
;
781 VkCommandBufferLevel level
;
782 struct radeon_winsys_cs
*cs
;
783 struct radv_cmd_state state
;
785 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
786 uint32_t dynamic_buffers
[16 * MAX_DYNAMIC_BUFFERS
];
787 VkShaderStageFlags push_constant_stages
;
789 struct radv_cmd_buffer_upload upload
;
796 void si_init_config(struct radv_physical_device
*physical_device
,
797 struct radv_cmd_buffer
*cmd_buffer
);
798 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
799 int count
, const VkViewport
*viewports
);
800 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
801 int count
, const VkRect2D
*scissors
);
802 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
);
803 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
804 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
805 uint64_t src_va
, uint64_t dest_va
,
807 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
808 uint64_t size
, unsigned value
);
809 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
810 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
811 struct radv_descriptor_set
*set
,
814 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
817 unsigned *out_offset
,
820 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
821 const struct radv_subpass
*subpass
,
824 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
825 unsigned size
, unsigned alignmnet
,
826 const void *data
, unsigned *out_offset
);
828 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
829 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
830 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
831 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
832 unsigned radv_cayman_get_maxdist(int log_samples
);
833 void radv_device_init_msaa(struct radv_device
*device
);
834 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
835 struct radv_image
*image
,
836 VkClearDepthStencilValue ds_clear_value
,
837 VkImageAspectFlags aspects
);
838 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
839 struct radv_image
*image
,
841 uint32_t color_values
[2]);
842 void radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
843 struct radeon_winsys_bo
*bo
,
844 uint64_t offset
, uint64_t size
, uint32_t value
);
847 * Takes x,y,z as exact numbers of invocations, instead of blocks.
849 * Limitations: Can't call normal dispatch functions without binding or rebinding
850 * the compute pipeline.
852 void radv_unaligned_dispatch(
853 struct radv_cmd_buffer
*cmd_buffer
,
859 struct radeon_winsys_bo
*bo
;
865 struct radv_shader_module
{
866 struct nir_shader
* nir
;
867 unsigned char sha1
[20];
872 union ac_shader_variant_key
;
875 radv_hash_shader(unsigned char *hash
, struct radv_shader_module
*module
,
876 const char *entrypoint
,
877 const VkSpecializationInfo
*spec_info
,
878 const struct radv_pipeline_layout
*layout
,
879 const union ac_shader_variant_key
*key
);
881 static inline gl_shader_stage
882 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
884 assert(__builtin_popcount(vk_stage
) == 1);
885 return ffs(vk_stage
) - 1;
888 static inline VkShaderStageFlagBits
889 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
891 return (1 << mesa_stage
);
894 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
896 #define radv_foreach_stage(stage, stage_bits) \
897 for (gl_shader_stage stage, \
898 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
899 stage = __builtin_ffs(__tmp) - 1, __tmp; \
900 __tmp &= ~(1 << (stage)))
902 struct radv_shader_variant
{
905 struct radeon_winsys_bo
*bo
;
906 struct ac_shader_config config
;
907 struct ac_shader_variant_info info
;
912 struct radv_depth_stencil_state
{
913 uint32_t db_depth_control
;
914 uint32_t db_stencil_control
;
915 uint32_t db_render_control
;
916 uint32_t db_render_override2
;
919 struct radv_blend_state
{
920 uint32_t cb_color_control
;
921 uint32_t cb_target_mask
;
922 uint32_t sx_mrt0_blend_opt
[8];
923 uint32_t cb_blend_control
[8];
925 uint32_t spi_shader_col_format
;
926 uint32_t cb_shader_mask
;
927 uint32_t db_alpha_to_mask
;
930 unsigned radv_format_meta_fs_key(VkFormat format
);
932 struct radv_raster_state
{
933 uint32_t pa_cl_clip_cntl
;
934 uint32_t pa_cl_vs_out_cntl
;
935 uint32_t spi_interp_control
;
936 uint32_t pa_su_point_size
;
937 uint32_t pa_su_point_minmax
;
938 uint32_t pa_su_line_cntl
;
939 uint32_t pa_su_vtx_cntl
;
940 uint32_t pa_su_sc_mode_cntl
;
943 struct radv_multisample_state
{
945 uint32_t pa_sc_line_cntl
;
946 uint32_t pa_sc_mode_cntl_0
;
947 uint32_t pa_sc_mode_cntl_1
;
948 uint32_t pa_sc_aa_config
;
949 uint32_t pa_sc_aa_mask
[2];
950 unsigned num_samples
;
953 struct radv_pipeline
{
954 struct radv_device
* device
;
955 uint32_t dynamic_state_mask
;
956 struct radv_dynamic_state dynamic_state
;
958 struct radv_pipeline_layout
* layout
;
960 bool needs_data_cache
;
962 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
963 VkShaderStageFlags active_stages
;
965 uint32_t va_rsrc_word3
[MAX_VERTEX_ATTRIBS
];
966 uint32_t va_format_size
[MAX_VERTEX_ATTRIBS
];
967 uint32_t va_binding
[MAX_VERTEX_ATTRIBS
];
968 uint32_t va_offset
[MAX_VERTEX_ATTRIBS
];
969 uint32_t num_vertex_attribs
;
970 uint32_t binding_stride
[MAX_VBS
];
974 struct radv_blend_state blend
;
975 struct radv_depth_stencil_state ds
;
976 struct radv_raster_state raster
;
977 struct radv_multisample_state ms
;
980 bool prim_restart_enable
;
985 struct radv_graphics_pipeline_create_info
{
988 bool db_stencil_clear
;
989 bool db_depth_disable_expclear
;
990 bool db_stencil_disable_expclear
;
991 bool db_flush_depth_inplace
;
992 bool db_flush_stencil_inplace
;
994 uint32_t custom_blend_mode
;
998 radv_pipeline_init(struct radv_pipeline
*pipeline
, struct radv_device
*device
,
999 struct radv_pipeline_cache
*cache
,
1000 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1001 const struct radv_graphics_pipeline_create_info
*extra
,
1002 const VkAllocationCallbacks
*alloc
);
1005 radv_graphics_pipeline_create(VkDevice device
,
1006 VkPipelineCache cache
,
1007 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1008 const struct radv_graphics_pipeline_create_info
*extra
,
1009 const VkAllocationCallbacks
*alloc
,
1010 VkPipeline
*pPipeline
);
1012 struct vk_format_description
;
1013 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1014 int first_non_void
);
1015 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1016 int first_non_void
);
1017 uint32_t radv_translate_colorformat(VkFormat format
);
1018 uint32_t radv_translate_color_numformat(VkFormat format
,
1019 const struct vk_format_description
*desc
,
1020 int first_non_void
);
1021 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1022 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1023 uint32_t radv_translate_dbformat(VkFormat format
);
1024 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1025 const struct vk_format_description
*desc
,
1026 int first_non_void
);
1027 uint32_t radv_translate_tex_numformat(VkFormat format
,
1028 const struct vk_format_description
*desc
,
1029 int first_non_void
);
1030 bool radv_format_pack_clear_color(VkFormat format
,
1031 uint32_t clear_vals
[2],
1032 VkClearColorValue
*value
);
1033 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1035 struct radv_fmask_info
{
1039 unsigned pitch_in_pixels
;
1040 unsigned bank_height
;
1041 unsigned slice_tile_max
;
1042 unsigned tile_mode_index
;
1045 struct radv_cmask_info
{
1053 unsigned slice_tile_max
;
1054 unsigned base_address_reg
;
1057 struct r600_htile_info
{
1068 /* The original VkFormat provided by the client. This may not match any
1069 * of the actual surface formats.
1072 VkImageAspectFlags aspects
;
1075 uint32_t array_size
;
1076 uint32_t samples
; /**< VkImageCreateInfo::samples */
1077 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1078 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1083 /* Set when bound */
1084 struct radeon_winsys_bo
*bo
;
1085 VkDeviceSize offset
;
1086 uint32_t dcc_offset
;
1087 struct radeon_surf surface
;
1089 struct radv_fmask_info fmask
;
1090 struct radv_cmask_info cmask
;
1091 uint32_t clear_value_offset
;
1093 /* Depth buffer compression and fast clear. */
1094 struct r600_htile_info htile
;
1097 bool radv_layout_has_htile(const struct radv_image
*image
,
1098 VkImageLayout layout
);
1099 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1100 VkImageLayout layout
);
1101 bool radv_layout_can_expclear(const struct radv_image
*image
,
1102 VkImageLayout layout
);
1103 bool radv_layout_has_cmask(const struct radv_image
*image
,
1104 VkImageLayout layout
);
1105 static inline uint32_t
1106 radv_get_layerCount(const struct radv_image
*image
,
1107 const VkImageSubresourceRange
*range
)
1109 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1110 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1113 static inline uint32_t
1114 radv_get_levelCount(const struct radv_image
*image
,
1115 const VkImageSubresourceRange
*range
)
1117 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1118 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1121 struct radeon_bo_metadata
;
1123 radv_init_metadata(struct radv_device
*device
,
1124 struct radv_image
*image
,
1125 struct radeon_bo_metadata
*metadata
);
1127 struct radv_image_view
{
1128 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1129 struct radeon_winsys_bo
*bo
;
1131 VkImageViewType type
;
1132 VkImageAspectFlags aspect_mask
;
1134 uint32_t base_layer
;
1135 uint32_t layer_count
;
1137 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1139 uint32_t descriptor
[8];
1140 uint32_t fmask_descriptor
[8];
1143 struct radv_image_create_info
{
1144 const VkImageCreateInfo
*vk_info
;
1149 VkResult
radv_image_create(VkDevice _device
,
1150 const struct radv_image_create_info
*info
,
1151 const VkAllocationCallbacks
* alloc
,
1154 void radv_image_view_init(struct radv_image_view
*view
,
1155 struct radv_device
*device
,
1156 const VkImageViewCreateInfo
* pCreateInfo
,
1157 struct radv_cmd_buffer
*cmd_buffer
,
1158 VkImageUsageFlags usage_mask
);
1159 void radv_image_set_optimal_micro_tile_mode(struct radv_device
*device
,
1160 struct radv_image
*image
, uint32_t micro_tile_mode
);
1161 struct radv_buffer_view
{
1162 struct radeon_winsys_bo
*bo
;
1164 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1167 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1168 struct radv_device
*device
,
1169 const VkBufferViewCreateInfo
* pCreateInfo
,
1170 struct radv_cmd_buffer
*cmd_buffer
);
1172 static inline struct VkExtent3D
1173 radv_sanitize_image_extent(const VkImageType imageType
,
1174 const struct VkExtent3D imageExtent
)
1176 switch (imageType
) {
1177 case VK_IMAGE_TYPE_1D
:
1178 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1179 case VK_IMAGE_TYPE_2D
:
1180 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1181 case VK_IMAGE_TYPE_3D
:
1184 unreachable("invalid image type");
1188 static inline struct VkOffset3D
1189 radv_sanitize_image_offset(const VkImageType imageType
,
1190 const struct VkOffset3D imageOffset
)
1192 switch (imageType
) {
1193 case VK_IMAGE_TYPE_1D
:
1194 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1195 case VK_IMAGE_TYPE_2D
:
1196 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1197 case VK_IMAGE_TYPE_3D
:
1200 unreachable("invalid image type");
1204 struct radv_sampler
{
1208 struct radv_color_buffer_info
{
1209 uint32_t cb_color_base
;
1210 uint32_t cb_color_pitch
;
1211 uint32_t cb_color_slice
;
1212 uint32_t cb_color_view
;
1213 uint32_t cb_color_info
;
1214 uint32_t cb_color_attrib
;
1215 uint32_t cb_dcc_control
;
1216 uint32_t cb_color_cmask
;
1217 uint32_t cb_color_cmask_slice
;
1218 uint32_t cb_color_fmask
;
1219 uint32_t cb_color_fmask_slice
;
1220 uint32_t cb_clear_value0
;
1221 uint32_t cb_clear_value1
;
1222 uint32_t cb_dcc_base
;
1223 uint32_t micro_tile_mode
;
1226 struct radv_ds_buffer_info
{
1227 uint32_t db_depth_info
;
1229 uint32_t db_stencil_info
;
1230 uint32_t db_z_read_base
;
1231 uint32_t db_stencil_read_base
;
1232 uint32_t db_z_write_base
;
1233 uint32_t db_stencil_write_base
;
1234 uint32_t db_depth_view
;
1235 uint32_t db_depth_size
;
1236 uint32_t db_depth_slice
;
1237 uint32_t db_htile_surface
;
1238 uint32_t db_htile_data_base
;
1239 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1243 struct radv_attachment_info
{
1245 struct radv_color_buffer_info cb
;
1246 struct radv_ds_buffer_info ds
;
1248 struct radv_image_view
*attachment
;
1251 struct radv_framebuffer
{
1256 uint32_t attachment_count
;
1257 struct radv_attachment_info attachments
[0];
1260 struct radv_subpass_barrier
{
1261 VkPipelineStageFlags src_stage_mask
;
1262 VkAccessFlags src_access_mask
;
1263 VkAccessFlags dst_access_mask
;
1266 struct radv_subpass
{
1267 uint32_t input_count
;
1268 VkAttachmentReference
* input_attachments
;
1269 uint32_t color_count
;
1270 VkAttachmentReference
* color_attachments
;
1271 VkAttachmentReference
* resolve_attachments
;
1272 VkAttachmentReference depth_stencil_attachment
;
1274 /** Subpass has at least one resolve attachment */
1277 struct radv_subpass_barrier start_barrier
;
1280 struct radv_render_pass_attachment
{
1283 VkAttachmentLoadOp load_op
;
1284 VkAttachmentLoadOp stencil_load_op
;
1285 VkImageLayout initial_layout
;
1286 VkImageLayout final_layout
;
1289 struct radv_render_pass
{
1290 uint32_t attachment_count
;
1291 uint32_t subpass_count
;
1292 VkAttachmentReference
* subpass_attachments
;
1293 struct radv_render_pass_attachment
* attachments
;
1294 struct radv_subpass_barrier end_barrier
;
1295 struct radv_subpass subpasses
[0];
1298 VkResult
radv_device_init_meta(struct radv_device
*device
);
1299 void radv_device_finish_meta(struct radv_device
*device
);
1301 struct radv_query_pool
{
1302 struct radeon_winsys_bo
*bo
;
1304 uint32_t availability_offset
;
1310 radv_temp_descriptor_set_create(struct radv_device
*device
,
1311 struct radv_cmd_buffer
*cmd_buffer
,
1312 VkDescriptorSetLayout _layout
,
1313 VkDescriptorSet
*_set
);
1316 radv_temp_descriptor_set_destroy(struct radv_device
*device
,
1317 VkDescriptorSet _set
);
1318 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1319 struct radv_image
*image
, uint32_t value
);
1320 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1321 struct radv_image
*image
, uint32_t value
);
1322 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1324 static inline struct __radv_type * \
1325 __radv_type ## _from_handle(__VkType _handle) \
1327 return (struct __radv_type *) _handle; \
1330 static inline __VkType \
1331 __radv_type ## _to_handle(struct __radv_type *_obj) \
1333 return (__VkType) _obj; \
1336 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1338 static inline struct __radv_type * \
1339 __radv_type ## _from_handle(__VkType _handle) \
1341 return (struct __radv_type *)(uintptr_t) _handle; \
1344 static inline __VkType \
1345 __radv_type ## _to_handle(struct __radv_type *_obj) \
1347 return (__VkType)(uintptr_t) _obj; \
1350 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1351 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1353 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1354 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1355 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1356 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1357 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1359 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1360 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1361 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1362 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1363 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1364 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1365 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1366 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1367 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1368 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1369 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1370 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1371 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1372 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1373 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1374 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1375 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1376 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1377 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1379 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1381 static inline const __VkType * \
1382 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1384 return (const __VkType *) __radv_obj; \
1387 #define RADV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1388 const __VkType *__vk_name = radv_common_to_ ## __VkType(__common_name)
1390 RADV_DEFINE_STRUCT_CASTS(radv_common
, VkMemoryBarrier
)
1391 RADV_DEFINE_STRUCT_CASTS(radv_common
, VkBufferMemoryBarrier
)
1392 RADV_DEFINE_STRUCT_CASTS(radv_common
, VkImageMemoryBarrier
)
1395 #endif /* RADV_PRIVATE_H */