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radv: emit geometry ring size and pointers via preamble (v2)
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_SAMPLES_LOG2 4
83 #define NUM_META_FS_KEYS 11
84 #define RADV_MAX_DRM_DEVICES 8
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 enum radv_mem_heap {
89 RADV_MEM_HEAP_VRAM,
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
91 RADV_MEM_HEAP_GTT,
92 RADV_MEM_HEAP_COUNT
93 };
94
95 enum radv_mem_type {
96 RADV_MEM_TYPE_VRAM,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
99 RADV_MEM_TYPE_GTT_CACHED,
100 RADV_MEM_TYPE_COUNT
101 };
102
103
104 enum {
105 RADV_DEBUG_FAST_CLEARS = 0x1,
106 RADV_DEBUG_NO_DCC = 0x2,
107 RADV_DEBUG_DUMP_SHADERS = 0x4,
108 RADV_DEBUG_NO_CACHE = 0x8,
109 RADV_DEBUG_DUMP_SHADER_STATS = 0x10,
110 RADV_DEBUG_NO_HIZ = 0x20,
111 RADV_DEBUG_NO_COMPUTE_QUEUE = 0x40,
112 RADV_DEBUG_UNSAFE_MATH = 0x80,
113 };
114
115 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
116
117 static inline uint32_t
118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint32_t
125 align_u32_npot(uint32_t v, uint32_t a)
126 {
127 return (v + a - 1) / a * a;
128 }
129
130 static inline uint64_t
131 align_u64(uint64_t v, uint64_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline int32_t
138 align_i32(int32_t v, int32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 /** Alignment must be a power of 2. */
145 static inline bool
146 radv_is_aligned(uintmax_t n, uintmax_t a)
147 {
148 assert(a == (a & -a));
149 return (n & (a - 1)) == 0;
150 }
151
152 static inline uint32_t
153 round_up_u32(uint32_t v, uint32_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint64_t
159 round_up_u64(uint64_t v, uint64_t a)
160 {
161 return (v + a - 1) / a;
162 }
163
164 static inline uint32_t
165 radv_minify(uint32_t n, uint32_t levels)
166 {
167 if (unlikely(n == 0))
168 return 0;
169 else
170 return MAX2(n >> levels, 1);
171 }
172 static inline float
173 radv_clamp_f(float f, float min, float max)
174 {
175 assert(min < max);
176
177 if (f > max)
178 return max;
179 else if (f < min)
180 return min;
181 else
182 return f;
183 }
184
185 static inline bool
186 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
187 {
188 if (*inout_mask & clear_mask) {
189 *inout_mask &= ~clear_mask;
190 return true;
191 } else {
192 return false;
193 }
194 }
195
196 #define for_each_bit(b, dword) \
197 for (uint32_t __dword = (dword); \
198 (b) = __builtin_ffs(__dword) - 1, __dword; \
199 __dword &= ~(1 << (b)))
200
201 #define typed_memcpy(dest, src, count) ({ \
202 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
203 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 })
205
206 #define zero(x) (memset(&(x), 0, sizeof(x)))
207
208 /* Whenever we generate an error, pass it through this function. Useful for
209 * debugging, where we can break on it. Only call at error site, not when
210 * propagating errors. Might be useful to plug in a stack trace here.
211 */
212
213 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
214
215 #ifdef DEBUG
216 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
217 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
218 #else
219 #define vk_error(error) error
220 #define vk_errorf(error, format, ...) error
221 #endif
222
223 void __radv_finishme(const char *file, int line, const char *format, ...)
224 radv_printflike(3, 4);
225 void radv_loge(const char *format, ...) radv_printflike(1, 2);
226 void radv_loge_v(const char *format, va_list va);
227
228 /**
229 * Print a FINISHME message, including its source location.
230 */
231 #define radv_finishme(format, ...) \
232 do { \
233 static bool reported = false; \
234 if (!reported) { \
235 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 reported = true; \
237 } \
238 } while (0)
239
240 /* A non-fatal assert. Useful for debugging. */
241 #ifdef DEBUG
242 #define radv_assert(x) ({ \
243 if (unlikely(!(x))) \
244 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
245 })
246 #else
247 #define radv_assert(x)
248 #endif
249
250 #define stub_return(v) \
251 do { \
252 radv_finishme("stub %s", __func__); \
253 return (v); \
254 } while (0)
255
256 #define stub() \
257 do { \
258 radv_finishme("stub %s", __func__); \
259 return; \
260 } while (0)
261
262 void *radv_resolve_entrypoint(uint32_t index);
263 void *radv_lookup_entrypoint(const char *name);
264
265 extern struct radv_dispatch_table dtable;
266
267 struct radv_extensions {
268 VkExtensionProperties *ext_array;
269 uint32_t num_ext;
270 };
271
272 struct radv_physical_device {
273 VK_LOADER_DATA _loader_data;
274
275 struct radv_instance * instance;
276
277 struct radeon_winsys *ws;
278 struct radeon_info rad_info;
279 char path[20];
280 const char * name;
281 uint8_t uuid[VK_UUID_SIZE];
282
283 struct wsi_device wsi_device;
284 struct radv_extensions extensions;
285 };
286
287 struct radv_instance {
288 VK_LOADER_DATA _loader_data;
289
290 VkAllocationCallbacks alloc;
291
292 uint32_t apiVersion;
293 int physicalDeviceCount;
294 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
295
296 uint64_t debug_flags;
297 };
298
299 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
300 void radv_finish_wsi(struct radv_physical_device *physical_device);
301
302 struct cache_entry;
303
304 struct radv_pipeline_cache {
305 struct radv_device * device;
306 pthread_mutex_t mutex;
307
308 uint32_t total_size;
309 uint32_t table_size;
310 uint32_t kernel_count;
311 struct cache_entry ** hash_table;
312 bool modified;
313
314 VkAllocationCallbacks alloc;
315 };
316
317 void
318 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
319 struct radv_device *device);
320 void
321 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
322 void
323 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
324 const void *data, size_t size);
325
326 struct radv_shader_variant *
327 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
328 struct radv_pipeline_cache *cache,
329 const unsigned char *sha1);
330
331 struct radv_shader_variant *
332 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
333 const unsigned char *sha1,
334 struct radv_shader_variant *variant,
335 const void *code, unsigned code_size);
336
337 void radv_shader_variant_destroy(struct radv_device *device,
338 struct radv_shader_variant *variant);
339
340 struct radv_meta_state {
341 VkAllocationCallbacks alloc;
342
343 struct radv_pipeline_cache cache;
344
345 /**
346 * Use array element `i` for images with `2^i` samples.
347 */
348 struct {
349 VkRenderPass render_pass[NUM_META_FS_KEYS];
350 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
351
352 VkRenderPass depthstencil_rp;
353 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
354 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
355 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
356 } clear[1 + MAX_SAMPLES_LOG2];
357
358 struct {
359 VkRenderPass render_pass[NUM_META_FS_KEYS];
360
361 /** Pipeline that blits from a 1D image. */
362 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
363
364 /** Pipeline that blits from a 2D image. */
365 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
366
367 /** Pipeline that blits from a 3D image. */
368 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
369
370 VkRenderPass depth_only_rp;
371 VkPipeline depth_only_1d_pipeline;
372 VkPipeline depth_only_2d_pipeline;
373 VkPipeline depth_only_3d_pipeline;
374
375 VkRenderPass stencil_only_rp;
376 VkPipeline stencil_only_1d_pipeline;
377 VkPipeline stencil_only_2d_pipeline;
378 VkPipeline stencil_only_3d_pipeline;
379 VkPipelineLayout pipeline_layout;
380 VkDescriptorSetLayout ds_layout;
381 } blit;
382
383 struct {
384 VkRenderPass render_passes[NUM_META_FS_KEYS];
385
386 VkPipelineLayout p_layouts[2];
387 VkDescriptorSetLayout ds_layouts[2];
388 VkPipeline pipelines[2][NUM_META_FS_KEYS];
389
390 VkRenderPass depth_only_rp;
391 VkPipeline depth_only_pipeline[2];
392
393 VkRenderPass stencil_only_rp;
394 VkPipeline stencil_only_pipeline[2];
395 } blit2d;
396
397 struct {
398 VkPipelineLayout img_p_layout;
399 VkDescriptorSetLayout img_ds_layout;
400 VkPipeline pipeline;
401 } itob;
402 struct {
403 VkRenderPass render_pass;
404 VkPipelineLayout img_p_layout;
405 VkDescriptorSetLayout img_ds_layout;
406 VkPipeline pipeline;
407 } btoi;
408 struct {
409 VkPipelineLayout img_p_layout;
410 VkDescriptorSetLayout img_ds_layout;
411 VkPipeline pipeline;
412 } itoi;
413 struct {
414 VkPipelineLayout img_p_layout;
415 VkDescriptorSetLayout img_ds_layout;
416 VkPipeline pipeline;
417 } cleari;
418
419 struct {
420 VkPipeline pipeline;
421 VkRenderPass pass;
422 } resolve;
423
424 struct {
425 VkDescriptorSetLayout ds_layout;
426 VkPipelineLayout p_layout;
427 struct {
428 VkPipeline pipeline;
429 VkPipeline i_pipeline;
430 } rc[MAX_SAMPLES_LOG2];
431 } resolve_compute;
432
433 struct {
434 VkPipeline decompress_pipeline;
435 VkPipeline resummarize_pipeline;
436 VkRenderPass pass;
437 } depth_decomp;
438
439 struct {
440 VkPipeline cmask_eliminate_pipeline;
441 VkPipeline fmask_decompress_pipeline;
442 VkRenderPass pass;
443 } fast_clear_flush;
444
445 struct {
446 VkPipelineLayout fill_p_layout;
447 VkPipelineLayout copy_p_layout;
448 VkDescriptorSetLayout fill_ds_layout;
449 VkDescriptorSetLayout copy_ds_layout;
450 VkPipeline fill_pipeline;
451 VkPipeline copy_pipeline;
452 } buffer;
453 };
454
455 /* queue types */
456 #define RADV_QUEUE_GENERAL 0
457 #define RADV_QUEUE_COMPUTE 1
458 #define RADV_QUEUE_TRANSFER 2
459
460 #define RADV_MAX_QUEUE_FAMILIES 3
461
462 enum ring_type radv_queue_family_to_ring(int f);
463
464 struct radv_queue {
465 VK_LOADER_DATA _loader_data;
466 struct radv_device * device;
467 struct radeon_winsys_ctx *hw_ctx;
468 int queue_family_index;
469 int queue_idx;
470
471 uint32_t scratch_size;
472 uint32_t compute_scratch_size;
473 uint32_t esgs_ring_size;
474 uint32_t gsvs_ring_size;
475
476 struct radeon_winsys_bo *scratch_bo;
477 struct radeon_winsys_bo *descriptor_bo;
478 struct radeon_winsys_bo *compute_scratch_bo;
479 struct radeon_winsys_bo *esgs_ring_bo;
480 struct radeon_winsys_bo *gsvs_ring_bo;
481 struct radeon_winsys_cs *preamble_cs;
482 };
483
484 struct radv_device {
485 VK_LOADER_DATA _loader_data;
486
487 VkAllocationCallbacks alloc;
488
489 struct radv_instance * instance;
490 struct radeon_winsys *ws;
491
492 struct radv_meta_state meta_state;
493
494 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
495 int queue_count[RADV_MAX_QUEUE_FAMILIES];
496 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
497
498 uint64_t debug_flags;
499
500 bool llvm_supports_spill;
501 uint32_t scratch_waves;
502
503 uint32_t gs_table_depth;
504
505 /* MSAA sample locations.
506 * The first index is the sample index.
507 * The second index is the coordinate: X, Y. */
508 float sample_locations_1x[1][2];
509 float sample_locations_2x[2][2];
510 float sample_locations_4x[4][2];
511 float sample_locations_8x[8][2];
512 float sample_locations_16x[16][2];
513
514 struct radeon_winsys_bo *trace_bo;
515 uint32_t *trace_id_ptr;
516
517 struct radv_physical_device *physical_device;
518 };
519
520 struct radv_device_memory {
521 struct radeon_winsys_bo *bo;
522 uint32_t type_index;
523 VkDeviceSize map_size;
524 void * map;
525 };
526
527
528 struct radv_descriptor_range {
529 uint64_t va;
530 uint32_t size;
531 };
532
533 struct radv_descriptor_set {
534 const struct radv_descriptor_set_layout *layout;
535 struct list_head descriptor_pool;
536 uint32_t size;
537
538 struct radv_buffer_view *buffer_views;
539 struct radeon_winsys_bo *bo;
540 uint64_t va;
541 uint32_t *mapped_ptr;
542 struct radv_descriptor_range *dynamic_descriptors;
543 struct radeon_winsys_bo *descriptors[0];
544 };
545
546 struct radv_descriptor_pool_free_node {
547 int next;
548 uint32_t offset;
549 uint32_t size;
550 };
551
552 struct radv_descriptor_pool {
553 struct list_head descriptor_sets;
554
555 struct radeon_winsys_bo *bo;
556 uint8_t *mapped_ptr;
557 uint64_t current_offset;
558 uint64_t size;
559
560 int free_list;
561 int full_list;
562 uint32_t max_sets;
563 struct radv_descriptor_pool_free_node free_nodes[];
564 };
565
566 struct radv_buffer {
567 struct radv_device * device;
568 VkDeviceSize size;
569
570 VkBufferUsageFlags usage;
571
572 /* Set when bound */
573 struct radeon_winsys_bo * bo;
574 VkDeviceSize offset;
575 };
576
577
578 enum radv_cmd_dirty_bits {
579 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
580 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
581 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
582 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
583 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
584 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
585 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
586 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
587 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
588 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
589 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
590 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
591 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
592 };
593 typedef uint32_t radv_cmd_dirty_mask_t;
594
595 enum radv_cmd_flush_bits {
596 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
597 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
598 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
599 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
600 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
601 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
602 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
603 /* Framebuffer caches */
604 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
605 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
606 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
607 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
608 /* Engine synchronization. */
609 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
610 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
611 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
612 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
613
614 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
615 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
616 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
617 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
618 };
619
620 struct radv_vertex_binding {
621 struct radv_buffer * buffer;
622 VkDeviceSize offset;
623 };
624
625 struct radv_dynamic_state {
626 struct {
627 uint32_t count;
628 VkViewport viewports[MAX_VIEWPORTS];
629 } viewport;
630
631 struct {
632 uint32_t count;
633 VkRect2D scissors[MAX_SCISSORS];
634 } scissor;
635
636 float line_width;
637
638 struct {
639 float bias;
640 float clamp;
641 float slope;
642 } depth_bias;
643
644 float blend_constants[4];
645
646 struct {
647 float min;
648 float max;
649 } depth_bounds;
650
651 struct {
652 uint32_t front;
653 uint32_t back;
654 } stencil_compare_mask;
655
656 struct {
657 uint32_t front;
658 uint32_t back;
659 } stencil_write_mask;
660
661 struct {
662 uint32_t front;
663 uint32_t back;
664 } stencil_reference;
665 };
666
667 extern const struct radv_dynamic_state default_dynamic_state;
668
669 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
670 const struct radv_dynamic_state *src,
671 uint32_t copy_mask);
672 /**
673 * Attachment state when recording a renderpass instance.
674 *
675 * The clear value is valid only if there exists a pending clear.
676 */
677 struct radv_attachment_state {
678 VkImageAspectFlags pending_clear_aspects;
679 VkClearValue clear_value;
680 VkImageLayout current_layout;
681 };
682
683 struct radv_cmd_state {
684 uint32_t vb_dirty;
685 bool vertex_descriptors_dirty;
686 radv_cmd_dirty_mask_t dirty;
687
688 struct radv_pipeline * pipeline;
689 struct radv_pipeline * emitted_pipeline;
690 struct radv_pipeline * compute_pipeline;
691 struct radv_pipeline * emitted_compute_pipeline;
692 struct radv_framebuffer * framebuffer;
693 struct radv_render_pass * pass;
694 const struct radv_subpass * subpass;
695 struct radv_dynamic_state dynamic;
696 struct radv_vertex_binding vertex_bindings[MAX_VBS];
697 struct radv_descriptor_set * descriptors[MAX_SETS];
698 struct radv_attachment_state * attachments;
699 VkRect2D render_area;
700 struct radv_buffer * index_buffer;
701 uint32_t index_type;
702 uint32_t index_offset;
703 uint32_t last_primitive_reset_index;
704 enum radv_cmd_flush_bits flush_bits;
705 unsigned active_occlusion_queries;
706 float offset_scale;
707 uint32_t descriptors_dirty;
708 uint32_t trace_id;
709 };
710
711 struct radv_cmd_pool {
712 VkAllocationCallbacks alloc;
713 struct list_head cmd_buffers;
714 uint32_t queue_family_index;
715 };
716
717 struct radv_cmd_buffer_upload {
718 uint8_t *map;
719 unsigned offset;
720 uint64_t size;
721 struct radeon_winsys_bo *upload_bo;
722 struct list_head list;
723 };
724
725 struct radv_cmd_buffer {
726 VK_LOADER_DATA _loader_data;
727
728 struct radv_device * device;
729
730 struct radv_cmd_pool * pool;
731 struct list_head pool_link;
732
733 VkCommandBufferUsageFlags usage_flags;
734 VkCommandBufferLevel level;
735 struct radeon_winsys_cs *cs;
736 struct radv_cmd_state state;
737 uint32_t queue_family_index;
738
739 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
740 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
741 VkShaderStageFlags push_constant_stages;
742
743 struct radv_cmd_buffer_upload upload;
744
745 bool record_fail;
746
747 uint32_t scratch_size_needed;
748 uint32_t compute_scratch_size_needed;
749 uint32_t esgs_ring_size_needed;
750 uint32_t gsvs_ring_size_needed;
751
752 int ring_offsets_idx; /* just used for verification */
753 };
754
755 struct radv_image;
756
757 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
758
759 void si_init_compute(struct radv_physical_device *physical_device,
760 struct radv_cmd_buffer *cmd_buffer);
761 void si_init_config(struct radv_physical_device *physical_device,
762 struct radv_cmd_buffer *cmd_buffer);
763 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
764 int count, const VkViewport *viewports);
765 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
766 int count, const VkRect2D *scissors);
767 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
768 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
769 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
770 uint64_t src_va, uint64_t dest_va,
771 uint64_t size);
772 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
773 uint64_t size, unsigned value);
774 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
775 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
776 struct radv_descriptor_set *set,
777 unsigned idx);
778 bool
779 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
780 unsigned size,
781 unsigned alignment,
782 unsigned *out_offset,
783 void **ptr);
784 void
785 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
786 const struct radv_subpass *subpass,
787 bool transitions);
788 bool
789 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
790 unsigned size, unsigned alignmnet,
791 const void *data, unsigned *out_offset);
792 void
793 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
794 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
795 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
796 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
797 unsigned radv_cayman_get_maxdist(int log_samples);
798 void radv_device_init_msaa(struct radv_device *device);
799 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
800 struct radv_image *image,
801 VkClearDepthStencilValue ds_clear_value,
802 VkImageAspectFlags aspects);
803 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
804 struct radv_image *image,
805 int idx,
806 uint32_t color_values[2]);
807 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
808 struct radeon_winsys_bo *bo,
809 uint64_t offset, uint64_t size, uint32_t value);
810 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
811
812 /*
813 * Takes x,y,z as exact numbers of invocations, instead of blocks.
814 *
815 * Limitations: Can't call normal dispatch functions without binding or rebinding
816 * the compute pipeline.
817 */
818 void radv_unaligned_dispatch(
819 struct radv_cmd_buffer *cmd_buffer,
820 uint32_t x,
821 uint32_t y,
822 uint32_t z);
823
824 struct radv_event {
825 struct radeon_winsys_bo *bo;
826 uint64_t *map;
827 };
828
829 struct nir_shader;
830
831 struct radv_shader_module {
832 struct nir_shader * nir;
833 unsigned char sha1[20];
834 uint32_t size;
835 char data[0];
836 };
837
838 union ac_shader_variant_key;
839
840 void
841 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
842 const char *entrypoint,
843 const VkSpecializationInfo *spec_info,
844 const struct radv_pipeline_layout *layout,
845 const union ac_shader_variant_key *key,
846 uint32_t is_geom_copy_shader);
847
848 static inline gl_shader_stage
849 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
850 {
851 assert(__builtin_popcount(vk_stage) == 1);
852 return ffs(vk_stage) - 1;
853 }
854
855 static inline VkShaderStageFlagBits
856 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
857 {
858 return (1 << mesa_stage);
859 }
860
861 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
862
863 #define radv_foreach_stage(stage, stage_bits) \
864 for (gl_shader_stage stage, \
865 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
866 stage = __builtin_ffs(__tmp) - 1, __tmp; \
867 __tmp &= ~(1 << (stage)))
868
869 struct radv_shader_variant {
870 uint32_t ref_count;
871
872 struct radeon_winsys_bo *bo;
873 struct ac_shader_config config;
874 struct ac_shader_variant_info info;
875 unsigned rsrc1;
876 unsigned rsrc2;
877 uint32_t code_size;
878 };
879
880 struct radv_depth_stencil_state {
881 uint32_t db_depth_control;
882 uint32_t db_stencil_control;
883 uint32_t db_render_control;
884 uint32_t db_render_override2;
885 };
886
887 struct radv_blend_state {
888 uint32_t cb_color_control;
889 uint32_t cb_target_mask;
890 uint32_t sx_mrt0_blend_opt[8];
891 uint32_t cb_blend_control[8];
892
893 uint32_t spi_shader_col_format;
894 uint32_t cb_shader_mask;
895 uint32_t db_alpha_to_mask;
896 };
897
898 unsigned radv_format_meta_fs_key(VkFormat format);
899
900 struct radv_raster_state {
901 uint32_t pa_cl_clip_cntl;
902 uint32_t pa_cl_vs_out_cntl;
903 uint32_t spi_interp_control;
904 uint32_t pa_su_point_size;
905 uint32_t pa_su_point_minmax;
906 uint32_t pa_su_line_cntl;
907 uint32_t pa_su_vtx_cntl;
908 uint32_t pa_su_sc_mode_cntl;
909 };
910
911 struct radv_multisample_state {
912 uint32_t db_eqaa;
913 uint32_t pa_sc_line_cntl;
914 uint32_t pa_sc_mode_cntl_0;
915 uint32_t pa_sc_mode_cntl_1;
916 uint32_t pa_sc_aa_config;
917 uint32_t pa_sc_aa_mask[2];
918 unsigned num_samples;
919 };
920
921 struct radv_pipeline {
922 struct radv_device * device;
923 uint32_t dynamic_state_mask;
924 struct radv_dynamic_state dynamic_state;
925
926 struct radv_pipeline_layout * layout;
927
928 bool needs_data_cache;
929
930 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
931 struct radv_shader_variant *gs_copy_shader;
932 VkShaderStageFlags active_stages;
933
934 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
935 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
936 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
937 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
938 uint32_t num_vertex_attribs;
939 uint32_t binding_stride[MAX_VBS];
940
941 union {
942 struct {
943 struct radv_blend_state blend;
944 struct radv_depth_stencil_state ds;
945 struct radv_raster_state raster;
946 struct radv_multisample_state ms;
947 unsigned prim;
948 unsigned gs_out;
949 bool prim_restart_enable;
950 unsigned esgs_ring_size;
951 unsigned gsvs_ring_size;
952 } graphics;
953 };
954
955 unsigned max_waves;
956 unsigned scratch_bytes_per_wave;
957 };
958
959 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
960 {
961 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
962 }
963
964 struct radv_graphics_pipeline_create_info {
965 bool use_rectlist;
966 bool db_depth_clear;
967 bool db_stencil_clear;
968 bool db_depth_disable_expclear;
969 bool db_stencil_disable_expclear;
970 bool db_flush_depth_inplace;
971 bool db_flush_stencil_inplace;
972 bool db_resummarize;
973 uint32_t custom_blend_mode;
974 };
975
976 VkResult
977 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
978 struct radv_pipeline_cache *cache,
979 const VkGraphicsPipelineCreateInfo *pCreateInfo,
980 const struct radv_graphics_pipeline_create_info *extra,
981 const VkAllocationCallbacks *alloc);
982
983 VkResult
984 radv_graphics_pipeline_create(VkDevice device,
985 VkPipelineCache cache,
986 const VkGraphicsPipelineCreateInfo *pCreateInfo,
987 const struct radv_graphics_pipeline_create_info *extra,
988 const VkAllocationCallbacks *alloc,
989 VkPipeline *pPipeline);
990
991 struct vk_format_description;
992 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
993 int first_non_void);
994 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
995 int first_non_void);
996 uint32_t radv_translate_colorformat(VkFormat format);
997 uint32_t radv_translate_color_numformat(VkFormat format,
998 const struct vk_format_description *desc,
999 int first_non_void);
1000 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1001 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1002 uint32_t radv_translate_dbformat(VkFormat format);
1003 uint32_t radv_translate_tex_dataformat(VkFormat format,
1004 const struct vk_format_description *desc,
1005 int first_non_void);
1006 uint32_t radv_translate_tex_numformat(VkFormat format,
1007 const struct vk_format_description *desc,
1008 int first_non_void);
1009 bool radv_format_pack_clear_color(VkFormat format,
1010 uint32_t clear_vals[2],
1011 VkClearColorValue *value);
1012 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1013
1014 struct radv_fmask_info {
1015 uint64_t offset;
1016 uint64_t size;
1017 unsigned alignment;
1018 unsigned pitch_in_pixels;
1019 unsigned bank_height;
1020 unsigned slice_tile_max;
1021 unsigned tile_mode_index;
1022 };
1023
1024 struct radv_cmask_info {
1025 uint64_t offset;
1026 uint64_t size;
1027 unsigned alignment;
1028 unsigned slice_tile_max;
1029 unsigned base_address_reg;
1030 };
1031
1032 struct r600_htile_info {
1033 uint64_t offset;
1034 uint64_t size;
1035 unsigned pitch;
1036 unsigned height;
1037 unsigned xalign;
1038 unsigned yalign;
1039 };
1040
1041 struct radv_image {
1042 VkImageType type;
1043 /* The original VkFormat provided by the client. This may not match any
1044 * of the actual surface formats.
1045 */
1046 VkFormat vk_format;
1047 VkImageAspectFlags aspects;
1048 VkExtent3D extent;
1049 uint32_t levels;
1050 uint32_t array_size;
1051 uint32_t samples; /**< VkImageCreateInfo::samples */
1052 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1053 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1054
1055 VkDeviceSize size;
1056 uint32_t alignment;
1057
1058 bool exclusive;
1059 unsigned queue_family_mask;
1060
1061 /* Set when bound */
1062 struct radeon_winsys_bo *bo;
1063 VkDeviceSize offset;
1064 uint32_t dcc_offset;
1065 struct radeon_surf surface;
1066
1067 struct radv_fmask_info fmask;
1068 struct radv_cmask_info cmask;
1069 uint32_t clear_value_offset;
1070
1071 /* Depth buffer compression and fast clear. */
1072 struct r600_htile_info htile;
1073 };
1074
1075 bool radv_layout_has_htile(const struct radv_image *image,
1076 VkImageLayout layout);
1077 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1078 VkImageLayout layout);
1079 bool radv_layout_can_expclear(const struct radv_image *image,
1080 VkImageLayout layout);
1081 bool radv_layout_can_fast_clear(const struct radv_image *image,
1082 VkImageLayout layout,
1083 unsigned queue_mask);
1084
1085
1086 unsigned radv_image_queue_family_mask(const struct radv_image *image, int family);
1087
1088 static inline uint32_t
1089 radv_get_layerCount(const struct radv_image *image,
1090 const VkImageSubresourceRange *range)
1091 {
1092 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1093 image->array_size - range->baseArrayLayer : range->layerCount;
1094 }
1095
1096 static inline uint32_t
1097 radv_get_levelCount(const struct radv_image *image,
1098 const VkImageSubresourceRange *range)
1099 {
1100 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1101 image->levels - range->baseMipLevel : range->levelCount;
1102 }
1103
1104 struct radeon_bo_metadata;
1105 void
1106 radv_init_metadata(struct radv_device *device,
1107 struct radv_image *image,
1108 struct radeon_bo_metadata *metadata);
1109
1110 struct radv_image_view {
1111 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1112 struct radeon_winsys_bo *bo;
1113
1114 VkImageViewType type;
1115 VkImageAspectFlags aspect_mask;
1116 VkFormat vk_format;
1117 uint32_t base_layer;
1118 uint32_t layer_count;
1119 uint32_t base_mip;
1120 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1121
1122 uint32_t descriptor[8];
1123 uint32_t fmask_descriptor[8];
1124 };
1125
1126 struct radv_image_create_info {
1127 const VkImageCreateInfo *vk_info;
1128 uint32_t stride;
1129 bool scanout;
1130 };
1131
1132 VkResult radv_image_create(VkDevice _device,
1133 const struct radv_image_create_info *info,
1134 const VkAllocationCallbacks* alloc,
1135 VkImage *pImage);
1136
1137 void radv_image_view_init(struct radv_image_view *view,
1138 struct radv_device *device,
1139 const VkImageViewCreateInfo* pCreateInfo,
1140 struct radv_cmd_buffer *cmd_buffer,
1141 VkImageUsageFlags usage_mask);
1142 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1143 struct radv_image *image, uint32_t micro_tile_mode);
1144 struct radv_buffer_view {
1145 struct radeon_winsys_bo *bo;
1146 VkFormat vk_format;
1147 uint64_t range; /**< VkBufferViewCreateInfo::range */
1148 uint32_t state[4];
1149 };
1150 void radv_buffer_view_init(struct radv_buffer_view *view,
1151 struct radv_device *device,
1152 const VkBufferViewCreateInfo* pCreateInfo,
1153 struct radv_cmd_buffer *cmd_buffer);
1154
1155 static inline struct VkExtent3D
1156 radv_sanitize_image_extent(const VkImageType imageType,
1157 const struct VkExtent3D imageExtent)
1158 {
1159 switch (imageType) {
1160 case VK_IMAGE_TYPE_1D:
1161 return (VkExtent3D) { imageExtent.width, 1, 1 };
1162 case VK_IMAGE_TYPE_2D:
1163 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1164 case VK_IMAGE_TYPE_3D:
1165 return imageExtent;
1166 default:
1167 unreachable("invalid image type");
1168 }
1169 }
1170
1171 static inline struct VkOffset3D
1172 radv_sanitize_image_offset(const VkImageType imageType,
1173 const struct VkOffset3D imageOffset)
1174 {
1175 switch (imageType) {
1176 case VK_IMAGE_TYPE_1D:
1177 return (VkOffset3D) { imageOffset.x, 0, 0 };
1178 case VK_IMAGE_TYPE_2D:
1179 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1180 case VK_IMAGE_TYPE_3D:
1181 return imageOffset;
1182 default:
1183 unreachable("invalid image type");
1184 }
1185 }
1186
1187 struct radv_sampler {
1188 uint32_t state[4];
1189 };
1190
1191 struct radv_color_buffer_info {
1192 uint32_t cb_color_base;
1193 uint32_t cb_color_pitch;
1194 uint32_t cb_color_slice;
1195 uint32_t cb_color_view;
1196 uint32_t cb_color_info;
1197 uint32_t cb_color_attrib;
1198 uint32_t cb_dcc_control;
1199 uint32_t cb_color_cmask;
1200 uint32_t cb_color_cmask_slice;
1201 uint32_t cb_color_fmask;
1202 uint32_t cb_color_fmask_slice;
1203 uint32_t cb_clear_value0;
1204 uint32_t cb_clear_value1;
1205 uint32_t cb_dcc_base;
1206 uint32_t micro_tile_mode;
1207 };
1208
1209 struct radv_ds_buffer_info {
1210 uint32_t db_depth_info;
1211 uint32_t db_z_info;
1212 uint32_t db_stencil_info;
1213 uint32_t db_z_read_base;
1214 uint32_t db_stencil_read_base;
1215 uint32_t db_z_write_base;
1216 uint32_t db_stencil_write_base;
1217 uint32_t db_depth_view;
1218 uint32_t db_depth_size;
1219 uint32_t db_depth_slice;
1220 uint32_t db_htile_surface;
1221 uint32_t db_htile_data_base;
1222 uint32_t pa_su_poly_offset_db_fmt_cntl;
1223 float offset_scale;
1224 };
1225
1226 struct radv_attachment_info {
1227 union {
1228 struct radv_color_buffer_info cb;
1229 struct radv_ds_buffer_info ds;
1230 };
1231 struct radv_image_view *attachment;
1232 };
1233
1234 struct radv_framebuffer {
1235 uint32_t width;
1236 uint32_t height;
1237 uint32_t layers;
1238
1239 uint32_t attachment_count;
1240 struct radv_attachment_info attachments[0];
1241 };
1242
1243 struct radv_subpass_barrier {
1244 VkPipelineStageFlags src_stage_mask;
1245 VkAccessFlags src_access_mask;
1246 VkAccessFlags dst_access_mask;
1247 };
1248
1249 struct radv_subpass {
1250 uint32_t input_count;
1251 VkAttachmentReference * input_attachments;
1252 uint32_t color_count;
1253 VkAttachmentReference * color_attachments;
1254 VkAttachmentReference * resolve_attachments;
1255 VkAttachmentReference depth_stencil_attachment;
1256
1257 /** Subpass has at least one resolve attachment */
1258 bool has_resolve;
1259
1260 struct radv_subpass_barrier start_barrier;
1261 };
1262
1263 struct radv_render_pass_attachment {
1264 VkFormat format;
1265 uint32_t samples;
1266 VkAttachmentLoadOp load_op;
1267 VkAttachmentLoadOp stencil_load_op;
1268 VkImageLayout initial_layout;
1269 VkImageLayout final_layout;
1270 };
1271
1272 struct radv_render_pass {
1273 uint32_t attachment_count;
1274 uint32_t subpass_count;
1275 VkAttachmentReference * subpass_attachments;
1276 struct radv_render_pass_attachment * attachments;
1277 struct radv_subpass_barrier end_barrier;
1278 struct radv_subpass subpasses[0];
1279 };
1280
1281 VkResult radv_device_init_meta(struct radv_device *device);
1282 void radv_device_finish_meta(struct radv_device *device);
1283
1284 struct radv_query_pool {
1285 struct radeon_winsys_bo *bo;
1286 uint32_t stride;
1287 uint32_t availability_offset;
1288 char *ptr;
1289 VkQueryType type;
1290 };
1291
1292 VkResult
1293 radv_temp_descriptor_set_create(struct radv_device *device,
1294 struct radv_cmd_buffer *cmd_buffer,
1295 VkDescriptorSetLayout _layout,
1296 VkDescriptorSet *_set);
1297
1298 void
1299 radv_temp_descriptor_set_destroy(struct radv_device *device,
1300 VkDescriptorSet _set);
1301 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1302 struct radv_image *image, uint32_t value);
1303 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1304 struct radv_image *image, uint32_t value);
1305
1306 struct radv_fence {
1307 struct radeon_winsys_fence *fence;
1308 bool submitted;
1309 bool signalled;
1310 };
1311
1312 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1313 \
1314 static inline struct __radv_type * \
1315 __radv_type ## _from_handle(__VkType _handle) \
1316 { \
1317 return (struct __radv_type *) _handle; \
1318 } \
1319 \
1320 static inline __VkType \
1321 __radv_type ## _to_handle(struct __radv_type *_obj) \
1322 { \
1323 return (__VkType) _obj; \
1324 }
1325
1326 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1327 \
1328 static inline struct __radv_type * \
1329 __radv_type ## _from_handle(__VkType _handle) \
1330 { \
1331 return (struct __radv_type *)(uintptr_t) _handle; \
1332 } \
1333 \
1334 static inline __VkType \
1335 __radv_type ## _to_handle(struct __radv_type *_obj) \
1336 { \
1337 return (__VkType)(uintptr_t) _obj; \
1338 }
1339
1340 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1341 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1342
1343 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1344 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1345 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1346 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1347 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1348
1349 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1350 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1351 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1352 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1353 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1354 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1355 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1356 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1357 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1358 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1359 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1360 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1361 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1362 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1363 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1364 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1365 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1366 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1367 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1368
1369 #endif /* RADV_PRIVATE_H */