2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
53 #include "vk_debug_report.h"
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "radv_descriptor_set.h"
62 #include "radv_extensions.h"
65 #include <llvm-c/TargetMachine.h>
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vk_icd.h>
77 #include <vulkan/vk_android_native_buffer.h>
79 #include "radv_entrypoints.h"
81 #include "wsi_common.h"
83 #define ATI_VENDOR_ID 0x1002
86 #define MAX_VERTEX_ATTRIBS 32
88 #define MAX_VIEWPORTS 16
89 #define MAX_SCISSORS 16
90 #define MAX_DISCARD_RECTANGLES 4
91 #define MAX_PUSH_CONSTANTS_SIZE 128
92 #define MAX_PUSH_DESCRIPTORS 32
93 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
94 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
95 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
96 #define MAX_SAMPLES_LOG2 4
97 #define NUM_META_FS_KEYS 13
98 #define RADV_MAX_DRM_DEVICES 8
101 #define NUM_DEPTH_CLEAR_PIPELINES 3
104 * This is the point we switch from using CP to compute shader
105 * for certain buffer operations.
107 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
111 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
118 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
119 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
120 RADV_MEM_TYPE_GTT_CACHED
,
124 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
126 static inline uint32_t
127 align_u32(uint32_t v
, uint32_t a
)
129 assert(a
!= 0 && a
== (a
& -a
));
130 return (v
+ a
- 1) & ~(a
- 1);
133 static inline uint32_t
134 align_u32_npot(uint32_t v
, uint32_t a
)
136 return (v
+ a
- 1) / a
* a
;
139 static inline uint64_t
140 align_u64(uint64_t v
, uint64_t a
)
142 assert(a
!= 0 && a
== (a
& -a
));
143 return (v
+ a
- 1) & ~(a
- 1);
146 static inline int32_t
147 align_i32(int32_t v
, int32_t a
)
149 assert(a
!= 0 && a
== (a
& -a
));
150 return (v
+ a
- 1) & ~(a
- 1);
153 /** Alignment must be a power of 2. */
155 radv_is_aligned(uintmax_t n
, uintmax_t a
)
157 assert(a
== (a
& -a
));
158 return (n
& (a
- 1)) == 0;
161 static inline uint32_t
162 round_up_u32(uint32_t v
, uint32_t a
)
164 return (v
+ a
- 1) / a
;
167 static inline uint64_t
168 round_up_u64(uint64_t v
, uint64_t a
)
170 return (v
+ a
- 1) / a
;
173 static inline uint32_t
174 radv_minify(uint32_t n
, uint32_t levels
)
176 if (unlikely(n
== 0))
179 return MAX2(n
>> levels
, 1);
182 radv_clamp_f(float f
, float min
, float max
)
195 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
197 if (*inout_mask
& clear_mask
) {
198 *inout_mask
&= ~clear_mask
;
205 #define for_each_bit(b, dword) \
206 for (uint32_t __dword = (dword); \
207 (b) = __builtin_ffs(__dword) - 1, __dword; \
208 __dword &= ~(1 << (b)))
210 #define typed_memcpy(dest, src, count) ({ \
211 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
212 memcpy((dest), (src), (count) * sizeof(*(src))); \
215 /* Whenever we generate an error, pass it through this function. Useful for
216 * debugging, where we can break on it. Only call at error site, not when
217 * propagating errors. Might be useful to plug in a stack trace here.
220 struct radv_instance
;
222 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
224 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
225 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
227 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
228 radv_printflike(3, 4);
229 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
230 void radv_loge_v(const char *format
, va_list va
);
233 * Print a FINISHME message, including its source location.
235 #define radv_finishme(format, ...) \
237 static bool reported = false; \
239 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
244 /* A non-fatal assert. Useful for debugging. */
246 #define radv_assert(x) ({ \
247 if (unlikely(!(x))) \
248 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
251 #define radv_assert(x)
254 #define stub_return(v) \
256 radv_finishme("stub %s", __func__); \
262 radv_finishme("stub %s", __func__); \
266 void *radv_lookup_entrypoint_unchecked(const char *name
);
267 void *radv_lookup_entrypoint_checked(const char *name
,
268 uint32_t core_version
,
269 const struct radv_instance_extension_table
*instance
,
270 const struct radv_device_extension_table
*device
);
272 struct radv_physical_device
{
273 VK_LOADER_DATA _loader_data
;
275 struct radv_instance
* instance
;
277 struct radeon_winsys
*ws
;
278 struct radeon_info rad_info
;
280 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
281 uint8_t driver_uuid
[VK_UUID_SIZE
];
282 uint8_t device_uuid
[VK_UUID_SIZE
];
283 uint8_t cache_uuid
[VK_UUID_SIZE
];
286 struct wsi_device wsi_device
;
288 bool has_rbplus
; /* if RB+ register exist */
289 bool rbplus_allowed
; /* if RB+ is allowed */
290 bool has_clear_state
;
291 bool cpdma_prefetch_writes_memory
;
292 bool has_scissor_bug
;
294 bool has_out_of_order_rast
;
295 bool out_of_order_rast_allowed
;
297 /* Whether DCC should be enabled for MSAA textures. */
298 bool dcc_msaa_allowed
;
300 /* This is the drivers on-disk cache used as a fallback as opposed to
301 * the pipeline cache defined by apps.
303 struct disk_cache
* disk_cache
;
305 VkPhysicalDeviceMemoryProperties memory_properties
;
306 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
308 struct radv_device_extension_table supported_extensions
;
311 struct radv_instance
{
312 VK_LOADER_DATA _loader_data
;
314 VkAllocationCallbacks alloc
;
317 int physicalDeviceCount
;
318 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
320 uint64_t debug_flags
;
321 uint64_t perftest_flags
;
323 struct vk_debug_report_instance debug_report_callbacks
;
325 struct radv_instance_extension_table enabled_extensions
;
328 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
329 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
331 bool radv_instance_extension_supported(const char *name
);
332 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
333 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
338 struct radv_pipeline_cache
{
339 struct radv_device
* device
;
340 pthread_mutex_t mutex
;
344 uint32_t kernel_count
;
345 struct cache_entry
** hash_table
;
348 VkAllocationCallbacks alloc
;
351 struct radv_pipeline_key
{
352 uint32_t instance_rate_inputs
;
353 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
354 uint64_t vertex_alpha_adjust
;
355 unsigned tess_input_vertices
;
359 uint8_t log2_ps_iter_samples
;
360 uint8_t log2_num_samples
;
361 uint32_t multisample
: 1;
362 uint32_t has_multiview_view_index
: 1;
363 uint32_t optimisations_disabled
: 1;
367 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
368 struct radv_device
*device
);
370 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
372 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
373 const void *data
, size_t size
);
375 struct radv_shader_variant
;
378 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
379 struct radv_pipeline_cache
*cache
,
380 const unsigned char *sha1
,
381 struct radv_shader_variant
**variants
);
384 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
385 struct radv_pipeline_cache
*cache
,
386 const unsigned char *sha1
,
387 struct radv_shader_variant
**variants
,
388 const void *const *codes
,
389 const unsigned *code_sizes
);
391 enum radv_blit_ds_layout
{
392 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
393 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
394 RADV_BLIT_DS_LAYOUT_COUNT
,
397 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
399 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
402 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
404 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
407 enum radv_meta_dst_layout
{
408 RADV_META_DST_LAYOUT_GENERAL
,
409 RADV_META_DST_LAYOUT_OPTIMAL
,
410 RADV_META_DST_LAYOUT_COUNT
,
413 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
415 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
418 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
420 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
423 struct radv_meta_state
{
424 VkAllocationCallbacks alloc
;
426 struct radv_pipeline_cache cache
;
429 * Use array element `i` for images with `2^i` samples.
432 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
433 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
435 VkRenderPass depthstencil_rp
;
436 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
437 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
438 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
439 } clear
[1 + MAX_SAMPLES_LOG2
];
441 VkPipelineLayout clear_color_p_layout
;
442 VkPipelineLayout clear_depth_p_layout
;
444 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
446 /** Pipeline that blits from a 1D image. */
447 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
449 /** Pipeline that blits from a 2D image. */
450 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
452 /** Pipeline that blits from a 3D image. */
453 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
455 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
456 VkPipeline depth_only_1d_pipeline
;
457 VkPipeline depth_only_2d_pipeline
;
458 VkPipeline depth_only_3d_pipeline
;
460 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
461 VkPipeline stencil_only_1d_pipeline
;
462 VkPipeline stencil_only_2d_pipeline
;
463 VkPipeline stencil_only_3d_pipeline
;
464 VkPipelineLayout pipeline_layout
;
465 VkDescriptorSetLayout ds_layout
;
469 VkPipelineLayout p_layouts
[5];
470 VkDescriptorSetLayout ds_layouts
[5];
471 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
473 VkPipeline depth_only_pipeline
[5];
475 VkPipeline stencil_only_pipeline
[5];
476 } blit2d
[1 + MAX_SAMPLES_LOG2
];
478 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
479 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
480 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
483 VkPipelineLayout img_p_layout
;
484 VkDescriptorSetLayout img_ds_layout
;
486 VkPipeline pipeline_3d
;
489 VkPipelineLayout img_p_layout
;
490 VkDescriptorSetLayout img_ds_layout
;
492 VkPipeline pipeline_3d
;
495 VkPipelineLayout img_p_layout
;
496 VkDescriptorSetLayout img_ds_layout
;
498 VkPipeline pipeline_3d
;
501 VkPipelineLayout img_p_layout
;
502 VkDescriptorSetLayout img_ds_layout
;
504 VkPipeline pipeline_3d
;
508 VkPipelineLayout p_layout
;
509 VkPipeline pipeline
[NUM_META_FS_KEYS
];
510 VkRenderPass pass
[NUM_META_FS_KEYS
];
514 VkDescriptorSetLayout ds_layout
;
515 VkPipelineLayout p_layout
;
518 VkPipeline i_pipeline
;
519 VkPipeline srgb_pipeline
;
520 } rc
[MAX_SAMPLES_LOG2
];
524 VkDescriptorSetLayout ds_layout
;
525 VkPipelineLayout p_layout
;
528 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
529 VkPipeline pipeline
[NUM_META_FS_KEYS
];
530 } rc
[MAX_SAMPLES_LOG2
];
534 VkPipelineLayout p_layout
;
535 VkPipeline decompress_pipeline
;
536 VkPipeline resummarize_pipeline
;
538 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
541 VkPipelineLayout p_layout
;
542 VkPipeline cmask_eliminate_pipeline
;
543 VkPipeline fmask_decompress_pipeline
;
544 VkPipeline dcc_decompress_pipeline
;
547 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
548 VkPipelineLayout dcc_decompress_compute_p_layout
;
549 VkPipeline dcc_decompress_compute_pipeline
;
553 VkPipelineLayout fill_p_layout
;
554 VkPipelineLayout copy_p_layout
;
555 VkDescriptorSetLayout fill_ds_layout
;
556 VkDescriptorSetLayout copy_ds_layout
;
557 VkPipeline fill_pipeline
;
558 VkPipeline copy_pipeline
;
562 VkDescriptorSetLayout ds_layout
;
563 VkPipelineLayout p_layout
;
564 VkPipeline occlusion_query_pipeline
;
565 VkPipeline pipeline_statistics_query_pipeline
;
570 #define RADV_QUEUE_GENERAL 0
571 #define RADV_QUEUE_COMPUTE 1
572 #define RADV_QUEUE_TRANSFER 2
574 #define RADV_MAX_QUEUE_FAMILIES 3
576 enum ring_type
radv_queue_family_to_ring(int f
);
579 VK_LOADER_DATA _loader_data
;
580 struct radv_device
* device
;
581 struct radeon_winsys_ctx
*hw_ctx
;
582 enum radeon_ctx_priority priority
;
583 uint32_t queue_family_index
;
585 VkDeviceQueueCreateFlags flags
;
587 uint32_t scratch_size
;
588 uint32_t compute_scratch_size
;
589 uint32_t esgs_ring_size
;
590 uint32_t gsvs_ring_size
;
592 bool has_sample_positions
;
594 struct radeon_winsys_bo
*scratch_bo
;
595 struct radeon_winsys_bo
*descriptor_bo
;
596 struct radeon_winsys_bo
*compute_scratch_bo
;
597 struct radeon_winsys_bo
*esgs_ring_bo
;
598 struct radeon_winsys_bo
*gsvs_ring_bo
;
599 struct radeon_winsys_bo
*tess_rings_bo
;
600 struct radeon_winsys_cs
*initial_preamble_cs
;
601 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
602 struct radeon_winsys_cs
*continue_preamble_cs
;
605 struct radv_bo_list
{
606 struct radv_winsys_bo_list list
;
608 pthread_mutex_t mutex
;
612 VK_LOADER_DATA _loader_data
;
614 VkAllocationCallbacks alloc
;
616 struct radv_instance
* instance
;
617 struct radeon_winsys
*ws
;
619 struct radv_meta_state meta_state
;
621 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
622 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
623 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
625 bool always_use_syncobj
;
626 bool has_distributed_tess
;
629 uint32_t tess_offchip_block_dw_size
;
630 uint32_t scratch_waves
;
631 uint32_t dispatch_initiator
;
633 uint32_t gs_table_depth
;
635 /* MSAA sample locations.
636 * The first index is the sample index.
637 * The second index is the coordinate: X, Y. */
638 float sample_locations_1x
[1][2];
639 float sample_locations_2x
[2][2];
640 float sample_locations_4x
[4][2];
641 float sample_locations_8x
[8][2];
642 float sample_locations_16x
[16][2];
645 uint32_t gfx_init_size_dw
;
646 struct radeon_winsys_bo
*gfx_init
;
648 struct radeon_winsys_bo
*trace_bo
;
649 uint32_t *trace_id_ptr
;
651 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
652 bool keep_shader_info
;
654 struct radv_physical_device
*physical_device
;
656 /* Backup in-memory cache to be used if the app doesn't provide one */
657 struct radv_pipeline_cache
* mem_cache
;
660 * use different counters so MSAA MRTs get consecutive surface indices,
661 * even if MASK is allocated in between.
663 uint32_t image_mrt_offset_counter
;
664 uint32_t fmask_mrt_offset_counter
;
665 struct list_head shader_slabs
;
666 mtx_t shader_slab_mutex
;
668 /* For detecting VM faults reported by dmesg. */
669 uint64_t dmesg_timestamp
;
671 struct radv_device_extension_table enabled_extensions
;
673 /* Whether the driver uses a global BO list. */
674 bool use_global_bo_list
;
676 struct radv_bo_list bo_list
;
679 struct radv_device_memory
{
680 struct radeon_winsys_bo
*bo
;
681 /* for dedicated allocations */
682 struct radv_image
*image
;
683 struct radv_buffer
*buffer
;
685 VkDeviceSize map_size
;
691 struct radv_descriptor_range
{
696 struct radv_descriptor_set
{
697 const struct radv_descriptor_set_layout
*layout
;
700 struct radeon_winsys_bo
*bo
;
702 uint32_t *mapped_ptr
;
703 struct radv_descriptor_range
*dynamic_descriptors
;
705 struct radeon_winsys_bo
*descriptors
[0];
708 struct radv_push_descriptor_set
710 struct radv_descriptor_set set
;
714 struct radv_descriptor_pool_entry
{
717 struct radv_descriptor_set
*set
;
720 struct radv_descriptor_pool
{
721 struct radeon_winsys_bo
*bo
;
723 uint64_t current_offset
;
726 uint8_t *host_memory_base
;
727 uint8_t *host_memory_ptr
;
728 uint8_t *host_memory_end
;
730 uint32_t entry_count
;
731 uint32_t max_entry_count
;
732 struct radv_descriptor_pool_entry entries
[0];
735 struct radv_descriptor_update_template_entry
{
736 VkDescriptorType descriptor_type
;
738 /* The number of descriptors to update */
739 uint32_t descriptor_count
;
741 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
744 /* In dwords. Not valid/used for dynamic descriptors */
747 uint32_t buffer_offset
;
749 /* Only valid for combined image samplers and samplers */
750 uint16_t has_sampler
;
756 /* For push descriptors */
757 const uint32_t *immutable_samplers
;
760 struct radv_descriptor_update_template
{
761 uint32_t entry_count
;
762 VkPipelineBindPoint bind_point
;
763 struct radv_descriptor_update_template_entry entry
[0];
769 VkBufferUsageFlags usage
;
770 VkBufferCreateFlags flags
;
773 struct radeon_winsys_bo
* bo
;
779 enum radv_dynamic_state_bits
{
780 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
781 RADV_DYNAMIC_SCISSOR
= 1 << 1,
782 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
783 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
784 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
785 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
786 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
787 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
788 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
789 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
790 RADV_DYNAMIC_ALL
= (1 << 10) - 1,
793 enum radv_cmd_dirty_bits
{
794 /* Keep the dynamic state dirty bits in sync with
795 * enum radv_dynamic_state_bits */
796 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
797 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
798 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
799 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
800 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
801 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
802 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
803 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
804 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
805 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
806 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 10) - 1,
807 RADV_CMD_DIRTY_PIPELINE
= 1 << 10,
808 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 11,
809 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 12,
810 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 13,
813 enum radv_cmd_flush_bits
{
814 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
815 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
816 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
817 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
818 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
819 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
820 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
821 /* Same as above, but only writes back and doesn't invalidate */
822 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
823 /* Framebuffer caches */
824 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
825 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
826 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
827 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
828 /* Engine synchronization. */
829 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
830 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
831 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
832 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
834 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
835 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
836 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
837 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
840 struct radv_vertex_binding
{
841 struct radv_buffer
* buffer
;
845 struct radv_viewport_state
{
847 VkViewport viewports
[MAX_VIEWPORTS
];
850 struct radv_scissor_state
{
852 VkRect2D scissors
[MAX_SCISSORS
];
855 struct radv_discard_rectangle_state
{
857 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
860 struct radv_dynamic_state
{
862 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
863 * Defines the set of saved dynamic state.
867 struct radv_viewport_state viewport
;
869 struct radv_scissor_state scissor
;
879 float blend_constants
[4];
889 } stencil_compare_mask
;
894 } stencil_write_mask
;
901 struct radv_discard_rectangle_state discard_rectangle
;
904 extern const struct radv_dynamic_state default_dynamic_state
;
907 radv_get_debug_option_name(int id
);
910 radv_get_perftest_option_name(int id
);
913 * Attachment state when recording a renderpass instance.
915 * The clear value is valid only if there exists a pending clear.
917 struct radv_attachment_state
{
918 VkImageAspectFlags pending_clear_aspects
;
919 uint32_t cleared_views
;
920 VkClearValue clear_value
;
921 VkImageLayout current_layout
;
924 struct radv_descriptor_state
{
925 struct radv_descriptor_set
*sets
[MAX_SETS
];
928 struct radv_push_descriptor_set push_set
;
932 struct radv_cmd_state
{
933 /* Vertex descriptors */
940 uint32_t prefetch_L2_mask
;
942 struct radv_pipeline
* pipeline
;
943 struct radv_pipeline
* emitted_pipeline
;
944 struct radv_pipeline
* compute_pipeline
;
945 struct radv_pipeline
* emitted_compute_pipeline
;
946 struct radv_framebuffer
* framebuffer
;
947 struct radv_render_pass
* pass
;
948 const struct radv_subpass
* subpass
;
949 struct radv_dynamic_state dynamic
;
950 struct radv_attachment_state
* attachments
;
951 VkRect2D render_area
;
954 struct radv_buffer
*index_buffer
;
955 uint64_t index_offset
;
957 uint32_t max_index_count
;
959 int32_t last_index_type
;
961 int32_t last_primitive_reset_en
;
962 uint32_t last_primitive_reset_index
;
963 enum radv_cmd_flush_bits flush_bits
;
964 unsigned active_occlusion_queries
;
965 bool perfect_occlusion_queries_enabled
;
968 uint32_t last_ia_multi_vgt_param
;
970 uint32_t last_num_instances
;
971 uint32_t last_first_instance
;
972 uint32_t last_vertex_offset
;
975 struct radv_cmd_pool
{
976 VkAllocationCallbacks alloc
;
977 struct list_head cmd_buffers
;
978 struct list_head free_cmd_buffers
;
979 uint32_t queue_family_index
;
982 struct radv_cmd_buffer_upload
{
986 struct radeon_winsys_bo
*upload_bo
;
987 struct list_head list
;
990 enum radv_cmd_buffer_status
{
991 RADV_CMD_BUFFER_STATUS_INVALID
,
992 RADV_CMD_BUFFER_STATUS_INITIAL
,
993 RADV_CMD_BUFFER_STATUS_RECORDING
,
994 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
995 RADV_CMD_BUFFER_STATUS_PENDING
,
998 struct radv_cmd_buffer
{
999 VK_LOADER_DATA _loader_data
;
1001 struct radv_device
* device
;
1003 struct radv_cmd_pool
* pool
;
1004 struct list_head pool_link
;
1006 VkCommandBufferUsageFlags usage_flags
;
1007 VkCommandBufferLevel level
;
1008 enum radv_cmd_buffer_status status
;
1009 struct radeon_winsys_cs
*cs
;
1010 struct radv_cmd_state state
;
1011 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1012 uint32_t queue_family_index
;
1014 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1015 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1016 VkShaderStageFlags push_constant_stages
;
1017 struct radv_descriptor_set meta_push_descriptors
;
1019 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1021 struct radv_cmd_buffer_upload upload
;
1023 uint32_t scratch_size_needed
;
1024 uint32_t compute_scratch_size_needed
;
1025 uint32_t esgs_ring_size_needed
;
1026 uint32_t gsvs_ring_size_needed
;
1027 bool tess_rings_needed
;
1028 bool sample_positions_needed
;
1030 VkResult record_result
;
1032 int ring_offsets_idx
; /* just used for verification */
1033 uint32_t gfx9_fence_offset
;
1034 struct radeon_winsys_bo
*gfx9_fence_bo
;
1035 uint32_t gfx9_fence_idx
;
1038 * Whether a query pool has been resetted and we have to flush caches.
1040 bool pending_reset_query
;
1045 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1047 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
1048 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
1050 void cik_create_gfx_config(struct radv_device
*device
);
1052 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
1053 int count
, const VkViewport
*viewports
);
1054 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
1055 int count
, const VkRect2D
*scissors
,
1056 const VkViewport
*viewports
, bool can_use_guardband
);
1057 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1058 bool instanced_draw
, bool indirect_draw
,
1059 uint32_t draw_vertex_count
);
1060 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
1062 enum chip_class chip_class
,
1064 unsigned event
, unsigned event_flags
,
1068 uint32_t new_fence
);
1070 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
1072 uint64_t va
, uint32_t ref
,
1074 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
1075 enum chip_class chip_class
,
1076 uint32_t *fence_ptr
, uint64_t va
,
1078 enum radv_cmd_flush_bits flush_bits
);
1079 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1080 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
1081 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1082 uint64_t src_va
, uint64_t dest_va
,
1084 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1086 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1087 uint64_t size
, unsigned value
);
1088 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1090 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1093 unsigned *out_offset
,
1096 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1097 const struct radv_subpass
*subpass
,
1100 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1101 unsigned size
, unsigned alignmnet
,
1102 const void *data
, unsigned *out_offset
);
1104 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1105 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1106 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1107 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1108 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
1109 unsigned radv_cayman_get_maxdist(int log_samples
);
1110 void radv_device_init_msaa(struct radv_device
*device
);
1111 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1112 struct radv_image
*image
,
1113 VkClearDepthStencilValue ds_clear_value
,
1114 VkImageAspectFlags aspects
);
1115 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1116 struct radv_image
*image
,
1118 uint32_t color_values
[2]);
1119 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1120 struct radv_image
*image
,
1122 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1123 struct radeon_winsys_bo
*bo
,
1124 uint64_t offset
, uint64_t size
, uint32_t value
);
1125 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1126 bool radv_get_memory_fd(struct radv_device
*device
,
1127 struct radv_device_memory
*memory
,
1131 radv_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
1132 unsigned sh_offset
, unsigned pointer_count
,
1133 bool use_32bit_pointers
)
1135 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1136 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1140 radv_emit_shader_pointer_body(struct radv_device
*device
,
1141 struct radeon_winsys_cs
*cs
,
1142 uint64_t va
, bool use_32bit_pointers
)
1144 radeon_emit(cs
, va
);
1146 if (use_32bit_pointers
) {
1148 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1150 radeon_emit(cs
, va
>> 32);
1155 radv_emit_shader_pointer(struct radv_device
*device
,
1156 struct radeon_winsys_cs
*cs
,
1157 uint32_t sh_offset
, uint64_t va
, bool global
)
1159 bool use_32bit_pointers
= HAVE_32BIT_POINTERS
&& !global
;
1161 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1162 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1165 static inline struct radv_descriptor_state
*
1166 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1167 VkPipelineBindPoint bind_point
)
1169 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1170 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1171 return &cmd_buffer
->descriptors
[bind_point
];
1175 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1177 * Limitations: Can't call normal dispatch functions without binding or rebinding
1178 * the compute pipeline.
1180 void radv_unaligned_dispatch(
1181 struct radv_cmd_buffer
*cmd_buffer
,
1187 struct radeon_winsys_bo
*bo
;
1191 struct radv_shader_module
;
1193 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1194 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1195 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1197 radv_hash_shaders(unsigned char *hash
,
1198 const VkPipelineShaderStageCreateInfo
**stages
,
1199 const struct radv_pipeline_layout
*layout
,
1200 const struct radv_pipeline_key
*key
,
1203 static inline gl_shader_stage
1204 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1206 assert(__builtin_popcount(vk_stage
) == 1);
1207 return ffs(vk_stage
) - 1;
1210 static inline VkShaderStageFlagBits
1211 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1213 return (1 << mesa_stage
);
1216 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1218 #define radv_foreach_stage(stage, stage_bits) \
1219 for (gl_shader_stage stage, \
1220 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1221 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1222 __tmp &= ~(1 << (stage)))
1224 unsigned radv_format_meta_fs_key(VkFormat format
);
1226 struct radv_multisample_state
{
1228 uint32_t pa_sc_line_cntl
;
1229 uint32_t pa_sc_mode_cntl_0
;
1230 uint32_t pa_sc_mode_cntl_1
;
1231 uint32_t pa_sc_aa_config
;
1232 uint32_t pa_sc_aa_mask
[2];
1233 unsigned num_samples
;
1236 struct radv_prim_vertex_count
{
1241 struct radv_vertex_elements_info
{
1242 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1243 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1244 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1245 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1249 struct radv_ia_multi_vgt_param_helpers
{
1251 bool partial_es_wave
;
1252 uint8_t primgroup_size
;
1253 bool wd_switch_on_eop
;
1254 bool ia_switch_on_eoi
;
1255 bool partial_vs_wave
;
1258 #define SI_GS_PER_ES 128
1260 struct radv_pipeline
{
1261 struct radv_device
* device
;
1262 struct radv_dynamic_state dynamic_state
;
1264 struct radv_pipeline_layout
* layout
;
1266 bool need_indirect_descriptor_sets
;
1267 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1268 struct radv_shader_variant
*gs_copy_shader
;
1269 VkShaderStageFlags active_stages
;
1271 struct radeon_winsys_cs cs
;
1273 struct radv_vertex_elements_info vertex_elements
;
1275 uint32_t binding_stride
[MAX_VBS
];
1277 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1280 struct radv_multisample_state ms
;
1281 uint32_t spi_baryc_cntl
;
1282 bool prim_restart_enable
;
1283 unsigned esgs_ring_size
;
1284 unsigned gsvs_ring_size
;
1285 uint32_t vtx_base_sgpr
;
1286 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1287 uint8_t vtx_emit_num
;
1288 struct radv_prim_vertex_count prim_vertex_count
;
1289 bool can_use_guardband
;
1290 uint32_t needed_dynamic_state
;
1291 bool disable_out_of_order_rast_for_occlusion
;
1293 /* Used for rbplus */
1294 uint32_t col_format
;
1295 uint32_t cb_target_mask
;
1300 unsigned scratch_bytes_per_wave
;
1303 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1305 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1308 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1310 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1313 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1314 gl_shader_stage stage
,
1317 struct radv_shader_variant
*radv_get_vertex_shader(struct radv_pipeline
*pipeline
);
1319 struct radv_graphics_pipeline_create_info
{
1321 bool db_depth_clear
;
1322 bool db_stencil_clear
;
1323 bool db_depth_disable_expclear
;
1324 bool db_stencil_disable_expclear
;
1325 bool db_flush_depth_inplace
;
1326 bool db_flush_stencil_inplace
;
1327 bool db_resummarize
;
1328 uint32_t custom_blend_mode
;
1332 radv_graphics_pipeline_create(VkDevice device
,
1333 VkPipelineCache cache
,
1334 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1335 const struct radv_graphics_pipeline_create_info
*extra
,
1336 const VkAllocationCallbacks
*alloc
,
1337 VkPipeline
*pPipeline
);
1339 struct vk_format_description
;
1340 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1341 int first_non_void
);
1342 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1343 int first_non_void
);
1344 uint32_t radv_translate_colorformat(VkFormat format
);
1345 uint32_t radv_translate_color_numformat(VkFormat format
,
1346 const struct vk_format_description
*desc
,
1347 int first_non_void
);
1348 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1349 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1350 uint32_t radv_translate_dbformat(VkFormat format
);
1351 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1352 const struct vk_format_description
*desc
,
1353 int first_non_void
);
1354 uint32_t radv_translate_tex_numformat(VkFormat format
,
1355 const struct vk_format_description
*desc
,
1356 int first_non_void
);
1357 bool radv_format_pack_clear_color(VkFormat format
,
1358 uint32_t clear_vals
[2],
1359 VkClearColorValue
*value
);
1360 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1361 bool radv_dcc_formats_compatible(VkFormat format1
,
1364 struct radv_fmask_info
{
1368 unsigned pitch_in_pixels
;
1369 unsigned bank_height
;
1370 unsigned slice_tile_max
;
1371 unsigned tile_mode_index
;
1372 unsigned tile_swizzle
;
1375 struct radv_cmask_info
{
1379 unsigned slice_tile_max
;
1384 /* The original VkFormat provided by the client. This may not match any
1385 * of the actual surface formats.
1388 VkImageAspectFlags aspects
;
1389 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1390 struct ac_surf_info info
;
1391 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1392 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1397 unsigned queue_family_mask
;
1401 /* Set when bound */
1402 struct radeon_winsys_bo
*bo
;
1403 VkDeviceSize offset
;
1404 uint64_t dcc_offset
;
1405 uint64_t htile_offset
;
1406 bool tc_compatible_htile
;
1407 struct radeon_surf surface
;
1409 struct radv_fmask_info fmask
;
1410 struct radv_cmask_info cmask
;
1411 uint64_t clear_value_offset
;
1412 uint64_t dcc_pred_offset
;
1414 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1415 VkDeviceMemory owned_memory
;
1418 /* Whether the image has a htile that is known consistent with the contents of
1420 bool radv_layout_has_htile(const struct radv_image
*image
,
1421 VkImageLayout layout
,
1422 unsigned queue_mask
);
1424 /* Whether the image has a htile that is known consistent with the contents of
1425 * the image and is allowed to be in compressed form.
1427 * If this is false reads that don't use the htile should be able to return
1430 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1431 VkImageLayout layout
,
1432 unsigned queue_mask
);
1434 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1435 VkImageLayout layout
,
1436 unsigned queue_mask
);
1438 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1439 VkImageLayout layout
,
1440 unsigned queue_mask
);
1443 * Return whether the image has CMASK metadata for color surfaces.
1446 radv_image_has_cmask(const struct radv_image
*image
)
1448 return image
->cmask
.size
;
1452 * Return whether the image has FMASK metadata for color surfaces.
1455 radv_image_has_fmask(const struct radv_image
*image
)
1457 return image
->fmask
.size
;
1461 * Return whether the image has DCC metadata for color surfaces.
1464 radv_image_has_dcc(const struct radv_image
*image
)
1466 return image
->surface
.dcc_size
;
1470 * Return whether DCC metadata is enabled for a level.
1473 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1475 return radv_image_has_dcc(image
) &&
1476 level
< image
->surface
.num_dcc_levels
;
1480 * Return whether the image has HTILE metadata for depth surfaces.
1483 radv_image_has_htile(const struct radv_image
*image
)
1485 return image
->surface
.htile_size
;
1489 * Return whether HTILE metadata is enabled for a level.
1492 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1494 return radv_image_has_htile(image
) && level
== 0;
1498 * Return whether the image is TC-compatible HTILE.
1501 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1503 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1506 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1508 static inline uint32_t
1509 radv_get_layerCount(const struct radv_image
*image
,
1510 const VkImageSubresourceRange
*range
)
1512 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1513 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1516 static inline uint32_t
1517 radv_get_levelCount(const struct radv_image
*image
,
1518 const VkImageSubresourceRange
*range
)
1520 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1521 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1524 struct radeon_bo_metadata
;
1526 radv_init_metadata(struct radv_device
*device
,
1527 struct radv_image
*image
,
1528 struct radeon_bo_metadata
*metadata
);
1530 struct radv_image_view
{
1531 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1532 struct radeon_winsys_bo
*bo
;
1534 VkImageViewType type
;
1535 VkImageAspectFlags aspect_mask
;
1537 uint32_t base_layer
;
1538 uint32_t layer_count
;
1540 uint32_t level_count
;
1541 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1543 uint32_t descriptor
[16];
1545 /* Descriptor for use as a storage image as opposed to a sampled image.
1546 * This has a few differences for cube maps (e.g. type).
1548 uint32_t storage_descriptor
[16];
1551 struct radv_image_create_info
{
1552 const VkImageCreateInfo
*vk_info
;
1554 bool no_metadata_planes
;
1557 VkResult
radv_image_create(VkDevice _device
,
1558 const struct radv_image_create_info
*info
,
1559 const VkAllocationCallbacks
* alloc
,
1563 radv_image_from_gralloc(VkDevice device_h
,
1564 const VkImageCreateInfo
*base_info
,
1565 const VkNativeBufferANDROID
*gralloc_info
,
1566 const VkAllocationCallbacks
*alloc
,
1567 VkImage
*out_image_h
);
1569 void radv_image_view_init(struct radv_image_view
*view
,
1570 struct radv_device
*device
,
1571 const VkImageViewCreateInfo
* pCreateInfo
);
1573 struct radv_buffer_view
{
1574 struct radeon_winsys_bo
*bo
;
1576 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1579 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1580 struct radv_device
*device
,
1581 const VkBufferViewCreateInfo
* pCreateInfo
);
1583 static inline struct VkExtent3D
1584 radv_sanitize_image_extent(const VkImageType imageType
,
1585 const struct VkExtent3D imageExtent
)
1587 switch (imageType
) {
1588 case VK_IMAGE_TYPE_1D
:
1589 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1590 case VK_IMAGE_TYPE_2D
:
1591 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1592 case VK_IMAGE_TYPE_3D
:
1595 unreachable("invalid image type");
1599 static inline struct VkOffset3D
1600 radv_sanitize_image_offset(const VkImageType imageType
,
1601 const struct VkOffset3D imageOffset
)
1603 switch (imageType
) {
1604 case VK_IMAGE_TYPE_1D
:
1605 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1606 case VK_IMAGE_TYPE_2D
:
1607 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1608 case VK_IMAGE_TYPE_3D
:
1611 unreachable("invalid image type");
1616 radv_image_extent_compare(const struct radv_image
*image
,
1617 const VkExtent3D
*extent
)
1619 if (extent
->width
!= image
->info
.width
||
1620 extent
->height
!= image
->info
.height
||
1621 extent
->depth
!= image
->info
.depth
)
1626 struct radv_sampler
{
1630 struct radv_color_buffer_info
{
1631 uint64_t cb_color_base
;
1632 uint64_t cb_color_cmask
;
1633 uint64_t cb_color_fmask
;
1634 uint64_t cb_dcc_base
;
1635 uint32_t cb_color_pitch
;
1636 uint32_t cb_color_slice
;
1637 uint32_t cb_color_view
;
1638 uint32_t cb_color_info
;
1639 uint32_t cb_color_attrib
;
1640 uint32_t cb_color_attrib2
;
1641 uint32_t cb_dcc_control
;
1642 uint32_t cb_color_cmask_slice
;
1643 uint32_t cb_color_fmask_slice
;
1646 struct radv_ds_buffer_info
{
1647 uint64_t db_z_read_base
;
1648 uint64_t db_stencil_read_base
;
1649 uint64_t db_z_write_base
;
1650 uint64_t db_stencil_write_base
;
1651 uint64_t db_htile_data_base
;
1652 uint32_t db_depth_info
;
1654 uint32_t db_stencil_info
;
1655 uint32_t db_depth_view
;
1656 uint32_t db_depth_size
;
1657 uint32_t db_depth_slice
;
1658 uint32_t db_htile_surface
;
1659 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1660 uint32_t db_z_info2
;
1661 uint32_t db_stencil_info2
;
1665 struct radv_attachment_info
{
1667 struct radv_color_buffer_info cb
;
1668 struct radv_ds_buffer_info ds
;
1670 struct radv_image_view
*attachment
;
1673 struct radv_framebuffer
{
1678 uint32_t attachment_count
;
1679 struct radv_attachment_info attachments
[0];
1682 struct radv_subpass_barrier
{
1683 VkPipelineStageFlags src_stage_mask
;
1684 VkAccessFlags src_access_mask
;
1685 VkAccessFlags dst_access_mask
;
1688 struct radv_subpass
{
1689 uint32_t input_count
;
1690 uint32_t color_count
;
1691 VkAttachmentReference
* input_attachments
;
1692 VkAttachmentReference
* color_attachments
;
1693 VkAttachmentReference
* resolve_attachments
;
1694 VkAttachmentReference depth_stencil_attachment
;
1696 /** Subpass has at least one resolve attachment */
1699 struct radv_subpass_barrier start_barrier
;
1702 VkSampleCountFlagBits max_sample_count
;
1705 struct radv_render_pass_attachment
{
1708 VkAttachmentLoadOp load_op
;
1709 VkAttachmentLoadOp stencil_load_op
;
1710 VkImageLayout initial_layout
;
1711 VkImageLayout final_layout
;
1715 struct radv_render_pass
{
1716 uint32_t attachment_count
;
1717 uint32_t subpass_count
;
1718 VkAttachmentReference
* subpass_attachments
;
1719 struct radv_render_pass_attachment
* attachments
;
1720 struct radv_subpass_barrier end_barrier
;
1721 struct radv_subpass subpasses
[0];
1724 VkResult
radv_device_init_meta(struct radv_device
*device
);
1725 void radv_device_finish_meta(struct radv_device
*device
);
1727 struct radv_query_pool
{
1728 struct radeon_winsys_bo
*bo
;
1730 uint32_t availability_offset
;
1734 uint32_t pipeline_stats_mask
;
1737 struct radv_semaphore
{
1738 /* use a winsys sem for non-exportable */
1739 struct radeon_winsys_sem
*sem
;
1741 uint32_t temp_syncobj
;
1744 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1745 VkPipelineBindPoint bind_point
,
1746 struct radv_descriptor_set
*set
,
1750 radv_update_descriptor_sets(struct radv_device
*device
,
1751 struct radv_cmd_buffer
*cmd_buffer
,
1752 VkDescriptorSet overrideSet
,
1753 uint32_t descriptorWriteCount
,
1754 const VkWriteDescriptorSet
*pDescriptorWrites
,
1755 uint32_t descriptorCopyCount
,
1756 const VkCopyDescriptorSet
*pDescriptorCopies
);
1759 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1760 struct radv_cmd_buffer
*cmd_buffer
,
1761 struct radv_descriptor_set
*set
,
1762 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1765 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1766 VkPipelineBindPoint pipelineBindPoint
,
1767 VkPipelineLayout _layout
,
1769 uint32_t descriptorWriteCount
,
1770 const VkWriteDescriptorSet
*pDescriptorWrites
);
1772 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1773 struct radv_image
*image
, uint32_t value
);
1776 struct radeon_winsys_fence
*fence
;
1781 uint32_t temp_syncobj
;
1784 /* radv_nir_to_llvm.c */
1785 struct radv_shader_variant_info
;
1786 struct radv_nir_compiler_options
;
1788 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm
,
1789 struct nir_shader
*geom_shader
,
1790 struct ac_shader_binary
*binary
,
1791 struct ac_shader_config
*config
,
1792 struct radv_shader_variant_info
*shader_info
,
1793 const struct radv_nir_compiler_options
*option
);
1795 void radv_compile_nir_shader(LLVMTargetMachineRef tm
,
1796 struct ac_shader_binary
*binary
,
1797 struct ac_shader_config
*config
,
1798 struct radv_shader_variant_info
*shader_info
,
1799 struct nir_shader
*const *nir
,
1801 const struct radv_nir_compiler_options
*options
);
1803 /* radv_shader_info.h */
1804 struct radv_shader_info
;
1806 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
1807 const struct radv_nir_compiler_options
*options
,
1808 struct radv_shader_info
*info
);
1810 struct radeon_winsys_sem
;
1812 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1814 static inline struct __radv_type * \
1815 __radv_type ## _from_handle(__VkType _handle) \
1817 return (struct __radv_type *) _handle; \
1820 static inline __VkType \
1821 __radv_type ## _to_handle(struct __radv_type *_obj) \
1823 return (__VkType) _obj; \
1826 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1828 static inline struct __radv_type * \
1829 __radv_type ## _from_handle(__VkType _handle) \
1831 return (struct __radv_type *)(uintptr_t) _handle; \
1834 static inline __VkType \
1835 __radv_type ## _to_handle(struct __radv_type *_obj) \
1837 return (__VkType)(uintptr_t) _obj; \
1840 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1841 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1843 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1844 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1845 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1846 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1847 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1849 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1850 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1851 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1852 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1853 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1854 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1855 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1856 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1857 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1858 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1859 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1860 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1861 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1862 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1863 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1864 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1865 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1866 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1867 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1868 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1869 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1871 #endif /* RADV_PRIVATE_H */