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68c161e0d85f5bc816bd51706772c562baf055e3
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_SAMPLES_LOG2 4
83 #define NUM_META_FS_KEYS 11
84 #define RADV_MAX_DRM_DEVICES 8
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 enum radv_mem_heap {
89 RADV_MEM_HEAP_VRAM,
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
91 RADV_MEM_HEAP_GTT,
92 RADV_MEM_HEAP_COUNT
93 };
94
95 enum radv_mem_type {
96 RADV_MEM_TYPE_VRAM,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
99 RADV_MEM_TYPE_GTT_CACHED,
100 RADV_MEM_TYPE_COUNT
101 };
102
103
104 enum {
105 RADV_DEBUG_FAST_CLEARS = 0x1,
106 RADV_DEBUG_NO_DCC = 0x2,
107 RADV_DEBUG_DUMP_SHADERS = 0x4,
108 RADV_DEBUG_NO_CACHE = 0x8,
109 RADV_DEBUG_DUMP_SHADER_STATS = 0x10,
110 RADV_DEBUG_NO_HIZ = 0x20,
111 RADV_DEBUG_NO_COMPUTE_QUEUE = 0x40,
112 RADV_DEBUG_UNSAFE_MATH = 0x80,
113 };
114
115 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
116
117 static inline uint32_t
118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint32_t
125 align_u32_npot(uint32_t v, uint32_t a)
126 {
127 return (v + a - 1) / a * a;
128 }
129
130 static inline uint64_t
131 align_u64(uint64_t v, uint64_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline int32_t
138 align_i32(int32_t v, int32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 /** Alignment must be a power of 2. */
145 static inline bool
146 radv_is_aligned(uintmax_t n, uintmax_t a)
147 {
148 assert(a == (a & -a));
149 return (n & (a - 1)) == 0;
150 }
151
152 static inline uint32_t
153 round_up_u32(uint32_t v, uint32_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint64_t
159 round_up_u64(uint64_t v, uint64_t a)
160 {
161 return (v + a - 1) / a;
162 }
163
164 static inline uint32_t
165 radv_minify(uint32_t n, uint32_t levels)
166 {
167 if (unlikely(n == 0))
168 return 0;
169 else
170 return MAX2(n >> levels, 1);
171 }
172 static inline float
173 radv_clamp_f(float f, float min, float max)
174 {
175 assert(min < max);
176
177 if (f > max)
178 return max;
179 else if (f < min)
180 return min;
181 else
182 return f;
183 }
184
185 static inline bool
186 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
187 {
188 if (*inout_mask & clear_mask) {
189 *inout_mask &= ~clear_mask;
190 return true;
191 } else {
192 return false;
193 }
194 }
195
196 #define for_each_bit(b, dword) \
197 for (uint32_t __dword = (dword); \
198 (b) = __builtin_ffs(__dword) - 1, __dword; \
199 __dword &= ~(1 << (b)))
200
201 #define typed_memcpy(dest, src, count) ({ \
202 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
203 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 })
205
206 #define zero(x) (memset(&(x), 0, sizeof(x)))
207
208 /* Whenever we generate an error, pass it through this function. Useful for
209 * debugging, where we can break on it. Only call at error site, not when
210 * propagating errors. Might be useful to plug in a stack trace here.
211 */
212
213 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
214
215 #ifdef DEBUG
216 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
217 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
218 #else
219 #define vk_error(error) error
220 #define vk_errorf(error, format, ...) error
221 #endif
222
223 void __radv_finishme(const char *file, int line, const char *format, ...)
224 radv_printflike(3, 4);
225 void radv_loge(const char *format, ...) radv_printflike(1, 2);
226 void radv_loge_v(const char *format, va_list va);
227
228 /**
229 * Print a FINISHME message, including its source location.
230 */
231 #define radv_finishme(format, ...) \
232 do { \
233 static bool reported = false; \
234 if (!reported) { \
235 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 reported = true; \
237 } \
238 } while (0)
239
240 /* A non-fatal assert. Useful for debugging. */
241 #ifdef DEBUG
242 #define radv_assert(x) ({ \
243 if (unlikely(!(x))) \
244 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
245 })
246 #else
247 #define radv_assert(x)
248 #endif
249
250 #define stub_return(v) \
251 do { \
252 radv_finishme("stub %s", __func__); \
253 return (v); \
254 } while (0)
255
256 #define stub() \
257 do { \
258 radv_finishme("stub %s", __func__); \
259 return; \
260 } while (0)
261
262 void *radv_resolve_entrypoint(uint32_t index);
263 void *radv_lookup_entrypoint(const char *name);
264
265 extern struct radv_dispatch_table dtable;
266
267 struct radv_extensions {
268 VkExtensionProperties *ext_array;
269 uint32_t num_ext;
270 };
271
272 struct radv_physical_device {
273 VK_LOADER_DATA _loader_data;
274
275 struct radv_instance * instance;
276
277 struct radeon_winsys *ws;
278 struct radeon_info rad_info;
279 char path[20];
280 const char * name;
281 uint8_t uuid[VK_UUID_SIZE];
282
283 struct wsi_device wsi_device;
284 struct radv_extensions extensions;
285 };
286
287 struct radv_instance {
288 VK_LOADER_DATA _loader_data;
289
290 VkAllocationCallbacks alloc;
291
292 uint32_t apiVersion;
293 int physicalDeviceCount;
294 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
295
296 uint64_t debug_flags;
297 };
298
299 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
300 void radv_finish_wsi(struct radv_physical_device *physical_device);
301
302 struct cache_entry;
303
304 struct radv_pipeline_cache {
305 struct radv_device * device;
306 pthread_mutex_t mutex;
307
308 uint32_t total_size;
309 uint32_t table_size;
310 uint32_t kernel_count;
311 struct cache_entry ** hash_table;
312 bool modified;
313
314 VkAllocationCallbacks alloc;
315 };
316
317 void
318 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
319 struct radv_device *device);
320 void
321 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
322 void
323 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
324 const void *data, size_t size);
325
326 struct radv_shader_variant *
327 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
328 struct radv_pipeline_cache *cache,
329 const unsigned char *sha1);
330
331 struct radv_shader_variant *
332 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
333 const unsigned char *sha1,
334 struct radv_shader_variant *variant,
335 const void *code, unsigned code_size);
336
337 void radv_shader_variant_destroy(struct radv_device *device,
338 struct radv_shader_variant *variant);
339
340 struct radv_meta_state {
341 VkAllocationCallbacks alloc;
342
343 struct radv_pipeline_cache cache;
344
345 /**
346 * Use array element `i` for images with `2^i` samples.
347 */
348 struct {
349 VkRenderPass render_pass[NUM_META_FS_KEYS];
350 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
351
352 VkRenderPass depthstencil_rp;
353 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
354 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
355 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
356 } clear[1 + MAX_SAMPLES_LOG2];
357
358 struct {
359 VkRenderPass render_pass[NUM_META_FS_KEYS];
360
361 /** Pipeline that blits from a 1D image. */
362 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
363
364 /** Pipeline that blits from a 2D image. */
365 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
366
367 /** Pipeline that blits from a 3D image. */
368 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
369
370 VkRenderPass depth_only_rp;
371 VkPipeline depth_only_1d_pipeline;
372 VkPipeline depth_only_2d_pipeline;
373 VkPipeline depth_only_3d_pipeline;
374
375 VkRenderPass stencil_only_rp;
376 VkPipeline stencil_only_1d_pipeline;
377 VkPipeline stencil_only_2d_pipeline;
378 VkPipeline stencil_only_3d_pipeline;
379 VkPipelineLayout pipeline_layout;
380 VkDescriptorSetLayout ds_layout;
381 } blit;
382
383 struct {
384 VkRenderPass render_passes[NUM_META_FS_KEYS];
385
386 VkPipelineLayout p_layouts[2];
387 VkDescriptorSetLayout ds_layouts[2];
388 VkPipeline pipelines[2][NUM_META_FS_KEYS];
389
390 VkRenderPass depth_only_rp;
391 VkPipeline depth_only_pipeline[2];
392
393 VkRenderPass stencil_only_rp;
394 VkPipeline stencil_only_pipeline[2];
395 } blit2d;
396
397 struct {
398 VkPipelineLayout img_p_layout;
399 VkDescriptorSetLayout img_ds_layout;
400 VkPipeline pipeline;
401 } itob;
402 struct {
403 VkRenderPass render_pass;
404 VkPipelineLayout img_p_layout;
405 VkDescriptorSetLayout img_ds_layout;
406 VkPipeline pipeline;
407 } btoi;
408 struct {
409 VkPipelineLayout img_p_layout;
410 VkDescriptorSetLayout img_ds_layout;
411 VkPipeline pipeline;
412 } itoi;
413 struct {
414 VkPipelineLayout img_p_layout;
415 VkDescriptorSetLayout img_ds_layout;
416 VkPipeline pipeline;
417 } cleari;
418
419 struct {
420 VkPipeline pipeline;
421 VkRenderPass pass;
422 } resolve;
423
424 struct {
425 VkDescriptorSetLayout ds_layout;
426 VkPipelineLayout p_layout;
427 struct {
428 VkPipeline pipeline;
429 VkPipeline i_pipeline;
430 } rc[MAX_SAMPLES_LOG2];
431 } resolve_compute;
432
433 struct {
434 VkPipeline decompress_pipeline;
435 VkPipeline resummarize_pipeline;
436 VkRenderPass pass;
437 } depth_decomp;
438
439 struct {
440 VkPipeline cmask_eliminate_pipeline;
441 VkPipeline fmask_decompress_pipeline;
442 VkRenderPass pass;
443 } fast_clear_flush;
444
445 struct {
446 VkPipelineLayout fill_p_layout;
447 VkPipelineLayout copy_p_layout;
448 VkDescriptorSetLayout fill_ds_layout;
449 VkDescriptorSetLayout copy_ds_layout;
450 VkPipeline fill_pipeline;
451 VkPipeline copy_pipeline;
452 } buffer;
453 };
454
455 /* queue types */
456 #define RADV_QUEUE_GENERAL 0
457 #define RADV_QUEUE_COMPUTE 1
458 #define RADV_QUEUE_TRANSFER 2
459
460 #define RADV_MAX_QUEUE_FAMILIES 3
461
462 enum ring_type radv_queue_family_to_ring(int f);
463
464 struct radv_queue {
465 VK_LOADER_DATA _loader_data;
466 struct radv_device * device;
467 struct radeon_winsys_ctx *hw_ctx;
468 int queue_family_index;
469 int queue_idx;
470
471 uint32_t scratch_size;
472 uint32_t compute_scratch_size;
473
474 struct radeon_winsys_bo *scratch_bo;
475 struct radeon_winsys_bo *descriptor_bo;
476 struct radeon_winsys_bo *compute_scratch_bo;
477 struct radeon_winsys_cs *preamble_cs;
478 };
479
480 struct radv_device {
481 VK_LOADER_DATA _loader_data;
482
483 VkAllocationCallbacks alloc;
484
485 struct radv_instance * instance;
486 struct radeon_winsys *ws;
487
488 struct radv_meta_state meta_state;
489
490 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
491 int queue_count[RADV_MAX_QUEUE_FAMILIES];
492 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
493
494 uint64_t debug_flags;
495
496 bool llvm_supports_spill;
497 uint32_t scratch_waves;
498 /* MSAA sample locations.
499 * The first index is the sample index.
500 * The second index is the coordinate: X, Y. */
501 float sample_locations_1x[1][2];
502 float sample_locations_2x[2][2];
503 float sample_locations_4x[4][2];
504 float sample_locations_8x[8][2];
505 float sample_locations_16x[16][2];
506
507 struct radeon_winsys_bo *trace_bo;
508 uint32_t *trace_id_ptr;
509
510 struct radv_physical_device *physical_device;
511 };
512
513 struct radv_device_memory {
514 struct radeon_winsys_bo *bo;
515 uint32_t type_index;
516 VkDeviceSize map_size;
517 void * map;
518 };
519
520
521 struct radv_descriptor_range {
522 uint64_t va;
523 uint32_t size;
524 };
525
526 struct radv_descriptor_set {
527 const struct radv_descriptor_set_layout *layout;
528 struct list_head descriptor_pool;
529 uint32_t size;
530
531 struct radv_buffer_view *buffer_views;
532 struct radeon_winsys_bo *bo;
533 uint64_t va;
534 uint32_t *mapped_ptr;
535 struct radv_descriptor_range *dynamic_descriptors;
536 struct radeon_winsys_bo *descriptors[0];
537 };
538
539 struct radv_descriptor_pool_free_node {
540 int next;
541 uint32_t offset;
542 uint32_t size;
543 };
544
545 struct radv_descriptor_pool {
546 struct list_head descriptor_sets;
547
548 struct radeon_winsys_bo *bo;
549 uint8_t *mapped_ptr;
550 uint64_t current_offset;
551 uint64_t size;
552
553 int free_list;
554 int full_list;
555 uint32_t max_sets;
556 struct radv_descriptor_pool_free_node free_nodes[];
557 };
558
559 struct radv_buffer {
560 struct radv_device * device;
561 VkDeviceSize size;
562
563 VkBufferUsageFlags usage;
564
565 /* Set when bound */
566 struct radeon_winsys_bo * bo;
567 VkDeviceSize offset;
568 };
569
570
571 enum radv_cmd_dirty_bits {
572 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
573 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
574 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
575 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
576 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
577 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
578 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
579 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
580 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
581 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
582 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
583 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
584 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
585 };
586 typedef uint32_t radv_cmd_dirty_mask_t;
587
588 enum radv_cmd_flush_bits {
589 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
590 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
591 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
592 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
593 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
594 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
595 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
596 /* Framebuffer caches */
597 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
598 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
599 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
600 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
601 /* Engine synchronization. */
602 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
603 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
604 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
605 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
606
607 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
608 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
609 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
610 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
611 };
612
613 struct radv_vertex_binding {
614 struct radv_buffer * buffer;
615 VkDeviceSize offset;
616 };
617
618 struct radv_dynamic_state {
619 struct {
620 uint32_t count;
621 VkViewport viewports[MAX_VIEWPORTS];
622 } viewport;
623
624 struct {
625 uint32_t count;
626 VkRect2D scissors[MAX_SCISSORS];
627 } scissor;
628
629 float line_width;
630
631 struct {
632 float bias;
633 float clamp;
634 float slope;
635 } depth_bias;
636
637 float blend_constants[4];
638
639 struct {
640 float min;
641 float max;
642 } depth_bounds;
643
644 struct {
645 uint32_t front;
646 uint32_t back;
647 } stencil_compare_mask;
648
649 struct {
650 uint32_t front;
651 uint32_t back;
652 } stencil_write_mask;
653
654 struct {
655 uint32_t front;
656 uint32_t back;
657 } stencil_reference;
658 };
659
660 extern const struct radv_dynamic_state default_dynamic_state;
661
662 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
663 const struct radv_dynamic_state *src,
664 uint32_t copy_mask);
665 /**
666 * Attachment state when recording a renderpass instance.
667 *
668 * The clear value is valid only if there exists a pending clear.
669 */
670 struct radv_attachment_state {
671 VkImageAspectFlags pending_clear_aspects;
672 VkClearValue clear_value;
673 VkImageLayout current_layout;
674 };
675
676 struct radv_cmd_state {
677 uint32_t vb_dirty;
678 bool vertex_descriptors_dirty;
679 radv_cmd_dirty_mask_t dirty;
680
681 struct radv_pipeline * pipeline;
682 struct radv_pipeline * emitted_pipeline;
683 struct radv_pipeline * compute_pipeline;
684 struct radv_pipeline * emitted_compute_pipeline;
685 struct radv_framebuffer * framebuffer;
686 struct radv_render_pass * pass;
687 const struct radv_subpass * subpass;
688 struct radv_dynamic_state dynamic;
689 struct radv_vertex_binding vertex_bindings[MAX_VBS];
690 struct radv_descriptor_set * descriptors[MAX_SETS];
691 struct radv_attachment_state * attachments;
692 VkRect2D render_area;
693 struct radv_buffer * index_buffer;
694 uint32_t index_type;
695 uint32_t index_offset;
696 uint32_t last_primitive_reset_index;
697 enum radv_cmd_flush_bits flush_bits;
698 unsigned active_occlusion_queries;
699 float offset_scale;
700 uint32_t descriptors_dirty;
701 uint32_t trace_id;
702 };
703
704 struct radv_cmd_pool {
705 VkAllocationCallbacks alloc;
706 struct list_head cmd_buffers;
707 uint32_t queue_family_index;
708 };
709
710 struct radv_cmd_buffer_upload {
711 uint8_t *map;
712 unsigned offset;
713 uint64_t size;
714 struct radeon_winsys_bo *upload_bo;
715 struct list_head list;
716 };
717
718 struct radv_cmd_buffer {
719 VK_LOADER_DATA _loader_data;
720
721 struct radv_device * device;
722
723 struct radv_cmd_pool * pool;
724 struct list_head pool_link;
725
726 VkCommandBufferUsageFlags usage_flags;
727 VkCommandBufferLevel level;
728 struct radeon_winsys_cs *cs;
729 struct radv_cmd_state state;
730 uint32_t queue_family_index;
731
732 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
733 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
734 VkShaderStageFlags push_constant_stages;
735
736 struct radv_cmd_buffer_upload upload;
737
738 bool record_fail;
739
740 uint32_t scratch_size_needed;
741 uint32_t compute_scratch_size_needed;
742 };
743
744 struct radv_image;
745
746 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
747
748 void si_init_compute(struct radv_physical_device *physical_device,
749 struct radv_cmd_buffer *cmd_buffer);
750 void si_init_config(struct radv_physical_device *physical_device,
751 struct radv_cmd_buffer *cmd_buffer);
752 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
753 int count, const VkViewport *viewports);
754 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
755 int count, const VkRect2D *scissors);
756 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
757 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
758 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
759 uint64_t src_va, uint64_t dest_va,
760 uint64_t size);
761 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
762 uint64_t size, unsigned value);
763 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
764 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
765 struct radv_descriptor_set *set,
766 unsigned idx);
767 bool
768 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
769 unsigned size,
770 unsigned alignment,
771 unsigned *out_offset,
772 void **ptr);
773 void
774 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
775 const struct radv_subpass *subpass,
776 bool transitions);
777 bool
778 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
779 unsigned size, unsigned alignmnet,
780 const void *data, unsigned *out_offset);
781 void
782 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
783 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
784 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
785 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
786 unsigned radv_cayman_get_maxdist(int log_samples);
787 void radv_device_init_msaa(struct radv_device *device);
788 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
789 struct radv_image *image,
790 VkClearDepthStencilValue ds_clear_value,
791 VkImageAspectFlags aspects);
792 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
793 struct radv_image *image,
794 int idx,
795 uint32_t color_values[2]);
796 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
797 struct radeon_winsys_bo *bo,
798 uint64_t offset, uint64_t size, uint32_t value);
799 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
800
801 /*
802 * Takes x,y,z as exact numbers of invocations, instead of blocks.
803 *
804 * Limitations: Can't call normal dispatch functions without binding or rebinding
805 * the compute pipeline.
806 */
807 void radv_unaligned_dispatch(
808 struct radv_cmd_buffer *cmd_buffer,
809 uint32_t x,
810 uint32_t y,
811 uint32_t z);
812
813 struct radv_event {
814 struct radeon_winsys_bo *bo;
815 uint64_t *map;
816 };
817
818 struct nir_shader;
819
820 struct radv_shader_module {
821 struct nir_shader * nir;
822 unsigned char sha1[20];
823 uint32_t size;
824 char data[0];
825 };
826
827 union ac_shader_variant_key;
828
829 void
830 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
831 const char *entrypoint,
832 const VkSpecializationInfo *spec_info,
833 const struct radv_pipeline_layout *layout,
834 const union ac_shader_variant_key *key);
835
836 static inline gl_shader_stage
837 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
838 {
839 assert(__builtin_popcount(vk_stage) == 1);
840 return ffs(vk_stage) - 1;
841 }
842
843 static inline VkShaderStageFlagBits
844 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
845 {
846 return (1 << mesa_stage);
847 }
848
849 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
850
851 #define radv_foreach_stage(stage, stage_bits) \
852 for (gl_shader_stage stage, \
853 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
854 stage = __builtin_ffs(__tmp) - 1, __tmp; \
855 __tmp &= ~(1 << (stage)))
856
857 struct radv_shader_variant {
858 uint32_t ref_count;
859
860 struct radeon_winsys_bo *bo;
861 struct ac_shader_config config;
862 struct ac_shader_variant_info info;
863 unsigned rsrc1;
864 unsigned rsrc2;
865 uint32_t code_size;
866 };
867
868 struct radv_depth_stencil_state {
869 uint32_t db_depth_control;
870 uint32_t db_stencil_control;
871 uint32_t db_render_control;
872 uint32_t db_render_override2;
873 };
874
875 struct radv_blend_state {
876 uint32_t cb_color_control;
877 uint32_t cb_target_mask;
878 uint32_t sx_mrt0_blend_opt[8];
879 uint32_t cb_blend_control[8];
880
881 uint32_t spi_shader_col_format;
882 uint32_t cb_shader_mask;
883 uint32_t db_alpha_to_mask;
884 };
885
886 unsigned radv_format_meta_fs_key(VkFormat format);
887
888 struct radv_raster_state {
889 uint32_t pa_cl_clip_cntl;
890 uint32_t pa_cl_vs_out_cntl;
891 uint32_t spi_interp_control;
892 uint32_t pa_su_point_size;
893 uint32_t pa_su_point_minmax;
894 uint32_t pa_su_line_cntl;
895 uint32_t pa_su_vtx_cntl;
896 uint32_t pa_su_sc_mode_cntl;
897 };
898
899 struct radv_multisample_state {
900 uint32_t db_eqaa;
901 uint32_t pa_sc_line_cntl;
902 uint32_t pa_sc_mode_cntl_0;
903 uint32_t pa_sc_mode_cntl_1;
904 uint32_t pa_sc_aa_config;
905 uint32_t pa_sc_aa_mask[2];
906 unsigned num_samples;
907 };
908
909 struct radv_pipeline {
910 struct radv_device * device;
911 uint32_t dynamic_state_mask;
912 struct radv_dynamic_state dynamic_state;
913
914 struct radv_pipeline_layout * layout;
915
916 bool needs_data_cache;
917
918 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
919 VkShaderStageFlags active_stages;
920
921 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
922 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
923 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
924 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
925 uint32_t num_vertex_attribs;
926 uint32_t binding_stride[MAX_VBS];
927
928 union {
929 struct {
930 struct radv_blend_state blend;
931 struct radv_depth_stencil_state ds;
932 struct radv_raster_state raster;
933 struct radv_multisample_state ms;
934 unsigned prim;
935 unsigned gs_out;
936 bool prim_restart_enable;
937 } graphics;
938 };
939
940 unsigned max_waves;
941 unsigned scratch_bytes_per_wave;
942 };
943
944 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
945 {
946 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
947 }
948
949 struct radv_graphics_pipeline_create_info {
950 bool use_rectlist;
951 bool db_depth_clear;
952 bool db_stencil_clear;
953 bool db_depth_disable_expclear;
954 bool db_stencil_disable_expclear;
955 bool db_flush_depth_inplace;
956 bool db_flush_stencil_inplace;
957 bool db_resummarize;
958 uint32_t custom_blend_mode;
959 };
960
961 VkResult
962 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
963 struct radv_pipeline_cache *cache,
964 const VkGraphicsPipelineCreateInfo *pCreateInfo,
965 const struct radv_graphics_pipeline_create_info *extra,
966 const VkAllocationCallbacks *alloc);
967
968 VkResult
969 radv_graphics_pipeline_create(VkDevice device,
970 VkPipelineCache cache,
971 const VkGraphicsPipelineCreateInfo *pCreateInfo,
972 const struct radv_graphics_pipeline_create_info *extra,
973 const VkAllocationCallbacks *alloc,
974 VkPipeline *pPipeline);
975
976 struct vk_format_description;
977 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
978 int first_non_void);
979 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
980 int first_non_void);
981 uint32_t radv_translate_colorformat(VkFormat format);
982 uint32_t radv_translate_color_numformat(VkFormat format,
983 const struct vk_format_description *desc,
984 int first_non_void);
985 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
986 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
987 uint32_t radv_translate_dbformat(VkFormat format);
988 uint32_t radv_translate_tex_dataformat(VkFormat format,
989 const struct vk_format_description *desc,
990 int first_non_void);
991 uint32_t radv_translate_tex_numformat(VkFormat format,
992 const struct vk_format_description *desc,
993 int first_non_void);
994 bool radv_format_pack_clear_color(VkFormat format,
995 uint32_t clear_vals[2],
996 VkClearColorValue *value);
997 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
998
999 struct radv_fmask_info {
1000 uint64_t offset;
1001 uint64_t size;
1002 unsigned alignment;
1003 unsigned pitch_in_pixels;
1004 unsigned bank_height;
1005 unsigned slice_tile_max;
1006 unsigned tile_mode_index;
1007 };
1008
1009 struct radv_cmask_info {
1010 uint64_t offset;
1011 uint64_t size;
1012 unsigned alignment;
1013 unsigned slice_tile_max;
1014 unsigned base_address_reg;
1015 };
1016
1017 struct r600_htile_info {
1018 uint64_t offset;
1019 uint64_t size;
1020 unsigned pitch;
1021 unsigned height;
1022 unsigned xalign;
1023 unsigned yalign;
1024 };
1025
1026 struct radv_image {
1027 VkImageType type;
1028 /* The original VkFormat provided by the client. This may not match any
1029 * of the actual surface formats.
1030 */
1031 VkFormat vk_format;
1032 VkImageAspectFlags aspects;
1033 VkExtent3D extent;
1034 uint32_t levels;
1035 uint32_t array_size;
1036 uint32_t samples; /**< VkImageCreateInfo::samples */
1037 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1038 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1039
1040 VkDeviceSize size;
1041 uint32_t alignment;
1042
1043 bool exclusive;
1044 unsigned queue_family_mask;
1045
1046 /* Set when bound */
1047 struct radeon_winsys_bo *bo;
1048 VkDeviceSize offset;
1049 uint32_t dcc_offset;
1050 struct radeon_surf surface;
1051
1052 struct radv_fmask_info fmask;
1053 struct radv_cmask_info cmask;
1054 uint32_t clear_value_offset;
1055
1056 /* Depth buffer compression and fast clear. */
1057 struct r600_htile_info htile;
1058 };
1059
1060 bool radv_layout_has_htile(const struct radv_image *image,
1061 VkImageLayout layout);
1062 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1063 VkImageLayout layout);
1064 bool radv_layout_can_expclear(const struct radv_image *image,
1065 VkImageLayout layout);
1066 bool radv_layout_can_fast_clear(const struct radv_image *image,
1067 VkImageLayout layout,
1068 unsigned queue_mask);
1069
1070
1071 unsigned radv_image_queue_family_mask(const struct radv_image *image, int family);
1072
1073 static inline uint32_t
1074 radv_get_layerCount(const struct radv_image *image,
1075 const VkImageSubresourceRange *range)
1076 {
1077 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1078 image->array_size - range->baseArrayLayer : range->layerCount;
1079 }
1080
1081 static inline uint32_t
1082 radv_get_levelCount(const struct radv_image *image,
1083 const VkImageSubresourceRange *range)
1084 {
1085 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1086 image->levels - range->baseMipLevel : range->levelCount;
1087 }
1088
1089 struct radeon_bo_metadata;
1090 void
1091 radv_init_metadata(struct radv_device *device,
1092 struct radv_image *image,
1093 struct radeon_bo_metadata *metadata);
1094
1095 struct radv_image_view {
1096 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1097 struct radeon_winsys_bo *bo;
1098
1099 VkImageViewType type;
1100 VkImageAspectFlags aspect_mask;
1101 VkFormat vk_format;
1102 uint32_t base_layer;
1103 uint32_t layer_count;
1104 uint32_t base_mip;
1105 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1106
1107 uint32_t descriptor[8];
1108 uint32_t fmask_descriptor[8];
1109 };
1110
1111 struct radv_image_create_info {
1112 const VkImageCreateInfo *vk_info;
1113 uint32_t stride;
1114 bool scanout;
1115 };
1116
1117 VkResult radv_image_create(VkDevice _device,
1118 const struct radv_image_create_info *info,
1119 const VkAllocationCallbacks* alloc,
1120 VkImage *pImage);
1121
1122 void radv_image_view_init(struct radv_image_view *view,
1123 struct radv_device *device,
1124 const VkImageViewCreateInfo* pCreateInfo,
1125 struct radv_cmd_buffer *cmd_buffer,
1126 VkImageUsageFlags usage_mask);
1127 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1128 struct radv_image *image, uint32_t micro_tile_mode);
1129 struct radv_buffer_view {
1130 struct radeon_winsys_bo *bo;
1131 VkFormat vk_format;
1132 uint64_t range; /**< VkBufferViewCreateInfo::range */
1133 uint32_t state[4];
1134 };
1135 void radv_buffer_view_init(struct radv_buffer_view *view,
1136 struct radv_device *device,
1137 const VkBufferViewCreateInfo* pCreateInfo,
1138 struct radv_cmd_buffer *cmd_buffer);
1139
1140 static inline struct VkExtent3D
1141 radv_sanitize_image_extent(const VkImageType imageType,
1142 const struct VkExtent3D imageExtent)
1143 {
1144 switch (imageType) {
1145 case VK_IMAGE_TYPE_1D:
1146 return (VkExtent3D) { imageExtent.width, 1, 1 };
1147 case VK_IMAGE_TYPE_2D:
1148 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1149 case VK_IMAGE_TYPE_3D:
1150 return imageExtent;
1151 default:
1152 unreachable("invalid image type");
1153 }
1154 }
1155
1156 static inline struct VkOffset3D
1157 radv_sanitize_image_offset(const VkImageType imageType,
1158 const struct VkOffset3D imageOffset)
1159 {
1160 switch (imageType) {
1161 case VK_IMAGE_TYPE_1D:
1162 return (VkOffset3D) { imageOffset.x, 0, 0 };
1163 case VK_IMAGE_TYPE_2D:
1164 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1165 case VK_IMAGE_TYPE_3D:
1166 return imageOffset;
1167 default:
1168 unreachable("invalid image type");
1169 }
1170 }
1171
1172 struct radv_sampler {
1173 uint32_t state[4];
1174 };
1175
1176 struct radv_color_buffer_info {
1177 uint32_t cb_color_base;
1178 uint32_t cb_color_pitch;
1179 uint32_t cb_color_slice;
1180 uint32_t cb_color_view;
1181 uint32_t cb_color_info;
1182 uint32_t cb_color_attrib;
1183 uint32_t cb_dcc_control;
1184 uint32_t cb_color_cmask;
1185 uint32_t cb_color_cmask_slice;
1186 uint32_t cb_color_fmask;
1187 uint32_t cb_color_fmask_slice;
1188 uint32_t cb_clear_value0;
1189 uint32_t cb_clear_value1;
1190 uint32_t cb_dcc_base;
1191 uint32_t micro_tile_mode;
1192 };
1193
1194 struct radv_ds_buffer_info {
1195 uint32_t db_depth_info;
1196 uint32_t db_z_info;
1197 uint32_t db_stencil_info;
1198 uint32_t db_z_read_base;
1199 uint32_t db_stencil_read_base;
1200 uint32_t db_z_write_base;
1201 uint32_t db_stencil_write_base;
1202 uint32_t db_depth_view;
1203 uint32_t db_depth_size;
1204 uint32_t db_depth_slice;
1205 uint32_t db_htile_surface;
1206 uint32_t db_htile_data_base;
1207 uint32_t pa_su_poly_offset_db_fmt_cntl;
1208 float offset_scale;
1209 };
1210
1211 struct radv_attachment_info {
1212 union {
1213 struct radv_color_buffer_info cb;
1214 struct radv_ds_buffer_info ds;
1215 };
1216 struct radv_image_view *attachment;
1217 };
1218
1219 struct radv_framebuffer {
1220 uint32_t width;
1221 uint32_t height;
1222 uint32_t layers;
1223
1224 uint32_t attachment_count;
1225 struct radv_attachment_info attachments[0];
1226 };
1227
1228 struct radv_subpass_barrier {
1229 VkPipelineStageFlags src_stage_mask;
1230 VkAccessFlags src_access_mask;
1231 VkAccessFlags dst_access_mask;
1232 };
1233
1234 struct radv_subpass {
1235 uint32_t input_count;
1236 VkAttachmentReference * input_attachments;
1237 uint32_t color_count;
1238 VkAttachmentReference * color_attachments;
1239 VkAttachmentReference * resolve_attachments;
1240 VkAttachmentReference depth_stencil_attachment;
1241
1242 /** Subpass has at least one resolve attachment */
1243 bool has_resolve;
1244
1245 struct radv_subpass_barrier start_barrier;
1246 };
1247
1248 struct radv_render_pass_attachment {
1249 VkFormat format;
1250 uint32_t samples;
1251 VkAttachmentLoadOp load_op;
1252 VkAttachmentLoadOp stencil_load_op;
1253 VkImageLayout initial_layout;
1254 VkImageLayout final_layout;
1255 };
1256
1257 struct radv_render_pass {
1258 uint32_t attachment_count;
1259 uint32_t subpass_count;
1260 VkAttachmentReference * subpass_attachments;
1261 struct radv_render_pass_attachment * attachments;
1262 struct radv_subpass_barrier end_barrier;
1263 struct radv_subpass subpasses[0];
1264 };
1265
1266 VkResult radv_device_init_meta(struct radv_device *device);
1267 void radv_device_finish_meta(struct radv_device *device);
1268
1269 struct radv_query_pool {
1270 struct radeon_winsys_bo *bo;
1271 uint32_t stride;
1272 uint32_t availability_offset;
1273 char *ptr;
1274 VkQueryType type;
1275 };
1276
1277 VkResult
1278 radv_temp_descriptor_set_create(struct radv_device *device,
1279 struct radv_cmd_buffer *cmd_buffer,
1280 VkDescriptorSetLayout _layout,
1281 VkDescriptorSet *_set);
1282
1283 void
1284 radv_temp_descriptor_set_destroy(struct radv_device *device,
1285 VkDescriptorSet _set);
1286 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1287 struct radv_image *image, uint32_t value);
1288 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1289 struct radv_image *image, uint32_t value);
1290
1291 struct radv_fence {
1292 struct radeon_winsys_fence *fence;
1293 bool submitted;
1294 bool signalled;
1295 };
1296
1297 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1298 \
1299 static inline struct __radv_type * \
1300 __radv_type ## _from_handle(__VkType _handle) \
1301 { \
1302 return (struct __radv_type *) _handle; \
1303 } \
1304 \
1305 static inline __VkType \
1306 __radv_type ## _to_handle(struct __radv_type *_obj) \
1307 { \
1308 return (__VkType) _obj; \
1309 }
1310
1311 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1312 \
1313 static inline struct __radv_type * \
1314 __radv_type ## _from_handle(__VkType _handle) \
1315 { \
1316 return (struct __radv_type *)(uintptr_t) _handle; \
1317 } \
1318 \
1319 static inline __VkType \
1320 __radv_type ## _to_handle(struct __radv_type *_obj) \
1321 { \
1322 return (__VkType)(uintptr_t) _obj; \
1323 }
1324
1325 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1326 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1327
1328 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1329 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1330 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1331 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1332 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1333
1334 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1335 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1336 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1337 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1338 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1339 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1340 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1341 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1342 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1343 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1344 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1345 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1346 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1347 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1348 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1349 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1350 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1351 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1352 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1353
1354 #endif /* RADV_PRIVATE_H */