2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
53 #include "vk_debug_report.h"
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_constants.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vulkan_android.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
80 #include "radv_entrypoints.h"
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
85 /* Helper to determine if we should compile
86 * any of the Android AHB support.
88 * To actually enable the ext we also need
89 * the necessary kernel support.
91 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
92 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
99 unsigned img_format
:9;
101 /* Various formats are only supported with workarounds for vertex fetch,
102 * and some 32_32_32 formats are supported natively, but only for buffers
103 * (possibly with some image support, actually, but no filtering). */
107 #include "gfx10_format_table.h"
109 enum radv_secure_compile_type
{
110 RADV_SC_TYPE_INIT_SUCCESS
,
111 RADV_SC_TYPE_INIT_FAILURE
,
112 RADV_SC_TYPE_COMPILE_PIPELINE
,
113 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
114 RADV_SC_TYPE_READ_DISK_CACHE
,
115 RADV_SC_TYPE_WRITE_DISK_CACHE
,
116 RADV_SC_TYPE_FORK_DEVICE
,
117 RADV_SC_TYPE_DESTROY_DEVICE
,
121 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
123 static inline uint32_t
124 align_u32(uint32_t v
, uint32_t a
)
126 assert(a
!= 0 && a
== (a
& -a
));
127 return (v
+ a
- 1) & ~(a
- 1);
130 static inline uint32_t
131 align_u32_npot(uint32_t v
, uint32_t a
)
133 return (v
+ a
- 1) / a
* a
;
136 static inline uint64_t
137 align_u64(uint64_t v
, uint64_t a
)
139 assert(a
!= 0 && a
== (a
& -a
));
140 return (v
+ a
- 1) & ~(a
- 1);
143 static inline int32_t
144 align_i32(int32_t v
, int32_t a
)
146 assert(a
!= 0 && a
== (a
& -a
));
147 return (v
+ a
- 1) & ~(a
- 1);
150 /** Alignment must be a power of 2. */
152 radv_is_aligned(uintmax_t n
, uintmax_t a
)
154 assert(a
== (a
& -a
));
155 return (n
& (a
- 1)) == 0;
158 static inline uint32_t
159 round_up_u32(uint32_t v
, uint32_t a
)
161 return (v
+ a
- 1) / a
;
164 static inline uint64_t
165 round_up_u64(uint64_t v
, uint64_t a
)
167 return (v
+ a
- 1) / a
;
170 static inline uint32_t
171 radv_minify(uint32_t n
, uint32_t levels
)
173 if (unlikely(n
== 0))
176 return MAX2(n
>> levels
, 1);
179 radv_clamp_f(float f
, float min
, float max
)
192 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
194 if (*inout_mask
& clear_mask
) {
195 *inout_mask
&= ~clear_mask
;
202 #define for_each_bit(b, dword) \
203 for (uint32_t __dword = (dword); \
204 (b) = __builtin_ffs(__dword) - 1, __dword; \
205 __dword &= ~(1 << (b)))
207 #define typed_memcpy(dest, src, count) ({ \
208 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
209 memcpy((dest), (src), (count) * sizeof(*(src))); \
212 /* Whenever we generate an error, pass it through this function. Useful for
213 * debugging, where we can break on it. Only call at error site, not when
214 * propagating errors. Might be useful to plug in a stack trace here.
217 struct radv_image_view
;
218 struct radv_instance
;
220 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
222 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
223 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
225 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
226 radv_printflike(3, 4);
227 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
228 void radv_loge_v(const char *format
, va_list va
);
229 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
230 void radv_logi_v(const char *format
, va_list va
);
233 * Print a FINISHME message, including its source location.
235 #define radv_finishme(format, ...) \
237 static bool reported = false; \
239 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
244 /* A non-fatal assert. Useful for debugging. */
246 #define radv_assert(x) ({ \
247 if (unlikely(!(x))) \
248 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
251 #define radv_assert(x) do {} while(0)
254 #define stub_return(v) \
256 radv_finishme("stub %s", __func__); \
262 radv_finishme("stub %s", __func__); \
266 int radv_get_instance_entrypoint_index(const char *name
);
267 int radv_get_device_entrypoint_index(const char *name
);
268 int radv_get_physical_device_entrypoint_index(const char *name
);
270 const char *radv_get_instance_entry_name(int index
);
271 const char *radv_get_physical_device_entry_name(int index
);
272 const char *radv_get_device_entry_name(int index
);
274 bool radv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
275 const struct radv_instance_extension_table
*instance
);
276 bool radv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
277 const struct radv_instance_extension_table
*instance
);
278 bool radv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
279 const struct radv_instance_extension_table
*instance
,
280 const struct radv_device_extension_table
*device
);
282 void *radv_lookup_entrypoint(const char *name
);
284 struct radv_physical_device
{
285 VK_LOADER_DATA _loader_data
;
287 /* Link in radv_instance::physical_devices */
288 struct list_head link
;
290 struct radv_instance
* instance
;
292 struct radeon_winsys
*ws
;
293 struct radeon_info rad_info
;
294 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
295 uint8_t driver_uuid
[VK_UUID_SIZE
];
296 uint8_t device_uuid
[VK_UUID_SIZE
];
297 uint8_t cache_uuid
[VK_UUID_SIZE
];
301 struct wsi_device wsi_device
;
303 bool out_of_order_rast_allowed
;
305 /* Whether DCC should be enabled for MSAA textures. */
306 bool dcc_msaa_allowed
;
308 /* Whether to enable the AMD_shader_ballot extension */
309 bool use_shader_ballot
;
311 /* Whether to enable NGG. */
314 /* Whether to enable NGG GS. */
317 /* Whether to enable NGG streamout. */
318 bool use_ngg_streamout
;
320 /* Number of threads per wave. */
321 uint8_t ps_wave_size
;
322 uint8_t cs_wave_size
;
323 uint8_t ge_wave_size
;
325 /* Whether to use the experimental compiler backend */
328 /* This is the drivers on-disk cache used as a fallback as opposed to
329 * the pipeline cache defined by apps.
331 struct disk_cache
* disk_cache
;
333 VkPhysicalDeviceMemoryProperties memory_properties
;
334 enum radeon_bo_domain memory_domains
[VK_MAX_MEMORY_TYPES
];
335 enum radeon_bo_flag memory_flags
[VK_MAX_MEMORY_TYPES
];
337 drmPciBusInfo bus_info
;
339 struct radv_device_extension_table supported_extensions
;
342 struct radv_instance
{
343 VK_LOADER_DATA _loader_data
;
345 VkAllocationCallbacks alloc
;
350 uint32_t engineVersion
;
352 uint64_t debug_flags
;
353 uint64_t perftest_flags
;
354 uint8_t num_sc_threads
;
356 struct vk_debug_report_instance debug_report_callbacks
;
358 struct radv_instance_extension_table enabled_extensions
;
359 struct radv_instance_dispatch_table dispatch
;
360 struct radv_physical_device_dispatch_table physical_device_dispatch
;
361 struct radv_device_dispatch_table device_dispatch
;
363 bool physical_devices_enumerated
;
364 struct list_head physical_devices
;
366 struct driOptionCache dri_options
;
367 struct driOptionCache available_dri_options
;
371 bool radv_device_use_secure_compile(struct radv_instance
*instance
)
373 return instance
->num_sc_threads
;
376 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
377 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
379 bool radv_instance_extension_supported(const char *name
);
380 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
381 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
386 struct radv_pipeline_cache
{
387 struct radv_device
* device
;
388 pthread_mutex_t mutex
;
392 uint32_t kernel_count
;
393 struct cache_entry
** hash_table
;
396 VkAllocationCallbacks alloc
;
399 struct radv_pipeline_key
{
400 uint32_t instance_rate_inputs
;
401 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
402 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
403 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
404 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
405 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
406 uint64_t vertex_alpha_adjust
;
407 uint32_t vertex_post_shuffle
;
408 unsigned tess_input_vertices
;
412 uint8_t log2_ps_iter_samples
;
414 uint32_t has_multiview_view_index
: 1;
415 uint32_t optimisations_disabled
: 1;
418 /* Non-zero if a required subgroup size is specified via
419 * VK_EXT_subgroup_size_control.
421 uint8_t compute_subgroup_size
;
424 struct radv_shader_binary
;
425 struct radv_shader_variant
;
428 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
429 struct radv_device
*device
);
431 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
433 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
434 const void *data
, size_t size
);
437 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
438 struct radv_pipeline_cache
*cache
,
439 const unsigned char *sha1
,
440 struct radv_shader_variant
**variants
,
441 bool *found_in_application_cache
);
444 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
445 struct radv_pipeline_cache
*cache
,
446 const unsigned char *sha1
,
447 struct radv_shader_variant
**variants
,
448 struct radv_shader_binary
*const *binaries
);
450 enum radv_blit_ds_layout
{
451 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
452 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
453 RADV_BLIT_DS_LAYOUT_COUNT
,
456 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
458 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
461 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
463 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
466 enum radv_meta_dst_layout
{
467 RADV_META_DST_LAYOUT_GENERAL
,
468 RADV_META_DST_LAYOUT_OPTIMAL
,
469 RADV_META_DST_LAYOUT_COUNT
,
472 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
474 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
477 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
479 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
482 struct radv_meta_state
{
483 VkAllocationCallbacks alloc
;
485 struct radv_pipeline_cache cache
;
488 * For on-demand pipeline creation, makes sure that
489 * only one thread tries to build a pipeline at the same time.
494 * Use array element `i` for images with `2^i` samples.
497 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
498 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
500 VkRenderPass depthstencil_rp
;
501 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
502 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
503 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
505 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
506 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
507 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
508 } clear
[MAX_SAMPLES_LOG2
];
510 VkPipelineLayout clear_color_p_layout
;
511 VkPipelineLayout clear_depth_p_layout
;
512 VkPipelineLayout clear_depth_unrestricted_p_layout
;
514 /* Optimized compute fast HTILE clear for stencil or depth only. */
515 VkPipeline clear_htile_mask_pipeline
;
516 VkPipelineLayout clear_htile_mask_p_layout
;
517 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
520 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
522 /** Pipeline that blits from a 1D image. */
523 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
525 /** Pipeline that blits from a 2D image. */
526 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
528 /** Pipeline that blits from a 3D image. */
529 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
531 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
532 VkPipeline depth_only_1d_pipeline
;
533 VkPipeline depth_only_2d_pipeline
;
534 VkPipeline depth_only_3d_pipeline
;
536 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
537 VkPipeline stencil_only_1d_pipeline
;
538 VkPipeline stencil_only_2d_pipeline
;
539 VkPipeline stencil_only_3d_pipeline
;
540 VkPipelineLayout pipeline_layout
;
541 VkDescriptorSetLayout ds_layout
;
545 VkPipelineLayout p_layouts
[5];
546 VkDescriptorSetLayout ds_layouts
[5];
547 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
549 VkPipeline depth_only_pipeline
[5];
551 VkPipeline stencil_only_pipeline
[5];
552 } blit2d
[MAX_SAMPLES_LOG2
];
554 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
555 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
556 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
559 VkPipelineLayout img_p_layout
;
560 VkDescriptorSetLayout img_ds_layout
;
562 VkPipeline pipeline_3d
;
565 VkPipelineLayout img_p_layout
;
566 VkDescriptorSetLayout img_ds_layout
;
568 VkPipeline pipeline_3d
;
571 VkPipelineLayout img_p_layout
;
572 VkDescriptorSetLayout img_ds_layout
;
576 VkPipelineLayout img_p_layout
;
577 VkDescriptorSetLayout img_ds_layout
;
579 VkPipeline pipeline_3d
;
582 VkPipelineLayout img_p_layout
;
583 VkDescriptorSetLayout img_ds_layout
;
587 VkPipelineLayout img_p_layout
;
588 VkDescriptorSetLayout img_ds_layout
;
590 VkPipeline pipeline_3d
;
593 VkPipelineLayout img_p_layout
;
594 VkDescriptorSetLayout img_ds_layout
;
599 VkPipelineLayout p_layout
;
600 VkPipeline pipeline
[NUM_META_FS_KEYS
];
601 VkRenderPass pass
[NUM_META_FS_KEYS
];
605 VkDescriptorSetLayout ds_layout
;
606 VkPipelineLayout p_layout
;
609 VkPipeline i_pipeline
;
610 VkPipeline srgb_pipeline
;
611 } rc
[MAX_SAMPLES_LOG2
];
613 VkPipeline depth_zero_pipeline
;
615 VkPipeline average_pipeline
;
616 VkPipeline max_pipeline
;
617 VkPipeline min_pipeline
;
618 } depth
[MAX_SAMPLES_LOG2
];
620 VkPipeline stencil_zero_pipeline
;
622 VkPipeline max_pipeline
;
623 VkPipeline min_pipeline
;
624 } stencil
[MAX_SAMPLES_LOG2
];
628 VkDescriptorSetLayout ds_layout
;
629 VkPipelineLayout p_layout
;
632 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
633 VkPipeline pipeline
[NUM_META_FS_KEYS
];
634 } rc
[MAX_SAMPLES_LOG2
];
636 VkRenderPass depth_render_pass
;
637 VkPipeline depth_zero_pipeline
;
639 VkPipeline average_pipeline
;
640 VkPipeline max_pipeline
;
641 VkPipeline min_pipeline
;
642 } depth
[MAX_SAMPLES_LOG2
];
644 VkRenderPass stencil_render_pass
;
645 VkPipeline stencil_zero_pipeline
;
647 VkPipeline max_pipeline
;
648 VkPipeline min_pipeline
;
649 } stencil
[MAX_SAMPLES_LOG2
];
653 VkPipelineLayout p_layout
;
654 VkPipeline decompress_pipeline
[NUM_DEPTH_DECOMPRESS_PIPELINES
];
655 VkPipeline resummarize_pipeline
;
657 } depth_decomp
[MAX_SAMPLES_LOG2
];
660 VkPipelineLayout p_layout
;
661 VkPipeline cmask_eliminate_pipeline
;
662 VkPipeline fmask_decompress_pipeline
;
663 VkPipeline dcc_decompress_pipeline
;
666 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
667 VkPipelineLayout dcc_decompress_compute_p_layout
;
668 VkPipeline dcc_decompress_compute_pipeline
;
672 VkPipelineLayout fill_p_layout
;
673 VkPipelineLayout copy_p_layout
;
674 VkDescriptorSetLayout fill_ds_layout
;
675 VkDescriptorSetLayout copy_ds_layout
;
676 VkPipeline fill_pipeline
;
677 VkPipeline copy_pipeline
;
681 VkDescriptorSetLayout ds_layout
;
682 VkPipelineLayout p_layout
;
683 VkPipeline occlusion_query_pipeline
;
684 VkPipeline pipeline_statistics_query_pipeline
;
685 VkPipeline tfb_query_pipeline
;
686 VkPipeline timestamp_query_pipeline
;
690 VkDescriptorSetLayout ds_layout
;
691 VkPipelineLayout p_layout
;
692 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
697 #define RADV_QUEUE_GENERAL 0
698 #define RADV_QUEUE_COMPUTE 1
699 #define RADV_QUEUE_TRANSFER 2
701 #define RADV_MAX_QUEUE_FAMILIES 3
703 enum ring_type
radv_queue_family_to_ring(int f
);
706 VK_LOADER_DATA _loader_data
;
707 struct radv_device
* device
;
708 struct radeon_winsys_ctx
*hw_ctx
;
709 enum radeon_ctx_priority priority
;
710 uint32_t queue_family_index
;
712 VkDeviceQueueCreateFlags flags
;
714 uint32_t scratch_size_per_wave
;
715 uint32_t scratch_waves
;
716 uint32_t compute_scratch_size_per_wave
;
717 uint32_t compute_scratch_waves
;
718 uint32_t esgs_ring_size
;
719 uint32_t gsvs_ring_size
;
723 bool has_sample_positions
;
725 struct radeon_winsys_bo
*scratch_bo
;
726 struct radeon_winsys_bo
*descriptor_bo
;
727 struct radeon_winsys_bo
*compute_scratch_bo
;
728 struct radeon_winsys_bo
*esgs_ring_bo
;
729 struct radeon_winsys_bo
*gsvs_ring_bo
;
730 struct radeon_winsys_bo
*tess_rings_bo
;
731 struct radeon_winsys_bo
*gds_bo
;
732 struct radeon_winsys_bo
*gds_oa_bo
;
733 struct radeon_cmdbuf
*initial_preamble_cs
;
734 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
735 struct radeon_cmdbuf
*continue_preamble_cs
;
737 struct list_head pending_submissions
;
738 pthread_mutex_t pending_mutex
;
741 struct radv_bo_list
{
742 struct radv_winsys_bo_list list
;
744 pthread_mutex_t mutex
;
747 VkResult
radv_bo_list_add(struct radv_device
*device
,
748 struct radeon_winsys_bo
*bo
);
749 void radv_bo_list_remove(struct radv_device
*device
,
750 struct radeon_winsys_bo
*bo
);
752 struct radv_secure_compile_process
{
753 /* Secure process file descriptors. Used to communicate between the
754 * user facing device and the idle forked device used to fork a clean
755 * process for each new pipeline compile.
758 int fd_secure_output
;
760 /* FIFO file descriptors used to communicate between the user facing
761 * device and the secure process that does the actual secure compile.
766 /* Secure compile process id */
769 /* Is the secure compile process currently in use by a thread */
773 struct radv_secure_compile_state
{
774 struct radv_secure_compile_process
*secure_compile_processes
;
775 uint32_t secure_compile_thread_counter
;
776 mtx_t secure_compile_mutex
;
778 /* Unique process ID used to build name for FIFO file descriptor */
783 VK_LOADER_DATA _loader_data
;
785 VkAllocationCallbacks alloc
;
787 struct radv_instance
* instance
;
788 struct radeon_winsys
*ws
;
790 struct radv_meta_state meta_state
;
792 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
793 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
794 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
796 bool always_use_syncobj
;
799 uint32_t tess_offchip_block_dw_size
;
800 uint32_t scratch_waves
;
801 uint32_t dispatch_initiator
;
803 uint32_t gs_table_depth
;
805 /* MSAA sample locations.
806 * The first index is the sample index.
807 * The second index is the coordinate: X, Y. */
808 float sample_locations_1x
[1][2];
809 float sample_locations_2x
[2][2];
810 float sample_locations_4x
[4][2];
811 float sample_locations_8x
[8][2];
814 uint32_t gfx_init_size_dw
;
815 struct radeon_winsys_bo
*gfx_init
;
817 struct radeon_winsys_bo
*trace_bo
;
818 uint32_t *trace_id_ptr
;
820 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
821 bool keep_shader_info
;
823 struct radv_physical_device
*physical_device
;
825 /* Backup in-memory cache to be used if the app doesn't provide one */
826 struct radv_pipeline_cache
* mem_cache
;
829 * use different counters so MSAA MRTs get consecutive surface indices,
830 * even if MASK is allocated in between.
832 uint32_t image_mrt_offset_counter
;
833 uint32_t fmask_mrt_offset_counter
;
834 struct list_head shader_slabs
;
835 mtx_t shader_slab_mutex
;
837 /* For detecting VM faults reported by dmesg. */
838 uint64_t dmesg_timestamp
;
840 struct radv_device_extension_table enabled_extensions
;
841 struct radv_device_dispatch_table dispatch
;
843 /* Whether the app has enabled the robustBufferAccess feature. */
844 bool robust_buffer_access
;
846 /* Whether the driver uses a global BO list. */
847 bool use_global_bo_list
;
849 struct radv_bo_list bo_list
;
851 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
854 struct radv_secure_compile_state
*sc_state
;
856 /* Condition variable for legacy timelines, to notify waiters when a
857 * new point gets submitted. */
858 pthread_cond_t timeline_cond
;
861 struct radeon_cmdbuf
*thread_trace_start_cs
[2];
862 struct radeon_cmdbuf
*thread_trace_stop_cs
[2];
863 struct radeon_winsys_bo
*thread_trace_bo
;
864 void *thread_trace_ptr
;
865 uint32_t thread_trace_buffer_size
;
866 int thread_trace_start_frame
;
868 /* Overallocation. */
869 bool overallocation_disallowed
;
870 uint64_t allocated_memory_size
[VK_MAX_MEMORY_HEAPS
];
871 mtx_t overallocation_mutex
;
874 struct radv_device_memory
{
875 struct radeon_winsys_bo
*bo
;
876 /* for dedicated allocations */
877 struct radv_image
*image
;
878 struct radv_buffer
*buffer
;
884 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
885 struct AHardwareBuffer
* android_hardware_buffer
;
890 struct radv_descriptor_range
{
895 struct radv_descriptor_set
{
896 const struct radv_descriptor_set_layout
*layout
;
898 uint32_t buffer_count
;
900 struct radeon_winsys_bo
*bo
;
902 uint32_t *mapped_ptr
;
903 struct radv_descriptor_range
*dynamic_descriptors
;
905 struct radeon_winsys_bo
*descriptors
[0];
908 struct radv_push_descriptor_set
910 struct radv_descriptor_set set
;
914 struct radv_descriptor_pool_entry
{
917 struct radv_descriptor_set
*set
;
920 struct radv_descriptor_pool
{
921 struct radeon_winsys_bo
*bo
;
923 uint64_t current_offset
;
926 uint8_t *host_memory_base
;
927 uint8_t *host_memory_ptr
;
928 uint8_t *host_memory_end
;
930 uint32_t entry_count
;
931 uint32_t max_entry_count
;
932 struct radv_descriptor_pool_entry entries
[0];
935 struct radv_descriptor_update_template_entry
{
936 VkDescriptorType descriptor_type
;
938 /* The number of descriptors to update */
939 uint32_t descriptor_count
;
941 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
944 /* In dwords. Not valid/used for dynamic descriptors */
947 uint32_t buffer_offset
;
949 /* Only valid for combined image samplers and samplers */
951 uint8_t sampler_offset
;
957 /* For push descriptors */
958 const uint32_t *immutable_samplers
;
961 struct radv_descriptor_update_template
{
962 uint32_t entry_count
;
963 VkPipelineBindPoint bind_point
;
964 struct radv_descriptor_update_template_entry entry
[0];
970 VkBufferUsageFlags usage
;
971 VkBufferCreateFlags flags
;
974 struct radeon_winsys_bo
* bo
;
980 enum radv_dynamic_state_bits
{
981 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
982 RADV_DYNAMIC_SCISSOR
= 1 << 1,
983 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
984 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
985 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
986 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
987 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
988 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
989 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
990 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
991 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
992 RADV_DYNAMIC_LINE_STIPPLE
= 1 << 11,
993 RADV_DYNAMIC_ALL
= (1 << 12) - 1,
996 enum radv_cmd_dirty_bits
{
997 /* Keep the dynamic state dirty bits in sync with
998 * enum radv_dynamic_state_bits */
999 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
1000 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
1001 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
1002 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
1003 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
1004 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
1005 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
1006 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
1007 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
1008 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
1009 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
1010 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 11,
1011 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 12) - 1,
1012 RADV_CMD_DIRTY_PIPELINE
= 1 << 12,
1013 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 13,
1014 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 14,
1015 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 15,
1016 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 16,
1019 enum radv_cmd_flush_bits
{
1020 /* Instruction cache. */
1021 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
1022 /* Scalar L1 cache. */
1023 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
1024 /* Vector L1 cache. */
1025 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
1026 /* L2 cache + L2 metadata cache writeback & invalidate.
1027 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1028 RADV_CMD_FLAG_INV_L2
= 1 << 3,
1029 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1030 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1031 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1032 RADV_CMD_FLAG_WB_L2
= 1 << 4,
1033 /* Framebuffer caches */
1034 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
1035 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
1036 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
1037 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
1038 /* Engine synchronization. */
1039 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1040 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1041 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1042 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1043 /* Pipeline query controls. */
1044 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1045 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1046 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1048 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1049 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1050 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1051 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1054 struct radv_vertex_binding
{
1055 struct radv_buffer
* buffer
;
1056 VkDeviceSize offset
;
1059 struct radv_streamout_binding
{
1060 struct radv_buffer
*buffer
;
1061 VkDeviceSize offset
;
1065 struct radv_streamout_state
{
1066 /* Mask of bound streamout buffers. */
1067 uint8_t enabled_mask
;
1069 /* External state that comes from the last vertex stage, it must be
1070 * set explicitely when binding a new graphics pipeline.
1072 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1073 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1075 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1076 uint32_t hw_enabled_mask
;
1078 /* State of VGT_STRMOUT_(CONFIG|EN) */
1079 bool streamout_enabled
;
1082 struct radv_viewport_state
{
1084 VkViewport viewports
[MAX_VIEWPORTS
];
1087 struct radv_scissor_state
{
1089 VkRect2D scissors
[MAX_SCISSORS
];
1092 struct radv_discard_rectangle_state
{
1094 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1097 struct radv_sample_locations_state
{
1098 VkSampleCountFlagBits per_pixel
;
1099 VkExtent2D grid_size
;
1101 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1104 struct radv_dynamic_state
{
1106 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1107 * Defines the set of saved dynamic state.
1111 struct radv_viewport_state viewport
;
1113 struct radv_scissor_state scissor
;
1123 float blend_constants
[4];
1133 } stencil_compare_mask
;
1138 } stencil_write_mask
;
1143 } stencil_reference
;
1145 struct radv_discard_rectangle_state discard_rectangle
;
1147 struct radv_sample_locations_state sample_location
;
1155 extern const struct radv_dynamic_state default_dynamic_state
;
1158 radv_get_debug_option_name(int id
);
1161 radv_get_perftest_option_name(int id
);
1163 struct radv_color_buffer_info
{
1164 uint64_t cb_color_base
;
1165 uint64_t cb_color_cmask
;
1166 uint64_t cb_color_fmask
;
1167 uint64_t cb_dcc_base
;
1168 uint32_t cb_color_slice
;
1169 uint32_t cb_color_view
;
1170 uint32_t cb_color_info
;
1171 uint32_t cb_color_attrib
;
1172 uint32_t cb_color_attrib2
; /* GFX9 and later */
1173 uint32_t cb_color_attrib3
; /* GFX10 and later */
1174 uint32_t cb_dcc_control
;
1175 uint32_t cb_color_cmask_slice
;
1176 uint32_t cb_color_fmask_slice
;
1178 uint32_t cb_color_pitch
; // GFX6-GFX8
1179 uint32_t cb_mrt_epitch
; // GFX9+
1183 struct radv_ds_buffer_info
{
1184 uint64_t db_z_read_base
;
1185 uint64_t db_stencil_read_base
;
1186 uint64_t db_z_write_base
;
1187 uint64_t db_stencil_write_base
;
1188 uint64_t db_htile_data_base
;
1189 uint32_t db_depth_info
;
1191 uint32_t db_stencil_info
;
1192 uint32_t db_depth_view
;
1193 uint32_t db_depth_size
;
1194 uint32_t db_depth_slice
;
1195 uint32_t db_htile_surface
;
1196 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1197 uint32_t db_z_info2
; /* GFX9 only */
1198 uint32_t db_stencil_info2
; /* GFX9 only */
1203 radv_initialise_color_surface(struct radv_device
*device
,
1204 struct radv_color_buffer_info
*cb
,
1205 struct radv_image_view
*iview
);
1207 radv_initialise_ds_surface(struct radv_device
*device
,
1208 struct radv_ds_buffer_info
*ds
,
1209 struct radv_image_view
*iview
);
1212 radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
);
1215 * Attachment state when recording a renderpass instance.
1217 * The clear value is valid only if there exists a pending clear.
1219 struct radv_attachment_state
{
1220 VkImageAspectFlags pending_clear_aspects
;
1221 uint32_t cleared_views
;
1222 VkClearValue clear_value
;
1223 VkImageLayout current_layout
;
1224 VkImageLayout current_stencil_layout
;
1225 bool current_in_render_loop
;
1226 struct radv_sample_locations_state sample_location
;
1229 struct radv_color_buffer_info cb
;
1230 struct radv_ds_buffer_info ds
;
1232 struct radv_image_view
*iview
;
1235 struct radv_descriptor_state
{
1236 struct radv_descriptor_set
*sets
[MAX_SETS
];
1239 struct radv_push_descriptor_set push_set
;
1241 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1244 struct radv_subpass_sample_locs_state
{
1245 uint32_t subpass_idx
;
1246 struct radv_sample_locations_state sample_location
;
1249 struct radv_cmd_state
{
1250 /* Vertex descriptors */
1257 uint32_t prefetch_L2_mask
;
1259 struct radv_pipeline
* pipeline
;
1260 struct radv_pipeline
* emitted_pipeline
;
1261 struct radv_pipeline
* compute_pipeline
;
1262 struct radv_pipeline
* emitted_compute_pipeline
;
1263 struct radv_framebuffer
* framebuffer
;
1264 struct radv_render_pass
* pass
;
1265 const struct radv_subpass
* subpass
;
1266 struct radv_dynamic_state dynamic
;
1267 struct radv_attachment_state
* attachments
;
1268 struct radv_streamout_state streamout
;
1269 VkRect2D render_area
;
1271 uint32_t num_subpass_sample_locs
;
1272 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1275 struct radv_buffer
*index_buffer
;
1276 uint64_t index_offset
;
1277 uint32_t index_type
;
1278 uint32_t max_index_count
;
1280 int32_t last_index_type
;
1282 int32_t last_primitive_reset_en
;
1283 uint32_t last_primitive_reset_index
;
1284 enum radv_cmd_flush_bits flush_bits
;
1285 unsigned active_occlusion_queries
;
1286 bool perfect_occlusion_queries_enabled
;
1287 unsigned active_pipeline_queries
;
1288 unsigned active_pipeline_gds_queries
;
1291 uint32_t last_ia_multi_vgt_param
;
1293 uint32_t last_num_instances
;
1294 uint32_t last_first_instance
;
1295 uint32_t last_vertex_offset
;
1297 uint32_t last_sx_ps_downconvert
;
1298 uint32_t last_sx_blend_opt_epsilon
;
1299 uint32_t last_sx_blend_opt_control
;
1301 /* Whether CP DMA is busy/idle. */
1304 /* Conditional rendering info. */
1305 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1306 uint64_t predication_va
;
1308 /* Inheritance info. */
1309 VkQueryPipelineStatisticFlags inherited_pipeline_statistics
;
1311 bool context_roll_without_scissor_emitted
;
1313 /* SQTT related state. */
1314 uint32_t current_event_type
;
1315 uint32_t num_events
;
1316 uint32_t num_layout_transitions
;
1319 struct radv_cmd_pool
{
1320 VkAllocationCallbacks alloc
;
1321 struct list_head cmd_buffers
;
1322 struct list_head free_cmd_buffers
;
1323 uint32_t queue_family_index
;
1326 struct radv_cmd_buffer_upload
{
1330 struct radeon_winsys_bo
*upload_bo
;
1331 struct list_head list
;
1334 enum radv_cmd_buffer_status
{
1335 RADV_CMD_BUFFER_STATUS_INVALID
,
1336 RADV_CMD_BUFFER_STATUS_INITIAL
,
1337 RADV_CMD_BUFFER_STATUS_RECORDING
,
1338 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1339 RADV_CMD_BUFFER_STATUS_PENDING
,
1342 struct radv_cmd_buffer
{
1343 VK_LOADER_DATA _loader_data
;
1345 struct radv_device
* device
;
1347 struct radv_cmd_pool
* pool
;
1348 struct list_head pool_link
;
1350 VkCommandBufferUsageFlags usage_flags
;
1351 VkCommandBufferLevel level
;
1352 enum radv_cmd_buffer_status status
;
1353 struct radeon_cmdbuf
*cs
;
1354 struct radv_cmd_state state
;
1355 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1356 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1357 uint32_t queue_family_index
;
1359 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1360 VkShaderStageFlags push_constant_stages
;
1361 struct radv_descriptor_set meta_push_descriptors
;
1363 struct radv_descriptor_state descriptors
[MAX_BIND_POINTS
];
1365 struct radv_cmd_buffer_upload upload
;
1367 uint32_t scratch_size_per_wave_needed
;
1368 uint32_t scratch_waves_wanted
;
1369 uint32_t compute_scratch_size_per_wave_needed
;
1370 uint32_t compute_scratch_waves_wanted
;
1371 uint32_t esgs_ring_size_needed
;
1372 uint32_t gsvs_ring_size_needed
;
1373 bool tess_rings_needed
;
1374 bool gds_needed
; /* for GFX10 streamout and NGG GS queries */
1375 bool gds_oa_needed
; /* for GFX10 streamout */
1376 bool sample_positions_needed
;
1378 VkResult record_result
;
1380 uint64_t gfx9_fence_va
;
1381 uint32_t gfx9_fence_idx
;
1382 uint64_t gfx9_eop_bug_va
;
1385 * Whether a query pool has been resetted and we have to flush caches.
1387 bool pending_reset_query
;
1390 * Bitmask of pending active query flushes.
1392 enum radv_cmd_flush_bits active_query_flush_bits
;
1396 struct radv_image_view
;
1398 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1400 void si_emit_graphics(struct radv_device
*device
,
1401 struct radeon_cmdbuf
*cs
);
1402 void si_emit_compute(struct radv_physical_device
*physical_device
,
1403 struct radeon_cmdbuf
*cs
);
1405 void cik_create_gfx_config(struct radv_device
*device
);
1407 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1408 int count
, const VkViewport
*viewports
);
1409 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1410 int count
, const VkRect2D
*scissors
,
1411 const VkViewport
*viewports
, bool can_use_guardband
);
1412 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1413 bool instanced_draw
, bool indirect_draw
,
1414 bool count_from_stream_output
,
1415 uint32_t draw_vertex_count
);
1416 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1417 enum chip_class chip_class
,
1419 unsigned event
, unsigned event_flags
,
1420 unsigned dst_sel
, unsigned data_sel
,
1423 uint64_t gfx9_eop_bug_va
);
1425 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1426 uint32_t ref
, uint32_t mask
);
1427 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1428 enum chip_class chip_class
,
1429 uint32_t *fence_ptr
, uint64_t va
,
1431 enum radv_cmd_flush_bits flush_bits
,
1432 uint64_t gfx9_eop_bug_va
);
1433 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1434 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1435 bool inverted
, uint64_t va
);
1436 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1437 uint64_t src_va
, uint64_t dest_va
,
1439 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1441 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1442 uint64_t size
, unsigned value
);
1443 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1445 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1447 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1450 unsigned *out_offset
,
1453 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1454 const struct radv_subpass
*subpass
);
1456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1457 unsigned size
, unsigned alignmnet
,
1458 const void *data
, unsigned *out_offset
);
1460 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1461 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1462 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1463 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1464 VkImageAspectFlags aspects
,
1465 VkResolveModeFlagBits resolve_mode
);
1466 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1467 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1468 VkImageAspectFlags aspects
,
1469 VkResolveModeFlagBits resolve_mode
);
1470 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1471 unsigned radv_get_default_max_sample_dist(int log_samples
);
1472 void radv_device_init_msaa(struct radv_device
*device
);
1474 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1475 const struct radv_image_view
*iview
,
1476 VkClearDepthStencilValue ds_clear_value
,
1477 VkImageAspectFlags aspects
);
1479 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1480 const struct radv_image_view
*iview
,
1482 uint32_t color_values
[2]);
1484 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1485 struct radv_image
*image
,
1486 const VkImageSubresourceRange
*range
, bool value
);
1488 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1489 struct radv_image
*image
,
1490 const VkImageSubresourceRange
*range
, bool value
);
1492 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1493 struct radeon_winsys_bo
*bo
,
1494 uint64_t offset
, uint64_t size
, uint32_t value
);
1495 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1496 bool radv_get_memory_fd(struct radv_device
*device
,
1497 struct radv_device_memory
*memory
,
1501 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1502 unsigned sh_offset
, unsigned pointer_count
,
1503 bool use_32bit_pointers
)
1505 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1506 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1510 radv_emit_shader_pointer_body(struct radv_device
*device
,
1511 struct radeon_cmdbuf
*cs
,
1512 uint64_t va
, bool use_32bit_pointers
)
1514 radeon_emit(cs
, va
);
1516 if (use_32bit_pointers
) {
1518 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1520 radeon_emit(cs
, va
>> 32);
1525 radv_emit_shader_pointer(struct radv_device
*device
,
1526 struct radeon_cmdbuf
*cs
,
1527 uint32_t sh_offset
, uint64_t va
, bool global
)
1529 bool use_32bit_pointers
= !global
;
1531 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1532 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1535 static inline struct radv_descriptor_state
*
1536 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1537 VkPipelineBindPoint bind_point
)
1539 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1540 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1541 return &cmd_buffer
->descriptors
[bind_point
];
1545 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1547 * Limitations: Can't call normal dispatch functions without binding or rebinding
1548 * the compute pipeline.
1550 void radv_unaligned_dispatch(
1551 struct radv_cmd_buffer
*cmd_buffer
,
1557 struct radeon_winsys_bo
*bo
;
1561 struct radv_shader_module
;
1563 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1564 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1565 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1566 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1567 #define RADV_HASH_SHADER_ACO (1 << 4)
1570 radv_hash_shaders(unsigned char *hash
,
1571 const VkPipelineShaderStageCreateInfo
**stages
,
1572 const struct radv_pipeline_layout
*layout
,
1573 const struct radv_pipeline_key
*key
,
1576 static inline gl_shader_stage
1577 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1579 assert(__builtin_popcount(vk_stage
) == 1);
1580 return ffs(vk_stage
) - 1;
1583 static inline VkShaderStageFlagBits
1584 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1586 return (1 << mesa_stage
);
1589 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1591 #define radv_foreach_stage(stage, stage_bits) \
1592 for (gl_shader_stage stage, \
1593 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1594 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1595 __tmp &= ~(1 << (stage)))
1597 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1598 unsigned radv_format_meta_fs_key(VkFormat format
);
1600 struct radv_multisample_state
{
1602 uint32_t pa_sc_line_cntl
;
1603 uint32_t pa_sc_mode_cntl_0
;
1604 uint32_t pa_sc_mode_cntl_1
;
1605 uint32_t pa_sc_aa_config
;
1606 uint32_t pa_sc_aa_mask
[2];
1607 unsigned num_samples
;
1610 struct radv_prim_vertex_count
{
1615 struct radv_vertex_elements_info
{
1616 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1619 struct radv_ia_multi_vgt_param_helpers
{
1621 bool partial_es_wave
;
1622 uint8_t primgroup_size
;
1623 bool wd_switch_on_eop
;
1624 bool ia_switch_on_eoi
;
1625 bool partial_vs_wave
;
1628 struct radv_binning_state
{
1629 uint32_t pa_sc_binner_cntl_0
;
1630 uint32_t db_dfsm_control
;
1633 #define SI_GS_PER_ES 128
1635 struct radv_pipeline
{
1636 struct radv_device
* device
;
1637 struct radv_dynamic_state dynamic_state
;
1639 struct radv_pipeline_layout
* layout
;
1641 bool need_indirect_descriptor_sets
;
1642 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1643 struct radv_shader_variant
*gs_copy_shader
;
1644 VkShaderStageFlags active_stages
;
1646 struct radeon_cmdbuf cs
;
1647 uint32_t ctx_cs_hash
;
1648 struct radeon_cmdbuf ctx_cs
;
1650 struct radv_vertex_elements_info vertex_elements
;
1652 uint32_t binding_stride
[MAX_VBS
];
1653 uint8_t num_vertex_bindings
;
1655 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1658 struct radv_multisample_state ms
;
1659 struct radv_binning_state binning
;
1660 uint32_t spi_baryc_cntl
;
1661 bool prim_restart_enable
;
1662 unsigned esgs_ring_size
;
1663 unsigned gsvs_ring_size
;
1664 uint32_t vtx_base_sgpr
;
1665 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1666 uint8_t vtx_emit_num
;
1667 struct radv_prim_vertex_count prim_vertex_count
;
1668 bool can_use_guardband
;
1669 uint32_t needed_dynamic_state
;
1670 bool disable_out_of_order_rast_for_occlusion
;
1673 /* Used for rbplus */
1674 uint32_t col_format
;
1675 uint32_t cb_target_mask
;
1680 unsigned scratch_bytes_per_wave
;
1682 /* Not NULL if graphics pipeline uses streamout. */
1683 struct radv_shader_variant
*streamout_shader
;
1686 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1688 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1691 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1693 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1696 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1698 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
);
1700 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1702 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1703 gl_shader_stage stage
,
1706 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1707 gl_shader_stage stage
);
1709 struct radv_graphics_pipeline_create_info
{
1711 bool db_depth_clear
;
1712 bool db_stencil_clear
;
1713 bool db_depth_disable_expclear
;
1714 bool db_stencil_disable_expclear
;
1715 bool depth_compress_disable
;
1716 bool stencil_compress_disable
;
1717 bool resummarize_enable
;
1718 uint32_t custom_blend_mode
;
1722 radv_graphics_pipeline_create(VkDevice device
,
1723 VkPipelineCache cache
,
1724 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1725 const struct radv_graphics_pipeline_create_info
*extra
,
1726 const VkAllocationCallbacks
*alloc
,
1727 VkPipeline
*pPipeline
);
1729 struct radv_binning_settings
{
1730 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
1731 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
1732 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
1735 struct radv_binning_settings
1736 radv_get_binning_settings(const struct radv_physical_device
*pdev
);
1738 struct vk_format_description
;
1739 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1740 int first_non_void
);
1741 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1742 int first_non_void
);
1743 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1744 uint32_t radv_translate_colorformat(VkFormat format
);
1745 uint32_t radv_translate_color_numformat(VkFormat format
,
1746 const struct vk_format_description
*desc
,
1747 int first_non_void
);
1748 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1749 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1750 uint32_t radv_translate_dbformat(VkFormat format
);
1751 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1752 const struct vk_format_description
*desc
,
1753 int first_non_void
);
1754 uint32_t radv_translate_tex_numformat(VkFormat format
,
1755 const struct vk_format_description
*desc
,
1756 int first_non_void
);
1757 bool radv_format_pack_clear_color(VkFormat format
,
1758 uint32_t clear_vals
[2],
1759 VkClearColorValue
*value
);
1760 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1761 bool radv_dcc_formats_compatible(VkFormat format1
,
1763 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1765 struct radv_image_plane
{
1767 struct radeon_surf surface
;
1773 /* The original VkFormat provided by the client. This may not match any
1774 * of the actual surface formats.
1777 VkImageAspectFlags aspects
;
1778 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1779 struct ac_surf_info info
;
1780 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1781 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1786 unsigned queue_family_mask
;
1790 /* Set when bound */
1791 struct radeon_winsys_bo
*bo
;
1792 VkDeviceSize offset
;
1793 uint64_t dcc_offset
;
1794 uint64_t htile_offset
;
1795 bool tc_compatible_htile
;
1796 bool tc_compatible_cmask
;
1798 uint64_t cmask_offset
;
1799 uint64_t fmask_offset
;
1800 uint64_t clear_value_offset
;
1801 uint64_t fce_pred_offset
;
1802 uint64_t dcc_pred_offset
;
1805 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1806 * stored at this offset is UINT_MAX, the driver will emit
1807 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1808 * SET_CONTEXT_REG packet.
1810 uint64_t tc_compat_zrange_offset
;
1812 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1813 VkDeviceMemory owned_memory
;
1815 unsigned plane_count
;
1816 struct radv_image_plane planes
[0];
1819 /* Whether the image has a htile that is known consistent with the contents of
1820 * the image and is allowed to be in compressed form.
1822 * If this is false reads that don't use the htile should be able to return
1825 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1826 VkImageLayout layout
,
1827 bool in_render_loop
,
1828 unsigned queue_mask
);
1830 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1831 VkImageLayout layout
,
1832 bool in_render_loop
,
1833 unsigned queue_mask
);
1835 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1836 const struct radv_image
*image
,
1837 VkImageLayout layout
,
1838 bool in_render_loop
,
1839 unsigned queue_mask
);
1842 * Return whether the image has CMASK metadata for color surfaces.
1845 radv_image_has_cmask(const struct radv_image
*image
)
1847 return image
->cmask_offset
;
1851 * Return whether the image has FMASK metadata for color surfaces.
1854 radv_image_has_fmask(const struct radv_image
*image
)
1856 return image
->fmask_offset
;
1860 * Return whether the image has DCC metadata for color surfaces.
1863 radv_image_has_dcc(const struct radv_image
*image
)
1865 return image
->planes
[0].surface
.dcc_size
;
1869 * Return whether the image is TC-compatible CMASK.
1872 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1874 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1878 * Return whether DCC metadata is enabled for a level.
1881 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1883 return radv_image_has_dcc(image
) &&
1884 level
< image
->planes
[0].surface
.num_dcc_levels
;
1888 * Return whether the image has CB metadata.
1891 radv_image_has_CB_metadata(const struct radv_image
*image
)
1893 return radv_image_has_cmask(image
) ||
1894 radv_image_has_fmask(image
) ||
1895 radv_image_has_dcc(image
);
1899 * Return whether the image has HTILE metadata for depth surfaces.
1902 radv_image_has_htile(const struct radv_image
*image
)
1904 return image
->planes
[0].surface
.htile_size
;
1908 * Return whether HTILE metadata is enabled for a level.
1911 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1913 return radv_image_has_htile(image
) && level
== 0;
1917 * Return whether the image is TC-compatible HTILE.
1920 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1922 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1925 static inline uint64_t
1926 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1927 uint32_t base_level
)
1929 uint64_t va
= radv_buffer_get_va(image
->bo
);
1930 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1934 static inline uint64_t
1935 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1936 uint32_t base_level
)
1938 uint64_t va
= radv_buffer_get_va(image
->bo
);
1939 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1943 static inline uint64_t
1944 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1945 uint32_t base_level
)
1947 uint64_t va
= radv_buffer_get_va(image
->bo
);
1948 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1952 static inline uint64_t
1953 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1954 uint32_t base_level
)
1956 uint64_t va
= radv_buffer_get_va(image
->bo
);
1957 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1961 static inline uint64_t
1962 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1963 uint32_t base_level
)
1965 uint64_t va
= radv_buffer_get_va(image
->bo
);
1966 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1970 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1972 static inline uint32_t
1973 radv_get_layerCount(const struct radv_image
*image
,
1974 const VkImageSubresourceRange
*range
)
1976 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1977 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1980 static inline uint32_t
1981 radv_get_levelCount(const struct radv_image
*image
,
1982 const VkImageSubresourceRange
*range
)
1984 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1985 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1988 struct radeon_bo_metadata
;
1990 radv_init_metadata(struct radv_device
*device
,
1991 struct radv_image
*image
,
1992 struct radeon_bo_metadata
*metadata
);
1995 radv_image_override_offset_stride(struct radv_device
*device
,
1996 struct radv_image
*image
,
1997 uint64_t offset
, uint32_t stride
);
1999 union radv_descriptor
{
2001 uint32_t plane0_descriptor
[8];
2002 uint32_t fmask_descriptor
[8];
2005 uint32_t plane_descriptors
[3][8];
2009 struct radv_image_view
{
2010 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
2011 struct radeon_winsys_bo
*bo
;
2013 VkImageViewType type
;
2014 VkImageAspectFlags aspect_mask
;
2017 bool multiple_planes
;
2018 uint32_t base_layer
;
2019 uint32_t layer_count
;
2021 uint32_t level_count
;
2022 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2024 union radv_descriptor descriptor
;
2026 /* Descriptor for use as a storage image as opposed to a sampled image.
2027 * This has a few differences for cube maps (e.g. type).
2029 union radv_descriptor storage_descriptor
;
2032 struct radv_image_create_info
{
2033 const VkImageCreateInfo
*vk_info
;
2035 bool no_metadata_planes
;
2036 const struct radeon_bo_metadata
*bo_metadata
;
2040 radv_image_create_layout(struct radv_device
*device
,
2041 struct radv_image_create_info create_info
,
2042 struct radv_image
*image
);
2044 VkResult
radv_image_create(VkDevice _device
,
2045 const struct radv_image_create_info
*info
,
2046 const VkAllocationCallbacks
* alloc
,
2049 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
2052 radv_image_from_gralloc(VkDevice device_h
,
2053 const VkImageCreateInfo
*base_info
,
2054 const VkNativeBufferANDROID
*gralloc_info
,
2055 const VkAllocationCallbacks
*alloc
,
2056 VkImage
*out_image_h
);
2058 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
2059 const VkImageUsageFlags vk_usage
);
2061 radv_import_ahb_memory(struct radv_device
*device
,
2062 struct radv_device_memory
*mem
,
2064 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2066 radv_create_ahb_memory(struct radv_device
*device
,
2067 struct radv_device_memory
*mem
,
2069 const VkMemoryAllocateInfo
*pAllocateInfo
);
2072 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2074 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2076 struct radv_image_view_extra_create_info
{
2077 bool disable_compression
;
2080 void radv_image_view_init(struct radv_image_view
*view
,
2081 struct radv_device
*device
,
2082 const VkImageViewCreateInfo
*pCreateInfo
,
2083 const struct radv_image_view_extra_create_info
* extra_create_info
);
2085 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2087 struct radv_sampler_ycbcr_conversion
{
2089 VkSamplerYcbcrModelConversion ycbcr_model
;
2090 VkSamplerYcbcrRange ycbcr_range
;
2091 VkComponentMapping components
;
2092 VkChromaLocation chroma_offsets
[2];
2093 VkFilter chroma_filter
;
2096 struct radv_buffer_view
{
2097 struct radeon_winsys_bo
*bo
;
2099 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2102 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2103 struct radv_device
*device
,
2104 const VkBufferViewCreateInfo
* pCreateInfo
);
2106 static inline struct VkExtent3D
2107 radv_sanitize_image_extent(const VkImageType imageType
,
2108 const struct VkExtent3D imageExtent
)
2110 switch (imageType
) {
2111 case VK_IMAGE_TYPE_1D
:
2112 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2113 case VK_IMAGE_TYPE_2D
:
2114 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2115 case VK_IMAGE_TYPE_3D
:
2118 unreachable("invalid image type");
2122 static inline struct VkOffset3D
2123 radv_sanitize_image_offset(const VkImageType imageType
,
2124 const struct VkOffset3D imageOffset
)
2126 switch (imageType
) {
2127 case VK_IMAGE_TYPE_1D
:
2128 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2129 case VK_IMAGE_TYPE_2D
:
2130 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2131 case VK_IMAGE_TYPE_3D
:
2134 unreachable("invalid image type");
2139 radv_image_extent_compare(const struct radv_image
*image
,
2140 const VkExtent3D
*extent
)
2142 if (extent
->width
!= image
->info
.width
||
2143 extent
->height
!= image
->info
.height
||
2144 extent
->depth
!= image
->info
.depth
)
2149 struct radv_sampler
{
2151 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2154 struct radv_framebuffer
{
2159 uint32_t attachment_count
;
2160 struct radv_image_view
*attachments
[0];
2163 struct radv_subpass_barrier
{
2164 VkPipelineStageFlags src_stage_mask
;
2165 VkAccessFlags src_access_mask
;
2166 VkAccessFlags dst_access_mask
;
2169 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2170 const struct radv_subpass_barrier
*barrier
);
2172 struct radv_subpass_attachment
{
2173 uint32_t attachment
;
2174 VkImageLayout layout
;
2175 VkImageLayout stencil_layout
;
2176 bool in_render_loop
;
2179 struct radv_subpass
{
2180 uint32_t attachment_count
;
2181 struct radv_subpass_attachment
* attachments
;
2183 uint32_t input_count
;
2184 uint32_t color_count
;
2185 struct radv_subpass_attachment
* input_attachments
;
2186 struct radv_subpass_attachment
* color_attachments
;
2187 struct radv_subpass_attachment
* resolve_attachments
;
2188 struct radv_subpass_attachment
* depth_stencil_attachment
;
2189 struct radv_subpass_attachment
* ds_resolve_attachment
;
2190 VkResolveModeFlagBits depth_resolve_mode
;
2191 VkResolveModeFlagBits stencil_resolve_mode
;
2193 /** Subpass has at least one color resolve attachment */
2194 bool has_color_resolve
;
2196 /** Subpass has at least one color attachment */
2199 struct radv_subpass_barrier start_barrier
;
2203 VkSampleCountFlagBits color_sample_count
;
2204 VkSampleCountFlagBits depth_sample_count
;
2205 VkSampleCountFlagBits max_sample_count
;
2209 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2211 struct radv_render_pass_attachment
{
2214 VkAttachmentLoadOp load_op
;
2215 VkAttachmentLoadOp stencil_load_op
;
2216 VkImageLayout initial_layout
;
2217 VkImageLayout final_layout
;
2218 VkImageLayout stencil_initial_layout
;
2219 VkImageLayout stencil_final_layout
;
2221 /* The subpass id in which the attachment will be used first/last. */
2222 uint32_t first_subpass_idx
;
2223 uint32_t last_subpass_idx
;
2226 struct radv_render_pass
{
2227 uint32_t attachment_count
;
2228 uint32_t subpass_count
;
2229 struct radv_subpass_attachment
* subpass_attachments
;
2230 struct radv_render_pass_attachment
* attachments
;
2231 struct radv_subpass_barrier end_barrier
;
2232 struct radv_subpass subpasses
[0];
2235 VkResult
radv_device_init_meta(struct radv_device
*device
);
2236 void radv_device_finish_meta(struct radv_device
*device
);
2238 struct radv_query_pool
{
2239 struct radeon_winsys_bo
*bo
;
2241 uint32_t availability_offset
;
2245 uint32_t pipeline_stats_mask
;
2249 RADV_SEMAPHORE_NONE
,
2250 RADV_SEMAPHORE_WINSYS
,
2251 RADV_SEMAPHORE_SYNCOBJ
,
2252 RADV_SEMAPHORE_TIMELINE
,
2253 } radv_semaphore_kind
;
2255 struct radv_deferred_queue_submission
;
2257 struct radv_timeline_waiter
{
2258 struct list_head list
;
2259 struct radv_deferred_queue_submission
*submission
;
2263 struct radv_timeline_point
{
2264 struct list_head list
;
2269 /* Separate from the list to accomodate CPU wait being async, as well
2270 * as prevent point deletion during submission. */
2271 unsigned wait_count
;
2274 struct radv_timeline
{
2275 /* Using a pthread mutex to be compatible with condition variables. */
2276 pthread_mutex_t mutex
;
2278 uint64_t highest_signaled
;
2279 uint64_t highest_submitted
;
2281 struct list_head points
;
2283 /* Keep free points on hand so we do not have to recreate syncobjs all
2285 struct list_head free_points
;
2287 /* Submissions that are deferred waiting for a specific value to be
2289 struct list_head waiters
;
2292 struct radv_semaphore_part
{
2293 radv_semaphore_kind kind
;
2296 struct radeon_winsys_sem
*ws_sem
;
2297 struct radv_timeline timeline
;
2301 struct radv_semaphore
{
2302 struct radv_semaphore_part permanent
;
2303 struct radv_semaphore_part temporary
;
2306 bool radv_queue_internal_submit(struct radv_queue
*queue
,
2307 struct radeon_cmdbuf
*cs
);
2309 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2310 VkPipelineBindPoint bind_point
,
2311 struct radv_descriptor_set
*set
,
2315 radv_update_descriptor_sets(struct radv_device
*device
,
2316 struct radv_cmd_buffer
*cmd_buffer
,
2317 VkDescriptorSet overrideSet
,
2318 uint32_t descriptorWriteCount
,
2319 const VkWriteDescriptorSet
*pDescriptorWrites
,
2320 uint32_t descriptorCopyCount
,
2321 const VkCopyDescriptorSet
*pDescriptorCopies
);
2324 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2325 struct radv_cmd_buffer
*cmd_buffer
,
2326 struct radv_descriptor_set
*set
,
2327 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2330 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2331 VkPipelineBindPoint pipelineBindPoint
,
2332 VkPipelineLayout _layout
,
2334 uint32_t descriptorWriteCount
,
2335 const VkWriteDescriptorSet
*pDescriptorWrites
);
2337 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2338 struct radv_image
*image
,
2339 const VkImageSubresourceRange
*range
, uint32_t value
);
2341 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2342 struct radv_image
*image
,
2343 const VkImageSubresourceRange
*range
);
2346 struct radeon_winsys_fence
*fence
;
2347 struct wsi_fence
*fence_wsi
;
2350 uint32_t temp_syncobj
;
2353 /* radv_nir_to_llvm.c */
2354 struct radv_shader_args
;
2356 void llvm_compile_shader(struct radv_device
*device
,
2357 unsigned shader_count
,
2358 struct nir_shader
*const *shaders
,
2359 struct radv_shader_binary
**binary
,
2360 struct radv_shader_args
*args
);
2362 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2363 gl_shader_stage stage
,
2364 const struct nir_shader
*nir
);
2366 /* radv_shader_info.h */
2367 struct radv_shader_info
;
2368 struct radv_shader_variant_key
;
2370 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2371 const struct radv_pipeline_layout
*layout
,
2372 const struct radv_shader_variant_key
*key
,
2373 struct radv_shader_info
*info
,
2376 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2379 struct radv_thread_trace_info
{
2380 uint32_t cur_offset
;
2381 uint32_t trace_status
;
2383 uint32_t gfx9_write_counter
;
2384 uint32_t gfx10_dropped_cntr
;
2388 struct radv_thread_trace_se
{
2389 struct radv_thread_trace_info info
;
2391 uint32_t shader_engine
;
2392 uint32_t compute_unit
;
2395 struct radv_thread_trace
{
2396 uint32_t num_traces
;
2397 struct radv_thread_trace_se traces
[4];
2400 bool radv_thread_trace_init(struct radv_device
*device
);
2401 void radv_thread_trace_finish(struct radv_device
*device
);
2402 bool radv_begin_thread_trace(struct radv_queue
*queue
);
2403 bool radv_end_thread_trace(struct radv_queue
*queue
);
2404 bool radv_get_thread_trace(struct radv_queue
*queue
,
2405 struct radv_thread_trace
*thread_trace
);
2406 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf
*cs
,
2407 const void *data
, uint32_t num_dwords
);
2410 int radv_dump_thread_trace(struct radv_device
*device
,
2411 const struct radv_thread_trace
*trace
);
2413 /* radv_sqtt_layer_.c */
2414 struct radv_barrier_data
{
2417 uint16_t depth_stencil_expand
: 1;
2418 uint16_t htile_hiz_range_expand
: 1;
2419 uint16_t depth_stencil_resummarize
: 1;
2420 uint16_t dcc_decompress
: 1;
2421 uint16_t fmask_decompress
: 1;
2422 uint16_t fast_clear_eliminate
: 1;
2423 uint16_t fmask_color_expand
: 1;
2424 uint16_t init_mask_ram
: 1;
2425 uint16_t reserved
: 8;
2428 } layout_transitions
;
2432 * Value for the reason field of an RGP barrier start marker originating from
2433 * the Vulkan client (does not include PAL-defined values). (Table 15)
2435 enum rgp_barrier_reason
{
2436 RGP_BARRIER_UNKNOWN_REASON
= 0xFFFFFFFF,
2438 /* External app-generated barrier reasons, i.e. API synchronization
2439 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2441 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
= 0x00000001,
2442 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
= 0x00000002,
2443 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
= 0x00000003,
2445 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2446 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2448 RGP_BARRIER_INTERNAL_BASE
= 0xC0000000,
2449 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 0,
2450 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 1,
2451 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL
= RGP_BARRIER_INTERNAL_BASE
+ 2,
2452 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 3
2455 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2456 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2457 void radv_describe_draw(struct radv_cmd_buffer
*cmd_buffer
);
2458 void radv_describe_dispatch(struct radv_cmd_buffer
*cmd_buffer
, int x
, int y
, int z
);
2459 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
,
2460 VkImageAspectFlagBits aspects
);
2461 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
);
2462 void radv_describe_barrier_start(struct radv_cmd_buffer
*cmd_buffer
,
2463 enum rgp_barrier_reason reason
);
2464 void radv_describe_barrier_end(struct radv_cmd_buffer
*cmd_buffer
);
2465 void radv_describe_layout_transition(struct radv_cmd_buffer
*cmd_buffer
,
2466 const struct radv_barrier_data
*barrier
);
2468 struct radeon_winsys_sem
;
2470 uint64_t radv_get_current_time(void);
2472 static inline uint32_t
2473 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2476 case 0: /* GL_POINTS */
2478 case 1: /* GL_LINES */
2479 case 3: /* GL_LINE_STRIP */
2481 case 4: /* GL_TRIANGLES */
2482 case 5: /* GL_TRIANGLE_STRIP */
2484 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2486 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2488 case 7: /* GL_QUADS */
2489 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2496 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
2497 const VkRenderPassBeginInfo
*pRenderPassBegin
);
2498 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
);
2500 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2502 static inline struct __radv_type * \
2503 __radv_type ## _from_handle(__VkType _handle) \
2505 return (struct __radv_type *) _handle; \
2508 static inline __VkType \
2509 __radv_type ## _to_handle(struct __radv_type *_obj) \
2511 return (__VkType) _obj; \
2514 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2516 static inline struct __radv_type * \
2517 __radv_type ## _from_handle(__VkType _handle) \
2519 return (struct __radv_type *)(uintptr_t) _handle; \
2522 static inline __VkType \
2523 __radv_type ## _to_handle(struct __radv_type *_obj) \
2525 return (__VkType)(uintptr_t) _obj; \
2528 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2529 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2531 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2532 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2533 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2534 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2535 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2537 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2538 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2539 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2540 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2541 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2542 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2543 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2544 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2545 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2546 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2547 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2548 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2549 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2550 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2551 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2552 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2553 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2554 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2555 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2556 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2557 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2558 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2560 #endif /* RADV_PRIVATE_H */