2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "radv_radeon_winsys.h"
52 #include "ac_binary.h"
53 #include "ac_nir_to_llvm.h"
54 #include "radv_descriptor_set.h"
56 #include <llvm-c/TargetMachine.h>
58 /* Pre-declarations needed for WSI entrypoints */
61 typedef struct xcb_connection_t xcb_connection_t
;
62 typedef uint32_t xcb_visualid_t
;
63 typedef uint32_t xcb_window_t
;
65 #include <vulkan/vulkan.h>
66 #include <vulkan/vulkan_intel.h>
67 #include <vulkan/vk_icd.h>
69 #include "radv_entrypoints.h"
73 #define MAX_VERTEX_ATTRIBS 32
75 #define MAX_VIEWPORTS 16
76 #define MAX_SCISSORS 16
77 #define MAX_PUSH_CONSTANTS_SIZE 128
78 #define MAX_DYNAMIC_BUFFERS 16
80 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
81 #define NUM_META_FS_KEYS 11
83 #define NUM_DEPTH_CLEAR_PIPELINES 3
85 #define radv_noreturn __attribute__((__noreturn__))
86 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
88 #define MIN(a, b) ((a) < (b) ? (a) : (b))
89 #define MAX(a, b) ((a) > (b) ? (a) : (b))
91 static inline uint32_t
92 align_u32(uint32_t v
, uint32_t a
)
94 assert(a
!= 0 && a
== (a
& -a
));
95 return (v
+ a
- 1) & ~(a
- 1);
98 static inline uint32_t
99 align_u32_npot(uint32_t v
, uint32_t a
)
101 return (v
+ a
- 1) / a
* a
;
104 static inline uint64_t
105 align_u64(uint64_t v
, uint64_t a
)
107 assert(a
!= 0 && a
== (a
& -a
));
108 return (v
+ a
- 1) & ~(a
- 1);
111 static inline int32_t
112 align_i32(int32_t v
, int32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 /** Alignment must be a power of 2. */
120 radv_is_aligned(uintmax_t n
, uintmax_t a
)
122 assert(a
== (a
& -a
));
123 return (n
& (a
- 1)) == 0;
126 static inline uint32_t
127 round_up_u32(uint32_t v
, uint32_t a
)
129 return (v
+ a
- 1) / a
;
132 static inline uint64_t
133 round_up_u64(uint64_t v
, uint64_t a
)
135 return (v
+ a
- 1) / a
;
138 static inline uint32_t
139 radv_minify(uint32_t n
, uint32_t levels
)
141 if (unlikely(n
== 0))
144 return MAX(n
>> levels
, 1);
147 radv_clamp_f(float f
, float min
, float max
)
160 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
162 if (*inout_mask
& clear_mask
) {
163 *inout_mask
&= ~clear_mask
;
170 #define for_each_bit(b, dword) \
171 for (uint32_t __dword = (dword); \
172 (b) = __builtin_ffs(__dword) - 1, __dword; \
173 __dword &= ~(1 << (b)))
175 #define typed_memcpy(dest, src, count) ({ \
176 static_assert(sizeof(*src) == sizeof(*dest), ""); \
177 memcpy((dest), (src), (count) * sizeof(*(src))); \
180 #define zero(x) (memset(&(x), 0, sizeof(x)))
182 /* Define no kernel as 1, since that's an illegal offset for a kernel */
186 VkStructureType sType
;
190 /* Whenever we generate an error, pass it through this function. Useful for
191 * debugging, where we can break on it. Only call at error site, not when
192 * propagating errors. Might be useful to plug in a stack trace here.
195 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
198 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
199 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
201 #define vk_error(error) error
202 #define vk_errorf(error, format, ...) error
205 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
206 radv_printflike(3, 4);
207 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
208 void radv_loge_v(const char *format
, va_list va
);
211 * Print a FINISHME message, including its source location.
213 #define radv_finishme(format, ...) \
214 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
216 /* A non-fatal assert. Useful for debugging. */
218 #define radv_assert(x) ({ \
219 if (unlikely(!(x))) \
220 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
223 #define radv_assert(x)
226 void radv_abortf(const char *format
, ...) radv_noreturn
radv_printflike(1, 2);
227 void radv_abortfv(const char *format
, va_list va
) radv_noreturn
;
229 #define stub_return(v) \
231 radv_finishme("stub %s", __func__); \
237 radv_finishme("stub %s", __func__); \
242 * A dynamically growable, circular buffer. Elements are added at head and
243 * removed from tail. head and tail are free-running uint32_t indices and we
244 * only compute the modulo with size when accessing the array. This way,
245 * number of bytes in the queue is always head - tail, even in case of
252 uint32_t element_size
;
257 int radv_vector_init(struct radv_vector
*queue
, uint32_t element_size
, uint32_t size
);
258 void *radv_vector_add(struct radv_vector
*queue
);
259 void *radv_vector_remove(struct radv_vector
*queue
);
262 radv_vector_length(struct radv_vector
*queue
)
264 return (queue
->head
- queue
->tail
) / queue
->element_size
;
268 radv_vector_head(struct radv_vector
*vector
)
270 assert(vector
->tail
< vector
->head
);
271 return (void *)((char *)vector
->data
+
272 ((vector
->head
- vector
->element_size
) &
273 (vector
->size
- 1)));
277 radv_vector_tail(struct radv_vector
*vector
)
279 return (void *)((char *)vector
->data
+ (vector
->tail
& (vector
->size
- 1)));
283 radv_vector_finish(struct radv_vector
*queue
)
288 #define radv_vector_foreach(elem, queue) \
289 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct radv_vector *), ""); \
290 for (uint32_t __radv_vector_offset = (queue)->tail; \
291 elem = (queue)->data + (__radv_vector_offset & ((queue)->size - 1)), __radv_vector_offset < (queue)->head; \
292 __radv_vector_offset += (queue)->element_size)
294 void *radv_resolve_entrypoint(uint32_t index
);
295 void *radv_lookup_entrypoint(const char *name
);
297 extern struct radv_dispatch_table dtable
;
300 radv_alloc(const VkAllocationCallbacks
*alloc
,
301 size_t size
, size_t align
,
302 VkSystemAllocationScope scope
)
304 return alloc
->pfnAllocation(alloc
->pUserData
, size
, align
, scope
);
308 radv_realloc(const VkAllocationCallbacks
*alloc
,
309 void *ptr
, size_t size
, size_t align
,
310 VkSystemAllocationScope scope
)
312 return alloc
->pfnReallocation(alloc
->pUserData
, ptr
, size
, align
, scope
);
316 radv_free(const VkAllocationCallbacks
*alloc
, void *data
)
318 alloc
->pfnFree(alloc
->pUserData
, data
);
322 radv_alloc2(const VkAllocationCallbacks
*parent_alloc
,
323 const VkAllocationCallbacks
*alloc
,
324 size_t size
, size_t align
,
325 VkSystemAllocationScope scope
)
328 return radv_alloc(alloc
, size
, align
, scope
);
330 return radv_alloc(parent_alloc
, size
, align
, scope
);
334 radv_free2(const VkAllocationCallbacks
*parent_alloc
,
335 const VkAllocationCallbacks
*alloc
,
339 radv_free(alloc
, data
);
341 radv_free(parent_alloc
, data
);
344 struct radv_wsi_interaface
;
346 #define VK_ICD_WSI_PLATFORM_MAX 5
348 struct radv_physical_device
{
349 VK_LOADER_DATA _loader_data
;
351 struct radv_instance
* instance
;
353 struct radeon_winsys
*ws
;
354 struct radeon_info rad_info
;
358 uint64_t aperture_size
;
359 int cmd_parser_version
;
360 uint32_t pci_vendor_id
;
361 uint32_t pci_device_id
;
363 struct radv_wsi_interface
* wsi
[VK_ICD_WSI_PLATFORM_MAX
];
366 struct radv_instance
{
367 VK_LOADER_DATA _loader_data
;
369 VkAllocationCallbacks alloc
;
372 int physicalDeviceCount
;
373 struct radv_physical_device physicalDevice
;
376 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
377 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
381 struct radv_pipeline_cache
{
382 struct radv_device
* device
;
383 pthread_mutex_t mutex
;
387 uint32_t kernel_count
;
388 struct cache_entry
** hash_table
;
391 VkAllocationCallbacks alloc
;
395 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
396 struct radv_device
*device
);
398 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
400 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
401 const void *data
, size_t size
);
403 struct radv_shader_variant
*
404 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
405 struct radv_pipeline_cache
*cache
,
406 const unsigned char *sha1
);
408 struct radv_shader_variant
*
409 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache
*cache
,
410 const unsigned char *sha1
,
411 struct radv_shader_variant
*variant
,
412 const void *code
, unsigned code_size
);
414 void radv_shader_variant_destroy(struct radv_device
*device
,
415 struct radv_shader_variant
*variant
);
417 struct radv_meta_state
{
418 VkAllocationCallbacks alloc
;
420 struct radv_pipeline_cache cache
;
423 * Use array element `i` for images with `2^i` samples.
426 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
427 struct radv_pipeline
*color_pipelines
[NUM_META_FS_KEYS
];
429 VkRenderPass depth_only_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
430 struct radv_pipeline
*depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
431 VkRenderPass stencil_only_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
432 struct radv_pipeline
*stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
433 VkRenderPass depthstencil_rp
[NUM_DEPTH_CLEAR_PIPELINES
];
434 struct radv_pipeline
*depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
435 } clear
[1 + MAX_SAMPLES_LOG2
];
438 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
440 /** Pipeline that blits from a 1D image. */
441 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
443 /** Pipeline that blits from a 2D image. */
444 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
446 /** Pipeline that blits from a 3D image. */
447 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
449 VkRenderPass depth_only_rp
;
450 VkPipeline depth_only_1d_pipeline
;
451 VkPipeline depth_only_2d_pipeline
;
452 VkPipeline depth_only_3d_pipeline
;
454 VkRenderPass stencil_only_rp
;
455 VkPipeline stencil_only_1d_pipeline
;
456 VkPipeline stencil_only_2d_pipeline
;
457 VkPipeline stencil_only_3d_pipeline
;
458 VkPipelineLayout pipeline_layout
;
459 VkDescriptorSetLayout ds_layout
;
463 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
465 VkPipelineLayout p_layouts
[2];
466 VkDescriptorSetLayout ds_layouts
[2];
467 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
469 VkRenderPass depth_only_rp
;
470 VkPipeline depth_only_pipeline
[2];
472 VkRenderPass stencil_only_rp
;
473 VkPipeline stencil_only_pipeline
[2];
477 VkPipelineLayout img_p_layout
;
478 VkDescriptorSetLayout img_ds_layout
;
482 VkRenderPass render_pass
;
483 VkPipelineLayout img_p_layout
;
484 VkDescriptorSetLayout img_ds_layout
;
494 VkDescriptorSetLayout ds_layout
;
495 VkPipelineLayout p_layout
;
498 VkPipeline i_pipeline
;
499 } rc
[MAX_SAMPLES_LOG2
];
503 VkPipeline decompress_pipeline
;
504 VkPipeline resummarize_pipeline
;
509 VkPipeline cmask_eliminate_pipeline
;
510 VkPipeline fmask_decompress_pipeline
;
515 VkPipelineLayout fill_p_layout
;
516 VkPipelineLayout copy_p_layout
;
517 VkDescriptorSetLayout fill_ds_layout
;
518 VkDescriptorSetLayout copy_ds_layout
;
519 VkPipeline fill_pipeline
;
520 VkPipeline copy_pipeline
;
525 VK_LOADER_DATA _loader_data
;
527 struct radv_device
* device
;
529 struct radv_state_pool
* pool
;
533 VK_LOADER_DATA _loader_data
;
535 VkAllocationCallbacks alloc
;
537 struct radv_instance
* instance
;
538 struct radeon_winsys
*ws
;
539 struct radeon_winsys_ctx
*hw_ctx
;
541 struct radv_meta_state meta_state
;
542 struct radv_queue queue
;
543 struct radeon_winsys_cs
*empty_cs
;
545 bool allow_fast_clears
;
548 /* MSAA sample locations.
549 * The first index is the sample index.
550 * The second index is the coordinate: X, Y. */
551 float sample_locations_1x
[1][2];
552 float sample_locations_2x
[2][2];
553 float sample_locations_4x
[4][2];
554 float sample_locations_8x
[8][2];
555 float sample_locations_16x
[16][2];
558 void radv_device_get_cache_uuid(void *uuid
);
560 struct radv_device_memory
{
561 struct radeon_winsys_bo
*bo
;
563 VkDeviceSize map_size
;
568 struct radv_descriptor_range
{
573 struct radv_descriptor_set
{
574 const struct radv_descriptor_set_layout
*layout
;
575 struct list_head descriptor_pool
;
578 struct radv_buffer_view
*buffer_views
;
579 struct radeon_winsys_bo
*bo
;
581 uint32_t *mapped_ptr
;
582 struct radv_descriptor_range
*dynamic_descriptors
;
583 struct radeon_winsys_bo
*descriptors
[0];
586 struct radv_descriptor_pool_free_node
{
592 struct radv_descriptor_pool
{
593 struct list_head descriptor_sets
;
595 struct radeon_winsys_bo
*bo
;
597 uint64_t current_offset
;
603 struct radv_descriptor_pool_free_node free_nodes
[];
607 struct radv_device
* device
;
610 VkBufferUsageFlags usage
;
613 struct radeon_winsys_bo
* bo
;
618 enum radv_cmd_dirty_bits
{
619 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
620 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
621 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
622 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
623 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
624 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
625 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
626 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
627 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
628 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
629 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
630 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
631 RADV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
633 typedef uint32_t radv_cmd_dirty_mask_t
;
635 enum radv_cmd_flush_bits
{
636 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
637 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
638 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
639 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
640 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
641 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
642 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
643 /* Framebuffer caches */
644 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 4,
645 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 5,
646 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 6,
647 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 7,
648 /* Engine synchronization. */
649 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 8,
650 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 9,
651 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 10,
652 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 11,
654 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
655 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
656 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
657 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
660 struct radv_vertex_binding
{
661 struct radv_buffer
* buffer
;
665 struct radv_dynamic_state
{
668 VkViewport viewports
[MAX_VIEWPORTS
];
673 VkRect2D scissors
[MAX_SCISSORS
];
684 float blend_constants
[4];
694 } stencil_compare_mask
;
699 } stencil_write_mask
;
707 extern const struct radv_dynamic_state default_dynamic_state
;
709 void radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
710 const struct radv_dynamic_state
*src
,
713 * Attachment state when recording a renderpass instance.
715 * The clear value is valid only if there exists a pending clear.
717 struct radv_attachment_state
{
718 VkImageAspectFlags pending_clear_aspects
;
719 VkClearValue clear_value
;
720 VkImageLayout current_layout
;
723 struct radv_cmd_state
{
725 bool vertex_descriptors_dirty
;
726 radv_cmd_dirty_mask_t dirty
;
728 struct radv_pipeline
* pipeline
;
729 struct radv_pipeline
* emitted_pipeline
;
730 struct radv_pipeline
* compute_pipeline
;
731 struct radv_pipeline
* emitted_compute_pipeline
;
732 struct radv_framebuffer
* framebuffer
;
733 struct radv_render_pass
* pass
;
734 const struct radv_subpass
* subpass
;
735 struct radv_dynamic_state dynamic
;
736 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
737 struct radv_descriptor_set
* descriptors
[MAX_SETS
];
738 struct radv_attachment_state
* attachments
;
739 VkRect2D render_area
;
740 struct radv_buffer
* index_buffer
;
742 uint32_t index_offset
;
743 uint32_t last_primitive_reset_index
;
744 enum radv_cmd_flush_bits flush_bits
;
745 unsigned active_occlusion_queries
;
748 struct radv_cmd_pool
{
749 VkAllocationCallbacks alloc
;
750 struct list_head cmd_buffers
;
753 struct radv_cmd_buffer_upload
{
757 struct radeon_winsys_bo
*upload_bo
;
758 struct list_head list
;
761 struct radv_cmd_buffer
{
762 VK_LOADER_DATA _loader_data
;
764 struct radv_device
* device
;
766 struct radv_cmd_pool
* pool
;
767 struct list_head pool_link
;
769 VkCommandBufferUsageFlags usage_flags
;
770 VkCommandBufferLevel level
;
771 struct radeon_winsys_cs
*cs
;
772 struct radv_cmd_state state
;
774 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
775 uint32_t dynamic_buffers
[16 * MAX_DYNAMIC_BUFFERS
];
776 VkShaderStageFlags push_constant_stages
;
778 struct radv_cmd_buffer_upload upload
;
785 void si_init_config(struct radv_physical_device
*physical_device
,
786 struct radv_cmd_buffer
*cmd_buffer
);
787 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
788 int count
, const VkViewport
*viewports
);
789 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
790 int count
, const VkRect2D
*scissors
);
791 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
);
792 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
793 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
794 uint64_t src_va
, uint64_t dest_va
,
796 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
797 uint64_t size
, unsigned value
);
798 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
799 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
800 struct radv_descriptor_set
*set
,
803 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
806 unsigned *out_offset
,
809 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
810 const struct radv_subpass
*subpass
,
813 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
814 unsigned size
, unsigned alignmnet
,
815 const void *data
, unsigned *out_offset
);
817 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
818 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
819 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
820 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
821 unsigned radv_cayman_get_maxdist(int log_samples
);
822 void radv_device_init_msaa(struct radv_device
*device
);
823 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
824 struct radv_image
*image
,
825 VkClearDepthStencilValue ds_clear_value
,
826 VkImageAspectFlags aspects
);
827 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
828 struct radv_image
*image
,
830 uint32_t color_values
[2]);
831 void radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
832 struct radeon_winsys_bo
*bo
,
833 uint64_t offset
, uint64_t size
, uint32_t value
);
836 * Takes x,y,z as exact numbers of invocations, instead of blocks.
838 * Limitations: Can't call normal dispatch functions without binding or rebinding
839 * the compute pipeline.
841 void radv_unaligned_dispatch(
842 struct radv_cmd_buffer
*cmd_buffer
,
848 struct radeon_winsys_bo
*bo
;
854 struct radv_shader_module
{
855 struct nir_shader
* nir
;
856 unsigned char sha1
[20];
861 union ac_shader_variant_key
;
864 radv_hash_shader(unsigned char *hash
, struct radv_shader_module
*module
,
865 const char *entrypoint
,
866 const VkSpecializationInfo
*spec_info
,
867 const struct radv_pipeline_layout
*layout
,
868 const union ac_shader_variant_key
*key
);
870 static inline gl_shader_stage
871 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
873 assert(__builtin_popcount(vk_stage
) == 1);
874 return ffs(vk_stage
) - 1;
877 static inline VkShaderStageFlagBits
878 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
880 return (1 << mesa_stage
);
883 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
885 #define radv_foreach_stage(stage, stage_bits) \
886 for (gl_shader_stage stage, \
887 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
888 stage = __builtin_ffs(__tmp) - 1, __tmp; \
889 __tmp &= ~(1 << (stage)))
891 struct radv_shader_variant
{
894 struct radeon_winsys_bo
*bo
;
895 struct ac_shader_config config
;
896 struct ac_shader_variant_info info
;
901 struct radv_depth_stencil_state
{
902 uint32_t db_depth_control
;
903 uint32_t db_stencil_control
;
904 uint32_t db_render_control
;
905 uint32_t db_render_override2
;
908 struct radv_blend_state
{
909 uint32_t cb_color_control
;
910 uint32_t cb_target_mask
;
911 uint32_t sx_mrt0_blend_opt
[8];
912 uint32_t cb_blend_control
[8];
914 uint32_t spi_shader_col_format
;
915 uint32_t cb_shader_mask
;
916 uint32_t db_alpha_to_mask
;
919 unsigned radv_format_meta_fs_key(VkFormat format
);
921 struct radv_raster_state
{
922 uint32_t pa_cl_clip_cntl
;
923 uint32_t pa_cl_vs_out_cntl
;
924 uint32_t spi_interp_control
;
925 uint32_t pa_su_point_size
;
926 uint32_t pa_su_point_minmax
;
927 uint32_t pa_su_line_cntl
;
928 uint32_t pa_su_vtx_cntl
;
929 uint32_t pa_su_sc_mode_cntl
;
932 struct radv_multisample_state
{
934 uint32_t pa_sc_line_cntl
;
935 uint32_t pa_sc_mode_cntl_0
;
936 uint32_t pa_sc_mode_cntl_1
;
937 uint32_t pa_sc_aa_config
;
938 uint32_t pa_sc_aa_mask
[2];
939 unsigned num_samples
;
942 struct radv_pipeline
{
943 struct radv_device
* device
;
944 uint32_t dynamic_state_mask
;
945 struct radv_dynamic_state dynamic_state
;
947 struct radv_pipeline_layout
* layout
;
949 bool needs_data_cache
;
951 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
952 VkShaderStageFlags active_stages
;
954 uint32_t va_rsrc_word3
[MAX_VERTEX_ATTRIBS
];
955 uint32_t va_format_size
[MAX_VERTEX_ATTRIBS
];
956 uint32_t va_binding
[MAX_VERTEX_ATTRIBS
];
957 uint32_t va_offset
[MAX_VERTEX_ATTRIBS
];
958 uint32_t num_vertex_attribs
;
959 uint32_t binding_stride
[MAX_VBS
];
963 struct radv_blend_state blend
;
964 struct radv_depth_stencil_state ds
;
965 struct radv_raster_state raster
;
966 struct radv_multisample_state ms
;
969 bool prim_restart_enable
;
974 struct radv_graphics_pipeline_create_info
{
977 bool db_stencil_clear
;
978 bool db_depth_disable_expclear
;
979 bool db_stencil_disable_expclear
;
980 bool db_flush_depth_inplace
;
981 bool db_flush_stencil_inplace
;
983 uint32_t custom_blend_mode
;
987 radv_pipeline_init(struct radv_pipeline
*pipeline
, struct radv_device
*device
,
988 struct radv_pipeline_cache
*cache
,
989 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
990 const struct radv_graphics_pipeline_create_info
*extra
,
991 const VkAllocationCallbacks
*alloc
);
994 radv_graphics_pipeline_create(VkDevice device
,
995 VkPipelineCache cache
,
996 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
997 const struct radv_graphics_pipeline_create_info
*extra
,
998 const VkAllocationCallbacks
*alloc
,
999 VkPipeline
*pPipeline
);
1001 struct vk_format_description
;
1002 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1003 int first_non_void
);
1004 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1005 int first_non_void
);
1006 uint32_t radv_translate_colorformat(VkFormat format
);
1007 uint32_t radv_translate_color_numformat(VkFormat format
,
1008 const struct vk_format_description
*desc
,
1009 int first_non_void
);
1010 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1011 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1012 uint32_t radv_translate_dbformat(VkFormat format
);
1013 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1014 const struct vk_format_description
*desc
,
1015 int first_non_void
);
1016 uint32_t radv_translate_tex_numformat(VkFormat format
,
1017 const struct vk_format_description
*desc
,
1018 int first_non_void
);
1019 bool radv_format_pack_clear_color(VkFormat format
,
1020 uint32_t clear_vals
[2],
1021 VkClearColorValue
*value
);
1022 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1024 struct radv_fmask_info
{
1028 unsigned pitch_in_pixels
;
1029 unsigned bank_height
;
1030 unsigned slice_tile_max
;
1031 unsigned tile_mode_index
;
1034 struct radv_cmask_info
{
1042 unsigned slice_tile_max
;
1043 unsigned base_address_reg
;
1046 struct r600_htile_info
{
1057 /* The original VkFormat provided by the client. This may not match any
1058 * of the actual surface formats.
1061 VkImageAspectFlags aspects
;
1064 uint32_t array_size
;
1065 uint32_t samples
; /**< VkImageCreateInfo::samples */
1066 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1067 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1072 /* Set when bound */
1073 struct radeon_winsys_bo
*bo
;
1074 VkDeviceSize offset
;
1075 uint32_t dcc_offset
;
1076 struct radeon_surf surface
;
1078 struct radv_fmask_info fmask
;
1079 struct radv_cmask_info cmask
;
1080 uint32_t clear_value_offset
;
1082 /* Depth buffer compression and fast clear. */
1083 struct r600_htile_info htile
;
1086 bool radv_layout_has_htile(const struct radv_image
*image
,
1087 VkImageLayout layout
);
1088 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1089 VkImageLayout layout
);
1090 bool radv_layout_can_expclear(const struct radv_image
*image
,
1091 VkImageLayout layout
);
1092 bool radv_layout_has_cmask(const struct radv_image
*image
,
1093 VkImageLayout layout
);
1094 static inline uint32_t
1095 radv_get_layerCount(const struct radv_image
*image
,
1096 const VkImageSubresourceRange
*range
)
1098 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1099 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1102 static inline uint32_t
1103 radv_get_levelCount(const struct radv_image
*image
,
1104 const VkImageSubresourceRange
*range
)
1106 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1107 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1110 struct radeon_bo_metadata
;
1112 radv_init_metadata(struct radv_device
*device
,
1113 struct radv_image
*image
,
1114 struct radeon_bo_metadata
*metadata
);
1116 struct radv_image_view
{
1117 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1118 struct radeon_winsys_bo
*bo
;
1120 VkImageViewType type
;
1121 VkImageAspectFlags aspect_mask
;
1123 uint32_t base_layer
;
1124 uint32_t layer_count
;
1126 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1128 uint32_t descriptor
[8];
1129 uint32_t fmask_descriptor
[8];
1132 struct radv_image_create_info
{
1133 const VkImageCreateInfo
*vk_info
;
1138 VkResult
radv_image_create(VkDevice _device
,
1139 const struct radv_image_create_info
*info
,
1140 const VkAllocationCallbacks
* alloc
,
1143 void radv_image_view_init(struct radv_image_view
*view
,
1144 struct radv_device
*device
,
1145 const VkImageViewCreateInfo
* pCreateInfo
,
1146 struct radv_cmd_buffer
*cmd_buffer
,
1147 VkImageUsageFlags usage_mask
);
1148 void radv_image_set_optimal_micro_tile_mode(struct radv_device
*device
,
1149 struct radv_image
*image
, uint32_t micro_tile_mode
);
1150 struct radv_buffer_view
{
1151 struct radeon_winsys_bo
*bo
;
1153 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1156 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1157 struct radv_device
*device
,
1158 const VkBufferViewCreateInfo
* pCreateInfo
,
1159 struct radv_cmd_buffer
*cmd_buffer
);
1161 static inline struct VkExtent3D
1162 radv_sanitize_image_extent(const VkImageType imageType
,
1163 const struct VkExtent3D imageExtent
)
1165 switch (imageType
) {
1166 case VK_IMAGE_TYPE_1D
:
1167 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1168 case VK_IMAGE_TYPE_2D
:
1169 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1170 case VK_IMAGE_TYPE_3D
:
1173 unreachable("invalid image type");
1177 static inline struct VkOffset3D
1178 radv_sanitize_image_offset(const VkImageType imageType
,
1179 const struct VkOffset3D imageOffset
)
1181 switch (imageType
) {
1182 case VK_IMAGE_TYPE_1D
:
1183 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1184 case VK_IMAGE_TYPE_2D
:
1185 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1186 case VK_IMAGE_TYPE_3D
:
1189 unreachable("invalid image type");
1193 struct radv_sampler
{
1197 struct radv_color_buffer_info
{
1198 uint32_t cb_color_base
;
1199 uint32_t cb_color_pitch
;
1200 uint32_t cb_color_slice
;
1201 uint32_t cb_color_view
;
1202 uint32_t cb_color_info
;
1203 uint32_t cb_color_attrib
;
1204 uint32_t cb_dcc_control
;
1205 uint32_t cb_color_cmask
;
1206 uint32_t cb_color_cmask_slice
;
1207 uint32_t cb_color_fmask
;
1208 uint32_t cb_color_fmask_slice
;
1209 uint32_t cb_clear_value0
;
1210 uint32_t cb_clear_value1
;
1211 uint32_t cb_dcc_base
;
1212 uint32_t micro_tile_mode
;
1215 struct radv_ds_buffer_info
{
1216 uint32_t db_depth_info
;
1218 uint32_t db_stencil_info
;
1219 uint32_t db_z_read_base
;
1220 uint32_t db_stencil_read_base
;
1221 uint32_t db_z_write_base
;
1222 uint32_t db_stencil_write_base
;
1223 uint32_t db_depth_view
;
1224 uint32_t db_depth_size
;
1225 uint32_t db_depth_slice
;
1226 uint32_t db_htile_surface
;
1227 uint32_t db_htile_data_base
;
1228 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1232 struct radv_attachment_info
{
1234 struct radv_color_buffer_info cb
;
1235 struct radv_ds_buffer_info ds
;
1237 struct radv_image_view
*attachment
;
1240 struct radv_framebuffer
{
1245 uint32_t attachment_count
;
1246 struct radv_attachment_info attachments
[0];
1249 struct radv_subpass_barrier
{
1250 VkPipelineStageFlags src_stage_mask
;
1251 VkAccessFlags src_access_mask
;
1252 VkAccessFlags dst_access_mask
;
1255 struct radv_subpass
{
1256 uint32_t input_count
;
1257 VkAttachmentReference
* input_attachments
;
1258 uint32_t color_count
;
1259 VkAttachmentReference
* color_attachments
;
1260 VkAttachmentReference
* resolve_attachments
;
1261 VkAttachmentReference depth_stencil_attachment
;
1263 /** Subpass has at least one resolve attachment */
1266 struct radv_subpass_barrier start_barrier
;
1269 struct radv_render_pass_attachment
{
1272 VkAttachmentLoadOp load_op
;
1273 VkAttachmentLoadOp stencil_load_op
;
1274 VkImageLayout initial_layout
;
1275 VkImageLayout final_layout
;
1278 struct radv_render_pass
{
1279 uint32_t attachment_count
;
1280 uint32_t subpass_count
;
1281 VkAttachmentReference
* subpass_attachments
;
1282 struct radv_render_pass_attachment
* attachments
;
1283 struct radv_subpass_barrier end_barrier
;
1284 struct radv_subpass subpasses
[0];
1287 VkResult
radv_device_init_meta(struct radv_device
*device
);
1288 void radv_device_finish_meta(struct radv_device
*device
);
1290 struct radv_query_pool
{
1291 struct radeon_winsys_bo
*bo
;
1293 uint32_t availability_offset
;
1299 radv_temp_descriptor_set_create(struct radv_device
*device
,
1300 struct radv_cmd_buffer
*cmd_buffer
,
1301 VkDescriptorSetLayout _layout
,
1302 VkDescriptorSet
*_set
);
1305 radv_temp_descriptor_set_destroy(struct radv_device
*device
,
1306 VkDescriptorSet _set
);
1307 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1308 struct radv_image
*image
, uint32_t value
);
1309 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1310 struct radv_image
*image
, uint32_t value
);
1311 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1313 static inline struct __radv_type * \
1314 __radv_type ## _from_handle(__VkType _handle) \
1316 return (struct __radv_type *) _handle; \
1319 static inline __VkType \
1320 __radv_type ## _to_handle(struct __radv_type *_obj) \
1322 return (__VkType) _obj; \
1325 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1327 static inline struct __radv_type * \
1328 __radv_type ## _from_handle(__VkType _handle) \
1330 return (struct __radv_type *)(uintptr_t) _handle; \
1333 static inline __VkType \
1334 __radv_type ## _to_handle(struct __radv_type *_obj) \
1336 return (__VkType)(uintptr_t) _obj; \
1339 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1340 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1342 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1343 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1344 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1345 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1346 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1348 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1349 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1350 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1351 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1352 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1353 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1354 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1355 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1356 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1357 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1358 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1359 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1360 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1361 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1362 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1363 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1364 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1365 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1366 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1368 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1370 static inline const __VkType * \
1371 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1373 return (const __VkType *) __radv_obj; \
1376 #define RADV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1377 const __VkType *__vk_name = radv_common_to_ ## __VkType(__common_name)
1379 RADV_DEFINE_STRUCT_CASTS(radv_common
, VkMemoryBarrier
)
1380 RADV_DEFINE_STRUCT_CASTS(radv_common
, VkBufferMemoryBarrier
)
1381 RADV_DEFINE_STRUCT_CASTS(radv_common
, VkImageMemoryBarrier
)
1384 #endif /* RADV_PRIVATE_H */