2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
52 #include "vk_debug_report.h"
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60 #include "radv_extensions.h"
62 #include <llvm-c/TargetMachine.h>
64 /* Pre-declarations needed for WSI entrypoints */
67 typedef struct xcb_connection_t xcb_connection_t
;
68 typedef uint32_t xcb_visualid_t
;
69 typedef uint32_t xcb_window_t
;
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
76 #include "radv_entrypoints.h"
78 #include "wsi_common.h"
80 #define ATI_VENDOR_ID 0x1002
83 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_VIEWPORTS 16
86 #define MAX_SCISSORS 16
87 #define MAX_DISCARD_RECTANGLES 4
88 #define MAX_PUSH_CONSTANTS_SIZE 128
89 #define MAX_PUSH_DESCRIPTORS 32
90 #define MAX_DYNAMIC_BUFFERS 16
91 #define MAX_SAMPLES_LOG2 4
92 #define NUM_META_FS_KEYS 13
93 #define RADV_MAX_DRM_DEVICES 8
96 #define NUM_DEPTH_CLEAR_PIPELINES 3
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
109 RADV_MEM_TYPE_GTT_CACHED
,
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115 static inline uint32_t
116 align_u32(uint32_t v
, uint32_t a
)
118 assert(a
!= 0 && a
== (a
& -a
));
119 return (v
+ a
- 1) & ~(a
- 1);
122 static inline uint32_t
123 align_u32_npot(uint32_t v
, uint32_t a
)
125 return (v
+ a
- 1) / a
* a
;
128 static inline uint64_t
129 align_u64(uint64_t v
, uint64_t a
)
131 assert(a
!= 0 && a
== (a
& -a
));
132 return (v
+ a
- 1) & ~(a
- 1);
135 static inline int32_t
136 align_i32(int32_t v
, int32_t a
)
138 assert(a
!= 0 && a
== (a
& -a
));
139 return (v
+ a
- 1) & ~(a
- 1);
142 /** Alignment must be a power of 2. */
144 radv_is_aligned(uintmax_t n
, uintmax_t a
)
146 assert(a
== (a
& -a
));
147 return (n
& (a
- 1)) == 0;
150 static inline uint32_t
151 round_up_u32(uint32_t v
, uint32_t a
)
153 return (v
+ a
- 1) / a
;
156 static inline uint64_t
157 round_up_u64(uint64_t v
, uint64_t a
)
159 return (v
+ a
- 1) / a
;
162 static inline uint32_t
163 radv_minify(uint32_t n
, uint32_t levels
)
165 if (unlikely(n
== 0))
168 return MAX2(n
>> levels
, 1);
171 radv_clamp_f(float f
, float min
, float max
)
184 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
186 if (*inout_mask
& clear_mask
) {
187 *inout_mask
&= ~clear_mask
;
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
209 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
212 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
213 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215 #define vk_error(error) error
216 #define vk_errorf(error, format, ...) error
219 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
220 radv_printflike(3, 4);
221 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
222 void radv_loge_v(const char *format
, va_list va
);
225 * Print a FINISHME message, including its source location.
227 #define radv_finishme(format, ...) \
229 static bool reported = false; \
231 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 /* A non-fatal assert. Useful for debugging. */
238 #define radv_assert(x) ({ \
239 if (unlikely(!(x))) \
240 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
243 #define radv_assert(x)
246 #define stub_return(v) \
248 radv_finishme("stub %s", __func__); \
254 radv_finishme("stub %s", __func__); \
258 void *radv_lookup_entrypoint_unchecked(const char *name
);
259 void *radv_lookup_entrypoint_checked(const char *name
,
260 uint32_t core_version
,
261 const struct radv_instance_extension_table
*instance
,
262 const struct radv_device_extension_table
*device
);
264 struct radv_physical_device
{
265 VK_LOADER_DATA _loader_data
;
267 struct radv_instance
* instance
;
269 struct radeon_winsys
*ws
;
270 struct radeon_info rad_info
;
272 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
273 uint8_t driver_uuid
[VK_UUID_SIZE
];
274 uint8_t device_uuid
[VK_UUID_SIZE
];
275 uint8_t cache_uuid
[VK_UUID_SIZE
];
278 struct wsi_device wsi_device
;
280 bool has_rbplus
; /* if RB+ register exist */
281 bool rbplus_allowed
; /* if RB+ is allowed */
282 bool has_clear_state
;
283 bool cpdma_prefetch_writes_memory
;
284 bool has_scissor_bug
;
286 /* This is the drivers on-disk cache used as a fallback as opposed to
287 * the pipeline cache defined by apps.
289 struct disk_cache
* disk_cache
;
291 VkPhysicalDeviceMemoryProperties memory_properties
;
292 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
294 struct radv_device_extension_table supported_extensions
;
297 struct radv_instance
{
298 VK_LOADER_DATA _loader_data
;
300 VkAllocationCallbacks alloc
;
303 int physicalDeviceCount
;
304 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
306 uint64_t debug_flags
;
307 uint64_t perftest_flags
;
309 struct vk_debug_report_instance debug_report_callbacks
;
311 struct radv_instance_extension_table enabled_extensions
;
314 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
315 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
317 bool radv_instance_extension_supported(const char *name
);
318 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
319 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
324 struct radv_pipeline_cache
{
325 struct radv_device
* device
;
326 pthread_mutex_t mutex
;
330 uint32_t kernel_count
;
331 struct cache_entry
** hash_table
;
334 VkAllocationCallbacks alloc
;
337 struct radv_pipeline_key
{
338 uint32_t instance_rate_inputs
;
339 unsigned tess_input_vertices
;
343 uint8_t log2_ps_iter_samples
;
344 uint8_t log2_num_samples
;
345 uint32_t multisample
: 1;
346 uint32_t has_multiview_view_index
: 1;
350 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
351 struct radv_device
*device
);
353 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
355 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
356 const void *data
, size_t size
);
358 struct radv_shader_variant
;
361 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
362 struct radv_pipeline_cache
*cache
,
363 const unsigned char *sha1
,
364 struct radv_shader_variant
**variants
);
367 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
368 struct radv_pipeline_cache
*cache
,
369 const unsigned char *sha1
,
370 struct radv_shader_variant
**variants
,
371 const void *const *codes
,
372 const unsigned *code_sizes
);
374 enum radv_blit_ds_layout
{
375 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
376 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
377 RADV_BLIT_DS_LAYOUT_COUNT
,
380 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
382 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
385 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
387 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
390 enum radv_meta_dst_layout
{
391 RADV_META_DST_LAYOUT_GENERAL
,
392 RADV_META_DST_LAYOUT_OPTIMAL
,
393 RADV_META_DST_LAYOUT_COUNT
,
396 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
398 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
401 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
403 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
406 struct radv_meta_state
{
407 VkAllocationCallbacks alloc
;
409 struct radv_pipeline_cache cache
;
412 * Use array element `i` for images with `2^i` samples.
415 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
416 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
418 VkRenderPass depthstencil_rp
;
419 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
420 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
421 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
422 } clear
[1 + MAX_SAMPLES_LOG2
];
424 VkPipelineLayout clear_color_p_layout
;
425 VkPipelineLayout clear_depth_p_layout
;
427 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
429 /** Pipeline that blits from a 1D image. */
430 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
432 /** Pipeline that blits from a 2D image. */
433 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
435 /** Pipeline that blits from a 3D image. */
436 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
438 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
439 VkPipeline depth_only_1d_pipeline
;
440 VkPipeline depth_only_2d_pipeline
;
441 VkPipeline depth_only_3d_pipeline
;
443 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
444 VkPipeline stencil_only_1d_pipeline
;
445 VkPipeline stencil_only_2d_pipeline
;
446 VkPipeline stencil_only_3d_pipeline
;
447 VkPipelineLayout pipeline_layout
;
448 VkDescriptorSetLayout ds_layout
;
452 VkRenderPass render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
454 VkPipelineLayout p_layouts
[3];
455 VkDescriptorSetLayout ds_layouts
[3];
456 VkPipeline pipelines
[3][NUM_META_FS_KEYS
];
458 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
459 VkPipeline depth_only_pipeline
[3];
461 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
462 VkPipeline stencil_only_pipeline
[3];
466 VkPipelineLayout img_p_layout
;
467 VkDescriptorSetLayout img_ds_layout
;
469 VkPipeline pipeline_3d
;
472 VkPipelineLayout img_p_layout
;
473 VkDescriptorSetLayout img_ds_layout
;
475 VkPipeline pipeline_3d
;
478 VkPipelineLayout img_p_layout
;
479 VkDescriptorSetLayout img_ds_layout
;
481 VkPipeline pipeline_3d
;
484 VkPipelineLayout img_p_layout
;
485 VkDescriptorSetLayout img_ds_layout
;
487 VkPipeline pipeline_3d
;
491 VkPipelineLayout p_layout
;
492 VkPipeline pipeline
[NUM_META_FS_KEYS
];
493 VkRenderPass pass
[NUM_META_FS_KEYS
];
497 VkDescriptorSetLayout ds_layout
;
498 VkPipelineLayout p_layout
;
501 VkPipeline i_pipeline
;
502 VkPipeline srgb_pipeline
;
503 } rc
[MAX_SAMPLES_LOG2
];
507 VkDescriptorSetLayout ds_layout
;
508 VkPipelineLayout p_layout
;
511 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
512 VkPipeline pipeline
[NUM_META_FS_KEYS
];
513 } rc
[MAX_SAMPLES_LOG2
];
517 VkPipelineLayout p_layout
;
518 VkPipeline decompress_pipeline
;
519 VkPipeline resummarize_pipeline
;
521 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
524 VkPipelineLayout p_layout
;
525 VkPipeline cmask_eliminate_pipeline
;
526 VkPipeline fmask_decompress_pipeline
;
527 VkPipeline dcc_decompress_pipeline
;
530 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
531 VkPipelineLayout dcc_decompress_compute_p_layout
;
532 VkPipeline dcc_decompress_compute_pipeline
;
536 VkPipelineLayout fill_p_layout
;
537 VkPipelineLayout copy_p_layout
;
538 VkDescriptorSetLayout fill_ds_layout
;
539 VkDescriptorSetLayout copy_ds_layout
;
540 VkPipeline fill_pipeline
;
541 VkPipeline copy_pipeline
;
545 VkDescriptorSetLayout ds_layout
;
546 VkPipelineLayout p_layout
;
547 VkPipeline occlusion_query_pipeline
;
548 VkPipeline pipeline_statistics_query_pipeline
;
553 #define RADV_QUEUE_GENERAL 0
554 #define RADV_QUEUE_COMPUTE 1
555 #define RADV_QUEUE_TRANSFER 2
557 #define RADV_MAX_QUEUE_FAMILIES 3
559 enum ring_type
radv_queue_family_to_ring(int f
);
562 VK_LOADER_DATA _loader_data
;
563 struct radv_device
* device
;
564 struct radeon_winsys_ctx
*hw_ctx
;
565 enum radeon_ctx_priority priority
;
566 uint32_t queue_family_index
;
569 uint32_t scratch_size
;
570 uint32_t compute_scratch_size
;
571 uint32_t esgs_ring_size
;
572 uint32_t gsvs_ring_size
;
574 bool has_sample_positions
;
576 struct radeon_winsys_bo
*scratch_bo
;
577 struct radeon_winsys_bo
*descriptor_bo
;
578 struct radeon_winsys_bo
*compute_scratch_bo
;
579 struct radeon_winsys_bo
*esgs_ring_bo
;
580 struct radeon_winsys_bo
*gsvs_ring_bo
;
581 struct radeon_winsys_bo
*tess_rings_bo
;
582 struct radeon_winsys_cs
*initial_preamble_cs
;
583 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
584 struct radeon_winsys_cs
*continue_preamble_cs
;
588 VK_LOADER_DATA _loader_data
;
590 VkAllocationCallbacks alloc
;
592 struct radv_instance
* instance
;
593 struct radeon_winsys
*ws
;
595 struct radv_meta_state meta_state
;
597 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
598 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
599 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
601 bool always_use_syncobj
;
602 bool llvm_supports_spill
;
603 bool has_distributed_tess
;
606 uint32_t tess_offchip_block_dw_size
;
607 uint32_t scratch_waves
;
608 uint32_t dispatch_initiator
;
610 uint32_t gs_table_depth
;
612 /* MSAA sample locations.
613 * The first index is the sample index.
614 * The second index is the coordinate: X, Y. */
615 float sample_locations_1x
[1][2];
616 float sample_locations_2x
[2][2];
617 float sample_locations_4x
[4][2];
618 float sample_locations_8x
[8][2];
619 float sample_locations_16x
[16][2];
622 uint32_t gfx_init_size_dw
;
623 struct radeon_winsys_bo
*gfx_init
;
625 struct radeon_winsys_bo
*trace_bo
;
626 uint32_t *trace_id_ptr
;
628 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
629 bool keep_shader_info
;
631 struct radv_physical_device
*physical_device
;
633 /* Backup in-memory cache to be used if the app doesn't provide one */
634 struct radv_pipeline_cache
* mem_cache
;
637 * use different counters so MSAA MRTs get consecutive surface indices,
638 * even if MASK is allocated in between.
640 uint32_t image_mrt_offset_counter
;
641 uint32_t fmask_mrt_offset_counter
;
642 struct list_head shader_slabs
;
643 mtx_t shader_slab_mutex
;
645 /* For detecting VM faults reported by dmesg. */
646 uint64_t dmesg_timestamp
;
648 struct radv_device_extension_table enabled_extensions
;
651 struct radv_device_memory
{
652 struct radeon_winsys_bo
*bo
;
653 /* for dedicated allocations */
654 struct radv_image
*image
;
655 struct radv_buffer
*buffer
;
657 VkDeviceSize map_size
;
663 struct radv_descriptor_range
{
668 struct radv_descriptor_set
{
669 const struct radv_descriptor_set_layout
*layout
;
672 struct radeon_winsys_bo
*bo
;
674 uint32_t *mapped_ptr
;
675 struct radv_descriptor_range
*dynamic_descriptors
;
677 struct radeon_winsys_bo
*descriptors
[0];
680 struct radv_push_descriptor_set
682 struct radv_descriptor_set set
;
686 struct radv_descriptor_pool_entry
{
689 struct radv_descriptor_set
*set
;
692 struct radv_descriptor_pool
{
693 struct radeon_winsys_bo
*bo
;
695 uint64_t current_offset
;
698 uint8_t *host_memory_base
;
699 uint8_t *host_memory_ptr
;
700 uint8_t *host_memory_end
;
702 uint32_t entry_count
;
703 uint32_t max_entry_count
;
704 struct radv_descriptor_pool_entry entries
[0];
707 struct radv_descriptor_update_template_entry
{
708 VkDescriptorType descriptor_type
;
710 /* The number of descriptors to update */
711 uint32_t descriptor_count
;
713 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
716 /* In dwords. Not valid/used for dynamic descriptors */
719 uint32_t buffer_offset
;
721 /* Only valid for combined image samplers and samplers */
722 uint16_t has_sampler
;
728 /* For push descriptors */
729 const uint32_t *immutable_samplers
;
732 struct radv_descriptor_update_template
{
733 uint32_t entry_count
;
734 VkPipelineBindPoint bind_point
;
735 struct radv_descriptor_update_template_entry entry
[0];
741 VkBufferUsageFlags usage
;
742 VkBufferCreateFlags flags
;
745 struct radeon_winsys_bo
* bo
;
751 enum radv_dynamic_state_bits
{
752 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
753 RADV_DYNAMIC_SCISSOR
= 1 << 1,
754 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
755 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
756 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
757 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
758 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
759 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
760 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
761 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
762 RADV_DYNAMIC_ALL
= (1 << 10) - 1,
765 enum radv_cmd_dirty_bits
{
766 /* Keep the dynamic state dirty bits in sync with
767 * enum radv_dynamic_state_bits */
768 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
769 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
770 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
771 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
772 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
773 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
774 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
775 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
776 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
777 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
778 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 10) - 1,
779 RADV_CMD_DIRTY_PIPELINE
= 1 << 10,
780 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 11,
781 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 12,
782 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 13,
785 enum radv_cmd_flush_bits
{
786 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
787 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
788 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
789 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
790 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
791 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
792 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
793 /* Same as above, but only writes back and doesn't invalidate */
794 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
795 /* Framebuffer caches */
796 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
797 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
798 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
799 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
800 /* Engine synchronization. */
801 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
802 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
803 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
804 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
806 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
807 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
808 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
809 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
812 struct radv_vertex_binding
{
813 struct radv_buffer
* buffer
;
817 struct radv_viewport_state
{
819 VkViewport viewports
[MAX_VIEWPORTS
];
822 struct radv_scissor_state
{
824 VkRect2D scissors
[MAX_SCISSORS
];
827 struct radv_discard_rectangle_state
{
829 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
832 struct radv_dynamic_state
{
834 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
835 * Defines the set of saved dynamic state.
839 struct radv_viewport_state viewport
;
841 struct radv_scissor_state scissor
;
851 float blend_constants
[4];
861 } stencil_compare_mask
;
866 } stencil_write_mask
;
873 struct radv_discard_rectangle_state discard_rectangle
;
876 extern const struct radv_dynamic_state default_dynamic_state
;
879 radv_get_debug_option_name(int id
);
882 radv_get_perftest_option_name(int id
);
885 * Attachment state when recording a renderpass instance.
887 * The clear value is valid only if there exists a pending clear.
889 struct radv_attachment_state
{
890 VkImageAspectFlags pending_clear_aspects
;
891 uint32_t cleared_views
;
892 VkClearValue clear_value
;
893 VkImageLayout current_layout
;
896 struct radv_descriptor_state
{
897 struct radv_descriptor_set
*sets
[MAX_SETS
];
900 struct radv_push_descriptor_set push_set
;
904 struct radv_cmd_state
{
905 /* Vertex descriptors */
906 bool vb_prefetch_dirty
;
913 struct radv_pipeline
* pipeline
;
914 struct radv_pipeline
* emitted_pipeline
;
915 struct radv_pipeline
* compute_pipeline
;
916 struct radv_pipeline
* emitted_compute_pipeline
;
917 struct radv_framebuffer
* framebuffer
;
918 struct radv_render_pass
* pass
;
919 const struct radv_subpass
* subpass
;
920 struct radv_dynamic_state dynamic
;
921 struct radv_attachment_state
* attachments
;
922 VkRect2D render_area
;
925 struct radv_buffer
*index_buffer
;
926 uint64_t index_offset
;
928 uint32_t max_index_count
;
930 int32_t last_index_type
;
932 int32_t last_primitive_reset_en
;
933 uint32_t last_primitive_reset_index
;
934 enum radv_cmd_flush_bits flush_bits
;
935 unsigned active_occlusion_queries
;
938 uint32_t last_ia_multi_vgt_param
;
940 uint32_t last_num_instances
;
941 uint32_t last_first_instance
;
942 uint32_t last_vertex_offset
;
945 struct radv_cmd_pool
{
946 VkAllocationCallbacks alloc
;
947 struct list_head cmd_buffers
;
948 struct list_head free_cmd_buffers
;
949 uint32_t queue_family_index
;
952 struct radv_cmd_buffer_upload
{
956 struct radeon_winsys_bo
*upload_bo
;
957 struct list_head list
;
960 enum radv_cmd_buffer_status
{
961 RADV_CMD_BUFFER_STATUS_INVALID
,
962 RADV_CMD_BUFFER_STATUS_INITIAL
,
963 RADV_CMD_BUFFER_STATUS_RECORDING
,
964 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
965 RADV_CMD_BUFFER_STATUS_PENDING
,
968 struct radv_cmd_buffer
{
969 VK_LOADER_DATA _loader_data
;
971 struct radv_device
* device
;
973 struct radv_cmd_pool
* pool
;
974 struct list_head pool_link
;
976 VkCommandBufferUsageFlags usage_flags
;
977 VkCommandBufferLevel level
;
978 enum radv_cmd_buffer_status status
;
979 struct radeon_winsys_cs
*cs
;
980 struct radv_cmd_state state
;
981 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
982 uint32_t queue_family_index
;
984 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
985 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
986 VkShaderStageFlags push_constant_stages
;
987 struct radv_descriptor_set meta_push_descriptors
;
989 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
991 struct radv_cmd_buffer_upload upload
;
993 uint32_t scratch_size_needed
;
994 uint32_t compute_scratch_size_needed
;
995 uint32_t esgs_ring_size_needed
;
996 uint32_t gsvs_ring_size_needed
;
997 bool tess_rings_needed
;
998 bool sample_positions_needed
;
1000 VkResult record_result
;
1002 int ring_offsets_idx
; /* just used for verification */
1003 uint32_t gfx9_fence_offset
;
1004 struct radeon_winsys_bo
*gfx9_fence_bo
;
1005 uint32_t gfx9_fence_idx
;
1008 * Whether a query pool has been resetted and we have to flush caches.
1010 bool pending_reset_query
;
1015 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1017 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
1018 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
1020 void cik_create_gfx_config(struct radv_device
*device
);
1022 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
1023 int count
, const VkViewport
*viewports
);
1024 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
1025 int count
, const VkRect2D
*scissors
,
1026 const VkViewport
*viewports
, bool can_use_guardband
);
1027 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1028 bool instanced_draw
, bool indirect_draw
,
1029 uint32_t draw_vertex_count
);
1030 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
1032 enum chip_class chip_class
,
1034 unsigned event
, unsigned event_flags
,
1038 uint32_t new_fence
);
1040 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
1042 uint64_t va
, uint32_t ref
,
1044 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
1045 enum chip_class chip_class
,
1046 uint32_t *fence_ptr
, uint64_t va
,
1048 enum radv_cmd_flush_bits flush_bits
);
1049 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1050 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
1051 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1052 uint64_t src_va
, uint64_t dest_va
,
1054 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1056 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1057 uint64_t size
, unsigned value
);
1058 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1060 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1063 unsigned *out_offset
,
1066 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1067 const struct radv_subpass
*subpass
,
1070 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1071 unsigned size
, unsigned alignmnet
,
1072 const void *data
, unsigned *out_offset
);
1074 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1075 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1076 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1077 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1078 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
1079 unsigned radv_cayman_get_maxdist(int log_samples
);
1080 void radv_device_init_msaa(struct radv_device
*device
);
1081 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1082 struct radv_image
*image
,
1083 VkClearDepthStencilValue ds_clear_value
,
1084 VkImageAspectFlags aspects
);
1085 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1086 struct radv_image
*image
,
1088 uint32_t color_values
[2]);
1089 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1090 struct radv_image
*image
,
1092 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1093 struct radeon_winsys_bo
*bo
,
1094 uint64_t offset
, uint64_t size
, uint32_t value
);
1095 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1096 bool radv_get_memory_fd(struct radv_device
*device
,
1097 struct radv_device_memory
*memory
,
1100 static inline struct radv_descriptor_state
*
1101 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1102 VkPipelineBindPoint bind_point
)
1104 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1105 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1106 return &cmd_buffer
->descriptors
[bind_point
];
1110 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1112 * Limitations: Can't call normal dispatch functions without binding or rebinding
1113 * the compute pipeline.
1115 void radv_unaligned_dispatch(
1116 struct radv_cmd_buffer
*cmd_buffer
,
1122 struct radeon_winsys_bo
*bo
;
1126 struct radv_shader_module
;
1128 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1129 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1130 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1132 radv_hash_shaders(unsigned char *hash
,
1133 const VkPipelineShaderStageCreateInfo
**stages
,
1134 const struct radv_pipeline_layout
*layout
,
1135 const struct radv_pipeline_key
*key
,
1138 static inline gl_shader_stage
1139 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1141 assert(__builtin_popcount(vk_stage
) == 1);
1142 return ffs(vk_stage
) - 1;
1145 static inline VkShaderStageFlagBits
1146 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1148 return (1 << mesa_stage
);
1151 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1153 #define radv_foreach_stage(stage, stage_bits) \
1154 for (gl_shader_stage stage, \
1155 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1156 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1157 __tmp &= ~(1 << (stage)))
1159 unsigned radv_format_meta_fs_key(VkFormat format
);
1161 struct radv_multisample_state
{
1163 uint32_t pa_sc_line_cntl
;
1164 uint32_t pa_sc_mode_cntl_0
;
1165 uint32_t pa_sc_mode_cntl_1
;
1166 uint32_t pa_sc_aa_config
;
1167 uint32_t pa_sc_aa_mask
[2];
1168 unsigned num_samples
;
1171 struct radv_prim_vertex_count
{
1176 struct radv_vertex_elements_info
{
1177 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1178 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1179 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1180 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1184 struct radv_ia_multi_vgt_param_helpers
{
1186 bool partial_es_wave
;
1187 uint8_t primgroup_size
;
1188 bool wd_switch_on_eop
;
1189 bool ia_switch_on_eoi
;
1190 bool partial_vs_wave
;
1193 #define SI_GS_PER_ES 128
1195 struct radv_pipeline
{
1196 struct radv_device
* device
;
1197 struct radv_dynamic_state dynamic_state
;
1199 struct radv_pipeline_layout
* layout
;
1201 bool needs_data_cache
;
1202 bool need_indirect_descriptor_sets
;
1203 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1204 struct radv_shader_variant
*gs_copy_shader
;
1205 VkShaderStageFlags active_stages
;
1207 struct radeon_winsys_cs cs
;
1209 struct radv_vertex_elements_info vertex_elements
;
1211 uint32_t binding_stride
[MAX_VBS
];
1213 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1216 struct radv_multisample_state ms
;
1217 uint32_t spi_baryc_cntl
;
1218 bool prim_restart_enable
;
1219 unsigned esgs_ring_size
;
1220 unsigned gsvs_ring_size
;
1221 uint32_t vtx_base_sgpr
;
1222 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1223 uint8_t vtx_emit_num
;
1224 struct radv_prim_vertex_count prim_vertex_count
;
1225 bool can_use_guardband
;
1226 uint32_t needed_dynamic_state
;
1231 unsigned scratch_bytes_per_wave
;
1234 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1236 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1239 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1241 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1244 struct ac_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1245 gl_shader_stage stage
,
1248 struct radv_shader_variant
*radv_get_vertex_shader(struct radv_pipeline
*pipeline
);
1250 struct radv_graphics_pipeline_create_info
{
1252 bool db_depth_clear
;
1253 bool db_stencil_clear
;
1254 bool db_depth_disable_expclear
;
1255 bool db_stencil_disable_expclear
;
1256 bool db_flush_depth_inplace
;
1257 bool db_flush_stencil_inplace
;
1258 bool db_resummarize
;
1259 uint32_t custom_blend_mode
;
1263 radv_graphics_pipeline_create(VkDevice device
,
1264 VkPipelineCache cache
,
1265 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1266 const struct radv_graphics_pipeline_create_info
*extra
,
1267 const VkAllocationCallbacks
*alloc
,
1268 VkPipeline
*pPipeline
);
1270 struct vk_format_description
;
1271 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1272 int first_non_void
);
1273 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1274 int first_non_void
);
1275 uint32_t radv_translate_colorformat(VkFormat format
);
1276 uint32_t radv_translate_color_numformat(VkFormat format
,
1277 const struct vk_format_description
*desc
,
1278 int first_non_void
);
1279 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1280 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1281 uint32_t radv_translate_dbformat(VkFormat format
);
1282 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1283 const struct vk_format_description
*desc
,
1284 int first_non_void
);
1285 uint32_t radv_translate_tex_numformat(VkFormat format
,
1286 const struct vk_format_description
*desc
,
1287 int first_non_void
);
1288 bool radv_format_pack_clear_color(VkFormat format
,
1289 uint32_t clear_vals
[2],
1290 VkClearColorValue
*value
);
1291 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1292 bool radv_dcc_formats_compatible(VkFormat format1
,
1295 struct radv_fmask_info
{
1299 unsigned pitch_in_pixels
;
1300 unsigned bank_height
;
1301 unsigned slice_tile_max
;
1302 unsigned tile_mode_index
;
1303 unsigned tile_swizzle
;
1306 struct radv_cmask_info
{
1310 unsigned slice_tile_max
;
1315 /* The original VkFormat provided by the client. This may not match any
1316 * of the actual surface formats.
1319 VkImageAspectFlags aspects
;
1320 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1321 struct ac_surf_info info
;
1322 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1323 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1328 unsigned queue_family_mask
;
1332 /* Set when bound */
1333 struct radeon_winsys_bo
*bo
;
1334 VkDeviceSize offset
;
1335 uint64_t dcc_offset
;
1336 uint64_t htile_offset
;
1337 bool tc_compatible_htile
;
1338 struct radeon_surf surface
;
1340 struct radv_fmask_info fmask
;
1341 struct radv_cmask_info cmask
;
1342 uint64_t clear_value_offset
;
1343 uint64_t dcc_pred_offset
;
1345 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1346 VkDeviceMemory owned_memory
;
1349 /* Whether the image has a htile that is known consistent with the contents of
1351 bool radv_layout_has_htile(const struct radv_image
*image
,
1352 VkImageLayout layout
,
1353 unsigned queue_mask
);
1355 /* Whether the image has a htile that is known consistent with the contents of
1356 * the image and is allowed to be in compressed form.
1358 * If this is false reads that don't use the htile should be able to return
1361 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1362 VkImageLayout layout
,
1363 unsigned queue_mask
);
1365 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1366 VkImageLayout layout
,
1367 unsigned queue_mask
);
1369 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1370 VkImageLayout layout
,
1371 unsigned queue_mask
);
1374 radv_vi_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1376 return image
->surface
.dcc_size
&& level
< image
->surface
.num_dcc_levels
;
1380 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1382 return image
->surface
.htile_size
&& level
== 0;
1385 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1387 static inline uint32_t
1388 radv_get_layerCount(const struct radv_image
*image
,
1389 const VkImageSubresourceRange
*range
)
1391 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1392 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1395 static inline uint32_t
1396 radv_get_levelCount(const struct radv_image
*image
,
1397 const VkImageSubresourceRange
*range
)
1399 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1400 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1403 struct radeon_bo_metadata
;
1405 radv_init_metadata(struct radv_device
*device
,
1406 struct radv_image
*image
,
1407 struct radeon_bo_metadata
*metadata
);
1409 struct radv_image_view
{
1410 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1411 struct radeon_winsys_bo
*bo
;
1413 VkImageViewType type
;
1414 VkImageAspectFlags aspect_mask
;
1416 uint32_t base_layer
;
1417 uint32_t layer_count
;
1419 uint32_t level_count
;
1420 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1422 uint32_t descriptor
[16];
1424 /* Descriptor for use as a storage image as opposed to a sampled image.
1425 * This has a few differences for cube maps (e.g. type).
1427 uint32_t storage_descriptor
[16];
1430 struct radv_image_create_info
{
1431 const VkImageCreateInfo
*vk_info
;
1433 bool no_metadata_planes
;
1436 VkResult
radv_image_create(VkDevice _device
,
1437 const struct radv_image_create_info
*info
,
1438 const VkAllocationCallbacks
* alloc
,
1442 radv_image_from_gralloc(VkDevice device_h
,
1443 const VkImageCreateInfo
*base_info
,
1444 const VkNativeBufferANDROID
*gralloc_info
,
1445 const VkAllocationCallbacks
*alloc
,
1446 VkImage
*out_image_h
);
1448 void radv_image_view_init(struct radv_image_view
*view
,
1449 struct radv_device
*device
,
1450 const VkImageViewCreateInfo
* pCreateInfo
);
1452 struct radv_buffer_view
{
1453 struct radeon_winsys_bo
*bo
;
1455 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1458 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1459 struct radv_device
*device
,
1460 const VkBufferViewCreateInfo
* pCreateInfo
);
1462 static inline struct VkExtent3D
1463 radv_sanitize_image_extent(const VkImageType imageType
,
1464 const struct VkExtent3D imageExtent
)
1466 switch (imageType
) {
1467 case VK_IMAGE_TYPE_1D
:
1468 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1469 case VK_IMAGE_TYPE_2D
:
1470 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1471 case VK_IMAGE_TYPE_3D
:
1474 unreachable("invalid image type");
1478 static inline struct VkOffset3D
1479 radv_sanitize_image_offset(const VkImageType imageType
,
1480 const struct VkOffset3D imageOffset
)
1482 switch (imageType
) {
1483 case VK_IMAGE_TYPE_1D
:
1484 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1485 case VK_IMAGE_TYPE_2D
:
1486 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1487 case VK_IMAGE_TYPE_3D
:
1490 unreachable("invalid image type");
1495 radv_image_extent_compare(const struct radv_image
*image
,
1496 const VkExtent3D
*extent
)
1498 if (extent
->width
!= image
->info
.width
||
1499 extent
->height
!= image
->info
.height
||
1500 extent
->depth
!= image
->info
.depth
)
1505 struct radv_sampler
{
1509 struct radv_color_buffer_info
{
1510 uint64_t cb_color_base
;
1511 uint64_t cb_color_cmask
;
1512 uint64_t cb_color_fmask
;
1513 uint64_t cb_dcc_base
;
1514 uint32_t cb_color_pitch
;
1515 uint32_t cb_color_slice
;
1516 uint32_t cb_color_view
;
1517 uint32_t cb_color_info
;
1518 uint32_t cb_color_attrib
;
1519 uint32_t cb_color_attrib2
;
1520 uint32_t cb_dcc_control
;
1521 uint32_t cb_color_cmask_slice
;
1522 uint32_t cb_color_fmask_slice
;
1525 struct radv_ds_buffer_info
{
1526 uint64_t db_z_read_base
;
1527 uint64_t db_stencil_read_base
;
1528 uint64_t db_z_write_base
;
1529 uint64_t db_stencil_write_base
;
1530 uint64_t db_htile_data_base
;
1531 uint32_t db_depth_info
;
1533 uint32_t db_stencil_info
;
1534 uint32_t db_depth_view
;
1535 uint32_t db_depth_size
;
1536 uint32_t db_depth_slice
;
1537 uint32_t db_htile_surface
;
1538 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1539 uint32_t db_z_info2
;
1540 uint32_t db_stencil_info2
;
1544 struct radv_attachment_info
{
1546 struct radv_color_buffer_info cb
;
1547 struct radv_ds_buffer_info ds
;
1549 struct radv_image_view
*attachment
;
1552 struct radv_framebuffer
{
1557 uint32_t attachment_count
;
1558 struct radv_attachment_info attachments
[0];
1561 struct radv_subpass_barrier
{
1562 VkPipelineStageFlags src_stage_mask
;
1563 VkAccessFlags src_access_mask
;
1564 VkAccessFlags dst_access_mask
;
1567 struct radv_subpass
{
1568 uint32_t input_count
;
1569 uint32_t color_count
;
1570 VkAttachmentReference
* input_attachments
;
1571 VkAttachmentReference
* color_attachments
;
1572 VkAttachmentReference
* resolve_attachments
;
1573 VkAttachmentReference depth_stencil_attachment
;
1575 /** Subpass has at least one resolve attachment */
1578 struct radv_subpass_barrier start_barrier
;
1583 struct radv_render_pass_attachment
{
1586 VkAttachmentLoadOp load_op
;
1587 VkAttachmentLoadOp stencil_load_op
;
1588 VkImageLayout initial_layout
;
1589 VkImageLayout final_layout
;
1593 struct radv_render_pass
{
1594 uint32_t attachment_count
;
1595 uint32_t subpass_count
;
1596 VkAttachmentReference
* subpass_attachments
;
1597 struct radv_render_pass_attachment
* attachments
;
1598 struct radv_subpass_barrier end_barrier
;
1599 struct radv_subpass subpasses
[0];
1602 VkResult
radv_device_init_meta(struct radv_device
*device
);
1603 void radv_device_finish_meta(struct radv_device
*device
);
1605 struct radv_query_pool
{
1606 struct radeon_winsys_bo
*bo
;
1608 uint32_t availability_offset
;
1612 uint32_t pipeline_stats_mask
;
1615 struct radv_semaphore
{
1616 /* use a winsys sem for non-exportable */
1617 struct radeon_winsys_sem
*sem
;
1619 uint32_t temp_syncobj
;
1622 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1624 const VkSemaphore
*wait_sems
,
1625 int num_signal_sems
,
1626 const VkSemaphore
*signal_sems
,
1628 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1630 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1631 VkPipelineBindPoint bind_point
,
1632 struct radv_descriptor_set
*set
,
1636 radv_update_descriptor_sets(struct radv_device
*device
,
1637 struct radv_cmd_buffer
*cmd_buffer
,
1638 VkDescriptorSet overrideSet
,
1639 uint32_t descriptorWriteCount
,
1640 const VkWriteDescriptorSet
*pDescriptorWrites
,
1641 uint32_t descriptorCopyCount
,
1642 const VkCopyDescriptorSet
*pDescriptorCopies
);
1645 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1646 struct radv_cmd_buffer
*cmd_buffer
,
1647 struct radv_descriptor_set
*set
,
1648 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1651 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1652 VkPipelineBindPoint pipelineBindPoint
,
1653 VkPipelineLayout _layout
,
1655 uint32_t descriptorWriteCount
,
1656 const VkWriteDescriptorSet
*pDescriptorWrites
);
1658 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1659 struct radv_image
*image
, uint32_t value
);
1660 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1661 struct radv_image
*image
, uint32_t value
);
1664 struct radeon_winsys_fence
*fence
;
1669 uint32_t temp_syncobj
;
1672 struct radeon_winsys_sem
;
1674 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1676 static inline struct __radv_type * \
1677 __radv_type ## _from_handle(__VkType _handle) \
1679 return (struct __radv_type *) _handle; \
1682 static inline __VkType \
1683 __radv_type ## _to_handle(struct __radv_type *_obj) \
1685 return (__VkType) _obj; \
1688 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1690 static inline struct __radv_type * \
1691 __radv_type ## _from_handle(__VkType _handle) \
1693 return (struct __radv_type *)(uintptr_t) _handle; \
1696 static inline __VkType \
1697 __radv_type ## _to_handle(struct __radv_type *_obj) \
1699 return (__VkType)(uintptr_t) _obj; \
1702 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1703 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1705 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1706 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1707 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1708 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1709 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1711 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1712 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1715 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1716 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1719 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1720 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1721 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1722 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1723 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1724 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1725 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1726 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1727 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1728 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1729 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1730 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1731 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1733 #endif /* RADV_PRIVATE_H */