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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
65 #include "radv_cs.h"
66
67 #include <llvm-c/TargetMachine.h>
68
69 /* Pre-declarations needed for WSI entrypoints */
70 struct wl_surface;
71 struct wl_display;
72 typedef struct xcb_connection_t xcb_connection_t;
73 typedef uint32_t xcb_visualid_t;
74 typedef uint32_t xcb_window_t;
75
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 #define ATI_VENDOR_ID 0x1002
87
88 #define MAX_VBS 32
89 #define MAX_VERTEX_ATTRIBS 32
90 #define MAX_RTS 8
91 #define MAX_VIEWPORTS 16
92 #define MAX_SCISSORS 16
93 #define MAX_DISCARD_RECTANGLES 4
94 #define MAX_SAMPLE_LOCATIONS 32
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_PUSH_DESCRIPTORS 32
97 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
98 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
99 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
100 #define MAX_SAMPLES_LOG2 4
101 #define NUM_META_FS_KEYS 12
102 #define RADV_MAX_DRM_DEVICES 8
103 #define MAX_VIEWS 8
104 #define MAX_SO_STREAMS 4
105 #define MAX_SO_BUFFERS 4
106 #define MAX_SO_OUTPUTS 64
107 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
108 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
109
110 #define NUM_DEPTH_CLEAR_PIPELINES 3
111
112 /*
113 * This is the point we switch from using CP to compute shader
114 * for certain buffer operations.
115 */
116 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
117
118 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
119
120 enum radv_mem_heap {
121 RADV_MEM_HEAP_VRAM,
122 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
123 RADV_MEM_HEAP_GTT,
124 RADV_MEM_HEAP_COUNT
125 };
126
127 enum radv_mem_type {
128 RADV_MEM_TYPE_VRAM,
129 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
130 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
131 RADV_MEM_TYPE_GTT_CACHED,
132 RADV_MEM_TYPE_COUNT
133 };
134
135 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
136
137 static inline uint32_t
138 align_u32(uint32_t v, uint32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 static inline uint32_t
145 align_u32_npot(uint32_t v, uint32_t a)
146 {
147 return (v + a - 1) / a * a;
148 }
149
150 static inline uint64_t
151 align_u64(uint64_t v, uint64_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 static inline int32_t
158 align_i32(int32_t v, int32_t a)
159 {
160 assert(a != 0 && a == (a & -a));
161 return (v + a - 1) & ~(a - 1);
162 }
163
164 /** Alignment must be a power of 2. */
165 static inline bool
166 radv_is_aligned(uintmax_t n, uintmax_t a)
167 {
168 assert(a == (a & -a));
169 return (n & (a - 1)) == 0;
170 }
171
172 static inline uint32_t
173 round_up_u32(uint32_t v, uint32_t a)
174 {
175 return (v + a - 1) / a;
176 }
177
178 static inline uint64_t
179 round_up_u64(uint64_t v, uint64_t a)
180 {
181 return (v + a - 1) / a;
182 }
183
184 static inline uint32_t
185 radv_minify(uint32_t n, uint32_t levels)
186 {
187 if (unlikely(n == 0))
188 return 0;
189 else
190 return MAX2(n >> levels, 1);
191 }
192 static inline float
193 radv_clamp_f(float f, float min, float max)
194 {
195 assert(min < max);
196
197 if (f > max)
198 return max;
199 else if (f < min)
200 return min;
201 else
202 return f;
203 }
204
205 static inline bool
206 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
207 {
208 if (*inout_mask & clear_mask) {
209 *inout_mask &= ~clear_mask;
210 return true;
211 } else {
212 return false;
213 }
214 }
215
216 #define for_each_bit(b, dword) \
217 for (uint32_t __dword = (dword); \
218 (b) = __builtin_ffs(__dword) - 1, __dword; \
219 __dword &= ~(1 << (b)))
220
221 #define typed_memcpy(dest, src, count) ({ \
222 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
223 memcpy((dest), (src), (count) * sizeof(*(src))); \
224 })
225
226 /* Whenever we generate an error, pass it through this function. Useful for
227 * debugging, where we can break on it. Only call at error site, not when
228 * propagating errors. Might be useful to plug in a stack trace here.
229 */
230
231 struct radv_instance;
232
233 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
234
235 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
236 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
237
238 void __radv_finishme(const char *file, int line, const char *format, ...)
239 radv_printflike(3, 4);
240 void radv_loge(const char *format, ...) radv_printflike(1, 2);
241 void radv_loge_v(const char *format, va_list va);
242 void radv_logi(const char *format, ...) radv_printflike(1, 2);
243 void radv_logi_v(const char *format, va_list va);
244
245 /**
246 * Print a FINISHME message, including its source location.
247 */
248 #define radv_finishme(format, ...) \
249 do { \
250 static bool reported = false; \
251 if (!reported) { \
252 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
253 reported = true; \
254 } \
255 } while (0)
256
257 /* A non-fatal assert. Useful for debugging. */
258 #ifdef DEBUG
259 #define radv_assert(x) ({ \
260 if (unlikely(!(x))) \
261 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
262 })
263 #else
264 #define radv_assert(x)
265 #endif
266
267 #define stub_return(v) \
268 do { \
269 radv_finishme("stub %s", __func__); \
270 return (v); \
271 } while (0)
272
273 #define stub() \
274 do { \
275 radv_finishme("stub %s", __func__); \
276 return; \
277 } while (0)
278
279 void *radv_lookup_entrypoint_unchecked(const char *name);
280 void *radv_lookup_entrypoint_checked(const char *name,
281 uint32_t core_version,
282 const struct radv_instance_extension_table *instance,
283 const struct radv_device_extension_table *device);
284 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
285 uint32_t core_version,
286 const struct radv_instance_extension_table *instance);
287
288 struct radv_physical_device {
289 VK_LOADER_DATA _loader_data;
290
291 struct radv_instance * instance;
292
293 struct radeon_winsys *ws;
294 struct radeon_info rad_info;
295 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
296 uint8_t driver_uuid[VK_UUID_SIZE];
297 uint8_t device_uuid[VK_UUID_SIZE];
298 uint8_t cache_uuid[VK_UUID_SIZE];
299
300 int local_fd;
301 int master_fd;
302 struct wsi_device wsi_device;
303
304 bool has_rbplus; /* if RB+ register exist */
305 bool rbplus_allowed; /* if RB+ is allowed */
306 bool has_clear_state;
307 bool cpdma_prefetch_writes_memory;
308 bool has_scissor_bug;
309
310 bool has_out_of_order_rast;
311 bool out_of_order_rast_allowed;
312
313 /* Whether DCC should be enabled for MSAA textures. */
314 bool dcc_msaa_allowed;
315
316 /* Whether LOAD_CONTEXT_REG packets are supported. */
317 bool has_load_ctx_reg_pkt;
318
319 /* This is the drivers on-disk cache used as a fallback as opposed to
320 * the pipeline cache defined by apps.
321 */
322 struct disk_cache * disk_cache;
323
324 VkPhysicalDeviceMemoryProperties memory_properties;
325 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
326
327 drmPciBusInfo bus_info;
328
329 struct radv_device_extension_table supported_extensions;
330 };
331
332 struct radv_instance {
333 VK_LOADER_DATA _loader_data;
334
335 VkAllocationCallbacks alloc;
336
337 uint32_t apiVersion;
338 int physicalDeviceCount;
339 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
340
341 uint64_t debug_flags;
342 uint64_t perftest_flags;
343
344 struct vk_debug_report_instance debug_report_callbacks;
345
346 struct radv_instance_extension_table enabled_extensions;
347
348 struct driOptionCache dri_options;
349 struct driOptionCache available_dri_options;
350 };
351
352 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
353 void radv_finish_wsi(struct radv_physical_device *physical_device);
354
355 bool radv_instance_extension_supported(const char *name);
356 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
357 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
358 const char *name);
359
360 struct cache_entry;
361
362 struct radv_pipeline_cache {
363 struct radv_device * device;
364 pthread_mutex_t mutex;
365
366 uint32_t total_size;
367 uint32_t table_size;
368 uint32_t kernel_count;
369 struct cache_entry ** hash_table;
370 bool modified;
371
372 VkAllocationCallbacks alloc;
373 };
374
375 struct radv_pipeline_key {
376 uint32_t instance_rate_inputs;
377 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
378 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
379 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
380 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
381 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
382 uint64_t vertex_alpha_adjust;
383 uint32_t vertex_post_shuffle;
384 unsigned tess_input_vertices;
385 uint32_t col_format;
386 uint32_t is_int8;
387 uint32_t is_int10;
388 uint8_t log2_ps_iter_samples;
389 uint8_t num_samples;
390 uint32_t has_multiview_view_index : 1;
391 uint32_t optimisations_disabled : 1;
392 };
393
394 void
395 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
396 struct radv_device *device);
397 void
398 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
399 bool
400 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
401 const void *data, size_t size);
402
403 struct radv_shader_variant;
404
405 bool
406 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
407 struct radv_pipeline_cache *cache,
408 const unsigned char *sha1,
409 struct radv_shader_variant **variants,
410 bool *found_in_application_cache);
411
412 void
413 radv_pipeline_cache_insert_shaders(struct radv_device *device,
414 struct radv_pipeline_cache *cache,
415 const unsigned char *sha1,
416 struct radv_shader_variant **variants,
417 const void *const *codes,
418 const unsigned *code_sizes);
419
420 enum radv_blit_ds_layout {
421 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
422 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
423 RADV_BLIT_DS_LAYOUT_COUNT,
424 };
425
426 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
427 {
428 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
429 }
430
431 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
432 {
433 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
434 }
435
436 enum radv_meta_dst_layout {
437 RADV_META_DST_LAYOUT_GENERAL,
438 RADV_META_DST_LAYOUT_OPTIMAL,
439 RADV_META_DST_LAYOUT_COUNT,
440 };
441
442 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
443 {
444 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
445 }
446
447 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
448 {
449 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
450 }
451
452 struct radv_meta_state {
453 VkAllocationCallbacks alloc;
454
455 struct radv_pipeline_cache cache;
456
457 /*
458 * For on-demand pipeline creation, makes sure that
459 * only one thread tries to build a pipeline at the same time.
460 */
461 mtx_t mtx;
462
463 /**
464 * Use array element `i` for images with `2^i` samples.
465 */
466 struct {
467 VkRenderPass render_pass[NUM_META_FS_KEYS];
468 VkPipeline color_pipelines[NUM_META_FS_KEYS];
469
470 VkRenderPass depthstencil_rp;
471 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
472 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
473 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
474 } clear[1 + MAX_SAMPLES_LOG2];
475
476 VkPipelineLayout clear_color_p_layout;
477 VkPipelineLayout clear_depth_p_layout;
478
479 /* Optimized compute fast HTILE clear for stencil or depth only. */
480 VkPipeline clear_htile_mask_pipeline;
481 VkPipelineLayout clear_htile_mask_p_layout;
482 VkDescriptorSetLayout clear_htile_mask_ds_layout;
483
484 struct {
485 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
486
487 /** Pipeline that blits from a 1D image. */
488 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
489
490 /** Pipeline that blits from a 2D image. */
491 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
492
493 /** Pipeline that blits from a 3D image. */
494 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
495
496 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
497 VkPipeline depth_only_1d_pipeline;
498 VkPipeline depth_only_2d_pipeline;
499 VkPipeline depth_only_3d_pipeline;
500
501 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
502 VkPipeline stencil_only_1d_pipeline;
503 VkPipeline stencil_only_2d_pipeline;
504 VkPipeline stencil_only_3d_pipeline;
505 VkPipelineLayout pipeline_layout;
506 VkDescriptorSetLayout ds_layout;
507 } blit;
508
509 struct {
510 VkPipelineLayout p_layouts[5];
511 VkDescriptorSetLayout ds_layouts[5];
512 VkPipeline pipelines[5][NUM_META_FS_KEYS];
513
514 VkPipeline depth_only_pipeline[5];
515
516 VkPipeline stencil_only_pipeline[5];
517 } blit2d[1 + MAX_SAMPLES_LOG2];
518
519 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
520 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
521 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
522
523 struct {
524 VkPipelineLayout img_p_layout;
525 VkDescriptorSetLayout img_ds_layout;
526 VkPipeline pipeline;
527 VkPipeline pipeline_3d;
528 } itob;
529 struct {
530 VkPipelineLayout img_p_layout;
531 VkDescriptorSetLayout img_ds_layout;
532 VkPipeline pipeline;
533 VkPipeline pipeline_3d;
534 } btoi;
535 struct {
536 VkPipelineLayout img_p_layout;
537 VkDescriptorSetLayout img_ds_layout;
538 VkPipeline pipeline;
539 } btoi_r32g32b32;
540 struct {
541 VkPipelineLayout img_p_layout;
542 VkDescriptorSetLayout img_ds_layout;
543 VkPipeline pipeline;
544 VkPipeline pipeline_3d;
545 } itoi;
546 struct {
547 VkPipelineLayout img_p_layout;
548 VkDescriptorSetLayout img_ds_layout;
549 VkPipeline pipeline;
550 } itoi_r32g32b32;
551 struct {
552 VkPipelineLayout img_p_layout;
553 VkDescriptorSetLayout img_ds_layout;
554 VkPipeline pipeline;
555 VkPipeline pipeline_3d;
556 } cleari;
557 struct {
558 VkPipelineLayout img_p_layout;
559 VkDescriptorSetLayout img_ds_layout;
560 VkPipeline pipeline;
561 } cleari_r32g32b32;
562
563 struct {
564 VkPipelineLayout p_layout;
565 VkPipeline pipeline[NUM_META_FS_KEYS];
566 VkRenderPass pass[NUM_META_FS_KEYS];
567 } resolve;
568
569 struct {
570 VkDescriptorSetLayout ds_layout;
571 VkPipelineLayout p_layout;
572 struct {
573 VkPipeline pipeline;
574 VkPipeline i_pipeline;
575 VkPipeline srgb_pipeline;
576 } rc[MAX_SAMPLES_LOG2];
577 } resolve_compute;
578
579 struct {
580 VkDescriptorSetLayout ds_layout;
581 VkPipelineLayout p_layout;
582
583 struct {
584 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
585 VkPipeline pipeline[NUM_META_FS_KEYS];
586 } rc[MAX_SAMPLES_LOG2];
587 } resolve_fragment;
588
589 struct {
590 VkPipelineLayout p_layout;
591 VkPipeline decompress_pipeline;
592 VkPipeline resummarize_pipeline;
593 VkRenderPass pass;
594 } depth_decomp[1 + MAX_SAMPLES_LOG2];
595
596 struct {
597 VkPipelineLayout p_layout;
598 VkPipeline cmask_eliminate_pipeline;
599 VkPipeline fmask_decompress_pipeline;
600 VkPipeline dcc_decompress_pipeline;
601 VkRenderPass pass;
602
603 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
604 VkPipelineLayout dcc_decompress_compute_p_layout;
605 VkPipeline dcc_decompress_compute_pipeline;
606 } fast_clear_flush;
607
608 struct {
609 VkPipelineLayout fill_p_layout;
610 VkPipelineLayout copy_p_layout;
611 VkDescriptorSetLayout fill_ds_layout;
612 VkDescriptorSetLayout copy_ds_layout;
613 VkPipeline fill_pipeline;
614 VkPipeline copy_pipeline;
615 } buffer;
616
617 struct {
618 VkDescriptorSetLayout ds_layout;
619 VkPipelineLayout p_layout;
620 VkPipeline occlusion_query_pipeline;
621 VkPipeline pipeline_statistics_query_pipeline;
622 VkPipeline tfb_query_pipeline;
623 } query;
624
625 struct {
626 VkDescriptorSetLayout ds_layout;
627 VkPipelineLayout p_layout;
628 VkPipeline pipeline[MAX_SAMPLES_LOG2];
629 } fmask_expand;
630 };
631
632 /* queue types */
633 #define RADV_QUEUE_GENERAL 0
634 #define RADV_QUEUE_COMPUTE 1
635 #define RADV_QUEUE_TRANSFER 2
636
637 #define RADV_MAX_QUEUE_FAMILIES 3
638
639 enum ring_type radv_queue_family_to_ring(int f);
640
641 struct radv_queue {
642 VK_LOADER_DATA _loader_data;
643 struct radv_device * device;
644 struct radeon_winsys_ctx *hw_ctx;
645 enum radeon_ctx_priority priority;
646 uint32_t queue_family_index;
647 int queue_idx;
648 VkDeviceQueueCreateFlags flags;
649
650 uint32_t scratch_size;
651 uint32_t compute_scratch_size;
652 uint32_t esgs_ring_size;
653 uint32_t gsvs_ring_size;
654 bool has_tess_rings;
655 bool has_sample_positions;
656
657 struct radeon_winsys_bo *scratch_bo;
658 struct radeon_winsys_bo *descriptor_bo;
659 struct radeon_winsys_bo *compute_scratch_bo;
660 struct radeon_winsys_bo *esgs_ring_bo;
661 struct radeon_winsys_bo *gsvs_ring_bo;
662 struct radeon_winsys_bo *tess_rings_bo;
663 struct radeon_cmdbuf *initial_preamble_cs;
664 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
665 struct radeon_cmdbuf *continue_preamble_cs;
666 };
667
668 struct radv_bo_list {
669 struct radv_winsys_bo_list list;
670 unsigned capacity;
671 pthread_mutex_t mutex;
672 };
673
674 struct radv_device {
675 VK_LOADER_DATA _loader_data;
676
677 VkAllocationCallbacks alloc;
678
679 struct radv_instance * instance;
680 struct radeon_winsys *ws;
681
682 struct radv_meta_state meta_state;
683
684 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
685 int queue_count[RADV_MAX_QUEUE_FAMILIES];
686 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
687
688 bool always_use_syncobj;
689 bool has_distributed_tess;
690 bool pbb_allowed;
691 bool dfsm_allowed;
692 uint32_t tess_offchip_block_dw_size;
693 uint32_t scratch_waves;
694 uint32_t dispatch_initiator;
695
696 uint32_t gs_table_depth;
697
698 /* MSAA sample locations.
699 * The first index is the sample index.
700 * The second index is the coordinate: X, Y. */
701 float sample_locations_1x[1][2];
702 float sample_locations_2x[2][2];
703 float sample_locations_4x[4][2];
704 float sample_locations_8x[8][2];
705
706 /* GFX7 and later */
707 uint32_t gfx_init_size_dw;
708 struct radeon_winsys_bo *gfx_init;
709
710 struct radeon_winsys_bo *trace_bo;
711 uint32_t *trace_id_ptr;
712
713 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
714 bool keep_shader_info;
715
716 struct radv_physical_device *physical_device;
717
718 /* Backup in-memory cache to be used if the app doesn't provide one */
719 struct radv_pipeline_cache * mem_cache;
720
721 /*
722 * use different counters so MSAA MRTs get consecutive surface indices,
723 * even if MASK is allocated in between.
724 */
725 uint32_t image_mrt_offset_counter;
726 uint32_t fmask_mrt_offset_counter;
727 struct list_head shader_slabs;
728 mtx_t shader_slab_mutex;
729
730 /* For detecting VM faults reported by dmesg. */
731 uint64_t dmesg_timestamp;
732
733 struct radv_device_extension_table enabled_extensions;
734
735 /* Whether the driver uses a global BO list. */
736 bool use_global_bo_list;
737
738 struct radv_bo_list bo_list;
739
740 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
741 int force_aniso;
742 };
743
744 struct radv_device_memory {
745 struct radeon_winsys_bo *bo;
746 /* for dedicated allocations */
747 struct radv_image *image;
748 struct radv_buffer *buffer;
749 uint32_t type_index;
750 VkDeviceSize map_size;
751 void * map;
752 void * user_ptr;
753 };
754
755
756 struct radv_descriptor_range {
757 uint64_t va;
758 uint32_t size;
759 };
760
761 struct radv_descriptor_set {
762 const struct radv_descriptor_set_layout *layout;
763 uint32_t size;
764
765 struct radeon_winsys_bo *bo;
766 uint64_t va;
767 uint32_t *mapped_ptr;
768 struct radv_descriptor_range *dynamic_descriptors;
769
770 struct radeon_winsys_bo *descriptors[0];
771 };
772
773 struct radv_push_descriptor_set
774 {
775 struct radv_descriptor_set set;
776 uint32_t capacity;
777 };
778
779 struct radv_descriptor_pool_entry {
780 uint32_t offset;
781 uint32_t size;
782 struct radv_descriptor_set *set;
783 };
784
785 struct radv_descriptor_pool {
786 struct radeon_winsys_bo *bo;
787 uint8_t *mapped_ptr;
788 uint64_t current_offset;
789 uint64_t size;
790
791 uint8_t *host_memory_base;
792 uint8_t *host_memory_ptr;
793 uint8_t *host_memory_end;
794
795 uint32_t entry_count;
796 uint32_t max_entry_count;
797 struct radv_descriptor_pool_entry entries[0];
798 };
799
800 struct radv_descriptor_update_template_entry {
801 VkDescriptorType descriptor_type;
802
803 /* The number of descriptors to update */
804 uint32_t descriptor_count;
805
806 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
807 uint32_t dst_offset;
808
809 /* In dwords. Not valid/used for dynamic descriptors */
810 uint32_t dst_stride;
811
812 uint32_t buffer_offset;
813
814 /* Only valid for combined image samplers and samplers */
815 uint8_t has_sampler;
816 uint8_t sampler_offset;
817
818 /* In bytes */
819 size_t src_offset;
820 size_t src_stride;
821
822 /* For push descriptors */
823 const uint32_t *immutable_samplers;
824 };
825
826 struct radv_descriptor_update_template {
827 uint32_t entry_count;
828 VkPipelineBindPoint bind_point;
829 struct radv_descriptor_update_template_entry entry[0];
830 };
831
832 struct radv_buffer {
833 VkDeviceSize size;
834
835 VkBufferUsageFlags usage;
836 VkBufferCreateFlags flags;
837
838 /* Set when bound */
839 struct radeon_winsys_bo * bo;
840 VkDeviceSize offset;
841
842 bool shareable;
843 };
844
845 enum radv_dynamic_state_bits {
846 RADV_DYNAMIC_VIEWPORT = 1 << 0,
847 RADV_DYNAMIC_SCISSOR = 1 << 1,
848 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
849 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
850 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
851 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
852 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
853 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
854 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
855 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
856 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
857 RADV_DYNAMIC_ALL = (1 << 11) - 1,
858 };
859
860 enum radv_cmd_dirty_bits {
861 /* Keep the dynamic state dirty bits in sync with
862 * enum radv_dynamic_state_bits */
863 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
864 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
865 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
866 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
867 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
868 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
869 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
870 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
871 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
872 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
873 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
874 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
875 RADV_CMD_DIRTY_PIPELINE = 1 << 11,
876 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
877 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
878 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
879 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
880 };
881
882 enum radv_cmd_flush_bits {
883 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
884 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
885 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
886 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
887 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
888 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
889 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
890 /* Same as above, but only writes back and doesn't invalidate */
891 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
892 /* Framebuffer caches */
893 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
894 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
895 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
896 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
897 /* Engine synchronization. */
898 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
899 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
900 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
901 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
902 /* Pipeline query controls. */
903 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
904 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
905 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
906
907 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
908 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
909 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
910 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
911 };
912
913 struct radv_vertex_binding {
914 struct radv_buffer * buffer;
915 VkDeviceSize offset;
916 };
917
918 struct radv_streamout_binding {
919 struct radv_buffer *buffer;
920 VkDeviceSize offset;
921 VkDeviceSize size;
922 };
923
924 struct radv_streamout_state {
925 /* Mask of bound streamout buffers. */
926 uint8_t enabled_mask;
927
928 /* External state that comes from the last vertex stage, it must be
929 * set explicitely when binding a new graphics pipeline.
930 */
931 uint16_t stride_in_dw[MAX_SO_BUFFERS];
932 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
933
934 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
935 uint32_t hw_enabled_mask;
936
937 /* State of VGT_STRMOUT_(CONFIG|EN) */
938 bool streamout_enabled;
939 };
940
941 struct radv_viewport_state {
942 uint32_t count;
943 VkViewport viewports[MAX_VIEWPORTS];
944 };
945
946 struct radv_scissor_state {
947 uint32_t count;
948 VkRect2D scissors[MAX_SCISSORS];
949 };
950
951 struct radv_discard_rectangle_state {
952 uint32_t count;
953 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
954 };
955
956 struct radv_sample_locations_state {
957 VkSampleCountFlagBits per_pixel;
958 VkExtent2D grid_size;
959 uint32_t count;
960 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
961 };
962
963 struct radv_dynamic_state {
964 /**
965 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
966 * Defines the set of saved dynamic state.
967 */
968 uint32_t mask;
969
970 struct radv_viewport_state viewport;
971
972 struct radv_scissor_state scissor;
973
974 float line_width;
975
976 struct {
977 float bias;
978 float clamp;
979 float slope;
980 } depth_bias;
981
982 float blend_constants[4];
983
984 struct {
985 float min;
986 float max;
987 } depth_bounds;
988
989 struct {
990 uint32_t front;
991 uint32_t back;
992 } stencil_compare_mask;
993
994 struct {
995 uint32_t front;
996 uint32_t back;
997 } stencil_write_mask;
998
999 struct {
1000 uint32_t front;
1001 uint32_t back;
1002 } stencil_reference;
1003
1004 struct radv_discard_rectangle_state discard_rectangle;
1005
1006 struct radv_sample_locations_state sample_location;
1007 };
1008
1009 extern const struct radv_dynamic_state default_dynamic_state;
1010
1011 const char *
1012 radv_get_debug_option_name(int id);
1013
1014 const char *
1015 radv_get_perftest_option_name(int id);
1016
1017 /**
1018 * Attachment state when recording a renderpass instance.
1019 *
1020 * The clear value is valid only if there exists a pending clear.
1021 */
1022 struct radv_attachment_state {
1023 VkImageAspectFlags pending_clear_aspects;
1024 uint32_t cleared_views;
1025 VkClearValue clear_value;
1026 VkImageLayout current_layout;
1027 };
1028
1029 struct radv_descriptor_state {
1030 struct radv_descriptor_set *sets[MAX_SETS];
1031 uint32_t dirty;
1032 uint32_t valid;
1033 struct radv_push_descriptor_set push_set;
1034 bool push_dirty;
1035 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1036 };
1037
1038 struct radv_cmd_state {
1039 /* Vertex descriptors */
1040 uint64_t vb_va;
1041 unsigned vb_size;
1042
1043 bool predicating;
1044 uint32_t dirty;
1045
1046 uint32_t prefetch_L2_mask;
1047
1048 struct radv_pipeline * pipeline;
1049 struct radv_pipeline * emitted_pipeline;
1050 struct radv_pipeline * compute_pipeline;
1051 struct radv_pipeline * emitted_compute_pipeline;
1052 struct radv_framebuffer * framebuffer;
1053 struct radv_render_pass * pass;
1054 const struct radv_subpass * subpass;
1055 struct radv_dynamic_state dynamic;
1056 struct radv_attachment_state * attachments;
1057 struct radv_streamout_state streamout;
1058 VkRect2D render_area;
1059
1060 /* Index buffer */
1061 struct radv_buffer *index_buffer;
1062 uint64_t index_offset;
1063 uint32_t index_type;
1064 uint32_t max_index_count;
1065 uint64_t index_va;
1066 int32_t last_index_type;
1067
1068 int32_t last_primitive_reset_en;
1069 uint32_t last_primitive_reset_index;
1070 enum radv_cmd_flush_bits flush_bits;
1071 unsigned active_occlusion_queries;
1072 bool perfect_occlusion_queries_enabled;
1073 unsigned active_pipeline_queries;
1074 float offset_scale;
1075 uint32_t trace_id;
1076 uint32_t last_ia_multi_vgt_param;
1077
1078 uint32_t last_num_instances;
1079 uint32_t last_first_instance;
1080 uint32_t last_vertex_offset;
1081
1082 /* Whether CP DMA is busy/idle. */
1083 bool dma_is_busy;
1084
1085 /* Conditional rendering info. */
1086 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1087 uint64_t predication_va;
1088
1089 bool context_roll_without_scissor_emitted;
1090 };
1091
1092 struct radv_cmd_pool {
1093 VkAllocationCallbacks alloc;
1094 struct list_head cmd_buffers;
1095 struct list_head free_cmd_buffers;
1096 uint32_t queue_family_index;
1097 };
1098
1099 struct radv_cmd_buffer_upload {
1100 uint8_t *map;
1101 unsigned offset;
1102 uint64_t size;
1103 struct radeon_winsys_bo *upload_bo;
1104 struct list_head list;
1105 };
1106
1107 enum radv_cmd_buffer_status {
1108 RADV_CMD_BUFFER_STATUS_INVALID,
1109 RADV_CMD_BUFFER_STATUS_INITIAL,
1110 RADV_CMD_BUFFER_STATUS_RECORDING,
1111 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1112 RADV_CMD_BUFFER_STATUS_PENDING,
1113 };
1114
1115 struct radv_cmd_buffer {
1116 VK_LOADER_DATA _loader_data;
1117
1118 struct radv_device * device;
1119
1120 struct radv_cmd_pool * pool;
1121 struct list_head pool_link;
1122
1123 VkCommandBufferUsageFlags usage_flags;
1124 VkCommandBufferLevel level;
1125 enum radv_cmd_buffer_status status;
1126 struct radeon_cmdbuf *cs;
1127 struct radv_cmd_state state;
1128 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1129 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1130 uint32_t queue_family_index;
1131
1132 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1133 VkShaderStageFlags push_constant_stages;
1134 struct radv_descriptor_set meta_push_descriptors;
1135
1136 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1137
1138 struct radv_cmd_buffer_upload upload;
1139
1140 uint32_t scratch_size_needed;
1141 uint32_t compute_scratch_size_needed;
1142 uint32_t esgs_ring_size_needed;
1143 uint32_t gsvs_ring_size_needed;
1144 bool tess_rings_needed;
1145 bool sample_positions_needed;
1146
1147 VkResult record_result;
1148
1149 uint64_t gfx9_fence_va;
1150 uint32_t gfx9_fence_idx;
1151 uint64_t gfx9_eop_bug_va;
1152
1153 /**
1154 * Whether a query pool has been resetted and we have to flush caches.
1155 */
1156 bool pending_reset_query;
1157
1158 /**
1159 * Bitmask of pending active query flushes.
1160 */
1161 enum radv_cmd_flush_bits active_query_flush_bits;
1162 };
1163
1164 struct radv_image;
1165
1166 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1167
1168 void si_emit_graphics(struct radv_physical_device *physical_device,
1169 struct radeon_cmdbuf *cs);
1170 void si_emit_compute(struct radv_physical_device *physical_device,
1171 struct radeon_cmdbuf *cs);
1172
1173 void cik_create_gfx_config(struct radv_device *device);
1174
1175 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1176 int count, const VkViewport *viewports);
1177 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1178 int count, const VkRect2D *scissors,
1179 const VkViewport *viewports, bool can_use_guardband);
1180 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1181 bool instanced_draw, bool indirect_draw,
1182 bool count_from_stream_output,
1183 uint32_t draw_vertex_count);
1184 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1185 enum chip_class chip_class,
1186 bool is_mec,
1187 unsigned event, unsigned event_flags,
1188 unsigned data_sel,
1189 uint64_t va,
1190 uint32_t new_fence,
1191 uint64_t gfx9_eop_bug_va);
1192
1193 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1194 uint32_t ref, uint32_t mask);
1195 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1196 enum chip_class chip_class,
1197 uint32_t *fence_ptr, uint64_t va,
1198 bool is_mec,
1199 enum radv_cmd_flush_bits flush_bits,
1200 uint64_t gfx9_eop_bug_va);
1201 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1202 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1203 bool inverted, uint64_t va);
1204 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1205 uint64_t src_va, uint64_t dest_va,
1206 uint64_t size);
1207 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1208 unsigned size);
1209 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1210 uint64_t size, unsigned value);
1211 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1212
1213 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1214 bool
1215 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1216 unsigned size,
1217 unsigned alignment,
1218 unsigned *out_offset,
1219 void **ptr);
1220 void
1221 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1222 const struct radv_subpass *subpass);
1223 bool
1224 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1225 unsigned size, unsigned alignmnet,
1226 const void *data, unsigned *out_offset);
1227
1228 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1229 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1230 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1231 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1232 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1233 unsigned radv_get_default_max_sample_dist(int log_samples);
1234 void radv_device_init_msaa(struct radv_device *device);
1235
1236 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1237 struct radv_image *image,
1238 VkClearDepthStencilValue ds_clear_value,
1239 VkImageAspectFlags aspects);
1240
1241 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1242 struct radv_image *image,
1243 int cb_idx,
1244 uint32_t color_values[2]);
1245
1246 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1247 struct radv_image *image, bool value);
1248
1249 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1250 struct radv_image *image, bool value);
1251
1252 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1253 struct radeon_winsys_bo *bo,
1254 uint64_t offset, uint64_t size, uint32_t value);
1255 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1256 bool radv_get_memory_fd(struct radv_device *device,
1257 struct radv_device_memory *memory,
1258 int *pFD);
1259
1260 static inline void
1261 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1262 unsigned sh_offset, unsigned pointer_count,
1263 bool use_32bit_pointers)
1264 {
1265 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1266 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1267 }
1268
1269 static inline void
1270 radv_emit_shader_pointer_body(struct radv_device *device,
1271 struct radeon_cmdbuf *cs,
1272 uint64_t va, bool use_32bit_pointers)
1273 {
1274 radeon_emit(cs, va);
1275
1276 if (use_32bit_pointers) {
1277 assert(va == 0 ||
1278 (va >> 32) == device->physical_device->rad_info.address32_hi);
1279 } else {
1280 radeon_emit(cs, va >> 32);
1281 }
1282 }
1283
1284 static inline void
1285 radv_emit_shader_pointer(struct radv_device *device,
1286 struct radeon_cmdbuf *cs,
1287 uint32_t sh_offset, uint64_t va, bool global)
1288 {
1289 bool use_32bit_pointers = !global;
1290
1291 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1292 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1293 }
1294
1295 static inline struct radv_descriptor_state *
1296 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1297 VkPipelineBindPoint bind_point)
1298 {
1299 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1300 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1301 return &cmd_buffer->descriptors[bind_point];
1302 }
1303
1304 /*
1305 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1306 *
1307 * Limitations: Can't call normal dispatch functions without binding or rebinding
1308 * the compute pipeline.
1309 */
1310 void radv_unaligned_dispatch(
1311 struct radv_cmd_buffer *cmd_buffer,
1312 uint32_t x,
1313 uint32_t y,
1314 uint32_t z);
1315
1316 struct radv_event {
1317 struct radeon_winsys_bo *bo;
1318 uint64_t *map;
1319 };
1320
1321 struct radv_shader_module;
1322
1323 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1324 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1325 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1326 void
1327 radv_hash_shaders(unsigned char *hash,
1328 const VkPipelineShaderStageCreateInfo **stages,
1329 const struct radv_pipeline_layout *layout,
1330 const struct radv_pipeline_key *key,
1331 uint32_t flags);
1332
1333 static inline gl_shader_stage
1334 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1335 {
1336 assert(__builtin_popcount(vk_stage) == 1);
1337 return ffs(vk_stage) - 1;
1338 }
1339
1340 static inline VkShaderStageFlagBits
1341 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1342 {
1343 return (1 << mesa_stage);
1344 }
1345
1346 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1347
1348 #define radv_foreach_stage(stage, stage_bits) \
1349 for (gl_shader_stage stage, \
1350 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1351 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1352 __tmp &= ~(1 << (stage)))
1353
1354 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1355 unsigned radv_format_meta_fs_key(VkFormat format);
1356
1357 struct radv_multisample_state {
1358 uint32_t db_eqaa;
1359 uint32_t pa_sc_line_cntl;
1360 uint32_t pa_sc_mode_cntl_0;
1361 uint32_t pa_sc_mode_cntl_1;
1362 uint32_t pa_sc_aa_config;
1363 uint32_t pa_sc_aa_mask[2];
1364 unsigned num_samples;
1365 };
1366
1367 struct radv_prim_vertex_count {
1368 uint8_t min;
1369 uint8_t incr;
1370 };
1371
1372 struct radv_vertex_elements_info {
1373 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1374 };
1375
1376 struct radv_ia_multi_vgt_param_helpers {
1377 uint32_t base;
1378 bool partial_es_wave;
1379 uint8_t primgroup_size;
1380 bool wd_switch_on_eop;
1381 bool ia_switch_on_eoi;
1382 bool partial_vs_wave;
1383 };
1384
1385 #define SI_GS_PER_ES 128
1386
1387 struct radv_pipeline {
1388 struct radv_device * device;
1389 struct radv_dynamic_state dynamic_state;
1390
1391 struct radv_pipeline_layout * layout;
1392
1393 bool need_indirect_descriptor_sets;
1394 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1395 struct radv_shader_variant *gs_copy_shader;
1396 VkShaderStageFlags active_stages;
1397
1398 struct radeon_cmdbuf cs;
1399 uint32_t ctx_cs_hash;
1400 struct radeon_cmdbuf ctx_cs;
1401
1402 struct radv_vertex_elements_info vertex_elements;
1403
1404 uint32_t binding_stride[MAX_VBS];
1405 uint8_t num_vertex_bindings;
1406
1407 uint32_t user_data_0[MESA_SHADER_STAGES];
1408 union {
1409 struct {
1410 struct radv_multisample_state ms;
1411 uint32_t spi_baryc_cntl;
1412 bool prim_restart_enable;
1413 unsigned esgs_ring_size;
1414 unsigned gsvs_ring_size;
1415 uint32_t vtx_base_sgpr;
1416 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1417 uint8_t vtx_emit_num;
1418 struct radv_prim_vertex_count prim_vertex_count;
1419 bool can_use_guardband;
1420 uint32_t needed_dynamic_state;
1421 bool disable_out_of_order_rast_for_occlusion;
1422
1423 /* Used for rbplus */
1424 uint32_t col_format;
1425 uint32_t cb_target_mask;
1426 } graphics;
1427 };
1428
1429 unsigned max_waves;
1430 unsigned scratch_bytes_per_wave;
1431
1432 /* Not NULL if graphics pipeline uses streamout. */
1433 struct radv_shader_variant *streamout_shader;
1434 };
1435
1436 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1437 {
1438 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1439 }
1440
1441 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1442 {
1443 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1444 }
1445
1446 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1447 gl_shader_stage stage,
1448 int idx);
1449
1450 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1451 gl_shader_stage stage);
1452
1453 struct radv_graphics_pipeline_create_info {
1454 bool use_rectlist;
1455 bool db_depth_clear;
1456 bool db_stencil_clear;
1457 bool db_depth_disable_expclear;
1458 bool db_stencil_disable_expclear;
1459 bool db_flush_depth_inplace;
1460 bool db_flush_stencil_inplace;
1461 bool db_resummarize;
1462 uint32_t custom_blend_mode;
1463 };
1464
1465 VkResult
1466 radv_graphics_pipeline_create(VkDevice device,
1467 VkPipelineCache cache,
1468 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1469 const struct radv_graphics_pipeline_create_info *extra,
1470 const VkAllocationCallbacks *alloc,
1471 VkPipeline *pPipeline);
1472
1473 struct vk_format_description;
1474 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1475 int first_non_void);
1476 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1477 int first_non_void);
1478 uint32_t radv_translate_colorformat(VkFormat format);
1479 uint32_t radv_translate_color_numformat(VkFormat format,
1480 const struct vk_format_description *desc,
1481 int first_non_void);
1482 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1483 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1484 uint32_t radv_translate_dbformat(VkFormat format);
1485 uint32_t radv_translate_tex_dataformat(VkFormat format,
1486 const struct vk_format_description *desc,
1487 int first_non_void);
1488 uint32_t radv_translate_tex_numformat(VkFormat format,
1489 const struct vk_format_description *desc,
1490 int first_non_void);
1491 bool radv_format_pack_clear_color(VkFormat format,
1492 uint32_t clear_vals[2],
1493 VkClearColorValue *value);
1494 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1495 bool radv_dcc_formats_compatible(VkFormat format1,
1496 VkFormat format2);
1497 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1498
1499 struct radv_fmask_info {
1500 uint64_t offset;
1501 uint64_t size;
1502 unsigned alignment;
1503 unsigned pitch_in_pixels;
1504 unsigned bank_height;
1505 unsigned slice_tile_max;
1506 unsigned tile_mode_index;
1507 unsigned tile_swizzle;
1508 };
1509
1510 struct radv_cmask_info {
1511 uint64_t offset;
1512 uint64_t size;
1513 unsigned alignment;
1514 unsigned slice_tile_max;
1515 };
1516
1517
1518 struct radv_image_plane {
1519 VkFormat format;
1520 struct radeon_surf surface;
1521 uint64_t offset;
1522 };
1523
1524 struct radv_image {
1525 VkImageType type;
1526 /* The original VkFormat provided by the client. This may not match any
1527 * of the actual surface formats.
1528 */
1529 VkFormat vk_format;
1530 VkImageAspectFlags aspects;
1531 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1532 struct ac_surf_info info;
1533 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1534 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1535
1536 VkDeviceSize size;
1537 uint32_t alignment;
1538
1539 unsigned queue_family_mask;
1540 bool exclusive;
1541 bool shareable;
1542
1543 /* Set when bound */
1544 struct radeon_winsys_bo *bo;
1545 VkDeviceSize offset;
1546 uint64_t dcc_offset;
1547 uint64_t htile_offset;
1548 bool tc_compatible_htile;
1549
1550 struct radv_fmask_info fmask;
1551 struct radv_cmask_info cmask;
1552 uint64_t clear_value_offset;
1553 uint64_t fce_pred_offset;
1554 uint64_t dcc_pred_offset;
1555
1556 /*
1557 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1558 * stored at this offset is UINT_MAX, the driver will emit
1559 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1560 * SET_CONTEXT_REG packet.
1561 */
1562 uint64_t tc_compat_zrange_offset;
1563
1564 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1565 VkDeviceMemory owned_memory;
1566
1567 unsigned plane_count;
1568 struct radv_image_plane planes[0];
1569 };
1570
1571 /* Whether the image has a htile that is known consistent with the contents of
1572 * the image. */
1573 bool radv_layout_has_htile(const struct radv_image *image,
1574 VkImageLayout layout,
1575 unsigned queue_mask);
1576
1577 /* Whether the image has a htile that is known consistent with the contents of
1578 * the image and is allowed to be in compressed form.
1579 *
1580 * If this is false reads that don't use the htile should be able to return
1581 * correct results.
1582 */
1583 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1584 VkImageLayout layout,
1585 unsigned queue_mask);
1586
1587 bool radv_layout_can_fast_clear(const struct radv_image *image,
1588 VkImageLayout layout,
1589 unsigned queue_mask);
1590
1591 bool radv_layout_dcc_compressed(const struct radv_image *image,
1592 VkImageLayout layout,
1593 unsigned queue_mask);
1594
1595 /**
1596 * Return whether the image has CMASK metadata for color surfaces.
1597 */
1598 static inline bool
1599 radv_image_has_cmask(const struct radv_image *image)
1600 {
1601 return image->cmask.size;
1602 }
1603
1604 /**
1605 * Return whether the image has FMASK metadata for color surfaces.
1606 */
1607 static inline bool
1608 radv_image_has_fmask(const struct radv_image *image)
1609 {
1610 return image->fmask.size;
1611 }
1612
1613 /**
1614 * Return whether the image has DCC metadata for color surfaces.
1615 */
1616 static inline bool
1617 radv_image_has_dcc(const struct radv_image *image)
1618 {
1619 return image->planes[0].surface.dcc_size;
1620 }
1621
1622 /**
1623 * Return whether DCC metadata is enabled for a level.
1624 */
1625 static inline bool
1626 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1627 {
1628 return radv_image_has_dcc(image) &&
1629 level < image->planes[0].surface.num_dcc_levels;
1630 }
1631
1632 /**
1633 * Return whether the image has CB metadata.
1634 */
1635 static inline bool
1636 radv_image_has_CB_metadata(const struct radv_image *image)
1637 {
1638 return radv_image_has_cmask(image) ||
1639 radv_image_has_fmask(image) ||
1640 radv_image_has_dcc(image);
1641 }
1642
1643 /**
1644 * Return whether the image has HTILE metadata for depth surfaces.
1645 */
1646 static inline bool
1647 radv_image_has_htile(const struct radv_image *image)
1648 {
1649 return image->planes[0].surface.htile_size;
1650 }
1651
1652 /**
1653 * Return whether HTILE metadata is enabled for a level.
1654 */
1655 static inline bool
1656 radv_htile_enabled(const struct radv_image *image, unsigned level)
1657 {
1658 return radv_image_has_htile(image) && level == 0;
1659 }
1660
1661 /**
1662 * Return whether the image is TC-compatible HTILE.
1663 */
1664 static inline bool
1665 radv_image_is_tc_compat_htile(const struct radv_image *image)
1666 {
1667 return radv_image_has_htile(image) && image->tc_compatible_htile;
1668 }
1669
1670 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1671
1672 static inline uint32_t
1673 radv_get_layerCount(const struct radv_image *image,
1674 const VkImageSubresourceRange *range)
1675 {
1676 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1677 image->info.array_size - range->baseArrayLayer : range->layerCount;
1678 }
1679
1680 static inline uint32_t
1681 radv_get_levelCount(const struct radv_image *image,
1682 const VkImageSubresourceRange *range)
1683 {
1684 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1685 image->info.levels - range->baseMipLevel : range->levelCount;
1686 }
1687
1688 struct radeon_bo_metadata;
1689 void
1690 radv_init_metadata(struct radv_device *device,
1691 struct radv_image *image,
1692 struct radeon_bo_metadata *metadata);
1693
1694 void
1695 radv_image_override_offset_stride(struct radv_device *device,
1696 struct radv_image *image,
1697 uint64_t offset, uint32_t stride);
1698
1699 union radv_descriptor {
1700 struct {
1701 uint32_t plane0_descriptor[8];
1702 uint32_t fmask_descriptor[8];
1703 };
1704 struct {
1705 uint32_t plane_descriptors[3][8];
1706 };
1707 };
1708
1709 struct radv_image_view {
1710 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1711 struct radeon_winsys_bo *bo;
1712
1713 VkImageViewType type;
1714 VkImageAspectFlags aspect_mask;
1715 VkFormat vk_format;
1716 unsigned plane_id;
1717 bool multiple_planes;
1718 uint32_t base_layer;
1719 uint32_t layer_count;
1720 uint32_t base_mip;
1721 uint32_t level_count;
1722 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1723
1724 union radv_descriptor descriptor;
1725
1726 /* Descriptor for use as a storage image as opposed to a sampled image.
1727 * This has a few differences for cube maps (e.g. type).
1728 */
1729 union radv_descriptor storage_descriptor;
1730 };
1731
1732 struct radv_image_create_info {
1733 const VkImageCreateInfo *vk_info;
1734 bool scanout;
1735 bool no_metadata_planes;
1736 };
1737
1738 VkResult radv_image_create(VkDevice _device,
1739 const struct radv_image_create_info *info,
1740 const VkAllocationCallbacks* alloc,
1741 VkImage *pImage);
1742
1743 VkResult
1744 radv_image_from_gralloc(VkDevice device_h,
1745 const VkImageCreateInfo *base_info,
1746 const VkNativeBufferANDROID *gralloc_info,
1747 const VkAllocationCallbacks *alloc,
1748 VkImage *out_image_h);
1749
1750 void radv_image_view_init(struct radv_image_view *view,
1751 struct radv_device *device,
1752 const VkImageViewCreateInfo* pCreateInfo);
1753
1754 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1755
1756 struct radv_sampler_ycbcr_conversion {
1757 VkFormat format;
1758 VkSamplerYcbcrModelConversion ycbcr_model;
1759 VkSamplerYcbcrRange ycbcr_range;
1760 VkComponentMapping components;
1761 VkChromaLocation chroma_offsets[2];
1762 VkFilter chroma_filter;
1763 };
1764
1765 struct radv_buffer_view {
1766 struct radeon_winsys_bo *bo;
1767 VkFormat vk_format;
1768 uint64_t range; /**< VkBufferViewCreateInfo::range */
1769 uint32_t state[4];
1770 };
1771 void radv_buffer_view_init(struct radv_buffer_view *view,
1772 struct radv_device *device,
1773 const VkBufferViewCreateInfo* pCreateInfo);
1774
1775 static inline struct VkExtent3D
1776 radv_sanitize_image_extent(const VkImageType imageType,
1777 const struct VkExtent3D imageExtent)
1778 {
1779 switch (imageType) {
1780 case VK_IMAGE_TYPE_1D:
1781 return (VkExtent3D) { imageExtent.width, 1, 1 };
1782 case VK_IMAGE_TYPE_2D:
1783 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1784 case VK_IMAGE_TYPE_3D:
1785 return imageExtent;
1786 default:
1787 unreachable("invalid image type");
1788 }
1789 }
1790
1791 static inline struct VkOffset3D
1792 radv_sanitize_image_offset(const VkImageType imageType,
1793 const struct VkOffset3D imageOffset)
1794 {
1795 switch (imageType) {
1796 case VK_IMAGE_TYPE_1D:
1797 return (VkOffset3D) { imageOffset.x, 0, 0 };
1798 case VK_IMAGE_TYPE_2D:
1799 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1800 case VK_IMAGE_TYPE_3D:
1801 return imageOffset;
1802 default:
1803 unreachable("invalid image type");
1804 }
1805 }
1806
1807 static inline bool
1808 radv_image_extent_compare(const struct radv_image *image,
1809 const VkExtent3D *extent)
1810 {
1811 if (extent->width != image->info.width ||
1812 extent->height != image->info.height ||
1813 extent->depth != image->info.depth)
1814 return false;
1815 return true;
1816 }
1817
1818 struct radv_sampler {
1819 uint32_t state[4];
1820 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1821 };
1822
1823 struct radv_color_buffer_info {
1824 uint64_t cb_color_base;
1825 uint64_t cb_color_cmask;
1826 uint64_t cb_color_fmask;
1827 uint64_t cb_dcc_base;
1828 uint32_t cb_color_slice;
1829 uint32_t cb_color_view;
1830 uint32_t cb_color_info;
1831 uint32_t cb_color_attrib;
1832 uint32_t cb_color_attrib2;
1833 uint32_t cb_dcc_control;
1834 uint32_t cb_color_cmask_slice;
1835 uint32_t cb_color_fmask_slice;
1836 union {
1837 uint32_t cb_color_pitch; // GFX6-GFX8
1838 uint32_t cb_mrt_epitch; // GFX9+
1839 };
1840 };
1841
1842 struct radv_ds_buffer_info {
1843 uint64_t db_z_read_base;
1844 uint64_t db_stencil_read_base;
1845 uint64_t db_z_write_base;
1846 uint64_t db_stencil_write_base;
1847 uint64_t db_htile_data_base;
1848 uint32_t db_depth_info;
1849 uint32_t db_z_info;
1850 uint32_t db_stencil_info;
1851 uint32_t db_depth_view;
1852 uint32_t db_depth_size;
1853 uint32_t db_depth_slice;
1854 uint32_t db_htile_surface;
1855 uint32_t pa_su_poly_offset_db_fmt_cntl;
1856 uint32_t db_z_info2;
1857 uint32_t db_stencil_info2;
1858 float offset_scale;
1859 };
1860
1861 struct radv_attachment_info {
1862 union {
1863 struct radv_color_buffer_info cb;
1864 struct radv_ds_buffer_info ds;
1865 };
1866 struct radv_image_view *attachment;
1867 };
1868
1869 struct radv_framebuffer {
1870 uint32_t width;
1871 uint32_t height;
1872 uint32_t layers;
1873
1874 uint32_t attachment_count;
1875 struct radv_attachment_info attachments[0];
1876 };
1877
1878 struct radv_subpass_barrier {
1879 VkPipelineStageFlags src_stage_mask;
1880 VkAccessFlags src_access_mask;
1881 VkAccessFlags dst_access_mask;
1882 };
1883
1884 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1885 const struct radv_subpass_barrier *barrier);
1886
1887 struct radv_subpass_attachment {
1888 uint32_t attachment;
1889 VkImageLayout layout;
1890 };
1891
1892 struct radv_subpass {
1893 uint32_t attachment_count;
1894 struct radv_subpass_attachment * attachments;
1895
1896 uint32_t input_count;
1897 uint32_t color_count;
1898 struct radv_subpass_attachment * input_attachments;
1899 struct radv_subpass_attachment * color_attachments;
1900 struct radv_subpass_attachment * resolve_attachments;
1901 struct radv_subpass_attachment * depth_stencil_attachment;
1902
1903 /** Subpass has at least one resolve attachment */
1904 bool has_resolve;
1905
1906 /** Subpass has at least one color attachment */
1907 bool has_color_att;
1908
1909 struct radv_subpass_barrier start_barrier;
1910
1911 uint32_t view_mask;
1912 VkSampleCountFlagBits max_sample_count;
1913 };
1914
1915 struct radv_render_pass_attachment {
1916 VkFormat format;
1917 uint32_t samples;
1918 VkAttachmentLoadOp load_op;
1919 VkAttachmentLoadOp stencil_load_op;
1920 VkImageLayout initial_layout;
1921 VkImageLayout final_layout;
1922
1923 /* The subpass id in which the attachment will be used last. */
1924 uint32_t last_subpass_idx;
1925 };
1926
1927 struct radv_render_pass {
1928 uint32_t attachment_count;
1929 uint32_t subpass_count;
1930 struct radv_subpass_attachment * subpass_attachments;
1931 struct radv_render_pass_attachment * attachments;
1932 struct radv_subpass_barrier end_barrier;
1933 struct radv_subpass subpasses[0];
1934 };
1935
1936 VkResult radv_device_init_meta(struct radv_device *device);
1937 void radv_device_finish_meta(struct radv_device *device);
1938
1939 struct radv_query_pool {
1940 struct radeon_winsys_bo *bo;
1941 uint32_t stride;
1942 uint32_t availability_offset;
1943 uint64_t size;
1944 char *ptr;
1945 VkQueryType type;
1946 uint32_t pipeline_stats_mask;
1947 };
1948
1949 struct radv_semaphore {
1950 /* use a winsys sem for non-exportable */
1951 struct radeon_winsys_sem *sem;
1952 uint32_t syncobj;
1953 uint32_t temp_syncobj;
1954 };
1955
1956 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1957 VkPipelineBindPoint bind_point,
1958 struct radv_descriptor_set *set,
1959 unsigned idx);
1960
1961 void
1962 radv_update_descriptor_sets(struct radv_device *device,
1963 struct radv_cmd_buffer *cmd_buffer,
1964 VkDescriptorSet overrideSet,
1965 uint32_t descriptorWriteCount,
1966 const VkWriteDescriptorSet *pDescriptorWrites,
1967 uint32_t descriptorCopyCount,
1968 const VkCopyDescriptorSet *pDescriptorCopies);
1969
1970 void
1971 radv_update_descriptor_set_with_template(struct radv_device *device,
1972 struct radv_cmd_buffer *cmd_buffer,
1973 struct radv_descriptor_set *set,
1974 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1975 const void *pData);
1976
1977 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1978 VkPipelineBindPoint pipelineBindPoint,
1979 VkPipelineLayout _layout,
1980 uint32_t set,
1981 uint32_t descriptorWriteCount,
1982 const VkWriteDescriptorSet *pDescriptorWrites);
1983
1984 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1985 struct radv_image *image, uint32_t value);
1986
1987 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
1988 struct radv_image *image);
1989
1990 struct radv_fence {
1991 struct radeon_winsys_fence *fence;
1992 struct wsi_fence *fence_wsi;
1993
1994 uint32_t syncobj;
1995 uint32_t temp_syncobj;
1996 };
1997
1998 /* radv_nir_to_llvm.c */
1999 struct radv_shader_variant_info;
2000 struct radv_nir_compiler_options;
2001
2002 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2003 struct nir_shader *geom_shader,
2004 struct ac_shader_binary *binary,
2005 struct ac_shader_config *config,
2006 struct radv_shader_variant_info *shader_info,
2007 const struct radv_nir_compiler_options *option);
2008
2009 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2010 struct ac_shader_binary *binary,
2011 struct ac_shader_config *config,
2012 struct radv_shader_variant_info *shader_info,
2013 struct nir_shader *const *nir,
2014 int nir_count,
2015 const struct radv_nir_compiler_options *options);
2016
2017 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2018 const struct nir_shader *nir);
2019
2020 /* radv_shader_info.h */
2021 struct radv_shader_info;
2022
2023 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2024 const struct radv_nir_compiler_options *options,
2025 struct radv_shader_info *info);
2026
2027 void radv_nir_shader_info_init(struct radv_shader_info *info);
2028
2029 struct radeon_winsys_sem;
2030
2031 uint64_t radv_get_current_time(void);
2032
2033 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2034 \
2035 static inline struct __radv_type * \
2036 __radv_type ## _from_handle(__VkType _handle) \
2037 { \
2038 return (struct __radv_type *) _handle; \
2039 } \
2040 \
2041 static inline __VkType \
2042 __radv_type ## _to_handle(struct __radv_type *_obj) \
2043 { \
2044 return (__VkType) _obj; \
2045 }
2046
2047 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2048 \
2049 static inline struct __radv_type * \
2050 __radv_type ## _from_handle(__VkType _handle) \
2051 { \
2052 return (struct __radv_type *)(uintptr_t) _handle; \
2053 } \
2054 \
2055 static inline __VkType \
2056 __radv_type ## _to_handle(struct __radv_type *_obj) \
2057 { \
2058 return (__VkType)(uintptr_t) _obj; \
2059 }
2060
2061 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2062 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2063
2064 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2065 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2066 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2067 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2068 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2069
2070 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2071 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2072 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2073 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2074 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2075 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2076 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2077 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2078 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2079 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2080 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2081 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2082 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2083 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2084 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2085 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2086 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2087 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2088 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2089 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2090 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2091 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2092
2093 #endif /* RADV_PRIVATE_H */