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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102 #define MAX_SO_STREAMS 4
103 #define MAX_SO_BUFFERS 4
104 #define MAX_SO_OUTPUTS 64
105
106 #define NUM_DEPTH_CLEAR_PIPELINES 3
107
108 /*
109 * This is the point we switch from using CP to compute shader
110 * for certain buffer operations.
111 */
112 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113
114 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
115
116 enum radv_mem_heap {
117 RADV_MEM_HEAP_VRAM,
118 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
119 RADV_MEM_HEAP_GTT,
120 RADV_MEM_HEAP_COUNT
121 };
122
123 enum radv_mem_type {
124 RADV_MEM_TYPE_VRAM,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
127 RADV_MEM_TYPE_GTT_CACHED,
128 RADV_MEM_TYPE_COUNT
129 };
130
131 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
132
133 static inline uint32_t
134 align_u32(uint32_t v, uint32_t a)
135 {
136 assert(a != 0 && a == (a & -a));
137 return (v + a - 1) & ~(a - 1);
138 }
139
140 static inline uint32_t
141 align_u32_npot(uint32_t v, uint32_t a)
142 {
143 return (v + a - 1) / a * a;
144 }
145
146 static inline uint64_t
147 align_u64(uint64_t v, uint64_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 static inline int32_t
154 align_i32(int32_t v, int32_t a)
155 {
156 assert(a != 0 && a == (a & -a));
157 return (v + a - 1) & ~(a - 1);
158 }
159
160 /** Alignment must be a power of 2. */
161 static inline bool
162 radv_is_aligned(uintmax_t n, uintmax_t a)
163 {
164 assert(a == (a & -a));
165 return (n & (a - 1)) == 0;
166 }
167
168 static inline uint32_t
169 round_up_u32(uint32_t v, uint32_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint64_t
175 round_up_u64(uint64_t v, uint64_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint32_t
181 radv_minify(uint32_t n, uint32_t levels)
182 {
183 if (unlikely(n == 0))
184 return 0;
185 else
186 return MAX2(n >> levels, 1);
187 }
188 static inline float
189 radv_clamp_f(float f, float min, float max)
190 {
191 assert(min < max);
192
193 if (f > max)
194 return max;
195 else if (f < min)
196 return min;
197 else
198 return f;
199 }
200
201 static inline bool
202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
203 {
204 if (*inout_mask & clear_mask) {
205 *inout_mask &= ~clear_mask;
206 return true;
207 } else {
208 return false;
209 }
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Whenever we generate an error, pass it through this function. Useful for
223 * debugging, where we can break on it. Only call at error site, not when
224 * propagating errors. Might be useful to plug in a stack trace here.
225 */
226
227 struct radv_instance;
228
229 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
230
231 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
232 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
233
234 void __radv_finishme(const char *file, int line, const char *format, ...)
235 radv_printflike(3, 4);
236 void radv_loge(const char *format, ...) radv_printflike(1, 2);
237 void radv_loge_v(const char *format, va_list va);
238 void radv_logi(const char *format, ...) radv_printflike(1, 2);
239 void radv_logi_v(const char *format, va_list va);
240
241 /**
242 * Print a FINISHME message, including its source location.
243 */
244 #define radv_finishme(format, ...) \
245 do { \
246 static bool reported = false; \
247 if (!reported) { \
248 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 reported = true; \
250 } \
251 } while (0)
252
253 /* A non-fatal assert. Useful for debugging. */
254 #ifdef DEBUG
255 #define radv_assert(x) ({ \
256 if (unlikely(!(x))) \
257 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
258 })
259 #else
260 #define radv_assert(x)
261 #endif
262
263 #define stub_return(v) \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return (v); \
267 } while (0)
268
269 #define stub() \
270 do { \
271 radv_finishme("stub %s", __func__); \
272 return; \
273 } while (0)
274
275 void *radv_lookup_entrypoint_unchecked(const char *name);
276 void *radv_lookup_entrypoint_checked(const char *name,
277 uint32_t core_version,
278 const struct radv_instance_extension_table *instance,
279 const struct radv_device_extension_table *device);
280
281 struct radv_physical_device {
282 VK_LOADER_DATA _loader_data;
283
284 struct radv_instance * instance;
285
286 struct radeon_winsys *ws;
287 struct radeon_info rad_info;
288 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
289 uint8_t driver_uuid[VK_UUID_SIZE];
290 uint8_t device_uuid[VK_UUID_SIZE];
291 uint8_t cache_uuid[VK_UUID_SIZE];
292
293 int local_fd;
294 int master_fd;
295 struct wsi_device wsi_device;
296
297 bool has_rbplus; /* if RB+ register exist */
298 bool rbplus_allowed; /* if RB+ is allowed */
299 bool has_clear_state;
300 bool cpdma_prefetch_writes_memory;
301 bool has_scissor_bug;
302
303 bool has_out_of_order_rast;
304 bool out_of_order_rast_allowed;
305
306 /* Whether DCC should be enabled for MSAA textures. */
307 bool dcc_msaa_allowed;
308
309 /* Whether LOAD_CONTEXT_REG packets are supported. */
310 bool has_load_ctx_reg_pkt;
311
312 /* This is the drivers on-disk cache used as a fallback as opposed to
313 * the pipeline cache defined by apps.
314 */
315 struct disk_cache * disk_cache;
316
317 VkPhysicalDeviceMemoryProperties memory_properties;
318 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
319
320 drmPciBusInfo bus_info;
321
322 struct radv_device_extension_table supported_extensions;
323 };
324
325 struct radv_instance {
326 VK_LOADER_DATA _loader_data;
327
328 VkAllocationCallbacks alloc;
329
330 uint32_t apiVersion;
331 int physicalDeviceCount;
332 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
333
334 uint64_t debug_flags;
335 uint64_t perftest_flags;
336
337 struct vk_debug_report_instance debug_report_callbacks;
338
339 struct radv_instance_extension_table enabled_extensions;
340 };
341
342 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
343 void radv_finish_wsi(struct radv_physical_device *physical_device);
344
345 bool radv_instance_extension_supported(const char *name);
346 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
347 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
348 const char *name);
349
350 struct cache_entry;
351
352 struct radv_pipeline_cache {
353 struct radv_device * device;
354 pthread_mutex_t mutex;
355
356 uint32_t total_size;
357 uint32_t table_size;
358 uint32_t kernel_count;
359 struct cache_entry ** hash_table;
360 bool modified;
361
362 VkAllocationCallbacks alloc;
363 };
364
365 struct radv_pipeline_key {
366 uint32_t instance_rate_inputs;
367 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
368 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
369 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
370 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
371 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
372 uint64_t vertex_alpha_adjust;
373 uint32_t vertex_post_shuffle;
374 unsigned tess_input_vertices;
375 uint32_t col_format;
376 uint32_t is_int8;
377 uint32_t is_int10;
378 uint8_t log2_ps_iter_samples;
379 uint8_t num_samples;
380 uint32_t has_multiview_view_index : 1;
381 uint32_t optimisations_disabled : 1;
382 };
383
384 void
385 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
386 struct radv_device *device);
387 void
388 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
389 bool
390 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
391 const void *data, size_t size);
392
393 struct radv_shader_variant;
394
395 bool
396 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
397 struct radv_pipeline_cache *cache,
398 const unsigned char *sha1,
399 struct radv_shader_variant **variants,
400 bool *found_in_application_cache);
401
402 void
403 radv_pipeline_cache_insert_shaders(struct radv_device *device,
404 struct radv_pipeline_cache *cache,
405 const unsigned char *sha1,
406 struct radv_shader_variant **variants,
407 const void *const *codes,
408 const unsigned *code_sizes);
409
410 enum radv_blit_ds_layout {
411 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
412 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
413 RADV_BLIT_DS_LAYOUT_COUNT,
414 };
415
416 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
417 {
418 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
419 }
420
421 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
422 {
423 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
424 }
425
426 enum radv_meta_dst_layout {
427 RADV_META_DST_LAYOUT_GENERAL,
428 RADV_META_DST_LAYOUT_OPTIMAL,
429 RADV_META_DST_LAYOUT_COUNT,
430 };
431
432 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
433 {
434 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
435 }
436
437 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
438 {
439 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
440 }
441
442 struct radv_meta_state {
443 VkAllocationCallbacks alloc;
444
445 struct radv_pipeline_cache cache;
446
447 /*
448 * For on-demand pipeline creation, makes sure that
449 * only one thread tries to build a pipeline at the same time.
450 */
451 mtx_t mtx;
452
453 /**
454 * Use array element `i` for images with `2^i` samples.
455 */
456 struct {
457 VkRenderPass render_pass[NUM_META_FS_KEYS];
458 VkPipeline color_pipelines[NUM_META_FS_KEYS];
459
460 VkRenderPass depthstencil_rp;
461 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
462 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
463 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
464 } clear[1 + MAX_SAMPLES_LOG2];
465
466 VkPipelineLayout clear_color_p_layout;
467 VkPipelineLayout clear_depth_p_layout;
468
469 /* Optimized compute fast HTILE clear for stencil or depth only. */
470 VkPipeline clear_htile_mask_pipeline;
471 VkPipelineLayout clear_htile_mask_p_layout;
472 VkDescriptorSetLayout clear_htile_mask_ds_layout;
473
474 struct {
475 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
476
477 /** Pipeline that blits from a 1D image. */
478 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
479
480 /** Pipeline that blits from a 2D image. */
481 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
482
483 /** Pipeline that blits from a 3D image. */
484 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
485
486 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
487 VkPipeline depth_only_1d_pipeline;
488 VkPipeline depth_only_2d_pipeline;
489 VkPipeline depth_only_3d_pipeline;
490
491 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
492 VkPipeline stencil_only_1d_pipeline;
493 VkPipeline stencil_only_2d_pipeline;
494 VkPipeline stencil_only_3d_pipeline;
495 VkPipelineLayout pipeline_layout;
496 VkDescriptorSetLayout ds_layout;
497 } blit;
498
499 struct {
500 VkPipelineLayout p_layouts[5];
501 VkDescriptorSetLayout ds_layouts[5];
502 VkPipeline pipelines[5][NUM_META_FS_KEYS];
503
504 VkPipeline depth_only_pipeline[5];
505
506 VkPipeline stencil_only_pipeline[5];
507 } blit2d[1 + MAX_SAMPLES_LOG2];
508
509 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
510 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
511 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
512
513 struct {
514 VkPipelineLayout img_p_layout;
515 VkDescriptorSetLayout img_ds_layout;
516 VkPipeline pipeline;
517 VkPipeline pipeline_3d;
518 } itob;
519 struct {
520 VkPipelineLayout img_p_layout;
521 VkDescriptorSetLayout img_ds_layout;
522 VkPipeline pipeline;
523 VkPipeline pipeline_3d;
524 } btoi;
525 struct {
526 VkPipelineLayout img_p_layout;
527 VkDescriptorSetLayout img_ds_layout;
528 VkPipeline pipeline;
529 } btoi_r32g32b32;
530 struct {
531 VkPipelineLayout img_p_layout;
532 VkDescriptorSetLayout img_ds_layout;
533 VkPipeline pipeline;
534 VkPipeline pipeline_3d;
535 } itoi;
536 struct {
537 VkPipelineLayout img_p_layout;
538 VkDescriptorSetLayout img_ds_layout;
539 VkPipeline pipeline;
540 } itoi_r32g32b32;
541 struct {
542 VkPipelineLayout img_p_layout;
543 VkDescriptorSetLayout img_ds_layout;
544 VkPipeline pipeline;
545 VkPipeline pipeline_3d;
546 } cleari;
547 struct {
548 VkPipelineLayout img_p_layout;
549 VkDescriptorSetLayout img_ds_layout;
550 VkPipeline pipeline;
551 } cleari_r32g32b32;
552
553 struct {
554 VkPipelineLayout p_layout;
555 VkPipeline pipeline[NUM_META_FS_KEYS];
556 VkRenderPass pass[NUM_META_FS_KEYS];
557 } resolve;
558
559 struct {
560 VkDescriptorSetLayout ds_layout;
561 VkPipelineLayout p_layout;
562 struct {
563 VkPipeline pipeline;
564 VkPipeline i_pipeline;
565 VkPipeline srgb_pipeline;
566 } rc[MAX_SAMPLES_LOG2];
567 } resolve_compute;
568
569 struct {
570 VkDescriptorSetLayout ds_layout;
571 VkPipelineLayout p_layout;
572
573 struct {
574 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
575 VkPipeline pipeline[NUM_META_FS_KEYS];
576 } rc[MAX_SAMPLES_LOG2];
577 } resolve_fragment;
578
579 struct {
580 VkPipelineLayout p_layout;
581 VkPipeline decompress_pipeline;
582 VkPipeline resummarize_pipeline;
583 VkRenderPass pass;
584 } depth_decomp[1 + MAX_SAMPLES_LOG2];
585
586 struct {
587 VkPipelineLayout p_layout;
588 VkPipeline cmask_eliminate_pipeline;
589 VkPipeline fmask_decompress_pipeline;
590 VkPipeline dcc_decompress_pipeline;
591 VkRenderPass pass;
592
593 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
594 VkPipelineLayout dcc_decompress_compute_p_layout;
595 VkPipeline dcc_decompress_compute_pipeline;
596 } fast_clear_flush;
597
598 struct {
599 VkPipelineLayout fill_p_layout;
600 VkPipelineLayout copy_p_layout;
601 VkDescriptorSetLayout fill_ds_layout;
602 VkDescriptorSetLayout copy_ds_layout;
603 VkPipeline fill_pipeline;
604 VkPipeline copy_pipeline;
605 } buffer;
606
607 struct {
608 VkDescriptorSetLayout ds_layout;
609 VkPipelineLayout p_layout;
610 VkPipeline occlusion_query_pipeline;
611 VkPipeline pipeline_statistics_query_pipeline;
612 VkPipeline tfb_query_pipeline;
613 } query;
614
615 struct {
616 VkDescriptorSetLayout ds_layout;
617 VkPipelineLayout p_layout;
618 VkPipeline pipeline[MAX_SAMPLES_LOG2];
619 } fmask_expand;
620 };
621
622 /* queue types */
623 #define RADV_QUEUE_GENERAL 0
624 #define RADV_QUEUE_COMPUTE 1
625 #define RADV_QUEUE_TRANSFER 2
626
627 #define RADV_MAX_QUEUE_FAMILIES 3
628
629 enum ring_type radv_queue_family_to_ring(int f);
630
631 struct radv_queue {
632 VK_LOADER_DATA _loader_data;
633 struct radv_device * device;
634 struct radeon_winsys_ctx *hw_ctx;
635 enum radeon_ctx_priority priority;
636 uint32_t queue_family_index;
637 int queue_idx;
638 VkDeviceQueueCreateFlags flags;
639
640 uint32_t scratch_size;
641 uint32_t compute_scratch_size;
642 uint32_t esgs_ring_size;
643 uint32_t gsvs_ring_size;
644 bool has_tess_rings;
645 bool has_sample_positions;
646
647 struct radeon_winsys_bo *scratch_bo;
648 struct radeon_winsys_bo *descriptor_bo;
649 struct radeon_winsys_bo *compute_scratch_bo;
650 struct radeon_winsys_bo *esgs_ring_bo;
651 struct radeon_winsys_bo *gsvs_ring_bo;
652 struct radeon_winsys_bo *tess_rings_bo;
653 struct radeon_cmdbuf *initial_preamble_cs;
654 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
655 struct radeon_cmdbuf *continue_preamble_cs;
656 };
657
658 struct radv_bo_list {
659 struct radv_winsys_bo_list list;
660 unsigned capacity;
661 pthread_mutex_t mutex;
662 };
663
664 struct radv_device {
665 VK_LOADER_DATA _loader_data;
666
667 VkAllocationCallbacks alloc;
668
669 struct radv_instance * instance;
670 struct radeon_winsys *ws;
671
672 struct radv_meta_state meta_state;
673
674 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
675 int queue_count[RADV_MAX_QUEUE_FAMILIES];
676 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
677
678 bool always_use_syncobj;
679 bool has_distributed_tess;
680 bool pbb_allowed;
681 bool dfsm_allowed;
682 uint32_t tess_offchip_block_dw_size;
683 uint32_t scratch_waves;
684 uint32_t dispatch_initiator;
685
686 uint32_t gs_table_depth;
687
688 /* MSAA sample locations.
689 * The first index is the sample index.
690 * The second index is the coordinate: X, Y. */
691 float sample_locations_1x[1][2];
692 float sample_locations_2x[2][2];
693 float sample_locations_4x[4][2];
694 float sample_locations_8x[8][2];
695 float sample_locations_16x[16][2];
696
697 /* CIK and later */
698 uint32_t gfx_init_size_dw;
699 struct radeon_winsys_bo *gfx_init;
700
701 struct radeon_winsys_bo *trace_bo;
702 uint32_t *trace_id_ptr;
703
704 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
705 bool keep_shader_info;
706
707 struct radv_physical_device *physical_device;
708
709 /* Backup in-memory cache to be used if the app doesn't provide one */
710 struct radv_pipeline_cache * mem_cache;
711
712 /*
713 * use different counters so MSAA MRTs get consecutive surface indices,
714 * even if MASK is allocated in between.
715 */
716 uint32_t image_mrt_offset_counter;
717 uint32_t fmask_mrt_offset_counter;
718 struct list_head shader_slabs;
719 mtx_t shader_slab_mutex;
720
721 /* For detecting VM faults reported by dmesg. */
722 uint64_t dmesg_timestamp;
723
724 struct radv_device_extension_table enabled_extensions;
725
726 /* Whether the driver uses a global BO list. */
727 bool use_global_bo_list;
728
729 struct radv_bo_list bo_list;
730
731 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
732 int force_aniso;
733 };
734
735 struct radv_device_memory {
736 struct radeon_winsys_bo *bo;
737 /* for dedicated allocations */
738 struct radv_image *image;
739 struct radv_buffer *buffer;
740 uint32_t type_index;
741 VkDeviceSize map_size;
742 void * map;
743 void * user_ptr;
744 };
745
746
747 struct radv_descriptor_range {
748 uint64_t va;
749 uint32_t size;
750 };
751
752 struct radv_descriptor_set {
753 const struct radv_descriptor_set_layout *layout;
754 uint32_t size;
755
756 struct radeon_winsys_bo *bo;
757 uint64_t va;
758 uint32_t *mapped_ptr;
759 struct radv_descriptor_range *dynamic_descriptors;
760
761 struct radeon_winsys_bo *descriptors[0];
762 };
763
764 struct radv_push_descriptor_set
765 {
766 struct radv_descriptor_set set;
767 uint32_t capacity;
768 };
769
770 struct radv_descriptor_pool_entry {
771 uint32_t offset;
772 uint32_t size;
773 struct radv_descriptor_set *set;
774 };
775
776 struct radv_descriptor_pool {
777 struct radeon_winsys_bo *bo;
778 uint8_t *mapped_ptr;
779 uint64_t current_offset;
780 uint64_t size;
781
782 uint8_t *host_memory_base;
783 uint8_t *host_memory_ptr;
784 uint8_t *host_memory_end;
785
786 uint32_t entry_count;
787 uint32_t max_entry_count;
788 struct radv_descriptor_pool_entry entries[0];
789 };
790
791 struct radv_descriptor_update_template_entry {
792 VkDescriptorType descriptor_type;
793
794 /* The number of descriptors to update */
795 uint32_t descriptor_count;
796
797 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
798 uint32_t dst_offset;
799
800 /* In dwords. Not valid/used for dynamic descriptors */
801 uint32_t dst_stride;
802
803 uint32_t buffer_offset;
804
805 /* Only valid for combined image samplers and samplers */
806 uint16_t has_sampler;
807
808 /* In bytes */
809 size_t src_offset;
810 size_t src_stride;
811
812 /* For push descriptors */
813 const uint32_t *immutable_samplers;
814 };
815
816 struct radv_descriptor_update_template {
817 uint32_t entry_count;
818 VkPipelineBindPoint bind_point;
819 struct radv_descriptor_update_template_entry entry[0];
820 };
821
822 struct radv_buffer {
823 VkDeviceSize size;
824
825 VkBufferUsageFlags usage;
826 VkBufferCreateFlags flags;
827
828 /* Set when bound */
829 struct radeon_winsys_bo * bo;
830 VkDeviceSize offset;
831
832 bool shareable;
833 };
834
835 enum radv_dynamic_state_bits {
836 RADV_DYNAMIC_VIEWPORT = 1 << 0,
837 RADV_DYNAMIC_SCISSOR = 1 << 1,
838 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
839 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
840 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
841 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
842 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
843 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
844 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
845 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
846 RADV_DYNAMIC_ALL = (1 << 10) - 1,
847 };
848
849 enum radv_cmd_dirty_bits {
850 /* Keep the dynamic state dirty bits in sync with
851 * enum radv_dynamic_state_bits */
852 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
853 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
854 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
855 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
856 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
857 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
858 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
859 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
860 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
861 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
862 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
863 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
864 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
865 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
866 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
867 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
868 };
869
870 enum radv_cmd_flush_bits {
871 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
872 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
873 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
874 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
875 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
876 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
877 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
878 /* Same as above, but only writes back and doesn't invalidate */
879 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
880 /* Framebuffer caches */
881 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
882 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
883 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
884 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
885 /* Engine synchronization. */
886 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
887 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
888 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
889 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
890 /* Pipeline query controls. */
891 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
892 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
893 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
894
895 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
896 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
897 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
898 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
899 };
900
901 struct radv_vertex_binding {
902 struct radv_buffer * buffer;
903 VkDeviceSize offset;
904 };
905
906 struct radv_streamout_binding {
907 struct radv_buffer *buffer;
908 VkDeviceSize offset;
909 VkDeviceSize size;
910 };
911
912 struct radv_streamout_state {
913 /* Mask of bound streamout buffers. */
914 uint8_t enabled_mask;
915
916 /* External state that comes from the last vertex stage, it must be
917 * set explicitely when binding a new graphics pipeline.
918 */
919 uint16_t stride_in_dw[MAX_SO_BUFFERS];
920 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
921
922 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
923 uint32_t hw_enabled_mask;
924
925 /* State of VGT_STRMOUT_(CONFIG|EN) */
926 bool streamout_enabled;
927 };
928
929 struct radv_viewport_state {
930 uint32_t count;
931 VkViewport viewports[MAX_VIEWPORTS];
932 };
933
934 struct radv_scissor_state {
935 uint32_t count;
936 VkRect2D scissors[MAX_SCISSORS];
937 };
938
939 struct radv_discard_rectangle_state {
940 uint32_t count;
941 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
942 };
943
944 struct radv_dynamic_state {
945 /**
946 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
947 * Defines the set of saved dynamic state.
948 */
949 uint32_t mask;
950
951 struct radv_viewport_state viewport;
952
953 struct radv_scissor_state scissor;
954
955 float line_width;
956
957 struct {
958 float bias;
959 float clamp;
960 float slope;
961 } depth_bias;
962
963 float blend_constants[4];
964
965 struct {
966 float min;
967 float max;
968 } depth_bounds;
969
970 struct {
971 uint32_t front;
972 uint32_t back;
973 } stencil_compare_mask;
974
975 struct {
976 uint32_t front;
977 uint32_t back;
978 } stencil_write_mask;
979
980 struct {
981 uint32_t front;
982 uint32_t back;
983 } stencil_reference;
984
985 struct radv_discard_rectangle_state discard_rectangle;
986 };
987
988 extern const struct radv_dynamic_state default_dynamic_state;
989
990 const char *
991 radv_get_debug_option_name(int id);
992
993 const char *
994 radv_get_perftest_option_name(int id);
995
996 /**
997 * Attachment state when recording a renderpass instance.
998 *
999 * The clear value is valid only if there exists a pending clear.
1000 */
1001 struct radv_attachment_state {
1002 VkImageAspectFlags pending_clear_aspects;
1003 uint32_t cleared_views;
1004 VkClearValue clear_value;
1005 VkImageLayout current_layout;
1006 };
1007
1008 struct radv_descriptor_state {
1009 struct radv_descriptor_set *sets[MAX_SETS];
1010 uint32_t dirty;
1011 uint32_t valid;
1012 struct radv_push_descriptor_set push_set;
1013 bool push_dirty;
1014 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1015 };
1016
1017 struct radv_cmd_state {
1018 /* Vertex descriptors */
1019 uint64_t vb_va;
1020 unsigned vb_size;
1021
1022 bool predicating;
1023 uint32_t dirty;
1024
1025 uint32_t prefetch_L2_mask;
1026
1027 struct radv_pipeline * pipeline;
1028 struct radv_pipeline * emitted_pipeline;
1029 struct radv_pipeline * compute_pipeline;
1030 struct radv_pipeline * emitted_compute_pipeline;
1031 struct radv_framebuffer * framebuffer;
1032 struct radv_render_pass * pass;
1033 const struct radv_subpass * subpass;
1034 struct radv_dynamic_state dynamic;
1035 struct radv_attachment_state * attachments;
1036 struct radv_streamout_state streamout;
1037 VkRect2D render_area;
1038
1039 /* Index buffer */
1040 struct radv_buffer *index_buffer;
1041 uint64_t index_offset;
1042 uint32_t index_type;
1043 uint32_t max_index_count;
1044 uint64_t index_va;
1045 int32_t last_index_type;
1046
1047 int32_t last_primitive_reset_en;
1048 uint32_t last_primitive_reset_index;
1049 enum radv_cmd_flush_bits flush_bits;
1050 unsigned active_occlusion_queries;
1051 bool perfect_occlusion_queries_enabled;
1052 unsigned active_pipeline_queries;
1053 float offset_scale;
1054 uint32_t trace_id;
1055 uint32_t last_ia_multi_vgt_param;
1056
1057 uint32_t last_num_instances;
1058 uint32_t last_first_instance;
1059 uint32_t last_vertex_offset;
1060
1061 /* Whether CP DMA is busy/idle. */
1062 bool dma_is_busy;
1063
1064 /* Conditional rendering info. */
1065 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1066 uint64_t predication_va;
1067
1068 bool context_roll_without_scissor_emitted;
1069 };
1070
1071 struct radv_cmd_pool {
1072 VkAllocationCallbacks alloc;
1073 struct list_head cmd_buffers;
1074 struct list_head free_cmd_buffers;
1075 uint32_t queue_family_index;
1076 };
1077
1078 struct radv_cmd_buffer_upload {
1079 uint8_t *map;
1080 unsigned offset;
1081 uint64_t size;
1082 struct radeon_winsys_bo *upload_bo;
1083 struct list_head list;
1084 };
1085
1086 enum radv_cmd_buffer_status {
1087 RADV_CMD_BUFFER_STATUS_INVALID,
1088 RADV_CMD_BUFFER_STATUS_INITIAL,
1089 RADV_CMD_BUFFER_STATUS_RECORDING,
1090 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1091 RADV_CMD_BUFFER_STATUS_PENDING,
1092 };
1093
1094 struct radv_cmd_buffer {
1095 VK_LOADER_DATA _loader_data;
1096
1097 struct radv_device * device;
1098
1099 struct radv_cmd_pool * pool;
1100 struct list_head pool_link;
1101
1102 VkCommandBufferUsageFlags usage_flags;
1103 VkCommandBufferLevel level;
1104 enum radv_cmd_buffer_status status;
1105 struct radeon_cmdbuf *cs;
1106 struct radv_cmd_state state;
1107 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1108 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1109 uint32_t queue_family_index;
1110
1111 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1112 VkShaderStageFlags push_constant_stages;
1113 struct radv_descriptor_set meta_push_descriptors;
1114
1115 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1116
1117 struct radv_cmd_buffer_upload upload;
1118
1119 uint32_t scratch_size_needed;
1120 uint32_t compute_scratch_size_needed;
1121 uint32_t esgs_ring_size_needed;
1122 uint32_t gsvs_ring_size_needed;
1123 bool tess_rings_needed;
1124 bool sample_positions_needed;
1125
1126 VkResult record_result;
1127
1128 uint64_t gfx9_fence_va;
1129 uint32_t gfx9_fence_idx;
1130 uint64_t gfx9_eop_bug_va;
1131
1132 /**
1133 * Whether a query pool has been resetted and we have to flush caches.
1134 */
1135 bool pending_reset_query;
1136 };
1137
1138 struct radv_image;
1139
1140 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1141
1142 void si_emit_graphics(struct radv_physical_device *physical_device,
1143 struct radeon_cmdbuf *cs);
1144 void si_emit_compute(struct radv_physical_device *physical_device,
1145 struct radeon_cmdbuf *cs);
1146
1147 void cik_create_gfx_config(struct radv_device *device);
1148
1149 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1150 int count, const VkViewport *viewports);
1151 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1152 int count, const VkRect2D *scissors,
1153 const VkViewport *viewports, bool can_use_guardband);
1154 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1155 bool instanced_draw, bool indirect_draw,
1156 uint32_t draw_vertex_count);
1157 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1158 enum chip_class chip_class,
1159 bool is_mec,
1160 unsigned event, unsigned event_flags,
1161 unsigned data_sel,
1162 uint64_t va,
1163 uint32_t new_fence,
1164 uint64_t gfx9_eop_bug_va);
1165
1166 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1167 uint32_t ref, uint32_t mask);
1168 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1169 enum chip_class chip_class,
1170 uint32_t *fence_ptr, uint64_t va,
1171 bool is_mec,
1172 enum radv_cmd_flush_bits flush_bits,
1173 uint64_t gfx9_eop_bug_va);
1174 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1175 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1176 bool inverted, uint64_t va);
1177 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1178 uint64_t src_va, uint64_t dest_va,
1179 uint64_t size);
1180 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1181 unsigned size);
1182 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1183 uint64_t size, unsigned value);
1184 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1185
1186 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1187 bool
1188 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1189 unsigned size,
1190 unsigned alignment,
1191 unsigned *out_offset,
1192 void **ptr);
1193 void
1194 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1195 const struct radv_subpass *subpass);
1196 bool
1197 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1198 unsigned size, unsigned alignmnet,
1199 const void *data, unsigned *out_offset);
1200
1201 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1202 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1203 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1204 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1205 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1206 unsigned radv_cayman_get_maxdist(int log_samples);
1207 void radv_device_init_msaa(struct radv_device *device);
1208
1209 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1210 struct radv_image *image,
1211 VkClearDepthStencilValue ds_clear_value,
1212 VkImageAspectFlags aspects);
1213
1214 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1215 struct radv_image *image,
1216 int cb_idx,
1217 uint32_t color_values[2]);
1218
1219 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1220 struct radv_image *image, bool value);
1221
1222 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1223 struct radv_image *image, bool value);
1224
1225 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1226 struct radeon_winsys_bo *bo,
1227 uint64_t offset, uint64_t size, uint32_t value);
1228 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1229 bool radv_get_memory_fd(struct radv_device *device,
1230 struct radv_device_memory *memory,
1231 int *pFD);
1232
1233 static inline void
1234 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1235 unsigned sh_offset, unsigned pointer_count,
1236 bool use_32bit_pointers)
1237 {
1238 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1239 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1240 }
1241
1242 static inline void
1243 radv_emit_shader_pointer_body(struct radv_device *device,
1244 struct radeon_cmdbuf *cs,
1245 uint64_t va, bool use_32bit_pointers)
1246 {
1247 radeon_emit(cs, va);
1248
1249 if (use_32bit_pointers) {
1250 assert(va == 0 ||
1251 (va >> 32) == device->physical_device->rad_info.address32_hi);
1252 } else {
1253 radeon_emit(cs, va >> 32);
1254 }
1255 }
1256
1257 static inline void
1258 radv_emit_shader_pointer(struct radv_device *device,
1259 struct radeon_cmdbuf *cs,
1260 uint32_t sh_offset, uint64_t va, bool global)
1261 {
1262 bool use_32bit_pointers = !global;
1263
1264 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1265 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1266 }
1267
1268 static inline struct radv_descriptor_state *
1269 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1270 VkPipelineBindPoint bind_point)
1271 {
1272 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1273 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1274 return &cmd_buffer->descriptors[bind_point];
1275 }
1276
1277 /*
1278 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1279 *
1280 * Limitations: Can't call normal dispatch functions without binding or rebinding
1281 * the compute pipeline.
1282 */
1283 void radv_unaligned_dispatch(
1284 struct radv_cmd_buffer *cmd_buffer,
1285 uint32_t x,
1286 uint32_t y,
1287 uint32_t z);
1288
1289 struct radv_event {
1290 struct radeon_winsys_bo *bo;
1291 uint64_t *map;
1292 };
1293
1294 struct radv_shader_module;
1295
1296 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1297 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1298 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1299 void
1300 radv_hash_shaders(unsigned char *hash,
1301 const VkPipelineShaderStageCreateInfo **stages,
1302 const struct radv_pipeline_layout *layout,
1303 const struct radv_pipeline_key *key,
1304 uint32_t flags);
1305
1306 static inline gl_shader_stage
1307 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1308 {
1309 assert(__builtin_popcount(vk_stage) == 1);
1310 return ffs(vk_stage) - 1;
1311 }
1312
1313 static inline VkShaderStageFlagBits
1314 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1315 {
1316 return (1 << mesa_stage);
1317 }
1318
1319 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1320
1321 #define radv_foreach_stage(stage, stage_bits) \
1322 for (gl_shader_stage stage, \
1323 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1324 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1325 __tmp &= ~(1 << (stage)))
1326
1327 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1328 unsigned radv_format_meta_fs_key(VkFormat format);
1329
1330 struct radv_multisample_state {
1331 uint32_t db_eqaa;
1332 uint32_t pa_sc_line_cntl;
1333 uint32_t pa_sc_mode_cntl_0;
1334 uint32_t pa_sc_mode_cntl_1;
1335 uint32_t pa_sc_aa_config;
1336 uint32_t pa_sc_aa_mask[2];
1337 unsigned num_samples;
1338 };
1339
1340 struct radv_prim_vertex_count {
1341 uint8_t min;
1342 uint8_t incr;
1343 };
1344
1345 struct radv_vertex_elements_info {
1346 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1347 };
1348
1349 struct radv_ia_multi_vgt_param_helpers {
1350 uint32_t base;
1351 bool partial_es_wave;
1352 uint8_t primgroup_size;
1353 bool wd_switch_on_eop;
1354 bool ia_switch_on_eoi;
1355 bool partial_vs_wave;
1356 };
1357
1358 #define SI_GS_PER_ES 128
1359
1360 struct radv_pipeline {
1361 struct radv_device * device;
1362 struct radv_dynamic_state dynamic_state;
1363
1364 struct radv_pipeline_layout * layout;
1365
1366 bool need_indirect_descriptor_sets;
1367 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1368 struct radv_shader_variant *gs_copy_shader;
1369 VkShaderStageFlags active_stages;
1370
1371 struct radeon_cmdbuf cs;
1372 uint32_t ctx_cs_hash;
1373 struct radeon_cmdbuf ctx_cs;
1374
1375 struct radv_vertex_elements_info vertex_elements;
1376
1377 uint32_t binding_stride[MAX_VBS];
1378 uint8_t num_vertex_bindings;
1379
1380 uint32_t user_data_0[MESA_SHADER_STAGES];
1381 union {
1382 struct {
1383 struct radv_multisample_state ms;
1384 uint32_t spi_baryc_cntl;
1385 bool prim_restart_enable;
1386 unsigned esgs_ring_size;
1387 unsigned gsvs_ring_size;
1388 uint32_t vtx_base_sgpr;
1389 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1390 uint8_t vtx_emit_num;
1391 struct radv_prim_vertex_count prim_vertex_count;
1392 bool can_use_guardband;
1393 uint32_t needed_dynamic_state;
1394 bool disable_out_of_order_rast_for_occlusion;
1395
1396 /* Used for rbplus */
1397 uint32_t col_format;
1398 uint32_t cb_target_mask;
1399 } graphics;
1400 };
1401
1402 unsigned max_waves;
1403 unsigned scratch_bytes_per_wave;
1404
1405 /* Not NULL if graphics pipeline uses streamout. */
1406 struct radv_shader_variant *streamout_shader;
1407 };
1408
1409 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1410 {
1411 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1412 }
1413
1414 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1415 {
1416 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1417 }
1418
1419 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1420 gl_shader_stage stage,
1421 int idx);
1422
1423 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1424 gl_shader_stage stage);
1425
1426 struct radv_graphics_pipeline_create_info {
1427 bool use_rectlist;
1428 bool db_depth_clear;
1429 bool db_stencil_clear;
1430 bool db_depth_disable_expclear;
1431 bool db_stencil_disable_expclear;
1432 bool db_flush_depth_inplace;
1433 bool db_flush_stencil_inplace;
1434 bool db_resummarize;
1435 uint32_t custom_blend_mode;
1436 };
1437
1438 VkResult
1439 radv_graphics_pipeline_create(VkDevice device,
1440 VkPipelineCache cache,
1441 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1442 const struct radv_graphics_pipeline_create_info *extra,
1443 const VkAllocationCallbacks *alloc,
1444 VkPipeline *pPipeline);
1445
1446 struct vk_format_description;
1447 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1448 int first_non_void);
1449 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1450 int first_non_void);
1451 uint32_t radv_translate_colorformat(VkFormat format);
1452 uint32_t radv_translate_color_numformat(VkFormat format,
1453 const struct vk_format_description *desc,
1454 int first_non_void);
1455 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1456 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1457 uint32_t radv_translate_dbformat(VkFormat format);
1458 uint32_t radv_translate_tex_dataformat(VkFormat format,
1459 const struct vk_format_description *desc,
1460 int first_non_void);
1461 uint32_t radv_translate_tex_numformat(VkFormat format,
1462 const struct vk_format_description *desc,
1463 int first_non_void);
1464 bool radv_format_pack_clear_color(VkFormat format,
1465 uint32_t clear_vals[2],
1466 VkClearColorValue *value);
1467 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1468 bool radv_dcc_formats_compatible(VkFormat format1,
1469 VkFormat format2);
1470 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1471
1472 struct radv_fmask_info {
1473 uint64_t offset;
1474 uint64_t size;
1475 unsigned alignment;
1476 unsigned pitch_in_pixels;
1477 unsigned bank_height;
1478 unsigned slice_tile_max;
1479 unsigned tile_mode_index;
1480 unsigned tile_swizzle;
1481 };
1482
1483 struct radv_cmask_info {
1484 uint64_t offset;
1485 uint64_t size;
1486 unsigned alignment;
1487 unsigned slice_tile_max;
1488 };
1489
1490 struct radv_image {
1491 VkImageType type;
1492 /* The original VkFormat provided by the client. This may not match any
1493 * of the actual surface formats.
1494 */
1495 VkFormat vk_format;
1496 VkImageAspectFlags aspects;
1497 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1498 struct ac_surf_info info;
1499 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1500 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1501
1502 VkDeviceSize size;
1503 uint32_t alignment;
1504
1505 unsigned queue_family_mask;
1506 bool exclusive;
1507 bool shareable;
1508
1509 /* Set when bound */
1510 struct radeon_winsys_bo *bo;
1511 VkDeviceSize offset;
1512 uint64_t dcc_offset;
1513 uint64_t htile_offset;
1514 bool tc_compatible_htile;
1515 struct radeon_surf surface;
1516
1517 struct radv_fmask_info fmask;
1518 struct radv_cmask_info cmask;
1519 uint64_t clear_value_offset;
1520 uint64_t fce_pred_offset;
1521 uint64_t dcc_pred_offset;
1522
1523 /*
1524 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1525 * stored at this offset is UINT_MAX, the driver will emit
1526 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1527 * SET_CONTEXT_REG packet.
1528 */
1529 uint64_t tc_compat_zrange_offset;
1530
1531 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1532 VkDeviceMemory owned_memory;
1533 };
1534
1535 /* Whether the image has a htile that is known consistent with the contents of
1536 * the image. */
1537 bool radv_layout_has_htile(const struct radv_image *image,
1538 VkImageLayout layout,
1539 unsigned queue_mask);
1540
1541 /* Whether the image has a htile that is known consistent with the contents of
1542 * the image and is allowed to be in compressed form.
1543 *
1544 * If this is false reads that don't use the htile should be able to return
1545 * correct results.
1546 */
1547 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1548 VkImageLayout layout,
1549 unsigned queue_mask);
1550
1551 bool radv_layout_can_fast_clear(const struct radv_image *image,
1552 VkImageLayout layout,
1553 unsigned queue_mask);
1554
1555 bool radv_layout_dcc_compressed(const struct radv_image *image,
1556 VkImageLayout layout,
1557 unsigned queue_mask);
1558
1559 /**
1560 * Return whether the image has CMASK metadata for color surfaces.
1561 */
1562 static inline bool
1563 radv_image_has_cmask(const struct radv_image *image)
1564 {
1565 return image->cmask.size;
1566 }
1567
1568 /**
1569 * Return whether the image has FMASK metadata for color surfaces.
1570 */
1571 static inline bool
1572 radv_image_has_fmask(const struct radv_image *image)
1573 {
1574 return image->fmask.size;
1575 }
1576
1577 /**
1578 * Return whether the image has DCC metadata for color surfaces.
1579 */
1580 static inline bool
1581 radv_image_has_dcc(const struct radv_image *image)
1582 {
1583 return image->surface.dcc_size;
1584 }
1585
1586 /**
1587 * Return whether DCC metadata is enabled for a level.
1588 */
1589 static inline bool
1590 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1591 {
1592 return radv_image_has_dcc(image) &&
1593 level < image->surface.num_dcc_levels;
1594 }
1595
1596 /**
1597 * Return whether the image has CB metadata.
1598 */
1599 static inline bool
1600 radv_image_has_CB_metadata(const struct radv_image *image)
1601 {
1602 return radv_image_has_cmask(image) ||
1603 radv_image_has_fmask(image) ||
1604 radv_image_has_dcc(image);
1605 }
1606
1607 /**
1608 * Return whether the image has HTILE metadata for depth surfaces.
1609 */
1610 static inline bool
1611 radv_image_has_htile(const struct radv_image *image)
1612 {
1613 return image->surface.htile_size;
1614 }
1615
1616 /**
1617 * Return whether HTILE metadata is enabled for a level.
1618 */
1619 static inline bool
1620 radv_htile_enabled(const struct radv_image *image, unsigned level)
1621 {
1622 return radv_image_has_htile(image) && level == 0;
1623 }
1624
1625 /**
1626 * Return whether the image is TC-compatible HTILE.
1627 */
1628 static inline bool
1629 radv_image_is_tc_compat_htile(const struct radv_image *image)
1630 {
1631 return radv_image_has_htile(image) && image->tc_compatible_htile;
1632 }
1633
1634 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1635
1636 static inline uint32_t
1637 radv_get_layerCount(const struct radv_image *image,
1638 const VkImageSubresourceRange *range)
1639 {
1640 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1641 image->info.array_size - range->baseArrayLayer : range->layerCount;
1642 }
1643
1644 static inline uint32_t
1645 radv_get_levelCount(const struct radv_image *image,
1646 const VkImageSubresourceRange *range)
1647 {
1648 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1649 image->info.levels - range->baseMipLevel : range->levelCount;
1650 }
1651
1652 struct radeon_bo_metadata;
1653 void
1654 radv_init_metadata(struct radv_device *device,
1655 struct radv_image *image,
1656 struct radeon_bo_metadata *metadata);
1657
1658 struct radv_image_view {
1659 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1660 struct radeon_winsys_bo *bo;
1661
1662 VkImageViewType type;
1663 VkImageAspectFlags aspect_mask;
1664 VkFormat vk_format;
1665 uint32_t base_layer;
1666 uint32_t layer_count;
1667 uint32_t base_mip;
1668 uint32_t level_count;
1669 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1670
1671 uint32_t descriptor[16];
1672
1673 /* Descriptor for use as a storage image as opposed to a sampled image.
1674 * This has a few differences for cube maps (e.g. type).
1675 */
1676 uint32_t storage_descriptor[16];
1677 };
1678
1679 struct radv_image_create_info {
1680 const VkImageCreateInfo *vk_info;
1681 bool scanout;
1682 bool no_metadata_planes;
1683 };
1684
1685 VkResult radv_image_create(VkDevice _device,
1686 const struct radv_image_create_info *info,
1687 const VkAllocationCallbacks* alloc,
1688 VkImage *pImage);
1689
1690 VkResult
1691 radv_image_from_gralloc(VkDevice device_h,
1692 const VkImageCreateInfo *base_info,
1693 const VkNativeBufferANDROID *gralloc_info,
1694 const VkAllocationCallbacks *alloc,
1695 VkImage *out_image_h);
1696
1697 void radv_image_view_init(struct radv_image_view *view,
1698 struct radv_device *device,
1699 const VkImageViewCreateInfo* pCreateInfo);
1700
1701 struct radv_buffer_view {
1702 struct radeon_winsys_bo *bo;
1703 VkFormat vk_format;
1704 uint64_t range; /**< VkBufferViewCreateInfo::range */
1705 uint32_t state[4];
1706 };
1707 void radv_buffer_view_init(struct radv_buffer_view *view,
1708 struct radv_device *device,
1709 const VkBufferViewCreateInfo* pCreateInfo);
1710
1711 static inline struct VkExtent3D
1712 radv_sanitize_image_extent(const VkImageType imageType,
1713 const struct VkExtent3D imageExtent)
1714 {
1715 switch (imageType) {
1716 case VK_IMAGE_TYPE_1D:
1717 return (VkExtent3D) { imageExtent.width, 1, 1 };
1718 case VK_IMAGE_TYPE_2D:
1719 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1720 case VK_IMAGE_TYPE_3D:
1721 return imageExtent;
1722 default:
1723 unreachable("invalid image type");
1724 }
1725 }
1726
1727 static inline struct VkOffset3D
1728 radv_sanitize_image_offset(const VkImageType imageType,
1729 const struct VkOffset3D imageOffset)
1730 {
1731 switch (imageType) {
1732 case VK_IMAGE_TYPE_1D:
1733 return (VkOffset3D) { imageOffset.x, 0, 0 };
1734 case VK_IMAGE_TYPE_2D:
1735 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1736 case VK_IMAGE_TYPE_3D:
1737 return imageOffset;
1738 default:
1739 unreachable("invalid image type");
1740 }
1741 }
1742
1743 static inline bool
1744 radv_image_extent_compare(const struct radv_image *image,
1745 const VkExtent3D *extent)
1746 {
1747 if (extent->width != image->info.width ||
1748 extent->height != image->info.height ||
1749 extent->depth != image->info.depth)
1750 return false;
1751 return true;
1752 }
1753
1754 struct radv_sampler {
1755 uint32_t state[4];
1756 };
1757
1758 struct radv_color_buffer_info {
1759 uint64_t cb_color_base;
1760 uint64_t cb_color_cmask;
1761 uint64_t cb_color_fmask;
1762 uint64_t cb_dcc_base;
1763 uint32_t cb_color_pitch;
1764 uint32_t cb_color_slice;
1765 uint32_t cb_color_view;
1766 uint32_t cb_color_info;
1767 uint32_t cb_color_attrib;
1768 uint32_t cb_color_attrib2;
1769 uint32_t cb_dcc_control;
1770 uint32_t cb_color_cmask_slice;
1771 uint32_t cb_color_fmask_slice;
1772 };
1773
1774 struct radv_ds_buffer_info {
1775 uint64_t db_z_read_base;
1776 uint64_t db_stencil_read_base;
1777 uint64_t db_z_write_base;
1778 uint64_t db_stencil_write_base;
1779 uint64_t db_htile_data_base;
1780 uint32_t db_depth_info;
1781 uint32_t db_z_info;
1782 uint32_t db_stencil_info;
1783 uint32_t db_depth_view;
1784 uint32_t db_depth_size;
1785 uint32_t db_depth_slice;
1786 uint32_t db_htile_surface;
1787 uint32_t pa_su_poly_offset_db_fmt_cntl;
1788 uint32_t db_z_info2;
1789 uint32_t db_stencil_info2;
1790 float offset_scale;
1791 };
1792
1793 struct radv_attachment_info {
1794 union {
1795 struct radv_color_buffer_info cb;
1796 struct radv_ds_buffer_info ds;
1797 };
1798 struct radv_image_view *attachment;
1799 };
1800
1801 struct radv_framebuffer {
1802 uint32_t width;
1803 uint32_t height;
1804 uint32_t layers;
1805
1806 uint32_t attachment_count;
1807 struct radv_attachment_info attachments[0];
1808 };
1809
1810 struct radv_subpass_barrier {
1811 VkPipelineStageFlags src_stage_mask;
1812 VkAccessFlags src_access_mask;
1813 VkAccessFlags dst_access_mask;
1814 };
1815
1816 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1817 const struct radv_subpass_barrier *barrier);
1818
1819 struct radv_subpass_attachment {
1820 uint32_t attachment;
1821 VkImageLayout layout;
1822 };
1823
1824 struct radv_subpass {
1825 uint32_t attachment_count;
1826 struct radv_subpass_attachment * attachments;
1827
1828 uint32_t input_count;
1829 uint32_t color_count;
1830 struct radv_subpass_attachment * input_attachments;
1831 struct radv_subpass_attachment * color_attachments;
1832 struct radv_subpass_attachment * resolve_attachments;
1833 struct radv_subpass_attachment * depth_stencil_attachment;
1834
1835 /** Subpass has at least one resolve attachment */
1836 bool has_resolve;
1837
1838 /** Subpass has at least one color attachment */
1839 bool has_color_att;
1840
1841 struct radv_subpass_barrier start_barrier;
1842
1843 uint32_t view_mask;
1844 VkSampleCountFlagBits max_sample_count;
1845 };
1846
1847 struct radv_render_pass_attachment {
1848 VkFormat format;
1849 uint32_t samples;
1850 VkAttachmentLoadOp load_op;
1851 VkAttachmentLoadOp stencil_load_op;
1852 VkImageLayout initial_layout;
1853 VkImageLayout final_layout;
1854
1855 /* The subpass id in which the attachment will be used last. */
1856 uint32_t last_subpass_idx;
1857 };
1858
1859 struct radv_render_pass {
1860 uint32_t attachment_count;
1861 uint32_t subpass_count;
1862 struct radv_subpass_attachment * subpass_attachments;
1863 struct radv_render_pass_attachment * attachments;
1864 struct radv_subpass_barrier end_barrier;
1865 struct radv_subpass subpasses[0];
1866 };
1867
1868 VkResult radv_device_init_meta(struct radv_device *device);
1869 void radv_device_finish_meta(struct radv_device *device);
1870
1871 struct radv_query_pool {
1872 struct radeon_winsys_bo *bo;
1873 uint32_t stride;
1874 uint32_t availability_offset;
1875 uint64_t size;
1876 char *ptr;
1877 VkQueryType type;
1878 uint32_t pipeline_stats_mask;
1879 };
1880
1881 struct radv_semaphore {
1882 /* use a winsys sem for non-exportable */
1883 struct radeon_winsys_sem *sem;
1884 uint32_t syncobj;
1885 uint32_t temp_syncobj;
1886 };
1887
1888 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1889 VkPipelineBindPoint bind_point,
1890 struct radv_descriptor_set *set,
1891 unsigned idx);
1892
1893 void
1894 radv_update_descriptor_sets(struct radv_device *device,
1895 struct radv_cmd_buffer *cmd_buffer,
1896 VkDescriptorSet overrideSet,
1897 uint32_t descriptorWriteCount,
1898 const VkWriteDescriptorSet *pDescriptorWrites,
1899 uint32_t descriptorCopyCount,
1900 const VkCopyDescriptorSet *pDescriptorCopies);
1901
1902 void
1903 radv_update_descriptor_set_with_template(struct radv_device *device,
1904 struct radv_cmd_buffer *cmd_buffer,
1905 struct radv_descriptor_set *set,
1906 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1907 const void *pData);
1908
1909 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1910 VkPipelineBindPoint pipelineBindPoint,
1911 VkPipelineLayout _layout,
1912 uint32_t set,
1913 uint32_t descriptorWriteCount,
1914 const VkWriteDescriptorSet *pDescriptorWrites);
1915
1916 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1917 struct radv_image *image, uint32_t value);
1918
1919 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
1920 struct radv_image *image);
1921
1922 struct radv_fence {
1923 struct radeon_winsys_fence *fence;
1924 struct wsi_fence *fence_wsi;
1925 bool submitted;
1926 bool signalled;
1927
1928 uint32_t syncobj;
1929 uint32_t temp_syncobj;
1930 };
1931
1932 /* radv_nir_to_llvm.c */
1933 struct radv_shader_variant_info;
1934 struct radv_nir_compiler_options;
1935
1936 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1937 struct nir_shader *geom_shader,
1938 struct ac_shader_binary *binary,
1939 struct ac_shader_config *config,
1940 struct radv_shader_variant_info *shader_info,
1941 const struct radv_nir_compiler_options *option);
1942
1943 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1944 struct ac_shader_binary *binary,
1945 struct ac_shader_config *config,
1946 struct radv_shader_variant_info *shader_info,
1947 struct nir_shader *const *nir,
1948 int nir_count,
1949 const struct radv_nir_compiler_options *options);
1950
1951 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
1952 const struct nir_shader *nir);
1953
1954 /* radv_shader_info.h */
1955 struct radv_shader_info;
1956
1957 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1958 const struct radv_nir_compiler_options *options,
1959 struct radv_shader_info *info);
1960
1961 void radv_nir_shader_info_init(struct radv_shader_info *info);
1962
1963 struct radeon_winsys_sem;
1964
1965 uint64_t radv_get_current_time(void);
1966
1967 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1968 \
1969 static inline struct __radv_type * \
1970 __radv_type ## _from_handle(__VkType _handle) \
1971 { \
1972 return (struct __radv_type *) _handle; \
1973 } \
1974 \
1975 static inline __VkType \
1976 __radv_type ## _to_handle(struct __radv_type *_obj) \
1977 { \
1978 return (__VkType) _obj; \
1979 }
1980
1981 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1982 \
1983 static inline struct __radv_type * \
1984 __radv_type ## _from_handle(__VkType _handle) \
1985 { \
1986 return (struct __radv_type *)(uintptr_t) _handle; \
1987 } \
1988 \
1989 static inline __VkType \
1990 __radv_type ## _to_handle(struct __radv_type *_obj) \
1991 { \
1992 return (__VkType)(uintptr_t) _obj; \
1993 }
1994
1995 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1996 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1997
1998 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1999 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2000 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2001 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2002 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2003
2004 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2005 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2006 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2007 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2008 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2009 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2010 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2011 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2012 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2013 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2014 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2015 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2016 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2017 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2018 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2019 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2020 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2021 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2022 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2023 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2024 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2025
2026 #endif /* RADV_PRIVATE_H */