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radv: Don't expose heaps with 0 memory.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 enum radv_mem_flags_bits {
110 /* enable implicit synchronization when accessing the underlying bo */
111 RADV_MEM_IMPLICIT_SYNC = 1 << 0,
112 };
113
114 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115
116 static inline uint32_t
117 align_u32(uint32_t v, uint32_t a)
118 {
119 assert(a != 0 && a == (a & -a));
120 return (v + a - 1) & ~(a - 1);
121 }
122
123 static inline uint32_t
124 align_u32_npot(uint32_t v, uint32_t a)
125 {
126 return (v + a - 1) / a * a;
127 }
128
129 static inline uint64_t
130 align_u64(uint64_t v, uint64_t a)
131 {
132 assert(a != 0 && a == (a & -a));
133 return (v + a - 1) & ~(a - 1);
134 }
135
136 static inline int32_t
137 align_i32(int32_t v, int32_t a)
138 {
139 assert(a != 0 && a == (a & -a));
140 return (v + a - 1) & ~(a - 1);
141 }
142
143 /** Alignment must be a power of 2. */
144 static inline bool
145 radv_is_aligned(uintmax_t n, uintmax_t a)
146 {
147 assert(a == (a & -a));
148 return (n & (a - 1)) == 0;
149 }
150
151 static inline uint32_t
152 round_up_u32(uint32_t v, uint32_t a)
153 {
154 return (v + a - 1) / a;
155 }
156
157 static inline uint64_t
158 round_up_u64(uint64_t v, uint64_t a)
159 {
160 return (v + a - 1) / a;
161 }
162
163 static inline uint32_t
164 radv_minify(uint32_t n, uint32_t levels)
165 {
166 if (unlikely(n == 0))
167 return 0;
168 else
169 return MAX2(n >> levels, 1);
170 }
171 static inline float
172 radv_clamp_f(float f, float min, float max)
173 {
174 assert(min < max);
175
176 if (f > max)
177 return max;
178 else if (f < min)
179 return min;
180 else
181 return f;
182 }
183
184 static inline bool
185 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
186 {
187 if (*inout_mask & clear_mask) {
188 *inout_mask &= ~clear_mask;
189 return true;
190 } else {
191 return false;
192 }
193 }
194
195 #define for_each_bit(b, dword) \
196 for (uint32_t __dword = (dword); \
197 (b) = __builtin_ffs(__dword) - 1, __dword; \
198 __dword &= ~(1 << (b)))
199
200 #define typed_memcpy(dest, src, count) ({ \
201 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
202 memcpy((dest), (src), (count) * sizeof(*(src))); \
203 })
204
205 /* Whenever we generate an error, pass it through this function. Useful for
206 * debugging, where we can break on it. Only call at error site, not when
207 * propagating errors. Might be useful to plug in a stack trace here.
208 */
209
210 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
211
212 #ifdef DEBUG
213 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215 #else
216 #define vk_error(error) error
217 #define vk_errorf(error, format, ...) error
218 #endif
219
220 void __radv_finishme(const char *file, int line, const char *format, ...)
221 radv_printflike(3, 4);
222 void radv_loge(const char *format, ...) radv_printflike(1, 2);
223 void radv_loge_v(const char *format, va_list va);
224
225 /**
226 * Print a FINISHME message, including its source location.
227 */
228 #define radv_finishme(format, ...) \
229 do { \
230 static bool reported = false; \
231 if (!reported) { \
232 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
233 reported = true; \
234 } \
235 } while (0)
236
237 /* A non-fatal assert. Useful for debugging. */
238 #ifdef DEBUG
239 #define radv_assert(x) ({ \
240 if (unlikely(!(x))) \
241 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
242 })
243 #else
244 #define radv_assert(x)
245 #endif
246
247 #define stub_return(v) \
248 do { \
249 radv_finishme("stub %s", __func__); \
250 return (v); \
251 } while (0)
252
253 #define stub() \
254 do { \
255 radv_finishme("stub %s", __func__); \
256 return; \
257 } while (0)
258
259 void *radv_lookup_entrypoint(const char *name);
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 struct radv_instance * instance;
265
266 struct radeon_winsys *ws;
267 struct radeon_info rad_info;
268 char path[20];
269 const char * name;
270 uint8_t driver_uuid[VK_UUID_SIZE];
271 uint8_t device_uuid[VK_UUID_SIZE];
272 uint8_t cache_uuid[VK_UUID_SIZE];
273
274 int local_fd;
275 struct wsi_device wsi_device;
276
277 bool has_rbplus; /* if RB+ register exist */
278 bool rbplus_allowed; /* if RB+ is allowed */
279 bool has_clear_state;
280
281 /* This is the drivers on-disk cache used as a fallback as opposed to
282 * the pipeline cache defined by apps.
283 */
284 struct disk_cache * disk_cache;
285
286 VkPhysicalDeviceMemoryProperties memory_properties;
287 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
288 };
289
290 struct radv_instance {
291 VK_LOADER_DATA _loader_data;
292
293 VkAllocationCallbacks alloc;
294
295 uint32_t apiVersion;
296 int physicalDeviceCount;
297 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
298
299 uint64_t debug_flags;
300 uint64_t perftest_flags;
301 };
302
303 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
304 void radv_finish_wsi(struct radv_physical_device *physical_device);
305
306 bool radv_instance_extension_supported(const char *name);
307 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
308 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
309 const char *name);
310
311 struct cache_entry;
312
313 struct radv_pipeline_cache {
314 struct radv_device * device;
315 pthread_mutex_t mutex;
316
317 uint32_t total_size;
318 uint32_t table_size;
319 uint32_t kernel_count;
320 struct cache_entry ** hash_table;
321 bool modified;
322
323 VkAllocationCallbacks alloc;
324 };
325
326 struct radv_pipeline_key {
327 uint32_t instance_rate_inputs;
328 unsigned tess_input_vertices;
329 uint32_t col_format;
330 uint32_t is_int8;
331 uint32_t is_int10;
332 uint32_t multisample : 1;
333 uint32_t has_multiview_view_index : 1;
334 };
335
336 void
337 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
338 struct radv_device *device);
339 void
340 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
341 void
342 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
343 const void *data, size_t size);
344
345 struct radv_shader_variant;
346
347 bool
348 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
349 struct radv_pipeline_cache *cache,
350 const unsigned char *sha1,
351 struct radv_shader_variant **variants);
352
353 void
354 radv_pipeline_cache_insert_shaders(struct radv_device *device,
355 struct radv_pipeline_cache *cache,
356 const unsigned char *sha1,
357 struct radv_shader_variant **variants,
358 const void *const *codes,
359 const unsigned *code_sizes);
360
361 struct radv_meta_state {
362 VkAllocationCallbacks alloc;
363
364 struct radv_pipeline_cache cache;
365
366 /**
367 * Use array element `i` for images with `2^i` samples.
368 */
369 struct {
370 VkRenderPass render_pass[NUM_META_FS_KEYS];
371 VkPipeline color_pipelines[NUM_META_FS_KEYS];
372
373 VkRenderPass depthstencil_rp;
374 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
375 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
376 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
377 } clear[1 + MAX_SAMPLES_LOG2];
378
379 VkPipelineLayout clear_color_p_layout;
380 VkPipelineLayout clear_depth_p_layout;
381 struct {
382 VkRenderPass render_pass[NUM_META_FS_KEYS];
383
384 /** Pipeline that blits from a 1D image. */
385 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
386
387 /** Pipeline that blits from a 2D image. */
388 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
389
390 /** Pipeline that blits from a 3D image. */
391 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
392
393 VkRenderPass depth_only_rp;
394 VkPipeline depth_only_1d_pipeline;
395 VkPipeline depth_only_2d_pipeline;
396 VkPipeline depth_only_3d_pipeline;
397
398 VkRenderPass stencil_only_rp;
399 VkPipeline stencil_only_1d_pipeline;
400 VkPipeline stencil_only_2d_pipeline;
401 VkPipeline stencil_only_3d_pipeline;
402 VkPipelineLayout pipeline_layout;
403 VkDescriptorSetLayout ds_layout;
404 } blit;
405
406 struct {
407 VkRenderPass render_passes[NUM_META_FS_KEYS];
408
409 VkPipelineLayout p_layouts[2];
410 VkDescriptorSetLayout ds_layouts[2];
411 VkPipeline pipelines[2][NUM_META_FS_KEYS];
412
413 VkRenderPass depth_only_rp;
414 VkPipeline depth_only_pipeline[2];
415
416 VkRenderPass stencil_only_rp;
417 VkPipeline stencil_only_pipeline[2];
418 } blit2d;
419
420 struct {
421 VkPipelineLayout img_p_layout;
422 VkDescriptorSetLayout img_ds_layout;
423 VkPipeline pipeline;
424 } itob;
425 struct {
426 VkPipelineLayout img_p_layout;
427 VkDescriptorSetLayout img_ds_layout;
428 VkPipeline pipeline;
429 } btoi;
430 struct {
431 VkPipelineLayout img_p_layout;
432 VkDescriptorSetLayout img_ds_layout;
433 VkPipeline pipeline;
434 } itoi;
435 struct {
436 VkPipelineLayout img_p_layout;
437 VkDescriptorSetLayout img_ds_layout;
438 VkPipeline pipeline;
439 } cleari;
440
441 struct {
442 VkPipeline pipeline;
443 VkRenderPass pass;
444 } resolve;
445
446 struct {
447 VkDescriptorSetLayout ds_layout;
448 VkPipelineLayout p_layout;
449 struct {
450 VkPipeline pipeline;
451 VkPipeline i_pipeline;
452 VkPipeline srgb_pipeline;
453 } rc[MAX_SAMPLES_LOG2];
454 } resolve_compute;
455
456 struct {
457 VkDescriptorSetLayout ds_layout;
458 VkPipelineLayout p_layout;
459
460 struct {
461 VkRenderPass render_pass[NUM_META_FS_KEYS];
462 VkPipeline pipeline[NUM_META_FS_KEYS];
463 } rc[MAX_SAMPLES_LOG2];
464 } resolve_fragment;
465
466 struct {
467 VkPipeline decompress_pipeline;
468 VkPipeline resummarize_pipeline;
469 VkRenderPass pass;
470 } depth_decomp[1 + MAX_SAMPLES_LOG2];
471
472 struct {
473 VkPipeline cmask_eliminate_pipeline;
474 VkPipeline fmask_decompress_pipeline;
475 VkRenderPass pass;
476 } fast_clear_flush;
477
478 struct {
479 VkPipelineLayout fill_p_layout;
480 VkPipelineLayout copy_p_layout;
481 VkDescriptorSetLayout fill_ds_layout;
482 VkDescriptorSetLayout copy_ds_layout;
483 VkPipeline fill_pipeline;
484 VkPipeline copy_pipeline;
485 } buffer;
486
487 struct {
488 VkDescriptorSetLayout ds_layout;
489 VkPipelineLayout p_layout;
490 VkPipeline occlusion_query_pipeline;
491 VkPipeline pipeline_statistics_query_pipeline;
492 } query;
493 };
494
495 /* queue types */
496 #define RADV_QUEUE_GENERAL 0
497 #define RADV_QUEUE_COMPUTE 1
498 #define RADV_QUEUE_TRANSFER 2
499
500 #define RADV_MAX_QUEUE_FAMILIES 3
501
502 enum ring_type radv_queue_family_to_ring(int f);
503
504 struct radv_queue {
505 VK_LOADER_DATA _loader_data;
506 struct radv_device * device;
507 struct radeon_winsys_ctx *hw_ctx;
508 enum radeon_ctx_priority priority;
509 int queue_family_index;
510 int queue_idx;
511
512 uint32_t scratch_size;
513 uint32_t compute_scratch_size;
514 uint32_t esgs_ring_size;
515 uint32_t gsvs_ring_size;
516 bool has_tess_rings;
517 bool has_sample_positions;
518
519 struct radeon_winsys_bo *scratch_bo;
520 struct radeon_winsys_bo *descriptor_bo;
521 struct radeon_winsys_bo *compute_scratch_bo;
522 struct radeon_winsys_bo *esgs_ring_bo;
523 struct radeon_winsys_bo *gsvs_ring_bo;
524 struct radeon_winsys_bo *tess_factor_ring_bo;
525 struct radeon_winsys_bo *tess_offchip_ring_bo;
526 struct radeon_winsys_cs *initial_preamble_cs;
527 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
528 struct radeon_winsys_cs *continue_preamble_cs;
529 };
530
531 struct radv_device {
532 VK_LOADER_DATA _loader_data;
533
534 VkAllocationCallbacks alloc;
535
536 struct radv_instance * instance;
537 struct radeon_winsys *ws;
538
539 struct radv_meta_state meta_state;
540
541 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
542 int queue_count[RADV_MAX_QUEUE_FAMILIES];
543 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
544
545 bool llvm_supports_spill;
546 bool has_distributed_tess;
547 bool dfsm_allowed;
548 uint32_t tess_offchip_block_dw_size;
549 uint32_t scratch_waves;
550
551 uint32_t gs_table_depth;
552
553 /* MSAA sample locations.
554 * The first index is the sample index.
555 * The second index is the coordinate: X, Y. */
556 float sample_locations_1x[1][2];
557 float sample_locations_2x[2][2];
558 float sample_locations_4x[4][2];
559 float sample_locations_8x[8][2];
560 float sample_locations_16x[16][2];
561
562 /* CIK and later */
563 uint32_t gfx_init_size_dw;
564 struct radeon_winsys_bo *gfx_init;
565
566 struct radeon_winsys_bo *trace_bo;
567 uint32_t *trace_id_ptr;
568
569 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
570 bool keep_shader_info;
571
572 struct radv_physical_device *physical_device;
573
574 /* Backup in-memory cache to be used if the app doesn't provide one */
575 struct radv_pipeline_cache * mem_cache;
576
577 /*
578 * use different counters so MSAA MRTs get consecutive surface indices,
579 * even if MASK is allocated in between.
580 */
581 uint32_t image_mrt_offset_counter;
582 uint32_t fmask_mrt_offset_counter;
583 struct list_head shader_slabs;
584 mtx_t shader_slab_mutex;
585
586 /* For detecting VM faults reported by dmesg. */
587 uint64_t dmesg_timestamp;
588 };
589
590 struct radv_device_memory {
591 struct radeon_winsys_bo *bo;
592 /* for dedicated allocations */
593 struct radv_image *image;
594 struct radv_buffer *buffer;
595 uint32_t type_index;
596 VkDeviceSize map_size;
597 void * map;
598 };
599
600
601 struct radv_descriptor_range {
602 uint64_t va;
603 uint32_t size;
604 };
605
606 struct radv_descriptor_set {
607 const struct radv_descriptor_set_layout *layout;
608 uint32_t size;
609
610 struct radeon_winsys_bo *bo;
611 uint64_t va;
612 uint32_t *mapped_ptr;
613 struct radv_descriptor_range *dynamic_descriptors;
614
615 struct list_head vram_list;
616
617 struct radeon_winsys_bo *descriptors[0];
618 };
619
620 struct radv_push_descriptor_set
621 {
622 struct radv_descriptor_set set;
623 uint32_t capacity;
624 };
625
626 struct radv_descriptor_pool {
627 struct radeon_winsys_bo *bo;
628 uint8_t *mapped_ptr;
629 uint64_t current_offset;
630 uint64_t size;
631
632 struct list_head vram_list;
633
634 uint8_t *host_memory_base;
635 uint8_t *host_memory_ptr;
636 uint8_t *host_memory_end;
637 };
638
639 struct radv_descriptor_update_template_entry {
640 VkDescriptorType descriptor_type;
641
642 /* The number of descriptors to update */
643 uint32_t descriptor_count;
644
645 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
646 uint32_t dst_offset;
647
648 /* In dwords. Not valid/used for dynamic descriptors */
649 uint32_t dst_stride;
650
651 uint32_t buffer_offset;
652
653 /* Only valid for combined image samplers and samplers */
654 uint16_t has_sampler;
655
656 /* In bytes */
657 size_t src_offset;
658 size_t src_stride;
659
660 /* For push descriptors */
661 const uint32_t *immutable_samplers;
662 };
663
664 struct radv_descriptor_update_template {
665 uint32_t entry_count;
666 struct radv_descriptor_update_template_entry entry[0];
667 };
668
669 struct radv_buffer {
670 struct radv_device * device;
671 VkDeviceSize size;
672
673 VkBufferUsageFlags usage;
674 VkBufferCreateFlags flags;
675
676 /* Set when bound */
677 struct radeon_winsys_bo * bo;
678 VkDeviceSize offset;
679
680 bool shareable;
681 };
682
683
684 enum radv_cmd_dirty_bits {
685 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
686 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
687 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
688 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
689 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
690 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
691 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
692 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
693 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
694 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
695 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
696 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
697 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
698 };
699 typedef uint32_t radv_cmd_dirty_mask_t;
700
701 enum radv_cmd_flush_bits {
702 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
703 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
704 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
705 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
706 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
707 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
708 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
709 /* Same as above, but only writes back and doesn't invalidate */
710 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
711 /* Framebuffer caches */
712 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
713 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
714 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
715 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
716 /* Engine synchronization. */
717 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
718 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
719 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
720 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
721
722 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
723 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
724 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
725 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
726 };
727
728 struct radv_vertex_binding {
729 struct radv_buffer * buffer;
730 VkDeviceSize offset;
731 };
732
733 struct radv_viewport_state {
734 uint32_t count;
735 VkViewport viewports[MAX_VIEWPORTS];
736 };
737
738 struct radv_scissor_state {
739 uint32_t count;
740 VkRect2D scissors[MAX_SCISSORS];
741 };
742
743 struct radv_dynamic_state {
744 /**
745 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
746 * Defines the set of saved dynamic state.
747 */
748 uint32_t mask;
749
750 struct radv_viewport_state viewport;
751
752 struct radv_scissor_state scissor;
753
754 float line_width;
755
756 struct {
757 float bias;
758 float clamp;
759 float slope;
760 } depth_bias;
761
762 float blend_constants[4];
763
764 struct {
765 float min;
766 float max;
767 } depth_bounds;
768
769 struct {
770 uint32_t front;
771 uint32_t back;
772 } stencil_compare_mask;
773
774 struct {
775 uint32_t front;
776 uint32_t back;
777 } stencil_write_mask;
778
779 struct {
780 uint32_t front;
781 uint32_t back;
782 } stencil_reference;
783 };
784
785 extern const struct radv_dynamic_state default_dynamic_state;
786
787 const char *
788 radv_get_debug_option_name(int id);
789
790 const char *
791 radv_get_perftest_option_name(int id);
792
793 /**
794 * Attachment state when recording a renderpass instance.
795 *
796 * The clear value is valid only if there exists a pending clear.
797 */
798 struct radv_attachment_state {
799 VkImageAspectFlags pending_clear_aspects;
800 uint32_t cleared_views;
801 VkClearValue clear_value;
802 VkImageLayout current_layout;
803 };
804
805 struct radv_cmd_state {
806 bool vb_dirty;
807 radv_cmd_dirty_mask_t dirty;
808 bool push_descriptors_dirty;
809 bool predicating;
810
811 struct radv_pipeline * pipeline;
812 struct radv_pipeline * emitted_pipeline;
813 struct radv_pipeline * compute_pipeline;
814 struct radv_pipeline * emitted_compute_pipeline;
815 struct radv_framebuffer * framebuffer;
816 struct radv_render_pass * pass;
817 const struct radv_subpass * subpass;
818 struct radv_dynamic_state dynamic;
819 struct radv_vertex_binding vertex_bindings[MAX_VBS];
820 struct radv_descriptor_set * descriptors[MAX_SETS];
821 struct radv_attachment_state * attachments;
822 VkRect2D render_area;
823
824 /* Index buffer */
825 struct radv_buffer *index_buffer;
826 uint64_t index_offset;
827 uint32_t index_type;
828 uint32_t max_index_count;
829 uint64_t index_va;
830
831 int32_t last_primitive_reset_en;
832 uint32_t last_primitive_reset_index;
833 enum radv_cmd_flush_bits flush_bits;
834 unsigned active_occlusion_queries;
835 float offset_scale;
836 uint32_t descriptors_dirty;
837 uint32_t trace_id;
838 uint32_t last_ia_multi_vgt_param;
839 };
840
841 struct radv_cmd_pool {
842 VkAllocationCallbacks alloc;
843 struct list_head cmd_buffers;
844 struct list_head free_cmd_buffers;
845 uint32_t queue_family_index;
846 };
847
848 struct radv_cmd_buffer_upload {
849 uint8_t *map;
850 unsigned offset;
851 uint64_t size;
852 struct radeon_winsys_bo *upload_bo;
853 struct list_head list;
854 };
855
856 struct radv_cmd_buffer {
857 VK_LOADER_DATA _loader_data;
858
859 struct radv_device * device;
860
861 struct radv_cmd_pool * pool;
862 struct list_head pool_link;
863
864 VkCommandBufferUsageFlags usage_flags;
865 VkCommandBufferLevel level;
866 struct radeon_winsys_cs *cs;
867 struct radv_cmd_state state;
868 uint32_t queue_family_index;
869
870 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
871 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
872 VkShaderStageFlags push_constant_stages;
873 struct radv_push_descriptor_set push_descriptors;
874 struct radv_descriptor_set meta_push_descriptors;
875
876 struct radv_cmd_buffer_upload upload;
877
878 uint32_t scratch_size_needed;
879 uint32_t compute_scratch_size_needed;
880 uint32_t esgs_ring_size_needed;
881 uint32_t gsvs_ring_size_needed;
882 bool tess_rings_needed;
883 bool sample_positions_needed;
884
885 VkResult record_result;
886
887 int ring_offsets_idx; /* just used for verification */
888 uint32_t gfx9_fence_offset;
889 struct radeon_winsys_bo *gfx9_fence_bo;
890 uint32_t gfx9_fence_idx;
891 };
892
893 struct radv_image;
894
895 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
896
897 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
898 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
899
900 void cik_create_gfx_config(struct radv_device *device);
901
902 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
903 int count, const VkViewport *viewports);
904 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
905 int count, const VkRect2D *scissors,
906 const VkViewport *viewports, bool can_use_guardband);
907 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
908 bool instanced_draw, bool indirect_draw,
909 uint32_t draw_vertex_count);
910 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
911 bool predicated,
912 enum chip_class chip_class,
913 bool is_mec,
914 unsigned event, unsigned event_flags,
915 unsigned data_sel,
916 uint64_t va,
917 uint32_t old_fence,
918 uint32_t new_fence);
919
920 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
921 bool predicated,
922 uint64_t va, uint32_t ref,
923 uint32_t mask);
924 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
925 bool predicated,
926 enum chip_class chip_class,
927 uint32_t *fence_ptr, uint64_t va,
928 bool is_mec,
929 enum radv_cmd_flush_bits flush_bits);
930 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
931 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
932 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
933 uint64_t src_va, uint64_t dest_va,
934 uint64_t size);
935 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
936 unsigned size);
937 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
938 uint64_t size, unsigned value);
939 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
940 bool
941 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
942 unsigned size,
943 unsigned alignment,
944 unsigned *out_offset,
945 void **ptr);
946 void
947 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
948 const struct radv_subpass *subpass,
949 bool transitions);
950 bool
951 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
952 unsigned size, unsigned alignmnet,
953 const void *data, unsigned *out_offset);
954 void
955 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
956 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
957 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
958 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
959 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
960 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
961 unsigned radv_cayman_get_maxdist(int log_samples);
962 void radv_device_init_msaa(struct radv_device *device);
963 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
964 struct radv_image *image,
965 VkClearDepthStencilValue ds_clear_value,
966 VkImageAspectFlags aspects);
967 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
968 struct radv_image *image,
969 int idx,
970 uint32_t color_values[2]);
971 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
972 struct radv_image *image,
973 bool value);
974 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
975 struct radeon_winsys_bo *bo,
976 uint64_t offset, uint64_t size, uint32_t value);
977 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
978 bool radv_get_memory_fd(struct radv_device *device,
979 struct radv_device_memory *memory,
980 int *pFD);
981 VkResult radv_alloc_memory(VkDevice _device,
982 const VkMemoryAllocateInfo* pAllocateInfo,
983 const VkAllocationCallbacks* pAllocator,
984 enum radv_mem_flags_bits flags,
985 VkDeviceMemory* pMem);
986
987 /*
988 * Takes x,y,z as exact numbers of invocations, instead of blocks.
989 *
990 * Limitations: Can't call normal dispatch functions without binding or rebinding
991 * the compute pipeline.
992 */
993 void radv_unaligned_dispatch(
994 struct radv_cmd_buffer *cmd_buffer,
995 uint32_t x,
996 uint32_t y,
997 uint32_t z);
998
999 struct radv_event {
1000 struct radeon_winsys_bo *bo;
1001 uint64_t *map;
1002 };
1003
1004 struct radv_shader_module;
1005
1006 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1007 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1008 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1009 void
1010 radv_hash_shaders(unsigned char *hash,
1011 const VkPipelineShaderStageCreateInfo **stages,
1012 const struct radv_pipeline_layout *layout,
1013 const struct radv_pipeline_key *key,
1014 uint32_t flags);
1015
1016 static inline gl_shader_stage
1017 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1018 {
1019 assert(__builtin_popcount(vk_stage) == 1);
1020 return ffs(vk_stage) - 1;
1021 }
1022
1023 static inline VkShaderStageFlagBits
1024 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1025 {
1026 return (1 << mesa_stage);
1027 }
1028
1029 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1030
1031 #define radv_foreach_stage(stage, stage_bits) \
1032 for (gl_shader_stage stage, \
1033 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1034 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1035 __tmp &= ~(1 << (stage)))
1036
1037 struct radv_depth_stencil_state {
1038 uint32_t db_depth_control;
1039 uint32_t db_stencil_control;
1040 uint32_t db_render_control;
1041 uint32_t db_render_override2;
1042 };
1043
1044 struct radv_blend_state {
1045 uint32_t cb_color_control;
1046 uint32_t cb_target_mask;
1047 uint32_t sx_mrt_blend_opt[8];
1048 uint32_t cb_blend_control[8];
1049
1050 uint32_t spi_shader_col_format;
1051 uint32_t cb_shader_mask;
1052 uint32_t db_alpha_to_mask;
1053 };
1054
1055 unsigned radv_format_meta_fs_key(VkFormat format);
1056
1057 struct radv_raster_state {
1058 uint32_t pa_cl_clip_cntl;
1059 uint32_t spi_interp_control;
1060 uint32_t pa_su_vtx_cntl;
1061 uint32_t pa_su_sc_mode_cntl;
1062 };
1063
1064 struct radv_multisample_state {
1065 uint32_t db_eqaa;
1066 uint32_t pa_sc_line_cntl;
1067 uint32_t pa_sc_mode_cntl_0;
1068 uint32_t pa_sc_mode_cntl_1;
1069 uint32_t pa_sc_aa_config;
1070 uint32_t pa_sc_aa_mask[2];
1071 unsigned num_samples;
1072 };
1073
1074 struct radv_prim_vertex_count {
1075 uint8_t min;
1076 uint8_t incr;
1077 };
1078
1079 struct radv_tessellation_state {
1080 uint32_t ls_hs_config;
1081 uint32_t tcs_in_layout;
1082 uint32_t tcs_out_layout;
1083 uint32_t tcs_out_offsets;
1084 uint32_t offchip_layout;
1085 unsigned num_patches;
1086 unsigned lds_size;
1087 unsigned num_tcs_input_cp;
1088 uint32_t tf_param;
1089 };
1090
1091 struct radv_gs_state {
1092 uint32_t vgt_gs_onchip_cntl;
1093 uint32_t vgt_gs_max_prims_per_subgroup;
1094 uint32_t vgt_esgs_ring_itemsize;
1095 uint32_t lds_size;
1096 };
1097
1098 struct radv_vertex_elements_info {
1099 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1100 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1101 uint32_t binding[MAX_VERTEX_ATTRIBS];
1102 uint32_t offset[MAX_VERTEX_ATTRIBS];
1103 uint32_t count;
1104 };
1105
1106 #define SI_GS_PER_ES 128
1107
1108 struct radv_pipeline {
1109 struct radv_device * device;
1110 struct radv_dynamic_state dynamic_state;
1111
1112 struct radv_pipeline_layout * layout;
1113
1114 bool needs_data_cache;
1115 bool need_indirect_descriptor_sets;
1116 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1117 struct radv_shader_variant *gs_copy_shader;
1118 VkShaderStageFlags active_stages;
1119
1120 struct radv_vertex_elements_info vertex_elements;
1121
1122 uint32_t binding_stride[MAX_VBS];
1123
1124 union {
1125 struct {
1126 struct radv_blend_state blend;
1127 struct radv_depth_stencil_state ds;
1128 struct radv_raster_state raster;
1129 struct radv_multisample_state ms;
1130 struct radv_tessellation_state tess;
1131 struct radv_gs_state gs;
1132 uint32_t db_shader_control;
1133 uint32_t shader_z_format;
1134 unsigned prim;
1135 unsigned gs_out;
1136 uint32_t vgt_gs_mode;
1137 bool vgt_primitiveid_en;
1138 bool prim_restart_enable;
1139 bool partial_es_wave;
1140 uint8_t primgroup_size;
1141 unsigned esgs_ring_size;
1142 unsigned gsvs_ring_size;
1143 uint32_t ps_input_cntl[32];
1144 uint32_t ps_input_cntl_num;
1145 uint32_t pa_cl_vs_out_cntl;
1146 uint32_t vgt_shader_stages_en;
1147 uint32_t vtx_base_sgpr;
1148 uint32_t base_ia_multi_vgt_param;
1149 bool wd_switch_on_eop;
1150 bool ia_switch_on_eoi;
1151 bool partial_vs_wave;
1152 uint8_t vtx_emit_num;
1153 uint32_t vtx_reuse_depth;
1154 struct radv_prim_vertex_count prim_vertex_count;
1155 bool can_use_guardband;
1156 } graphics;
1157 };
1158
1159 unsigned max_waves;
1160 unsigned scratch_bytes_per_wave;
1161 };
1162
1163 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1164 {
1165 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1166 }
1167
1168 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1169 {
1170 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1171 }
1172
1173 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1174 gl_shader_stage stage,
1175 int idx);
1176
1177 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1178
1179 struct radv_graphics_pipeline_create_info {
1180 bool use_rectlist;
1181 bool db_depth_clear;
1182 bool db_stencil_clear;
1183 bool db_depth_disable_expclear;
1184 bool db_stencil_disable_expclear;
1185 bool db_flush_depth_inplace;
1186 bool db_flush_stencil_inplace;
1187 bool db_resummarize;
1188 uint32_t custom_blend_mode;
1189 };
1190
1191 VkResult
1192 radv_graphics_pipeline_create(VkDevice device,
1193 VkPipelineCache cache,
1194 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1195 const struct radv_graphics_pipeline_create_info *extra,
1196 const VkAllocationCallbacks *alloc,
1197 VkPipeline *pPipeline);
1198
1199 struct vk_format_description;
1200 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1201 int first_non_void);
1202 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1203 int first_non_void);
1204 uint32_t radv_translate_colorformat(VkFormat format);
1205 uint32_t radv_translate_color_numformat(VkFormat format,
1206 const struct vk_format_description *desc,
1207 int first_non_void);
1208 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1209 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1210 uint32_t radv_translate_dbformat(VkFormat format);
1211 uint32_t radv_translate_tex_dataformat(VkFormat format,
1212 const struct vk_format_description *desc,
1213 int first_non_void);
1214 uint32_t radv_translate_tex_numformat(VkFormat format,
1215 const struct vk_format_description *desc,
1216 int first_non_void);
1217 bool radv_format_pack_clear_color(VkFormat format,
1218 uint32_t clear_vals[2],
1219 VkClearColorValue *value);
1220 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1221 bool radv_dcc_formats_compatible(VkFormat format1,
1222 VkFormat format2);
1223
1224 struct radv_fmask_info {
1225 uint64_t offset;
1226 uint64_t size;
1227 unsigned alignment;
1228 unsigned pitch_in_pixels;
1229 unsigned bank_height;
1230 unsigned slice_tile_max;
1231 unsigned tile_mode_index;
1232 unsigned tile_swizzle;
1233 };
1234
1235 struct radv_cmask_info {
1236 uint64_t offset;
1237 uint64_t size;
1238 unsigned alignment;
1239 unsigned slice_tile_max;
1240 unsigned base_address_reg;
1241 };
1242
1243 struct radv_image {
1244 VkImageType type;
1245 /* The original VkFormat provided by the client. This may not match any
1246 * of the actual surface formats.
1247 */
1248 VkFormat vk_format;
1249 VkImageAspectFlags aspects;
1250 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1251 struct ac_surf_info info;
1252 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1253 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1254
1255 VkDeviceSize size;
1256 uint32_t alignment;
1257
1258 unsigned queue_family_mask;
1259 bool exclusive;
1260 bool shareable;
1261
1262 /* Set when bound */
1263 struct radeon_winsys_bo *bo;
1264 VkDeviceSize offset;
1265 uint64_t dcc_offset;
1266 uint64_t htile_offset;
1267 bool tc_compatible_htile;
1268 struct radeon_surf surface;
1269
1270 struct radv_fmask_info fmask;
1271 struct radv_cmask_info cmask;
1272 uint64_t clear_value_offset;
1273 uint64_t dcc_pred_offset;
1274 };
1275
1276 /* Whether the image has a htile that is known consistent with the contents of
1277 * the image. */
1278 bool radv_layout_has_htile(const struct radv_image *image,
1279 VkImageLayout layout,
1280 unsigned queue_mask);
1281
1282 /* Whether the image has a htile that is known consistent with the contents of
1283 * the image and is allowed to be in compressed form.
1284 *
1285 * If this is false reads that don't use the htile should be able to return
1286 * correct results.
1287 */
1288 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1289 VkImageLayout layout,
1290 unsigned queue_mask);
1291
1292 bool radv_layout_can_fast_clear(const struct radv_image *image,
1293 VkImageLayout layout,
1294 unsigned queue_mask);
1295
1296 static inline bool
1297 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1298 {
1299 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1300 }
1301
1302 static inline bool
1303 radv_htile_enabled(const struct radv_image *image, unsigned level)
1304 {
1305 return image->surface.htile_size && level == 0;
1306 }
1307
1308 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1309
1310 static inline uint32_t
1311 radv_get_layerCount(const struct radv_image *image,
1312 const VkImageSubresourceRange *range)
1313 {
1314 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1315 image->info.array_size - range->baseArrayLayer : range->layerCount;
1316 }
1317
1318 static inline uint32_t
1319 radv_get_levelCount(const struct radv_image *image,
1320 const VkImageSubresourceRange *range)
1321 {
1322 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1323 image->info.levels - range->baseMipLevel : range->levelCount;
1324 }
1325
1326 struct radeon_bo_metadata;
1327 void
1328 radv_init_metadata(struct radv_device *device,
1329 struct radv_image *image,
1330 struct radeon_bo_metadata *metadata);
1331
1332 struct radv_image_view {
1333 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1334 struct radeon_winsys_bo *bo;
1335
1336 VkImageViewType type;
1337 VkImageAspectFlags aspect_mask;
1338 VkFormat vk_format;
1339 uint32_t base_layer;
1340 uint32_t layer_count;
1341 uint32_t base_mip;
1342 uint32_t level_count;
1343 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1344
1345 uint32_t descriptor[8];
1346 uint32_t fmask_descriptor[8];
1347
1348 /* Descriptor for use as a storage image as opposed to a sampled image.
1349 * This has a few differences for cube maps (e.g. type).
1350 */
1351 uint32_t storage_descriptor[8];
1352 uint32_t storage_fmask_descriptor[8];
1353 };
1354
1355 struct radv_image_create_info {
1356 const VkImageCreateInfo *vk_info;
1357 bool scanout;
1358 };
1359
1360 VkResult radv_image_create(VkDevice _device,
1361 const struct radv_image_create_info *info,
1362 const VkAllocationCallbacks* alloc,
1363 VkImage *pImage);
1364
1365 void radv_image_view_init(struct radv_image_view *view,
1366 struct radv_device *device,
1367 const VkImageViewCreateInfo* pCreateInfo);
1368
1369 struct radv_buffer_view {
1370 struct radeon_winsys_bo *bo;
1371 VkFormat vk_format;
1372 uint64_t range; /**< VkBufferViewCreateInfo::range */
1373 uint32_t state[4];
1374 };
1375 void radv_buffer_view_init(struct radv_buffer_view *view,
1376 struct radv_device *device,
1377 const VkBufferViewCreateInfo* pCreateInfo);
1378
1379 static inline struct VkExtent3D
1380 radv_sanitize_image_extent(const VkImageType imageType,
1381 const struct VkExtent3D imageExtent)
1382 {
1383 switch (imageType) {
1384 case VK_IMAGE_TYPE_1D:
1385 return (VkExtent3D) { imageExtent.width, 1, 1 };
1386 case VK_IMAGE_TYPE_2D:
1387 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1388 case VK_IMAGE_TYPE_3D:
1389 return imageExtent;
1390 default:
1391 unreachable("invalid image type");
1392 }
1393 }
1394
1395 static inline struct VkOffset3D
1396 radv_sanitize_image_offset(const VkImageType imageType,
1397 const struct VkOffset3D imageOffset)
1398 {
1399 switch (imageType) {
1400 case VK_IMAGE_TYPE_1D:
1401 return (VkOffset3D) { imageOffset.x, 0, 0 };
1402 case VK_IMAGE_TYPE_2D:
1403 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1404 case VK_IMAGE_TYPE_3D:
1405 return imageOffset;
1406 default:
1407 unreachable("invalid image type");
1408 }
1409 }
1410
1411 static inline bool
1412 radv_image_extent_compare(const struct radv_image *image,
1413 const VkExtent3D *extent)
1414 {
1415 if (extent->width != image->info.width ||
1416 extent->height != image->info.height ||
1417 extent->depth != image->info.depth)
1418 return false;
1419 return true;
1420 }
1421
1422 struct radv_sampler {
1423 uint32_t state[4];
1424 };
1425
1426 struct radv_color_buffer_info {
1427 uint64_t cb_color_base;
1428 uint64_t cb_color_cmask;
1429 uint64_t cb_color_fmask;
1430 uint64_t cb_dcc_base;
1431 uint32_t cb_color_pitch;
1432 uint32_t cb_color_slice;
1433 uint32_t cb_color_view;
1434 uint32_t cb_color_info;
1435 uint32_t cb_color_attrib;
1436 uint32_t cb_color_attrib2;
1437 uint32_t cb_dcc_control;
1438 uint32_t cb_color_cmask_slice;
1439 uint32_t cb_color_fmask_slice;
1440 uint32_t cb_clear_value0;
1441 uint32_t cb_clear_value1;
1442 uint32_t micro_tile_mode;
1443 uint32_t gfx9_epitch;
1444 };
1445
1446 struct radv_ds_buffer_info {
1447 uint64_t db_z_read_base;
1448 uint64_t db_stencil_read_base;
1449 uint64_t db_z_write_base;
1450 uint64_t db_stencil_write_base;
1451 uint64_t db_htile_data_base;
1452 uint32_t db_depth_info;
1453 uint32_t db_z_info;
1454 uint32_t db_stencil_info;
1455 uint32_t db_depth_view;
1456 uint32_t db_depth_size;
1457 uint32_t db_depth_slice;
1458 uint32_t db_htile_surface;
1459 uint32_t pa_su_poly_offset_db_fmt_cntl;
1460 uint32_t db_z_info2;
1461 uint32_t db_stencil_info2;
1462 float offset_scale;
1463 };
1464
1465 struct radv_attachment_info {
1466 union {
1467 struct radv_color_buffer_info cb;
1468 struct radv_ds_buffer_info ds;
1469 };
1470 struct radv_image_view *attachment;
1471 };
1472
1473 struct radv_framebuffer {
1474 uint32_t width;
1475 uint32_t height;
1476 uint32_t layers;
1477
1478 uint32_t attachment_count;
1479 struct radv_attachment_info attachments[0];
1480 };
1481
1482 struct radv_subpass_barrier {
1483 VkPipelineStageFlags src_stage_mask;
1484 VkAccessFlags src_access_mask;
1485 VkAccessFlags dst_access_mask;
1486 };
1487
1488 struct radv_subpass {
1489 uint32_t input_count;
1490 uint32_t color_count;
1491 VkAttachmentReference * input_attachments;
1492 VkAttachmentReference * color_attachments;
1493 VkAttachmentReference * resolve_attachments;
1494 VkAttachmentReference depth_stencil_attachment;
1495
1496 /** Subpass has at least one resolve attachment */
1497 bool has_resolve;
1498
1499 struct radv_subpass_barrier start_barrier;
1500
1501 uint32_t view_mask;
1502 };
1503
1504 struct radv_render_pass_attachment {
1505 VkFormat format;
1506 uint32_t samples;
1507 VkAttachmentLoadOp load_op;
1508 VkAttachmentLoadOp stencil_load_op;
1509 VkImageLayout initial_layout;
1510 VkImageLayout final_layout;
1511 uint32_t view_mask;
1512 };
1513
1514 struct radv_render_pass {
1515 uint32_t attachment_count;
1516 uint32_t subpass_count;
1517 VkAttachmentReference * subpass_attachments;
1518 struct radv_render_pass_attachment * attachments;
1519 struct radv_subpass_barrier end_barrier;
1520 struct radv_subpass subpasses[0];
1521 };
1522
1523 VkResult radv_device_init_meta(struct radv_device *device);
1524 void radv_device_finish_meta(struct radv_device *device);
1525
1526 struct radv_query_pool {
1527 struct radeon_winsys_bo *bo;
1528 uint32_t stride;
1529 uint32_t availability_offset;
1530 char *ptr;
1531 VkQueryType type;
1532 uint32_t pipeline_stats_mask;
1533 };
1534
1535 struct radv_semaphore {
1536 /* use a winsys sem for non-exportable */
1537 struct radeon_winsys_sem *sem;
1538 uint32_t syncobj;
1539 uint32_t temp_syncobj;
1540 };
1541
1542 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1543 int num_wait_sems,
1544 const VkSemaphore *wait_sems,
1545 int num_signal_sems,
1546 const VkSemaphore *signal_sems);
1547 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1548
1549 void
1550 radv_update_descriptor_sets(struct radv_device *device,
1551 struct radv_cmd_buffer *cmd_buffer,
1552 VkDescriptorSet overrideSet,
1553 uint32_t descriptorWriteCount,
1554 const VkWriteDescriptorSet *pDescriptorWrites,
1555 uint32_t descriptorCopyCount,
1556 const VkCopyDescriptorSet *pDescriptorCopies);
1557
1558 void
1559 radv_update_descriptor_set_with_template(struct radv_device *device,
1560 struct radv_cmd_buffer *cmd_buffer,
1561 struct radv_descriptor_set *set,
1562 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1563 const void *pData);
1564
1565 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1566 VkPipelineBindPoint pipelineBindPoint,
1567 VkPipelineLayout _layout,
1568 uint32_t set,
1569 uint32_t descriptorWriteCount,
1570 const VkWriteDescriptorSet *pDescriptorWrites);
1571
1572 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1573 struct radv_image *image, uint32_t value);
1574 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1575 struct radv_image *image, uint32_t value);
1576
1577 struct radv_fence {
1578 struct radeon_winsys_fence *fence;
1579 bool submitted;
1580 bool signalled;
1581 };
1582
1583 struct radeon_winsys_sem;
1584
1585 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1586 \
1587 static inline struct __radv_type * \
1588 __radv_type ## _from_handle(__VkType _handle) \
1589 { \
1590 return (struct __radv_type *) _handle; \
1591 } \
1592 \
1593 static inline __VkType \
1594 __radv_type ## _to_handle(struct __radv_type *_obj) \
1595 { \
1596 return (__VkType) _obj; \
1597 }
1598
1599 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1600 \
1601 static inline struct __radv_type * \
1602 __radv_type ## _from_handle(__VkType _handle) \
1603 { \
1604 return (struct __radv_type *)(uintptr_t) _handle; \
1605 } \
1606 \
1607 static inline __VkType \
1608 __radv_type ## _to_handle(struct __radv_type *_obj) \
1609 { \
1610 return (__VkType)(uintptr_t) _obj; \
1611 }
1612
1613 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1614 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1615
1616 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1617 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1618 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1619 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1620 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1621
1622 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1623 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1624 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1625 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1626 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1627 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1628 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1629 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1630 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1631 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1632 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1633 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1634 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1635 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1636 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1637 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1638 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1639 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1640 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1641 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1642 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1643
1644 #endif /* RADV_PRIVATE_H */