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radv: drop local MIN/MAX macros.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "radv_radeon_winsys.h"
52 #include "ac_binary.h"
53 #include "ac_nir_to_llvm.h"
54 #include "radv_descriptor_set.h"
55
56 #include <llvm-c/TargetMachine.h>
57
58 /* Pre-declarations needed for WSI entrypoints */
59 struct wl_surface;
60 struct wl_display;
61 typedef struct xcb_connection_t xcb_connection_t;
62 typedef uint32_t xcb_visualid_t;
63 typedef uint32_t xcb_window_t;
64
65 #include <vulkan/vulkan.h>
66 #include <vulkan/vulkan_intel.h>
67 #include <vulkan/vk_icd.h>
68
69 #include "radv_entrypoints.h"
70
71
72 #define MAX_VBS 32
73 #define MAX_VERTEX_ATTRIBS 32
74 #define MAX_RTS 8
75 #define MAX_VIEWPORTS 16
76 #define MAX_SCISSORS 16
77 #define MAX_PUSH_CONSTANTS_SIZE 128
78 #define MAX_DYNAMIC_BUFFERS 16
79 #define MAX_IMAGES 8
80 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
81 #define NUM_META_FS_KEYS 11
82
83 #define NUM_DEPTH_CLEAR_PIPELINES 3
84
85 #define radv_noreturn __attribute__((__noreturn__))
86 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
87
88 static inline uint32_t
89 align_u32(uint32_t v, uint32_t a)
90 {
91 assert(a != 0 && a == (a & -a));
92 return (v + a - 1) & ~(a - 1);
93 }
94
95 static inline uint32_t
96 align_u32_npot(uint32_t v, uint32_t a)
97 {
98 return (v + a - 1) / a * a;
99 }
100
101 static inline uint64_t
102 align_u64(uint64_t v, uint64_t a)
103 {
104 assert(a != 0 && a == (a & -a));
105 return (v + a - 1) & ~(a - 1);
106 }
107
108 static inline int32_t
109 align_i32(int32_t v, int32_t a)
110 {
111 assert(a != 0 && a == (a & -a));
112 return (v + a - 1) & ~(a - 1);
113 }
114
115 /** Alignment must be a power of 2. */
116 static inline bool
117 radv_is_aligned(uintmax_t n, uintmax_t a)
118 {
119 assert(a == (a & -a));
120 return (n & (a - 1)) == 0;
121 }
122
123 static inline uint32_t
124 round_up_u32(uint32_t v, uint32_t a)
125 {
126 return (v + a - 1) / a;
127 }
128
129 static inline uint64_t
130 round_up_u64(uint64_t v, uint64_t a)
131 {
132 return (v + a - 1) / a;
133 }
134
135 static inline uint32_t
136 radv_minify(uint32_t n, uint32_t levels)
137 {
138 if (unlikely(n == 0))
139 return 0;
140 else
141 return MAX2(n >> levels, 1);
142 }
143 static inline float
144 radv_clamp_f(float f, float min, float max)
145 {
146 assert(min < max);
147
148 if (f > max)
149 return max;
150 else if (f < min)
151 return min;
152 else
153 return f;
154 }
155
156 static inline bool
157 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
158 {
159 if (*inout_mask & clear_mask) {
160 *inout_mask &= ~clear_mask;
161 return true;
162 } else {
163 return false;
164 }
165 }
166
167 #define for_each_bit(b, dword) \
168 for (uint32_t __dword = (dword); \
169 (b) = __builtin_ffs(__dword) - 1, __dword; \
170 __dword &= ~(1 << (b)))
171
172 #define typed_memcpy(dest, src, count) ({ \
173 static_assert(sizeof(*src) == sizeof(*dest), ""); \
174 memcpy((dest), (src), (count) * sizeof(*(src))); \
175 })
176
177 #define zero(x) (memset(&(x), 0, sizeof(x)))
178
179 /* Define no kernel as 1, since that's an illegal offset for a kernel */
180 #define NO_KERNEL 1
181
182 struct radv_common {
183 VkStructureType sType;
184 const void* pNext;
185 };
186
187 /* Whenever we generate an error, pass it through this function. Useful for
188 * debugging, where we can break on it. Only call at error site, not when
189 * propagating errors. Might be useful to plug in a stack trace here.
190 */
191
192 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
193
194 #ifdef DEBUG
195 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
196 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
197 #else
198 #define vk_error(error) error
199 #define vk_errorf(error, format, ...) error
200 #endif
201
202 void __radv_finishme(const char *file, int line, const char *format, ...)
203 radv_printflike(3, 4);
204 void radv_loge(const char *format, ...) radv_printflike(1, 2);
205 void radv_loge_v(const char *format, va_list va);
206
207 /**
208 * Print a FINISHME message, including its source location.
209 */
210 #define radv_finishme(format, ...) \
211 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
212
213 /* A non-fatal assert. Useful for debugging. */
214 #ifdef DEBUG
215 #define radv_assert(x) ({ \
216 if (unlikely(!(x))) \
217 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
218 })
219 #else
220 #define radv_assert(x)
221 #endif
222
223 void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
224 void radv_abortfv(const char *format, va_list va) radv_noreturn;
225
226 #define stub_return(v) \
227 do { \
228 radv_finishme("stub %s", __func__); \
229 return (v); \
230 } while (0)
231
232 #define stub() \
233 do { \
234 radv_finishme("stub %s", __func__); \
235 return; \
236 } while (0)
237
238 void *radv_resolve_entrypoint(uint32_t index);
239 void *radv_lookup_entrypoint(const char *name);
240
241 extern struct radv_dispatch_table dtable;
242
243 static inline void *
244 radv_alloc(const VkAllocationCallbacks *alloc,
245 size_t size, size_t align,
246 VkSystemAllocationScope scope)
247 {
248 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
249 }
250
251 static inline void *
252 radv_realloc(const VkAllocationCallbacks *alloc,
253 void *ptr, size_t size, size_t align,
254 VkSystemAllocationScope scope)
255 {
256 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
257 }
258
259 static inline void
260 radv_free(const VkAllocationCallbacks *alloc, void *data)
261 {
262 alloc->pfnFree(alloc->pUserData, data);
263 }
264
265 static inline void *
266 radv_alloc2(const VkAllocationCallbacks *parent_alloc,
267 const VkAllocationCallbacks *alloc,
268 size_t size, size_t align,
269 VkSystemAllocationScope scope)
270 {
271 if (alloc)
272 return radv_alloc(alloc, size, align, scope);
273 else
274 return radv_alloc(parent_alloc, size, align, scope);
275 }
276
277 static inline void
278 radv_free2(const VkAllocationCallbacks *parent_alloc,
279 const VkAllocationCallbacks *alloc,
280 void *data)
281 {
282 if (alloc)
283 radv_free(alloc, data);
284 else
285 radv_free(parent_alloc, data);
286 }
287
288 struct radv_wsi_interaface;
289
290 #define VK_ICD_WSI_PLATFORM_MAX 5
291
292 struct radv_physical_device {
293 VK_LOADER_DATA _loader_data;
294
295 struct radv_instance * instance;
296
297 struct radeon_winsys *ws;
298 struct radeon_info rad_info;
299 uint32_t chipset_id;
300 char path[20];
301 const char * name;
302 uint64_t aperture_size;
303 int cmd_parser_version;
304 uint32_t pci_vendor_id;
305 uint32_t pci_device_id;
306
307 struct radv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
308 };
309
310 struct radv_instance {
311 VK_LOADER_DATA _loader_data;
312
313 VkAllocationCallbacks alloc;
314
315 uint32_t apiVersion;
316 int physicalDeviceCount;
317 struct radv_physical_device physicalDevice;
318 };
319
320 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
321 void radv_finish_wsi(struct radv_physical_device *physical_device);
322
323 struct cache_entry;
324
325 struct radv_pipeline_cache {
326 struct radv_device * device;
327 pthread_mutex_t mutex;
328
329 uint32_t total_size;
330 uint32_t table_size;
331 uint32_t kernel_count;
332 struct cache_entry ** hash_table;
333 bool modified;
334
335 VkAllocationCallbacks alloc;
336 };
337
338 void
339 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
340 struct radv_device *device);
341 void
342 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
343 void
344 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
345 const void *data, size_t size);
346
347 struct radv_shader_variant *
348 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
349 struct radv_pipeline_cache *cache,
350 const unsigned char *sha1);
351
352 struct radv_shader_variant *
353 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
354 const unsigned char *sha1,
355 struct radv_shader_variant *variant,
356 const void *code, unsigned code_size);
357
358 void radv_shader_variant_destroy(struct radv_device *device,
359 struct radv_shader_variant *variant);
360
361 struct radv_meta_state {
362 VkAllocationCallbacks alloc;
363
364 struct radv_pipeline_cache cache;
365
366 /**
367 * Use array element `i` for images with `2^i` samples.
368 */
369 struct {
370 VkRenderPass render_pass[NUM_META_FS_KEYS];
371 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
372
373 VkRenderPass depth_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
374 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
375 VkRenderPass stencil_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
376 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
377 VkRenderPass depthstencil_rp[NUM_DEPTH_CLEAR_PIPELINES];
378 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
379 } clear[1 + MAX_SAMPLES_LOG2];
380
381 struct {
382 VkRenderPass render_pass[NUM_META_FS_KEYS];
383
384 /** Pipeline that blits from a 1D image. */
385 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
386
387 /** Pipeline that blits from a 2D image. */
388 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
389
390 /** Pipeline that blits from a 3D image. */
391 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
392
393 VkRenderPass depth_only_rp;
394 VkPipeline depth_only_1d_pipeline;
395 VkPipeline depth_only_2d_pipeline;
396 VkPipeline depth_only_3d_pipeline;
397
398 VkRenderPass stencil_only_rp;
399 VkPipeline stencil_only_1d_pipeline;
400 VkPipeline stencil_only_2d_pipeline;
401 VkPipeline stencil_only_3d_pipeline;
402 VkPipelineLayout pipeline_layout;
403 VkDescriptorSetLayout ds_layout;
404 } blit;
405
406 struct {
407 VkRenderPass render_passes[NUM_META_FS_KEYS];
408
409 VkPipelineLayout p_layouts[2];
410 VkDescriptorSetLayout ds_layouts[2];
411 VkPipeline pipelines[2][NUM_META_FS_KEYS];
412
413 VkRenderPass depth_only_rp;
414 VkPipeline depth_only_pipeline[2];
415
416 VkRenderPass stencil_only_rp;
417 VkPipeline stencil_only_pipeline[2];
418 } blit2d;
419
420 struct {
421 VkPipelineLayout img_p_layout;
422 VkDescriptorSetLayout img_ds_layout;
423 VkPipeline pipeline;
424 } itob;
425 struct {
426 VkRenderPass render_pass;
427 VkPipelineLayout img_p_layout;
428 VkDescriptorSetLayout img_ds_layout;
429 VkPipeline pipeline;
430 } btoi;
431
432 struct {
433 VkPipeline pipeline;
434 VkRenderPass pass;
435 } resolve;
436
437 struct {
438 VkDescriptorSetLayout ds_layout;
439 VkPipelineLayout p_layout;
440 struct {
441 VkPipeline pipeline;
442 VkPipeline i_pipeline;
443 } rc[MAX_SAMPLES_LOG2];
444 } resolve_compute;
445
446 struct {
447 VkPipeline decompress_pipeline;
448 VkPipeline resummarize_pipeline;
449 VkRenderPass pass;
450 } depth_decomp;
451
452 struct {
453 VkPipeline cmask_eliminate_pipeline;
454 VkPipeline fmask_decompress_pipeline;
455 VkRenderPass pass;
456 } fast_clear_flush;
457
458 struct {
459 VkPipelineLayout fill_p_layout;
460 VkPipelineLayout copy_p_layout;
461 VkDescriptorSetLayout fill_ds_layout;
462 VkDescriptorSetLayout copy_ds_layout;
463 VkPipeline fill_pipeline;
464 VkPipeline copy_pipeline;
465 } buffer;
466 };
467
468 struct radv_queue {
469 VK_LOADER_DATA _loader_data;
470
471 struct radv_device * device;
472
473 struct radv_state_pool * pool;
474 };
475
476 struct radv_device {
477 VK_LOADER_DATA _loader_data;
478
479 VkAllocationCallbacks alloc;
480
481 struct radv_instance * instance;
482 struct radeon_winsys *ws;
483 struct radeon_winsys_ctx *hw_ctx;
484
485 struct radv_meta_state meta_state;
486 struct radv_queue queue;
487 struct radeon_winsys_cs *empty_cs;
488
489 bool allow_fast_clears;
490 bool allow_dcc;
491
492 /* MSAA sample locations.
493 * The first index is the sample index.
494 * The second index is the coordinate: X, Y. */
495 float sample_locations_1x[1][2];
496 float sample_locations_2x[2][2];
497 float sample_locations_4x[4][2];
498 float sample_locations_8x[8][2];
499 float sample_locations_16x[16][2];
500 };
501
502 void radv_device_get_cache_uuid(void *uuid);
503
504 struct radv_device_memory {
505 struct radeon_winsys_bo *bo;
506 uint32_t type_index;
507 VkDeviceSize map_size;
508 void * map;
509 };
510
511
512 struct radv_descriptor_range {
513 uint64_t va;
514 uint32_t size;
515 };
516
517 struct radv_descriptor_set {
518 const struct radv_descriptor_set_layout *layout;
519 struct list_head descriptor_pool;
520 uint32_t size;
521
522 struct radv_buffer_view *buffer_views;
523 struct radeon_winsys_bo *bo;
524 uint64_t va;
525 uint32_t *mapped_ptr;
526 struct radv_descriptor_range *dynamic_descriptors;
527 struct radeon_winsys_bo *descriptors[0];
528 };
529
530 struct radv_descriptor_pool_free_node {
531 int next;
532 uint32_t offset;
533 uint32_t size;
534 };
535
536 struct radv_descriptor_pool {
537 struct list_head descriptor_sets;
538
539 struct radeon_winsys_bo *bo;
540 uint8_t *mapped_ptr;
541 uint64_t current_offset;
542 uint64_t size;
543
544 int free_list;
545 int full_list;
546 uint32_t max_sets;
547 struct radv_descriptor_pool_free_node free_nodes[];
548 };
549
550 struct radv_buffer {
551 struct radv_device * device;
552 VkDeviceSize size;
553
554 VkBufferUsageFlags usage;
555
556 /* Set when bound */
557 struct radeon_winsys_bo * bo;
558 VkDeviceSize offset;
559 };
560
561
562 enum radv_cmd_dirty_bits {
563 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
564 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
565 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
566 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
567 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
568 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
569 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
570 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
571 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
572 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
573 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
574 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
575 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
576 };
577 typedef uint32_t radv_cmd_dirty_mask_t;
578
579 enum radv_cmd_flush_bits {
580 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
581 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
582 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
583 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
584 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
585 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
586 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
587 /* Framebuffer caches */
588 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
589 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
590 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
591 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
592 /* Engine synchronization. */
593 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
594 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
595 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
596 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
597
598 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
599 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
600 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
601 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
602 };
603
604 struct radv_vertex_binding {
605 struct radv_buffer * buffer;
606 VkDeviceSize offset;
607 };
608
609 struct radv_dynamic_state {
610 struct {
611 uint32_t count;
612 VkViewport viewports[MAX_VIEWPORTS];
613 } viewport;
614
615 struct {
616 uint32_t count;
617 VkRect2D scissors[MAX_SCISSORS];
618 } scissor;
619
620 float line_width;
621
622 struct {
623 float bias;
624 float clamp;
625 float slope;
626 } depth_bias;
627
628 float blend_constants[4];
629
630 struct {
631 float min;
632 float max;
633 } depth_bounds;
634
635 struct {
636 uint32_t front;
637 uint32_t back;
638 } stencil_compare_mask;
639
640 struct {
641 uint32_t front;
642 uint32_t back;
643 } stencil_write_mask;
644
645 struct {
646 uint32_t front;
647 uint32_t back;
648 } stencil_reference;
649 };
650
651 extern const struct radv_dynamic_state default_dynamic_state;
652
653 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
654 const struct radv_dynamic_state *src,
655 uint32_t copy_mask);
656 /**
657 * Attachment state when recording a renderpass instance.
658 *
659 * The clear value is valid only if there exists a pending clear.
660 */
661 struct radv_attachment_state {
662 VkImageAspectFlags pending_clear_aspects;
663 VkClearValue clear_value;
664 VkImageLayout current_layout;
665 };
666
667 struct radv_cmd_state {
668 uint32_t vb_dirty;
669 bool vertex_descriptors_dirty;
670 radv_cmd_dirty_mask_t dirty;
671
672 struct radv_pipeline * pipeline;
673 struct radv_pipeline * emitted_pipeline;
674 struct radv_pipeline * compute_pipeline;
675 struct radv_pipeline * emitted_compute_pipeline;
676 struct radv_framebuffer * framebuffer;
677 struct radv_render_pass * pass;
678 const struct radv_subpass * subpass;
679 struct radv_dynamic_state dynamic;
680 struct radv_vertex_binding vertex_bindings[MAX_VBS];
681 struct radv_descriptor_set * descriptors[MAX_SETS];
682 struct radv_attachment_state * attachments;
683 VkRect2D render_area;
684 struct radv_buffer * index_buffer;
685 uint32_t index_type;
686 uint32_t index_offset;
687 uint32_t last_primitive_reset_index;
688 enum radv_cmd_flush_bits flush_bits;
689 unsigned active_occlusion_queries;
690 float offset_scale;
691 };
692 struct radv_cmd_pool {
693 VkAllocationCallbacks alloc;
694 struct list_head cmd_buffers;
695 };
696
697 struct radv_cmd_buffer_upload {
698 uint8_t *map;
699 unsigned offset;
700 uint64_t size;
701 struct radeon_winsys_bo *upload_bo;
702 struct list_head list;
703 };
704
705 struct radv_cmd_buffer {
706 VK_LOADER_DATA _loader_data;
707
708 struct radv_device * device;
709
710 struct radv_cmd_pool * pool;
711 struct list_head pool_link;
712
713 VkCommandBufferUsageFlags usage_flags;
714 VkCommandBufferLevel level;
715 struct radeon_winsys_cs *cs;
716 struct radv_cmd_state state;
717
718 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
719 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
720 VkShaderStageFlags push_constant_stages;
721
722 struct radv_cmd_buffer_upload upload;
723
724 bool record_fail;
725 };
726
727 struct radv_image;
728
729 void si_init_config(struct radv_physical_device *physical_device,
730 struct radv_cmd_buffer *cmd_buffer);
731 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
732 int count, const VkViewport *viewports);
733 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
734 int count, const VkRect2D *scissors);
735 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
736 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
737 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
738 uint64_t src_va, uint64_t dest_va,
739 uint64_t size);
740 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
741 uint64_t size, unsigned value);
742 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
743 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
744 struct radv_descriptor_set *set,
745 unsigned idx);
746 bool
747 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
748 unsigned size,
749 unsigned alignment,
750 unsigned *out_offset,
751 void **ptr);
752 void
753 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
754 const struct radv_subpass *subpass,
755 bool transitions);
756 bool
757 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
758 unsigned size, unsigned alignmnet,
759 const void *data, unsigned *out_offset);
760 void
761 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
762 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
763 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
764 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
765 unsigned radv_cayman_get_maxdist(int log_samples);
766 void radv_device_init_msaa(struct radv_device *device);
767 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
768 struct radv_image *image,
769 VkClearDepthStencilValue ds_clear_value,
770 VkImageAspectFlags aspects);
771 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
772 struct radv_image *image,
773 int idx,
774 uint32_t color_values[2]);
775 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
776 struct radeon_winsys_bo *bo,
777 uint64_t offset, uint64_t size, uint32_t value);
778
779 /*
780 * Takes x,y,z as exact numbers of invocations, instead of blocks.
781 *
782 * Limitations: Can't call normal dispatch functions without binding or rebinding
783 * the compute pipeline.
784 */
785 void radv_unaligned_dispatch(
786 struct radv_cmd_buffer *cmd_buffer,
787 uint32_t x,
788 uint32_t y,
789 uint32_t z);
790
791 struct radv_event {
792 struct radeon_winsys_bo *bo;
793 uint64_t *map;
794 };
795
796 struct nir_shader;
797
798 struct radv_shader_module {
799 struct nir_shader * nir;
800 unsigned char sha1[20];
801 uint32_t size;
802 char data[0];
803 };
804
805 union ac_shader_variant_key;
806
807 void
808 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
809 const char *entrypoint,
810 const VkSpecializationInfo *spec_info,
811 const struct radv_pipeline_layout *layout,
812 const union ac_shader_variant_key *key);
813
814 static inline gl_shader_stage
815 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
816 {
817 assert(__builtin_popcount(vk_stage) == 1);
818 return ffs(vk_stage) - 1;
819 }
820
821 static inline VkShaderStageFlagBits
822 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
823 {
824 return (1 << mesa_stage);
825 }
826
827 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
828
829 #define radv_foreach_stage(stage, stage_bits) \
830 for (gl_shader_stage stage, \
831 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
832 stage = __builtin_ffs(__tmp) - 1, __tmp; \
833 __tmp &= ~(1 << (stage)))
834
835 struct radv_shader_variant {
836 uint32_t ref_count;
837
838 struct radeon_winsys_bo *bo;
839 struct ac_shader_config config;
840 struct ac_shader_variant_info info;
841 unsigned rsrc1;
842 unsigned rsrc2;
843 };
844
845 struct radv_depth_stencil_state {
846 uint32_t db_depth_control;
847 uint32_t db_stencil_control;
848 uint32_t db_render_control;
849 uint32_t db_render_override2;
850 };
851
852 struct radv_blend_state {
853 uint32_t cb_color_control;
854 uint32_t cb_target_mask;
855 uint32_t sx_mrt0_blend_opt[8];
856 uint32_t cb_blend_control[8];
857
858 uint32_t spi_shader_col_format;
859 uint32_t cb_shader_mask;
860 uint32_t db_alpha_to_mask;
861 };
862
863 unsigned radv_format_meta_fs_key(VkFormat format);
864
865 struct radv_raster_state {
866 uint32_t pa_cl_clip_cntl;
867 uint32_t pa_cl_vs_out_cntl;
868 uint32_t spi_interp_control;
869 uint32_t pa_su_point_size;
870 uint32_t pa_su_point_minmax;
871 uint32_t pa_su_line_cntl;
872 uint32_t pa_su_vtx_cntl;
873 uint32_t pa_su_sc_mode_cntl;
874 };
875
876 struct radv_multisample_state {
877 uint32_t db_eqaa;
878 uint32_t pa_sc_line_cntl;
879 uint32_t pa_sc_mode_cntl_0;
880 uint32_t pa_sc_mode_cntl_1;
881 uint32_t pa_sc_aa_config;
882 uint32_t pa_sc_aa_mask[2];
883 unsigned num_samples;
884 };
885
886 struct radv_pipeline {
887 struct radv_device * device;
888 uint32_t dynamic_state_mask;
889 struct radv_dynamic_state dynamic_state;
890
891 struct radv_pipeline_layout * layout;
892
893 bool needs_data_cache;
894
895 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
896 VkShaderStageFlags active_stages;
897
898 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
899 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
900 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
901 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
902 uint32_t num_vertex_attribs;
903 uint32_t binding_stride[MAX_VBS];
904
905 union {
906 struct {
907 struct radv_blend_state blend;
908 struct radv_depth_stencil_state ds;
909 struct radv_raster_state raster;
910 struct radv_multisample_state ms;
911 unsigned prim;
912 unsigned gs_out;
913 bool prim_restart_enable;
914 } graphics;
915 };
916 };
917
918 struct radv_graphics_pipeline_create_info {
919 bool use_rectlist;
920 bool db_depth_clear;
921 bool db_stencil_clear;
922 bool db_depth_disable_expclear;
923 bool db_stencil_disable_expclear;
924 bool db_flush_depth_inplace;
925 bool db_flush_stencil_inplace;
926 bool db_resummarize;
927 uint32_t custom_blend_mode;
928 };
929
930 VkResult
931 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
932 struct radv_pipeline_cache *cache,
933 const VkGraphicsPipelineCreateInfo *pCreateInfo,
934 const struct radv_graphics_pipeline_create_info *extra,
935 const VkAllocationCallbacks *alloc);
936
937 VkResult
938 radv_graphics_pipeline_create(VkDevice device,
939 VkPipelineCache cache,
940 const VkGraphicsPipelineCreateInfo *pCreateInfo,
941 const struct radv_graphics_pipeline_create_info *extra,
942 const VkAllocationCallbacks *alloc,
943 VkPipeline *pPipeline);
944
945 struct vk_format_description;
946 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
947 int first_non_void);
948 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
949 int first_non_void);
950 uint32_t radv_translate_colorformat(VkFormat format);
951 uint32_t radv_translate_color_numformat(VkFormat format,
952 const struct vk_format_description *desc,
953 int first_non_void);
954 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
955 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
956 uint32_t radv_translate_dbformat(VkFormat format);
957 uint32_t radv_translate_tex_dataformat(VkFormat format,
958 const struct vk_format_description *desc,
959 int first_non_void);
960 uint32_t radv_translate_tex_numformat(VkFormat format,
961 const struct vk_format_description *desc,
962 int first_non_void);
963 bool radv_format_pack_clear_color(VkFormat format,
964 uint32_t clear_vals[2],
965 VkClearColorValue *value);
966 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
967
968 struct radv_fmask_info {
969 uint64_t offset;
970 uint64_t size;
971 unsigned alignment;
972 unsigned pitch_in_pixels;
973 unsigned bank_height;
974 unsigned slice_tile_max;
975 unsigned tile_mode_index;
976 };
977
978 struct radv_cmask_info {
979 uint64_t offset;
980 uint64_t size;
981 unsigned alignment;
982 unsigned pitch;
983 unsigned height;
984 unsigned xalign;
985 unsigned yalign;
986 unsigned slice_tile_max;
987 unsigned base_address_reg;
988 };
989
990 struct r600_htile_info {
991 uint64_t offset;
992 uint64_t size;
993 unsigned pitch;
994 unsigned height;
995 unsigned xalign;
996 unsigned yalign;
997 };
998
999 struct radv_image {
1000 VkImageType type;
1001 /* The original VkFormat provided by the client. This may not match any
1002 * of the actual surface formats.
1003 */
1004 VkFormat vk_format;
1005 VkImageAspectFlags aspects;
1006 VkExtent3D extent;
1007 uint32_t levels;
1008 uint32_t array_size;
1009 uint32_t samples; /**< VkImageCreateInfo::samples */
1010 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1011 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1012
1013 VkDeviceSize size;
1014 uint32_t alignment;
1015
1016 /* Set when bound */
1017 struct radeon_winsys_bo *bo;
1018 VkDeviceSize offset;
1019 uint32_t dcc_offset;
1020 struct radeon_surf surface;
1021
1022 struct radv_fmask_info fmask;
1023 struct radv_cmask_info cmask;
1024 uint32_t clear_value_offset;
1025
1026 /* Depth buffer compression and fast clear. */
1027 struct r600_htile_info htile;
1028 };
1029
1030 bool radv_layout_has_htile(const struct radv_image *image,
1031 VkImageLayout layout);
1032 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1033 VkImageLayout layout);
1034 bool radv_layout_can_expclear(const struct radv_image *image,
1035 VkImageLayout layout);
1036 bool radv_layout_has_cmask(const struct radv_image *image,
1037 VkImageLayout layout);
1038 static inline uint32_t
1039 radv_get_layerCount(const struct radv_image *image,
1040 const VkImageSubresourceRange *range)
1041 {
1042 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1043 image->array_size - range->baseArrayLayer : range->layerCount;
1044 }
1045
1046 static inline uint32_t
1047 radv_get_levelCount(const struct radv_image *image,
1048 const VkImageSubresourceRange *range)
1049 {
1050 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1051 image->levels - range->baseMipLevel : range->levelCount;
1052 }
1053
1054 struct radeon_bo_metadata;
1055 void
1056 radv_init_metadata(struct radv_device *device,
1057 struct radv_image *image,
1058 struct radeon_bo_metadata *metadata);
1059
1060 struct radv_image_view {
1061 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1062 struct radeon_winsys_bo *bo;
1063
1064 VkImageViewType type;
1065 VkImageAspectFlags aspect_mask;
1066 VkFormat vk_format;
1067 uint32_t base_layer;
1068 uint32_t layer_count;
1069 uint32_t base_mip;
1070 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1071
1072 uint32_t descriptor[8];
1073 uint32_t fmask_descriptor[8];
1074 };
1075
1076 struct radv_image_create_info {
1077 const VkImageCreateInfo *vk_info;
1078 uint32_t stride;
1079 bool scanout;
1080 };
1081
1082 VkResult radv_image_create(VkDevice _device,
1083 const struct radv_image_create_info *info,
1084 const VkAllocationCallbacks* alloc,
1085 VkImage *pImage);
1086
1087 void radv_image_view_init(struct radv_image_view *view,
1088 struct radv_device *device,
1089 const VkImageViewCreateInfo* pCreateInfo,
1090 struct radv_cmd_buffer *cmd_buffer,
1091 VkImageUsageFlags usage_mask);
1092 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1093 struct radv_image *image, uint32_t micro_tile_mode);
1094 struct radv_buffer_view {
1095 struct radeon_winsys_bo *bo;
1096 VkFormat vk_format;
1097 uint64_t range; /**< VkBufferViewCreateInfo::range */
1098 uint32_t state[4];
1099 };
1100 void radv_buffer_view_init(struct radv_buffer_view *view,
1101 struct radv_device *device,
1102 const VkBufferViewCreateInfo* pCreateInfo,
1103 struct radv_cmd_buffer *cmd_buffer);
1104
1105 static inline struct VkExtent3D
1106 radv_sanitize_image_extent(const VkImageType imageType,
1107 const struct VkExtent3D imageExtent)
1108 {
1109 switch (imageType) {
1110 case VK_IMAGE_TYPE_1D:
1111 return (VkExtent3D) { imageExtent.width, 1, 1 };
1112 case VK_IMAGE_TYPE_2D:
1113 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1114 case VK_IMAGE_TYPE_3D:
1115 return imageExtent;
1116 default:
1117 unreachable("invalid image type");
1118 }
1119 }
1120
1121 static inline struct VkOffset3D
1122 radv_sanitize_image_offset(const VkImageType imageType,
1123 const struct VkOffset3D imageOffset)
1124 {
1125 switch (imageType) {
1126 case VK_IMAGE_TYPE_1D:
1127 return (VkOffset3D) { imageOffset.x, 0, 0 };
1128 case VK_IMAGE_TYPE_2D:
1129 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1130 case VK_IMAGE_TYPE_3D:
1131 return imageOffset;
1132 default:
1133 unreachable("invalid image type");
1134 }
1135 }
1136
1137 struct radv_sampler {
1138 uint32_t state[4];
1139 };
1140
1141 struct radv_color_buffer_info {
1142 uint32_t cb_color_base;
1143 uint32_t cb_color_pitch;
1144 uint32_t cb_color_slice;
1145 uint32_t cb_color_view;
1146 uint32_t cb_color_info;
1147 uint32_t cb_color_attrib;
1148 uint32_t cb_dcc_control;
1149 uint32_t cb_color_cmask;
1150 uint32_t cb_color_cmask_slice;
1151 uint32_t cb_color_fmask;
1152 uint32_t cb_color_fmask_slice;
1153 uint32_t cb_clear_value0;
1154 uint32_t cb_clear_value1;
1155 uint32_t cb_dcc_base;
1156 uint32_t micro_tile_mode;
1157 };
1158
1159 struct radv_ds_buffer_info {
1160 uint32_t db_depth_info;
1161 uint32_t db_z_info;
1162 uint32_t db_stencil_info;
1163 uint32_t db_z_read_base;
1164 uint32_t db_stencil_read_base;
1165 uint32_t db_z_write_base;
1166 uint32_t db_stencil_write_base;
1167 uint32_t db_depth_view;
1168 uint32_t db_depth_size;
1169 uint32_t db_depth_slice;
1170 uint32_t db_htile_surface;
1171 uint32_t db_htile_data_base;
1172 uint32_t pa_su_poly_offset_db_fmt_cntl;
1173 float offset_scale;
1174 };
1175
1176 struct radv_attachment_info {
1177 union {
1178 struct radv_color_buffer_info cb;
1179 struct radv_ds_buffer_info ds;
1180 };
1181 struct radv_image_view *attachment;
1182 };
1183
1184 struct radv_framebuffer {
1185 uint32_t width;
1186 uint32_t height;
1187 uint32_t layers;
1188
1189 uint32_t attachment_count;
1190 struct radv_attachment_info attachments[0];
1191 };
1192
1193 struct radv_subpass_barrier {
1194 VkPipelineStageFlags src_stage_mask;
1195 VkAccessFlags src_access_mask;
1196 VkAccessFlags dst_access_mask;
1197 };
1198
1199 struct radv_subpass {
1200 uint32_t input_count;
1201 VkAttachmentReference * input_attachments;
1202 uint32_t color_count;
1203 VkAttachmentReference * color_attachments;
1204 VkAttachmentReference * resolve_attachments;
1205 VkAttachmentReference depth_stencil_attachment;
1206
1207 /** Subpass has at least one resolve attachment */
1208 bool has_resolve;
1209
1210 struct radv_subpass_barrier start_barrier;
1211 };
1212
1213 struct radv_render_pass_attachment {
1214 VkFormat format;
1215 uint32_t samples;
1216 VkAttachmentLoadOp load_op;
1217 VkAttachmentLoadOp stencil_load_op;
1218 VkImageLayout initial_layout;
1219 VkImageLayout final_layout;
1220 };
1221
1222 struct radv_render_pass {
1223 uint32_t attachment_count;
1224 uint32_t subpass_count;
1225 VkAttachmentReference * subpass_attachments;
1226 struct radv_render_pass_attachment * attachments;
1227 struct radv_subpass_barrier end_barrier;
1228 struct radv_subpass subpasses[0];
1229 };
1230
1231 VkResult radv_device_init_meta(struct radv_device *device);
1232 void radv_device_finish_meta(struct radv_device *device);
1233
1234 struct radv_query_pool {
1235 struct radeon_winsys_bo *bo;
1236 uint32_t stride;
1237 uint32_t availability_offset;
1238 char *ptr;
1239 VkQueryType type;
1240 };
1241
1242 VkResult
1243 radv_temp_descriptor_set_create(struct radv_device *device,
1244 struct radv_cmd_buffer *cmd_buffer,
1245 VkDescriptorSetLayout _layout,
1246 VkDescriptorSet *_set);
1247
1248 void
1249 radv_temp_descriptor_set_destroy(struct radv_device *device,
1250 VkDescriptorSet _set);
1251 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1252 struct radv_image *image, uint32_t value);
1253 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1254 struct radv_image *image, uint32_t value);
1255 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1256 \
1257 static inline struct __radv_type * \
1258 __radv_type ## _from_handle(__VkType _handle) \
1259 { \
1260 return (struct __radv_type *) _handle; \
1261 } \
1262 \
1263 static inline __VkType \
1264 __radv_type ## _to_handle(struct __radv_type *_obj) \
1265 { \
1266 return (__VkType) _obj; \
1267 }
1268
1269 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1270 \
1271 static inline struct __radv_type * \
1272 __radv_type ## _from_handle(__VkType _handle) \
1273 { \
1274 return (struct __radv_type *)(uintptr_t) _handle; \
1275 } \
1276 \
1277 static inline __VkType \
1278 __radv_type ## _to_handle(struct __radv_type *_obj) \
1279 { \
1280 return (__VkType)(uintptr_t) _obj; \
1281 }
1282
1283 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1284 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1285
1286 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1287 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1288 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1289 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1290 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1291
1292 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1293 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1294 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1295 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1296 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1297 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1298 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1299 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1300 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1301 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1302 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1303 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1304 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1305 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1306 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1307 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1308 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1309 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1310 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1311
1312 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1313 \
1314 static inline const __VkType * \
1315 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1316 { \
1317 return (const __VkType *) __radv_obj; \
1318 }
1319
1320 #define RADV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1321 const __VkType *__vk_name = radv_common_to_ ## __VkType(__common_name)
1322
1323 RADV_DEFINE_STRUCT_CASTS(radv_common, VkMemoryBarrier)
1324 RADV_DEFINE_STRUCT_CASTS(radv_common, VkBufferMemoryBarrier)
1325 RADV_DEFINE_STRUCT_CASTS(radv_common, VkImageMemoryBarrier)
1326
1327
1328 #endif /* RADV_PRIVATE_H */