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radv: factor out radv_alloc_memory
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 enum radv_mem_flags_bits {
110 /* enable implicit synchronization when accessing the underlying bo */
111 RADV_MEM_IMPLICIT_SYNC = 1 << 0,
112 };
113
114 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115
116 static inline uint32_t
117 align_u32(uint32_t v, uint32_t a)
118 {
119 assert(a != 0 && a == (a & -a));
120 return (v + a - 1) & ~(a - 1);
121 }
122
123 static inline uint32_t
124 align_u32_npot(uint32_t v, uint32_t a)
125 {
126 return (v + a - 1) / a * a;
127 }
128
129 static inline uint64_t
130 align_u64(uint64_t v, uint64_t a)
131 {
132 assert(a != 0 && a == (a & -a));
133 return (v + a - 1) & ~(a - 1);
134 }
135
136 static inline int32_t
137 align_i32(int32_t v, int32_t a)
138 {
139 assert(a != 0 && a == (a & -a));
140 return (v + a - 1) & ~(a - 1);
141 }
142
143 /** Alignment must be a power of 2. */
144 static inline bool
145 radv_is_aligned(uintmax_t n, uintmax_t a)
146 {
147 assert(a == (a & -a));
148 return (n & (a - 1)) == 0;
149 }
150
151 static inline uint32_t
152 round_up_u32(uint32_t v, uint32_t a)
153 {
154 return (v + a - 1) / a;
155 }
156
157 static inline uint64_t
158 round_up_u64(uint64_t v, uint64_t a)
159 {
160 return (v + a - 1) / a;
161 }
162
163 static inline uint32_t
164 radv_minify(uint32_t n, uint32_t levels)
165 {
166 if (unlikely(n == 0))
167 return 0;
168 else
169 return MAX2(n >> levels, 1);
170 }
171 static inline float
172 radv_clamp_f(float f, float min, float max)
173 {
174 assert(min < max);
175
176 if (f > max)
177 return max;
178 else if (f < min)
179 return min;
180 else
181 return f;
182 }
183
184 static inline bool
185 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
186 {
187 if (*inout_mask & clear_mask) {
188 *inout_mask &= ~clear_mask;
189 return true;
190 } else {
191 return false;
192 }
193 }
194
195 #define for_each_bit(b, dword) \
196 for (uint32_t __dword = (dword); \
197 (b) = __builtin_ffs(__dword) - 1, __dword; \
198 __dword &= ~(1 << (b)))
199
200 #define typed_memcpy(dest, src, count) ({ \
201 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
202 memcpy((dest), (src), (count) * sizeof(*(src))); \
203 })
204
205 /* Whenever we generate an error, pass it through this function. Useful for
206 * debugging, where we can break on it. Only call at error site, not when
207 * propagating errors. Might be useful to plug in a stack trace here.
208 */
209
210 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
211
212 #ifdef DEBUG
213 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215 #else
216 #define vk_error(error) error
217 #define vk_errorf(error, format, ...) error
218 #endif
219
220 void __radv_finishme(const char *file, int line, const char *format, ...)
221 radv_printflike(3, 4);
222 void radv_loge(const char *format, ...) radv_printflike(1, 2);
223 void radv_loge_v(const char *format, va_list va);
224
225 /**
226 * Print a FINISHME message, including its source location.
227 */
228 #define radv_finishme(format, ...) \
229 do { \
230 static bool reported = false; \
231 if (!reported) { \
232 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
233 reported = true; \
234 } \
235 } while (0)
236
237 /* A non-fatal assert. Useful for debugging. */
238 #ifdef DEBUG
239 #define radv_assert(x) ({ \
240 if (unlikely(!(x))) \
241 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
242 })
243 #else
244 #define radv_assert(x)
245 #endif
246
247 #define stub_return(v) \
248 do { \
249 radv_finishme("stub %s", __func__); \
250 return (v); \
251 } while (0)
252
253 #define stub() \
254 do { \
255 radv_finishme("stub %s", __func__); \
256 return; \
257 } while (0)
258
259 void *radv_lookup_entrypoint(const char *name);
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 struct radv_instance * instance;
265
266 struct radeon_winsys *ws;
267 struct radeon_info rad_info;
268 char path[20];
269 const char * name;
270 uint8_t driver_uuid[VK_UUID_SIZE];
271 uint8_t device_uuid[VK_UUID_SIZE];
272 uint8_t cache_uuid[VK_UUID_SIZE];
273
274 int local_fd;
275 struct wsi_device wsi_device;
276
277 bool has_rbplus; /* if RB+ register exist */
278 bool rbplus_allowed; /* if RB+ is allowed */
279 bool has_clear_state;
280
281 /* This is the drivers on-disk cache used as a fallback as opposed to
282 * the pipeline cache defined by apps.
283 */
284 struct disk_cache * disk_cache;
285 };
286
287 struct radv_instance {
288 VK_LOADER_DATA _loader_data;
289
290 VkAllocationCallbacks alloc;
291
292 uint32_t apiVersion;
293 int physicalDeviceCount;
294 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
295
296 uint64_t debug_flags;
297 uint64_t perftest_flags;
298 };
299
300 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
301 void radv_finish_wsi(struct radv_physical_device *physical_device);
302
303 bool radv_instance_extension_supported(const char *name);
304 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
305 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
306 const char *name);
307
308 struct cache_entry;
309
310 struct radv_pipeline_cache {
311 struct radv_device * device;
312 pthread_mutex_t mutex;
313
314 uint32_t total_size;
315 uint32_t table_size;
316 uint32_t kernel_count;
317 struct cache_entry ** hash_table;
318 bool modified;
319
320 VkAllocationCallbacks alloc;
321 };
322
323 void
324 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
325 struct radv_device *device);
326 void
327 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
328 void
329 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
330 const void *data, size_t size);
331
332 struct radv_shader_variant;
333
334 bool
335 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
336 struct radv_pipeline_cache *cache,
337 const unsigned char *sha1,
338 struct radv_shader_variant **variants);
339
340 void
341 radv_pipeline_cache_insert_shaders(struct radv_device *device,
342 struct radv_pipeline_cache *cache,
343 const unsigned char *sha1,
344 struct radv_shader_variant **variants,
345 const void *const *codes,
346 const unsigned *code_sizes);
347
348 struct radv_meta_state {
349 VkAllocationCallbacks alloc;
350
351 struct radv_pipeline_cache cache;
352
353 /**
354 * Use array element `i` for images with `2^i` samples.
355 */
356 struct {
357 VkRenderPass render_pass[NUM_META_FS_KEYS];
358 VkPipeline color_pipelines[NUM_META_FS_KEYS];
359
360 VkRenderPass depthstencil_rp;
361 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
362 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
363 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
364 } clear[1 + MAX_SAMPLES_LOG2];
365
366 VkPipelineLayout clear_color_p_layout;
367 VkPipelineLayout clear_depth_p_layout;
368 struct {
369 VkRenderPass render_pass[NUM_META_FS_KEYS];
370
371 /** Pipeline that blits from a 1D image. */
372 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
373
374 /** Pipeline that blits from a 2D image. */
375 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
376
377 /** Pipeline that blits from a 3D image. */
378 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
379
380 VkRenderPass depth_only_rp;
381 VkPipeline depth_only_1d_pipeline;
382 VkPipeline depth_only_2d_pipeline;
383 VkPipeline depth_only_3d_pipeline;
384
385 VkRenderPass stencil_only_rp;
386 VkPipeline stencil_only_1d_pipeline;
387 VkPipeline stencil_only_2d_pipeline;
388 VkPipeline stencil_only_3d_pipeline;
389 VkPipelineLayout pipeline_layout;
390 VkDescriptorSetLayout ds_layout;
391 } blit;
392
393 struct {
394 VkRenderPass render_passes[NUM_META_FS_KEYS];
395
396 VkPipelineLayout p_layouts[2];
397 VkDescriptorSetLayout ds_layouts[2];
398 VkPipeline pipelines[2][NUM_META_FS_KEYS];
399
400 VkRenderPass depth_only_rp;
401 VkPipeline depth_only_pipeline[2];
402
403 VkRenderPass stencil_only_rp;
404 VkPipeline stencil_only_pipeline[2];
405 } blit2d;
406
407 struct {
408 VkPipelineLayout img_p_layout;
409 VkDescriptorSetLayout img_ds_layout;
410 VkPipeline pipeline;
411 } itob;
412 struct {
413 VkPipelineLayout img_p_layout;
414 VkDescriptorSetLayout img_ds_layout;
415 VkPipeline pipeline;
416 } btoi;
417 struct {
418 VkPipelineLayout img_p_layout;
419 VkDescriptorSetLayout img_ds_layout;
420 VkPipeline pipeline;
421 } itoi;
422 struct {
423 VkPipelineLayout img_p_layout;
424 VkDescriptorSetLayout img_ds_layout;
425 VkPipeline pipeline;
426 } cleari;
427
428 struct {
429 VkPipeline pipeline;
430 VkRenderPass pass;
431 } resolve;
432
433 struct {
434 VkDescriptorSetLayout ds_layout;
435 VkPipelineLayout p_layout;
436 struct {
437 VkPipeline pipeline;
438 VkPipeline i_pipeline;
439 VkPipeline srgb_pipeline;
440 } rc[MAX_SAMPLES_LOG2];
441 } resolve_compute;
442
443 struct {
444 VkDescriptorSetLayout ds_layout;
445 VkPipelineLayout p_layout;
446
447 struct {
448 VkRenderPass render_pass[NUM_META_FS_KEYS];
449 VkPipeline pipeline[NUM_META_FS_KEYS];
450 } rc[MAX_SAMPLES_LOG2];
451 } resolve_fragment;
452
453 struct {
454 VkPipeline decompress_pipeline;
455 VkPipeline resummarize_pipeline;
456 VkRenderPass pass;
457 } depth_decomp[1 + MAX_SAMPLES_LOG2];
458
459 struct {
460 VkPipeline cmask_eliminate_pipeline;
461 VkPipeline fmask_decompress_pipeline;
462 VkRenderPass pass;
463 } fast_clear_flush;
464
465 struct {
466 VkPipelineLayout fill_p_layout;
467 VkPipelineLayout copy_p_layout;
468 VkDescriptorSetLayout fill_ds_layout;
469 VkDescriptorSetLayout copy_ds_layout;
470 VkPipeline fill_pipeline;
471 VkPipeline copy_pipeline;
472 } buffer;
473
474 struct {
475 VkDescriptorSetLayout ds_layout;
476 VkPipelineLayout p_layout;
477 VkPipeline occlusion_query_pipeline;
478 VkPipeline pipeline_statistics_query_pipeline;
479 } query;
480 };
481
482 /* queue types */
483 #define RADV_QUEUE_GENERAL 0
484 #define RADV_QUEUE_COMPUTE 1
485 #define RADV_QUEUE_TRANSFER 2
486
487 #define RADV_MAX_QUEUE_FAMILIES 3
488
489 enum ring_type radv_queue_family_to_ring(int f);
490
491 struct radv_queue {
492 VK_LOADER_DATA _loader_data;
493 struct radv_device * device;
494 struct radeon_winsys_ctx *hw_ctx;
495 enum radeon_ctx_priority priority;
496 int queue_family_index;
497 int queue_idx;
498
499 uint32_t scratch_size;
500 uint32_t compute_scratch_size;
501 uint32_t esgs_ring_size;
502 uint32_t gsvs_ring_size;
503 bool has_tess_rings;
504 bool has_sample_positions;
505
506 struct radeon_winsys_bo *scratch_bo;
507 struct radeon_winsys_bo *descriptor_bo;
508 struct radeon_winsys_bo *compute_scratch_bo;
509 struct radeon_winsys_bo *esgs_ring_bo;
510 struct radeon_winsys_bo *gsvs_ring_bo;
511 struct radeon_winsys_bo *tess_factor_ring_bo;
512 struct radeon_winsys_bo *tess_offchip_ring_bo;
513 struct radeon_winsys_cs *initial_preamble_cs;
514 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
515 struct radeon_winsys_cs *continue_preamble_cs;
516 };
517
518 struct radv_device {
519 VK_LOADER_DATA _loader_data;
520
521 VkAllocationCallbacks alloc;
522
523 struct radv_instance * instance;
524 struct radeon_winsys *ws;
525
526 struct radv_meta_state meta_state;
527
528 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
529 int queue_count[RADV_MAX_QUEUE_FAMILIES];
530 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
531
532 bool llvm_supports_spill;
533 bool has_distributed_tess;
534 uint32_t tess_offchip_block_dw_size;
535 uint32_t scratch_waves;
536
537 uint32_t gs_table_depth;
538
539 /* MSAA sample locations.
540 * The first index is the sample index.
541 * The second index is the coordinate: X, Y. */
542 float sample_locations_1x[1][2];
543 float sample_locations_2x[2][2];
544 float sample_locations_4x[4][2];
545 float sample_locations_8x[8][2];
546 float sample_locations_16x[16][2];
547
548 /* CIK and later */
549 uint32_t gfx_init_size_dw;
550 struct radeon_winsys_bo *gfx_init;
551
552 struct radeon_winsys_bo *trace_bo;
553 uint32_t *trace_id_ptr;
554
555 struct radv_physical_device *physical_device;
556
557 /* Backup in-memory cache to be used if the app doesn't provide one */
558 struct radv_pipeline_cache * mem_cache;
559
560 /*
561 * use different counters so MSAA MRTs get consecutive surface indices,
562 * even if MASK is allocated in between.
563 */
564 uint32_t image_mrt_offset_counter;
565 uint32_t fmask_mrt_offset_counter;
566 struct list_head shader_slabs;
567 mtx_t shader_slab_mutex;
568
569 /* For detecting VM faults reported by dmesg. */
570 uint64_t dmesg_timestamp;
571 };
572
573 struct radv_device_memory {
574 struct radeon_winsys_bo *bo;
575 /* for dedicated allocations */
576 struct radv_image *image;
577 struct radv_buffer *buffer;
578 uint32_t type_index;
579 VkDeviceSize map_size;
580 void * map;
581 };
582
583
584 struct radv_descriptor_range {
585 uint64_t va;
586 uint32_t size;
587 };
588
589 struct radv_descriptor_set {
590 const struct radv_descriptor_set_layout *layout;
591 uint32_t size;
592
593 struct radeon_winsys_bo *bo;
594 uint64_t va;
595 uint32_t *mapped_ptr;
596 struct radv_descriptor_range *dynamic_descriptors;
597
598 struct list_head vram_list;
599
600 struct radeon_winsys_bo *descriptors[0];
601 };
602
603 struct radv_push_descriptor_set
604 {
605 struct radv_descriptor_set set;
606 uint32_t capacity;
607 };
608
609 struct radv_descriptor_pool {
610 struct radeon_winsys_bo *bo;
611 uint8_t *mapped_ptr;
612 uint64_t current_offset;
613 uint64_t size;
614
615 struct list_head vram_list;
616
617 uint8_t *host_memory_base;
618 uint8_t *host_memory_ptr;
619 uint8_t *host_memory_end;
620 };
621
622 struct radv_descriptor_update_template_entry {
623 VkDescriptorType descriptor_type;
624
625 /* The number of descriptors to update */
626 uint32_t descriptor_count;
627
628 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
629 uint32_t dst_offset;
630
631 /* In dwords. Not valid/used for dynamic descriptors */
632 uint32_t dst_stride;
633
634 uint32_t buffer_offset;
635
636 /* Only valid for combined image samplers and samplers */
637 uint16_t has_sampler;
638
639 /* In bytes */
640 size_t src_offset;
641 size_t src_stride;
642
643 /* For push descriptors */
644 const uint32_t *immutable_samplers;
645 };
646
647 struct radv_descriptor_update_template {
648 uint32_t entry_count;
649 struct radv_descriptor_update_template_entry entry[0];
650 };
651
652 struct radv_buffer {
653 struct radv_device * device;
654 VkDeviceSize size;
655
656 VkBufferUsageFlags usage;
657 VkBufferCreateFlags flags;
658
659 /* Set when bound */
660 struct radeon_winsys_bo * bo;
661 VkDeviceSize offset;
662 };
663
664
665 enum radv_cmd_dirty_bits {
666 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
667 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
668 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
669 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
670 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
671 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
672 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
673 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
674 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
675 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
676 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
677 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
678 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
679 };
680 typedef uint32_t radv_cmd_dirty_mask_t;
681
682 enum radv_cmd_flush_bits {
683 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
684 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
685 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
686 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
687 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
688 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
689 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
690 /* Same as above, but only writes back and doesn't invalidate */
691 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
692 /* Framebuffer caches */
693 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
694 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
695 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
696 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
697 /* Engine synchronization. */
698 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
699 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
700 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
701 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
702
703 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
704 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
705 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
706 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
707 };
708
709 struct radv_vertex_binding {
710 struct radv_buffer * buffer;
711 VkDeviceSize offset;
712 };
713
714 struct radv_viewport_state {
715 uint32_t count;
716 VkViewport viewports[MAX_VIEWPORTS];
717 };
718
719 struct radv_scissor_state {
720 uint32_t count;
721 VkRect2D scissors[MAX_SCISSORS];
722 };
723
724 struct radv_dynamic_state {
725 struct radv_viewport_state viewport;
726
727 struct radv_scissor_state scissor;
728
729 float line_width;
730
731 struct {
732 float bias;
733 float clamp;
734 float slope;
735 } depth_bias;
736
737 float blend_constants[4];
738
739 struct {
740 float min;
741 float max;
742 } depth_bounds;
743
744 struct {
745 uint32_t front;
746 uint32_t back;
747 } stencil_compare_mask;
748
749 struct {
750 uint32_t front;
751 uint32_t back;
752 } stencil_write_mask;
753
754 struct {
755 uint32_t front;
756 uint32_t back;
757 } stencil_reference;
758 };
759
760 extern const struct radv_dynamic_state default_dynamic_state;
761
762 const char *
763 radv_get_debug_option_name(int id);
764
765 const char *
766 radv_get_perftest_option_name(int id);
767
768 /**
769 * Attachment state when recording a renderpass instance.
770 *
771 * The clear value is valid only if there exists a pending clear.
772 */
773 struct radv_attachment_state {
774 VkImageAspectFlags pending_clear_aspects;
775 uint32_t cleared_views;
776 VkClearValue clear_value;
777 VkImageLayout current_layout;
778 };
779
780 struct radv_cmd_state {
781 bool vb_dirty;
782 radv_cmd_dirty_mask_t dirty;
783 bool push_descriptors_dirty;
784 bool predicating;
785
786 struct radv_pipeline * pipeline;
787 struct radv_pipeline * emitted_pipeline;
788 struct radv_pipeline * compute_pipeline;
789 struct radv_pipeline * emitted_compute_pipeline;
790 struct radv_framebuffer * framebuffer;
791 struct radv_render_pass * pass;
792 const struct radv_subpass * subpass;
793 struct radv_dynamic_state dynamic;
794 struct radv_vertex_binding vertex_bindings[MAX_VBS];
795 struct radv_descriptor_set * descriptors[MAX_SETS];
796 struct radv_attachment_state * attachments;
797 VkRect2D render_area;
798 uint32_t index_type;
799 uint32_t max_index_count;
800 uint64_t index_va;
801 int32_t last_primitive_reset_en;
802 uint32_t last_primitive_reset_index;
803 enum radv_cmd_flush_bits flush_bits;
804 unsigned active_occlusion_queries;
805 float offset_scale;
806 uint32_t descriptors_dirty;
807 uint32_t trace_id;
808 uint32_t last_ia_multi_vgt_param;
809 };
810
811 struct radv_cmd_pool {
812 VkAllocationCallbacks alloc;
813 struct list_head cmd_buffers;
814 struct list_head free_cmd_buffers;
815 uint32_t queue_family_index;
816 };
817
818 struct radv_cmd_buffer_upload {
819 uint8_t *map;
820 unsigned offset;
821 uint64_t size;
822 struct radeon_winsys_bo *upload_bo;
823 struct list_head list;
824 };
825
826 struct radv_cmd_buffer {
827 VK_LOADER_DATA _loader_data;
828
829 struct radv_device * device;
830
831 struct radv_cmd_pool * pool;
832 struct list_head pool_link;
833
834 VkCommandBufferUsageFlags usage_flags;
835 VkCommandBufferLevel level;
836 struct radeon_winsys_cs *cs;
837 struct radv_cmd_state state;
838 uint32_t queue_family_index;
839
840 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
841 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
842 VkShaderStageFlags push_constant_stages;
843 struct radv_push_descriptor_set push_descriptors;
844 struct radv_descriptor_set meta_push_descriptors;
845
846 struct radv_cmd_buffer_upload upload;
847
848 uint32_t scratch_size_needed;
849 uint32_t compute_scratch_size_needed;
850 uint32_t esgs_ring_size_needed;
851 uint32_t gsvs_ring_size_needed;
852 bool tess_rings_needed;
853 bool sample_positions_needed;
854
855 VkResult record_result;
856
857 int ring_offsets_idx; /* just used for verification */
858 uint32_t gfx9_fence_offset;
859 struct radeon_winsys_bo *gfx9_fence_bo;
860 uint32_t gfx9_fence_idx;
861 };
862
863 struct radv_image;
864
865 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
866
867 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
868 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
869
870 void cik_create_gfx_config(struct radv_device *device);
871
872 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
873 int count, const VkViewport *viewports);
874 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
875 int count, const VkRect2D *scissors,
876 const VkViewport *viewports, bool can_use_guardband);
877 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
878 bool instanced_draw, bool indirect_draw,
879 uint32_t draw_vertex_count);
880 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
881 bool predicated,
882 enum chip_class chip_class,
883 bool is_mec,
884 unsigned event, unsigned event_flags,
885 unsigned data_sel,
886 uint64_t va,
887 uint32_t old_fence,
888 uint32_t new_fence);
889
890 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
891 bool predicated,
892 uint64_t va, uint32_t ref,
893 uint32_t mask);
894 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
895 bool predicated,
896 enum chip_class chip_class,
897 uint32_t *fence_ptr, uint64_t va,
898 bool is_mec,
899 enum radv_cmd_flush_bits flush_bits);
900 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
901 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
902 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
903 uint64_t src_va, uint64_t dest_va,
904 uint64_t size);
905 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
906 unsigned size);
907 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
908 uint64_t size, unsigned value);
909 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
910 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
911 struct radv_descriptor_set *set,
912 unsigned idx);
913 bool
914 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
915 unsigned size,
916 unsigned alignment,
917 unsigned *out_offset,
918 void **ptr);
919 void
920 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
921 const struct radv_subpass *subpass,
922 bool transitions);
923 bool
924 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
925 unsigned size, unsigned alignmnet,
926 const void *data, unsigned *out_offset);
927 void
928 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
929 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
930 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
931 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
932 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
933 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
934 unsigned radv_cayman_get_maxdist(int log_samples);
935 void radv_device_init_msaa(struct radv_device *device);
936 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
937 struct radv_image *image,
938 VkClearDepthStencilValue ds_clear_value,
939 VkImageAspectFlags aspects);
940 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
941 struct radv_image *image,
942 int idx,
943 uint32_t color_values[2]);
944 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
945 struct radv_image *image,
946 bool value);
947 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
948 struct radeon_winsys_bo *bo,
949 uint64_t offset, uint64_t size, uint32_t value);
950 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
951 bool radv_get_memory_fd(struct radv_device *device,
952 struct radv_device_memory *memory,
953 int *pFD);
954 VkResult radv_alloc_memory(VkDevice _device,
955 const VkMemoryAllocateInfo* pAllocateInfo,
956 const VkAllocationCallbacks* pAllocator,
957 enum radv_mem_flags_bits flags,
958 VkDeviceMemory* pMem);
959
960 /*
961 * Takes x,y,z as exact numbers of invocations, instead of blocks.
962 *
963 * Limitations: Can't call normal dispatch functions without binding or rebinding
964 * the compute pipeline.
965 */
966 void radv_unaligned_dispatch(
967 struct radv_cmd_buffer *cmd_buffer,
968 uint32_t x,
969 uint32_t y,
970 uint32_t z);
971
972 struct radv_event {
973 struct radeon_winsys_bo *bo;
974 uint64_t *map;
975 };
976
977 struct radv_shader_module;
978 struct ac_shader_variant_key;
979
980 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
981 #define RADV_HASH_SHADER_SISCHED (1 << 1)
982 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
983 void
984 radv_hash_shaders(unsigned char *hash,
985 const VkPipelineShaderStageCreateInfo **stages,
986 const struct radv_pipeline_layout *layout,
987 const struct ac_shader_variant_key *keys,
988 uint32_t flags);
989
990 static inline gl_shader_stage
991 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
992 {
993 assert(__builtin_popcount(vk_stage) == 1);
994 return ffs(vk_stage) - 1;
995 }
996
997 static inline VkShaderStageFlagBits
998 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
999 {
1000 return (1 << mesa_stage);
1001 }
1002
1003 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1004
1005 #define radv_foreach_stage(stage, stage_bits) \
1006 for (gl_shader_stage stage, \
1007 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1008 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1009 __tmp &= ~(1 << (stage)))
1010
1011 struct radv_depth_stencil_state {
1012 uint32_t db_depth_control;
1013 uint32_t db_stencil_control;
1014 uint32_t db_render_control;
1015 uint32_t db_render_override2;
1016 };
1017
1018 struct radv_blend_state {
1019 uint32_t cb_color_control;
1020 uint32_t cb_target_mask;
1021 uint32_t sx_mrt_blend_opt[8];
1022 uint32_t cb_blend_control[8];
1023
1024 uint32_t spi_shader_col_format;
1025 uint32_t cb_shader_mask;
1026 uint32_t db_alpha_to_mask;
1027 };
1028
1029 unsigned radv_format_meta_fs_key(VkFormat format);
1030
1031 struct radv_raster_state {
1032 uint32_t pa_cl_clip_cntl;
1033 uint32_t spi_interp_control;
1034 uint32_t pa_su_vtx_cntl;
1035 uint32_t pa_su_sc_mode_cntl;
1036 };
1037
1038 struct radv_multisample_state {
1039 uint32_t db_eqaa;
1040 uint32_t pa_sc_line_cntl;
1041 uint32_t pa_sc_mode_cntl_0;
1042 uint32_t pa_sc_mode_cntl_1;
1043 uint32_t pa_sc_aa_config;
1044 uint32_t pa_sc_aa_mask[2];
1045 unsigned num_samples;
1046 };
1047
1048 struct radv_prim_vertex_count {
1049 uint8_t min;
1050 uint8_t incr;
1051 };
1052
1053 struct radv_tessellation_state {
1054 uint32_t ls_hs_config;
1055 uint32_t tcs_in_layout;
1056 uint32_t tcs_out_layout;
1057 uint32_t tcs_out_offsets;
1058 uint32_t offchip_layout;
1059 unsigned num_patches;
1060 unsigned lds_size;
1061 unsigned num_tcs_input_cp;
1062 uint32_t tf_param;
1063 };
1064
1065 struct radv_gs_state {
1066 uint32_t vgt_gs_onchip_cntl;
1067 uint32_t vgt_gs_max_prims_per_subgroup;
1068 uint32_t vgt_esgs_ring_itemsize;
1069 uint32_t lds_size;
1070 };
1071
1072 struct radv_vertex_elements_info {
1073 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1074 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1075 uint32_t binding[MAX_VERTEX_ATTRIBS];
1076 uint32_t offset[MAX_VERTEX_ATTRIBS];
1077 uint32_t count;
1078 };
1079
1080 #define SI_GS_PER_ES 128
1081
1082 struct radv_pipeline {
1083 struct radv_device * device;
1084 uint32_t dynamic_state_mask;
1085 struct radv_dynamic_state dynamic_state;
1086
1087 struct radv_pipeline_layout * layout;
1088
1089 bool needs_data_cache;
1090 bool need_indirect_descriptor_sets;
1091 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1092 struct radv_shader_variant *gs_copy_shader;
1093 VkShaderStageFlags active_stages;
1094
1095 struct radv_vertex_elements_info vertex_elements;
1096
1097 uint32_t binding_stride[MAX_VBS];
1098
1099 union {
1100 struct {
1101 struct radv_blend_state blend;
1102 struct radv_depth_stencil_state ds;
1103 struct radv_raster_state raster;
1104 struct radv_multisample_state ms;
1105 struct radv_tessellation_state tess;
1106 struct radv_gs_state gs;
1107 uint32_t db_shader_control;
1108 uint32_t shader_z_format;
1109 unsigned prim;
1110 unsigned gs_out;
1111 uint32_t vgt_gs_mode;
1112 bool vgt_primitiveid_en;
1113 bool prim_restart_enable;
1114 bool partial_es_wave;
1115 uint8_t primgroup_size;
1116 unsigned esgs_ring_size;
1117 unsigned gsvs_ring_size;
1118 uint32_t ps_input_cntl[32];
1119 uint32_t ps_input_cntl_num;
1120 uint32_t pa_cl_vs_out_cntl;
1121 uint32_t vgt_shader_stages_en;
1122 uint32_t vtx_base_sgpr;
1123 uint32_t base_ia_multi_vgt_param;
1124 bool wd_switch_on_eop;
1125 bool ia_switch_on_eoi;
1126 bool partial_vs_wave;
1127 uint8_t vtx_emit_num;
1128 uint32_t vtx_reuse_depth;
1129 struct radv_prim_vertex_count prim_vertex_count;
1130 bool can_use_guardband;
1131 } graphics;
1132 };
1133
1134 unsigned max_waves;
1135 unsigned scratch_bytes_per_wave;
1136 };
1137
1138 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1139 {
1140 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1141 }
1142
1143 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1144 {
1145 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1146 }
1147
1148 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1149 gl_shader_stage stage,
1150 int idx);
1151
1152 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1153
1154 struct radv_graphics_pipeline_create_info {
1155 bool use_rectlist;
1156 bool db_depth_clear;
1157 bool db_stencil_clear;
1158 bool db_depth_disable_expclear;
1159 bool db_stencil_disable_expclear;
1160 bool db_flush_depth_inplace;
1161 bool db_flush_stencil_inplace;
1162 bool db_resummarize;
1163 uint32_t custom_blend_mode;
1164 };
1165
1166 VkResult
1167 radv_graphics_pipeline_create(VkDevice device,
1168 VkPipelineCache cache,
1169 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1170 const struct radv_graphics_pipeline_create_info *extra,
1171 const VkAllocationCallbacks *alloc,
1172 VkPipeline *pPipeline);
1173
1174 struct vk_format_description;
1175 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1176 int first_non_void);
1177 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1178 int first_non_void);
1179 uint32_t radv_translate_colorformat(VkFormat format);
1180 uint32_t radv_translate_color_numformat(VkFormat format,
1181 const struct vk_format_description *desc,
1182 int first_non_void);
1183 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1184 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1185 uint32_t radv_translate_dbformat(VkFormat format);
1186 uint32_t radv_translate_tex_dataformat(VkFormat format,
1187 const struct vk_format_description *desc,
1188 int first_non_void);
1189 uint32_t radv_translate_tex_numformat(VkFormat format,
1190 const struct vk_format_description *desc,
1191 int first_non_void);
1192 bool radv_format_pack_clear_color(VkFormat format,
1193 uint32_t clear_vals[2],
1194 VkClearColorValue *value);
1195 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1196 bool radv_dcc_formats_compatible(VkFormat format1,
1197 VkFormat format2);
1198
1199 struct radv_fmask_info {
1200 uint64_t offset;
1201 uint64_t size;
1202 unsigned alignment;
1203 unsigned pitch_in_pixels;
1204 unsigned bank_height;
1205 unsigned slice_tile_max;
1206 unsigned tile_mode_index;
1207 unsigned tile_swizzle;
1208 };
1209
1210 struct radv_cmask_info {
1211 uint64_t offset;
1212 uint64_t size;
1213 unsigned alignment;
1214 unsigned slice_tile_max;
1215 unsigned base_address_reg;
1216 };
1217
1218 struct radv_image {
1219 VkImageType type;
1220 /* The original VkFormat provided by the client. This may not match any
1221 * of the actual surface formats.
1222 */
1223 VkFormat vk_format;
1224 VkImageAspectFlags aspects;
1225 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1226 struct ac_surf_info info;
1227 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1228 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1229
1230 VkDeviceSize size;
1231 uint32_t alignment;
1232
1233 unsigned queue_family_mask;
1234 bool exclusive;
1235 bool shareable;
1236
1237 /* Set when bound */
1238 struct radeon_winsys_bo *bo;
1239 VkDeviceSize offset;
1240 uint64_t dcc_offset;
1241 uint64_t htile_offset;
1242 bool tc_compatible_htile;
1243 struct radeon_surf surface;
1244
1245 struct radv_fmask_info fmask;
1246 struct radv_cmask_info cmask;
1247 uint64_t clear_value_offset;
1248 uint64_t dcc_pred_offset;
1249 };
1250
1251 /* Whether the image has a htile that is known consistent with the contents of
1252 * the image. */
1253 bool radv_layout_has_htile(const struct radv_image *image,
1254 VkImageLayout layout,
1255 unsigned queue_mask);
1256
1257 /* Whether the image has a htile that is known consistent with the contents of
1258 * the image and is allowed to be in compressed form.
1259 *
1260 * If this is false reads that don't use the htile should be able to return
1261 * correct results.
1262 */
1263 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1264 VkImageLayout layout,
1265 unsigned queue_mask);
1266
1267 bool radv_layout_can_fast_clear(const struct radv_image *image,
1268 VkImageLayout layout,
1269 unsigned queue_mask);
1270
1271 static inline bool
1272 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1273 {
1274 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1275 }
1276
1277 static inline bool
1278 radv_htile_enabled(const struct radv_image *image, unsigned level)
1279 {
1280 return image->surface.htile_size && level == 0;
1281 }
1282
1283 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1284
1285 static inline uint32_t
1286 radv_get_layerCount(const struct radv_image *image,
1287 const VkImageSubresourceRange *range)
1288 {
1289 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1290 image->info.array_size - range->baseArrayLayer : range->layerCount;
1291 }
1292
1293 static inline uint32_t
1294 radv_get_levelCount(const struct radv_image *image,
1295 const VkImageSubresourceRange *range)
1296 {
1297 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1298 image->info.levels - range->baseMipLevel : range->levelCount;
1299 }
1300
1301 struct radeon_bo_metadata;
1302 void
1303 radv_init_metadata(struct radv_device *device,
1304 struct radv_image *image,
1305 struct radeon_bo_metadata *metadata);
1306
1307 struct radv_image_view {
1308 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1309 struct radeon_winsys_bo *bo;
1310
1311 VkImageViewType type;
1312 VkImageAspectFlags aspect_mask;
1313 VkFormat vk_format;
1314 uint32_t base_layer;
1315 uint32_t layer_count;
1316 uint32_t base_mip;
1317 uint32_t level_count;
1318 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1319
1320 uint32_t descriptor[8];
1321 uint32_t fmask_descriptor[8];
1322
1323 /* Descriptor for use as a storage image as opposed to a sampled image.
1324 * This has a few differences for cube maps (e.g. type).
1325 */
1326 uint32_t storage_descriptor[8];
1327 uint32_t storage_fmask_descriptor[8];
1328 };
1329
1330 struct radv_image_create_info {
1331 const VkImageCreateInfo *vk_info;
1332 bool scanout;
1333 };
1334
1335 VkResult radv_image_create(VkDevice _device,
1336 const struct radv_image_create_info *info,
1337 const VkAllocationCallbacks* alloc,
1338 VkImage *pImage);
1339
1340 void radv_image_view_init(struct radv_image_view *view,
1341 struct radv_device *device,
1342 const VkImageViewCreateInfo* pCreateInfo);
1343
1344 struct radv_buffer_view {
1345 struct radeon_winsys_bo *bo;
1346 VkFormat vk_format;
1347 uint64_t range; /**< VkBufferViewCreateInfo::range */
1348 uint32_t state[4];
1349 };
1350 void radv_buffer_view_init(struct radv_buffer_view *view,
1351 struct radv_device *device,
1352 const VkBufferViewCreateInfo* pCreateInfo);
1353
1354 static inline struct VkExtent3D
1355 radv_sanitize_image_extent(const VkImageType imageType,
1356 const struct VkExtent3D imageExtent)
1357 {
1358 switch (imageType) {
1359 case VK_IMAGE_TYPE_1D:
1360 return (VkExtent3D) { imageExtent.width, 1, 1 };
1361 case VK_IMAGE_TYPE_2D:
1362 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1363 case VK_IMAGE_TYPE_3D:
1364 return imageExtent;
1365 default:
1366 unreachable("invalid image type");
1367 }
1368 }
1369
1370 static inline struct VkOffset3D
1371 radv_sanitize_image_offset(const VkImageType imageType,
1372 const struct VkOffset3D imageOffset)
1373 {
1374 switch (imageType) {
1375 case VK_IMAGE_TYPE_1D:
1376 return (VkOffset3D) { imageOffset.x, 0, 0 };
1377 case VK_IMAGE_TYPE_2D:
1378 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1379 case VK_IMAGE_TYPE_3D:
1380 return imageOffset;
1381 default:
1382 unreachable("invalid image type");
1383 }
1384 }
1385
1386 static inline bool
1387 radv_image_extent_compare(const struct radv_image *image,
1388 const VkExtent3D *extent)
1389 {
1390 if (extent->width != image->info.width ||
1391 extent->height != image->info.height ||
1392 extent->depth != image->info.depth)
1393 return false;
1394 return true;
1395 }
1396
1397 struct radv_sampler {
1398 uint32_t state[4];
1399 };
1400
1401 struct radv_color_buffer_info {
1402 uint64_t cb_color_base;
1403 uint64_t cb_color_cmask;
1404 uint64_t cb_color_fmask;
1405 uint64_t cb_dcc_base;
1406 uint32_t cb_color_pitch;
1407 uint32_t cb_color_slice;
1408 uint32_t cb_color_view;
1409 uint32_t cb_color_info;
1410 uint32_t cb_color_attrib;
1411 uint32_t cb_color_attrib2;
1412 uint32_t cb_dcc_control;
1413 uint32_t cb_color_cmask_slice;
1414 uint32_t cb_color_fmask_slice;
1415 uint32_t cb_clear_value0;
1416 uint32_t cb_clear_value1;
1417 uint32_t micro_tile_mode;
1418 uint32_t gfx9_epitch;
1419 };
1420
1421 struct radv_ds_buffer_info {
1422 uint64_t db_z_read_base;
1423 uint64_t db_stencil_read_base;
1424 uint64_t db_z_write_base;
1425 uint64_t db_stencil_write_base;
1426 uint64_t db_htile_data_base;
1427 uint32_t db_depth_info;
1428 uint32_t db_z_info;
1429 uint32_t db_stencil_info;
1430 uint32_t db_depth_view;
1431 uint32_t db_depth_size;
1432 uint32_t db_depth_slice;
1433 uint32_t db_htile_surface;
1434 uint32_t pa_su_poly_offset_db_fmt_cntl;
1435 uint32_t db_z_info2;
1436 uint32_t db_stencil_info2;
1437 float offset_scale;
1438 };
1439
1440 struct radv_attachment_info {
1441 union {
1442 struct radv_color_buffer_info cb;
1443 struct radv_ds_buffer_info ds;
1444 };
1445 struct radv_image_view *attachment;
1446 };
1447
1448 struct radv_framebuffer {
1449 uint32_t width;
1450 uint32_t height;
1451 uint32_t layers;
1452
1453 uint32_t attachment_count;
1454 struct radv_attachment_info attachments[0];
1455 };
1456
1457 struct radv_subpass_barrier {
1458 VkPipelineStageFlags src_stage_mask;
1459 VkAccessFlags src_access_mask;
1460 VkAccessFlags dst_access_mask;
1461 };
1462
1463 struct radv_subpass {
1464 uint32_t input_count;
1465 uint32_t color_count;
1466 VkAttachmentReference * input_attachments;
1467 VkAttachmentReference * color_attachments;
1468 VkAttachmentReference * resolve_attachments;
1469 VkAttachmentReference depth_stencil_attachment;
1470
1471 /** Subpass has at least one resolve attachment */
1472 bool has_resolve;
1473
1474 struct radv_subpass_barrier start_barrier;
1475
1476 uint32_t view_mask;
1477 };
1478
1479 struct radv_render_pass_attachment {
1480 VkFormat format;
1481 uint32_t samples;
1482 VkAttachmentLoadOp load_op;
1483 VkAttachmentLoadOp stencil_load_op;
1484 VkImageLayout initial_layout;
1485 VkImageLayout final_layout;
1486 uint32_t view_mask;
1487 };
1488
1489 struct radv_render_pass {
1490 uint32_t attachment_count;
1491 uint32_t subpass_count;
1492 VkAttachmentReference * subpass_attachments;
1493 struct radv_render_pass_attachment * attachments;
1494 struct radv_subpass_barrier end_barrier;
1495 struct radv_subpass subpasses[0];
1496 };
1497
1498 VkResult radv_device_init_meta(struct radv_device *device);
1499 void radv_device_finish_meta(struct radv_device *device);
1500
1501 struct radv_query_pool {
1502 struct radeon_winsys_bo *bo;
1503 uint32_t stride;
1504 uint32_t availability_offset;
1505 char *ptr;
1506 VkQueryType type;
1507 uint32_t pipeline_stats_mask;
1508 };
1509
1510 struct radv_semaphore {
1511 /* use a winsys sem for non-exportable */
1512 struct radeon_winsys_sem *sem;
1513 uint32_t syncobj;
1514 uint32_t temp_syncobj;
1515 };
1516
1517 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1518 int num_wait_sems,
1519 const VkSemaphore *wait_sems,
1520 int num_signal_sems,
1521 const VkSemaphore *signal_sems);
1522 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1523
1524 void
1525 radv_update_descriptor_sets(struct radv_device *device,
1526 struct radv_cmd_buffer *cmd_buffer,
1527 VkDescriptorSet overrideSet,
1528 uint32_t descriptorWriteCount,
1529 const VkWriteDescriptorSet *pDescriptorWrites,
1530 uint32_t descriptorCopyCount,
1531 const VkCopyDescriptorSet *pDescriptorCopies);
1532
1533 void
1534 radv_update_descriptor_set_with_template(struct radv_device *device,
1535 struct radv_cmd_buffer *cmd_buffer,
1536 struct radv_descriptor_set *set,
1537 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1538 const void *pData);
1539
1540 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1541 VkPipelineBindPoint pipelineBindPoint,
1542 VkPipelineLayout _layout,
1543 uint32_t set,
1544 uint32_t descriptorWriteCount,
1545 const VkWriteDescriptorSet *pDescriptorWrites);
1546
1547 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1548 struct radv_image *image, uint32_t value);
1549 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1550 struct radv_image *image, uint32_t value);
1551
1552 struct radv_fence {
1553 struct radeon_winsys_fence *fence;
1554 bool submitted;
1555 bool signalled;
1556 };
1557
1558 struct radeon_winsys_sem;
1559
1560 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1561 \
1562 static inline struct __radv_type * \
1563 __radv_type ## _from_handle(__VkType _handle) \
1564 { \
1565 return (struct __radv_type *) _handle; \
1566 } \
1567 \
1568 static inline __VkType \
1569 __radv_type ## _to_handle(struct __radv_type *_obj) \
1570 { \
1571 return (__VkType) _obj; \
1572 }
1573
1574 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1575 \
1576 static inline struct __radv_type * \
1577 __radv_type ## _from_handle(__VkType _handle) \
1578 { \
1579 return (struct __radv_type *)(uintptr_t) _handle; \
1580 } \
1581 \
1582 static inline __VkType \
1583 __radv_type ## _to_handle(struct __radv_type *_obj) \
1584 { \
1585 return (__VkType)(uintptr_t) _obj; \
1586 }
1587
1588 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1589 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1590
1591 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1592 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1593 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1594 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1595 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1596
1597 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1598 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1599 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1600 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1601 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1602 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1603 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1604 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1605 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1606 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1607 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1608 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1609 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1610 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1611 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1612 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1613 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1614 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1615 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1616 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1617 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1618
1619 #endif /* RADV_PRIVATE_H */