src/amd/vulkan/radv_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_PRIVATE_H
  29 #define RADV_PRIVATE_H
  30
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <stdbool.h>
  34 #include <pthread.h>
  35 #include <assert.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <valgrind.h>
  40 #include <memcheck.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x)
  44 #endif
  45
  46 #include <amdgpu.h>
  47 #include "compiler/shader_enums.h"
  48 #include "util/macros.h"
  49 #include "util/list.h"
  50 #include "util/vk_alloc.h"
  51 #include "main/macros.h"
  52
  53 #include "radv_radeon_winsys.h"
  54 #include "ac_binary.h"
  55 #include "ac_nir_to_llvm.h"
  56 #include "radv_descriptor_set.h"
  57
  58 #include <llvm-c/TargetMachine.h>
  59
  60 /* Pre-declarations needed for WSI entrypoints */
  61 struct wl_surface;
  62 struct wl_display;
  63 typedef struct xcb_connection_t xcb_connection_t;
  64 typedef uint32_t xcb_visualid_t;
  65 typedef uint32_t xcb_window_t;
  66
  67 #include <vulkan/vulkan.h>
  68 #include <vulkan/vulkan_intel.h>
  69 #include <vulkan/vk_icd.h>
  70
  71 #include "radv_entrypoints.h"
  72
  73 #include "wsi_common.h"
  74
  75 #define MAX_VBS         32
  76 #define MAX_VERTEX_ATTRIBS 32
  77 #define MAX_RTS          8
  78 #define MAX_VIEWPORTS   16
  79 #define MAX_SCISSORS    16
  80 #define MAX_PUSH_CONSTANTS_SIZE 128
  81 #define MAX_DYNAMIC_BUFFERS 16
  82 #define MAX_IMAGES 8
  83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
  84 #define NUM_META_FS_KEYS 11
  85
  86 #define NUM_DEPTH_CLEAR_PIPELINES 3
  87
  88 #define radv_noreturn __attribute__((__noreturn__))
  89 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
  90
  91 static inline uint32_t
  92 align_u32(uint32_t v, uint32_t a)
  93 {
  94         assert(a != 0 && a == (a & -a));
  95         return (v + a - 1) & ~(a - 1);
  96 }
  97
  98 static inline uint32_t
  99 align_u32_npot(uint32_t v, uint32_t a)
 100 {
 101         return (v + a - 1) / a * a;
 102 }
 103
 104 static inline uint64_t
 105 align_u64(uint64_t v, uint64_t a)
 106 {
 107         assert(a != 0 && a == (a & -a));
 108         return (v + a - 1) & ~(a - 1);
 109 }
 110
 111 static inline int32_t
 112 align_i32(int32_t v, int32_t a)
 113 {
 114         assert(a != 0 && a == (a & -a));
 115         return (v + a - 1) & ~(a - 1);
 116 }
 117
 118 /** Alignment must be a power of 2. */
 119 static inline bool
 120 radv_is_aligned(uintmax_t n, uintmax_t a)
 121 {
 122         assert(a == (a & -a));
 123         return (n & (a - 1)) == 0;
 124 }
 125
 126 static inline uint32_t
 127 round_up_u32(uint32_t v, uint32_t a)
 128 {
 129         return (v + a - 1) / a;
 130 }
 131
 132 static inline uint64_t
 133 round_up_u64(uint64_t v, uint64_t a)
 134 {
 135         return (v + a - 1) / a;
 136 }
 137
 138 static inline uint32_t
 139 radv_minify(uint32_t n, uint32_t levels)
 140 {
 141         if (unlikely(n == 0))
 142                 return 0;
 143         else
 144                 return MAX2(n >> levels, 1);
 145 }
 146 static inline float
 147 radv_clamp_f(float f, float min, float max)
 148 {
 149         assert(min < max);
 150
 151         if (f > max)
 152                 return max;
 153         else if (f < min)
 154                 return min;
 155         else
 156                 return f;
 157 }
 158
 159 static inline bool
 160 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
 161 {
 162         if (*inout_mask & clear_mask) {
 163                 *inout_mask &= ~clear_mask;
 164                 return true;
 165         } else {
 166                 return false;
 167         }
 168 }
 169
 170 #define for_each_bit(b, dword)                          \
 171         for (uint32_t __dword = (dword);                \
 172              (b) = __builtin_ffs(__dword) - 1, __dword; \
 173              __dword &= ~(1 << (b)))
 174
 175 #define typed_memcpy(dest, src, count) ({                               \
 176                         static_assert(sizeof(*src) == sizeof(*dest), ""); \
 177                         memcpy((dest), (src), (count) * sizeof(*(src))); \
 178                 })
 179
 180 #define zero(x) (memset(&(x), 0, sizeof(x)))
 181
 182 /* Define no kernel as 1, since that's an illegal offset for a kernel */
 183 #define NO_KERNEL 1
 184
 185 struct radv_common {
 186         VkStructureType                             sType;
 187         const void*                                 pNext;
 188 };
 189
 190 /* Whenever we generate an error, pass it through this function. Useful for
 191  * debugging, where we can break on it. Only call at error site, not when
 192  * propagating errors. Might be useful to plug in a stack trace here.
 193  */
 194
 195 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
 196
 197 #ifdef DEBUG
 198 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
 199 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
 200 #else
 201 #define vk_error(error) error
 202 #define vk_errorf(error, format, ...) error
 203 #endif
 204
 205 void __radv_finishme(const char *file, int line, const char *format, ...)
 206         radv_printflike(3, 4);
 207 void radv_loge(const char *format, ...) radv_printflike(1, 2);
 208 void radv_loge_v(const char *format, va_list va);
 209
 210 /**
 211  * Print a FINISHME message, including its source location.
 212  */
 213 #define radv_finishme(format, ...)                                      \
 214         __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
 215
 216 /* A non-fatal assert.  Useful for debugging. */
 217 #ifdef DEBUG
 218 #define radv_assert(x) ({                                               \
 219                         if (unlikely(!(x)))                             \
 220                                 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
 221                 })
 222 #else
 223 #define radv_assert(x)
 224 #endif
 225
 226 void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
 227 void radv_abortfv(const char *format, va_list va) radv_noreturn;
 228
 229 #define stub_return(v)                                  \
 230         do {                                            \
 231                 radv_finishme("stub %s", __func__);     \
 232                 return (v);                             \
 233         } while (0)
 234
 235 #define stub()                                          \
 236         do {                                            \
 237                 radv_finishme("stub %s", __func__);     \
 238                 return;                                 \
 239         } while (0)
 240
 241 void *radv_resolve_entrypoint(uint32_t index);
 242 void *radv_lookup_entrypoint(const char *name);
 243
 244 extern struct radv_dispatch_table dtable;
 245
 246 struct radv_physical_device {
 247         VK_LOADER_DATA                              _loader_data;
 248
 249         struct radv_instance *                       instance;
 250
 251         struct radeon_winsys *ws;
 252         struct radeon_info rad_info;
 253         uint32_t                                    chipset_id;
 254         char                                        path[20];
 255         const char *                                name;
 256         uint64_t                                    aperture_size;
 257         int                                         cmd_parser_version;
 258         uint32_t                    pci_vendor_id;
 259         uint32_t                    pci_device_id;
 260
 261         uint8_t                                     uuid[VK_UUID_SIZE];
 262
 263         struct wsi_device                       wsi_device;
 264 };
 265
 266 struct radv_instance {
 267         VK_LOADER_DATA                              _loader_data;
 268
 269         VkAllocationCallbacks                       alloc;
 270
 271         uint32_t                                    apiVersion;
 272         int                                         physicalDeviceCount;
 273         struct radv_physical_device                  physicalDevice;
 274 };
 275
 276 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
 277 void radv_finish_wsi(struct radv_physical_device *physical_device);
 278
 279 struct cache_entry;
 280
 281 struct radv_pipeline_cache {
 282         struct radv_device *                          device;
 283         pthread_mutex_t                              mutex;
 284
 285         uint32_t                                     total_size;
 286         uint32_t                                     table_size;
 287         uint32_t                                     kernel_count;
 288         struct cache_entry **                        hash_table;
 289         bool                                         modified;
 290
 291         VkAllocationCallbacks                        alloc;
 292 };
 293
 294 void
 295 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 296                          struct radv_device *device);
 297 void
 298 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
 299 void
 300 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 301                          const void *data, size_t size);
 302
 303 struct radv_shader_variant *
 304 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
 305                                                struct radv_pipeline_cache *cache,
 306                                                const unsigned char *sha1);
 307
 308 struct radv_shader_variant *
 309 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
 310                                   const unsigned char *sha1,
 311                                   struct radv_shader_variant *variant,
 312                                   const void *code, unsigned code_size);
 313
 314 void radv_shader_variant_destroy(struct radv_device *device,
 315                                  struct radv_shader_variant *variant);
 316
 317 struct radv_meta_state {
 318         VkAllocationCallbacks alloc;
 319
 320         struct radv_pipeline_cache cache;
 321
 322         /**
 323          * Use array element `i` for images with `2^i` samples.
 324          */
 325         struct {
 326                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 327                 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
 328
 329                 VkRenderPass depth_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
 330                 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 331                 VkRenderPass stencil_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
 332                 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 333                 VkRenderPass depthstencil_rp[NUM_DEPTH_CLEAR_PIPELINES];
 334                 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 335         } clear[1 + MAX_SAMPLES_LOG2];
 336
 337         struct {
 338                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 339
 340                 /** Pipeline that blits from a 1D image. */
 341                 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
 342
 343                 /** Pipeline that blits from a 2D image. */
 344                 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
 345
 346                 /** Pipeline that blits from a 3D image. */
 347                 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 348
 349                 VkRenderPass depth_only_rp;
 350                 VkPipeline depth_only_1d_pipeline;
 351                 VkPipeline depth_only_2d_pipeline;
 352                 VkPipeline depth_only_3d_pipeline;
 353
 354                 VkRenderPass stencil_only_rp;
 355                 VkPipeline stencil_only_1d_pipeline;
 356                 VkPipeline stencil_only_2d_pipeline;
 357                 VkPipeline stencil_only_3d_pipeline;
 358                 VkPipelineLayout                          pipeline_layout;
 359                 VkDescriptorSetLayout                     ds_layout;
 360         } blit;
 361
 362         struct {
 363                 VkRenderPass render_passes[NUM_META_FS_KEYS];
 364
 365                 VkPipelineLayout p_layouts[2];
 366                 VkDescriptorSetLayout ds_layouts[2];
 367                 VkPipeline pipelines[2][NUM_META_FS_KEYS];
 368
 369                 VkRenderPass depth_only_rp;
 370                 VkPipeline depth_only_pipeline[2];
 371
 372                 VkRenderPass stencil_only_rp;
 373                 VkPipeline stencil_only_pipeline[2];
 374         } blit2d;
 375
 376         struct {
 377                 VkPipelineLayout                          img_p_layout;
 378                 VkDescriptorSetLayout                     img_ds_layout;
 379                 VkPipeline pipeline;
 380         } itob;
 381         struct {
 382                 VkRenderPass render_pass;
 383                 VkPipelineLayout                          img_p_layout;
 384                 VkDescriptorSetLayout                     img_ds_layout;
 385                 VkPipeline pipeline;
 386         } btoi;
 387
 388         struct {
 389                 VkPipeline                                pipeline;
 390                 VkRenderPass                              pass;
 391         } resolve;
 392
 393         struct {
 394                 VkDescriptorSetLayout                     ds_layout;
 395                 VkPipelineLayout                          p_layout;
 396                 struct {
 397                         VkPipeline                                pipeline;
 398                         VkPipeline                                i_pipeline;
 399                 } rc[MAX_SAMPLES_LOG2];
 400         } resolve_compute;
 401
 402         struct {
 403                 VkPipeline                                decompress_pipeline;
 404                 VkPipeline                                resummarize_pipeline;
 405                 VkRenderPass                              pass;
 406         } depth_decomp;
 407
 408         struct {
 409                 VkPipeline                                cmask_eliminate_pipeline;
 410                 VkPipeline                                fmask_decompress_pipeline;
 411                 VkRenderPass                              pass;
 412         } fast_clear_flush;
 413
 414         struct {
 415                 VkPipelineLayout fill_p_layout;
 416                 VkPipelineLayout copy_p_layout;
 417                 VkDescriptorSetLayout fill_ds_layout;
 418                 VkDescriptorSetLayout copy_ds_layout;
 419                 VkPipeline fill_pipeline;
 420                 VkPipeline copy_pipeline;
 421         } buffer;
 422 };
 423
 424 struct radv_queue {
 425         VK_LOADER_DATA                              _loader_data;
 426
 427         struct radv_device *                         device;
 428
 429         struct radv_state_pool *                     pool;
 430 };
 431
 432 struct radv_device {
 433         VK_LOADER_DATA                              _loader_data;
 434
 435         VkAllocationCallbacks                       alloc;
 436
 437         struct radv_instance *                       instance;
 438         struct radeon_winsys *ws;
 439         struct radeon_winsys_ctx *hw_ctx;
 440
 441         struct radv_meta_state                       meta_state;
 442         struct radv_queue                            queue;
 443         struct radeon_winsys_cs *empty_cs;
 444
 445         bool allow_fast_clears;
 446         bool allow_dcc;
 447         bool shader_stats_dump;
 448
 449         /* MSAA sample locations.
 450          * The first index is the sample index.
 451          * The second index is the coordinate: X, Y. */
 452         float sample_locations_1x[1][2];
 453         float sample_locations_2x[2][2];
 454         float sample_locations_4x[4][2];
 455         float sample_locations_8x[8][2];
 456         float sample_locations_16x[16][2];
 457 };
 458
 459 struct radv_device_memory {
 460         struct radeon_winsys_bo                      *bo;
 461         uint32_t                                     type_index;
 462         VkDeviceSize                                 map_size;
 463         void *                                       map;
 464 };
 465
 466
 467 struct radv_descriptor_range {
 468         uint64_t va;
 469         uint32_t size;
 470 };
 471
 472 struct radv_descriptor_set {
 473         const struct radv_descriptor_set_layout *layout;
 474         struct list_head descriptor_pool;
 475         uint32_t size;
 476
 477         struct radv_buffer_view *buffer_views;
 478         struct radeon_winsys_bo *bo;
 479         uint64_t va;
 480         uint32_t *mapped_ptr;
 481         struct radv_descriptor_range *dynamic_descriptors;
 482         struct radeon_winsys_bo *descriptors[0];
 483 };
 484
 485 struct radv_descriptor_pool_free_node {
 486         int next;
 487         uint32_t offset;
 488         uint32_t size;
 489 };
 490
 491 struct radv_descriptor_pool {
 492         struct list_head descriptor_sets;
 493
 494         struct radeon_winsys_bo *bo;
 495         uint8_t *mapped_ptr;
 496         uint64_t current_offset;
 497         uint64_t size;
 498
 499         int free_list;
 500         int full_list;
 501         uint32_t max_sets;
 502         struct radv_descriptor_pool_free_node free_nodes[];
 503 };
 504
 505 struct radv_buffer {
 506         struct radv_device *                          device;
 507         VkDeviceSize                                 size;
 508
 509         VkBufferUsageFlags                           usage;
 510
 511         /* Set when bound */
 512         struct radeon_winsys_bo *                      bo;
 513         VkDeviceSize                                 offset;
 514 };
 515
 516
 517 enum radv_cmd_dirty_bits {
 518         RADV_CMD_DIRTY_DYNAMIC_VIEWPORT                  = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
 519         RADV_CMD_DIRTY_DYNAMIC_SCISSOR                   = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
 520         RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH                = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
 521         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS                = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
 522         RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS           = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
 523         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS              = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
 524         RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
 525         RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
 526         RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
 527         RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 9) - 1,
 528         RADV_CMD_DIRTY_PIPELINE                          = 1 << 9,
 529         RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 10,
 530         RADV_CMD_DIRTY_RENDER_TARGETS                    = 1 << 11,
 531 };
 532 typedef uint32_t radv_cmd_dirty_mask_t;
 533
 534 enum radv_cmd_flush_bits {
 535         RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
 536         /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
 537         RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
 538         /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
 539         RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
 540         /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
 541         RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
 542         /* Framebuffer caches */
 543         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
 544         RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
 545         RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
 546         RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
 547         /* Engine synchronization. */
 548         RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
 549         RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
 550         RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
 551         RADV_CMD_FLAG_VGT_FLUSH        = 1 << 11,
 552
 553         RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 554                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
 555                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 556                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
 557 };
 558
 559 struct radv_vertex_binding {
 560         struct radv_buffer *                          buffer;
 561         VkDeviceSize                                 offset;
 562 };
 563
 564 struct radv_dynamic_state {
 565         struct {
 566                 uint32_t                                  count;
 567                 VkViewport                                viewports[MAX_VIEWPORTS];
 568         } viewport;
 569
 570         struct {
 571                 uint32_t                                  count;
 572                 VkRect2D                                  scissors[MAX_SCISSORS];
 573         } scissor;
 574
 575         float                                        line_width;
 576
 577         struct {
 578                 float                                     bias;
 579                 float                                     clamp;
 580                 float                                     slope;
 581         } depth_bias;
 582
 583         float                                        blend_constants[4];
 584
 585         struct {
 586                 float                                     min;
 587                 float                                     max;
 588         } depth_bounds;
 589
 590         struct {
 591                 uint32_t                                  front;
 592                 uint32_t                                  back;
 593         } stencil_compare_mask;
 594
 595         struct {
 596                 uint32_t                                  front;
 597                 uint32_t                                  back;
 598         } stencil_write_mask;
 599
 600         struct {
 601                 uint32_t                                  front;
 602                 uint32_t                                  back;
 603         } stencil_reference;
 604 };
 605
 606 extern const struct radv_dynamic_state default_dynamic_state;
 607
 608 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
 609                              const struct radv_dynamic_state *src,
 610                              uint32_t copy_mask);
 611 /**
 612  * Attachment state when recording a renderpass instance.
 613  *
 614  * The clear value is valid only if there exists a pending clear.
 615  */
 616 struct radv_attachment_state {
 617         VkImageAspectFlags                           pending_clear_aspects;
 618         VkClearValue                                 clear_value;
 619         VkImageLayout                                current_layout;
 620 };
 621
 622 struct radv_cmd_state {
 623         uint32_t                                      vb_dirty;
 624         bool                                          vertex_descriptors_dirty;
 625         radv_cmd_dirty_mask_t                         dirty;
 626
 627         struct radv_pipeline *                        pipeline;
 628         struct radv_pipeline *                        emitted_pipeline;
 629         struct radv_pipeline *                        compute_pipeline;
 630         struct radv_pipeline *                        emitted_compute_pipeline;
 631         struct radv_framebuffer *                     framebuffer;
 632         struct radv_render_pass *                     pass;
 633         const struct radv_subpass *                         subpass;
 634         struct radv_dynamic_state                     dynamic;
 635         struct radv_vertex_binding                    vertex_bindings[MAX_VBS];
 636         struct radv_descriptor_set *                  descriptors[MAX_SETS];
 637         struct radv_attachment_state *                attachments;
 638         VkRect2D                                     render_area;
 639         struct radv_buffer *                         index_buffer;
 640         uint32_t                                     index_type;
 641         uint32_t                                     index_offset;
 642         uint32_t                                     last_primitive_reset_index;
 643         enum radv_cmd_flush_bits                     flush_bits;
 644         unsigned                                     active_occlusion_queries;
 645         float                                        offset_scale;
 646 };
 647 struct radv_cmd_pool {
 648         VkAllocationCallbacks                        alloc;
 649         struct list_head                             cmd_buffers;
 650 };
 651
 652 struct radv_cmd_buffer_upload {
 653         uint8_t *map;
 654         unsigned offset;
 655         uint64_t size;
 656         struct radeon_winsys_bo *upload_bo;
 657         struct list_head list;
 658 };
 659
 660 struct radv_cmd_buffer {
 661         VK_LOADER_DATA                               _loader_data;
 662
 663         struct radv_device *                          device;
 664
 665         struct radv_cmd_pool *                        pool;
 666         struct list_head                             pool_link;
 667
 668         VkCommandBufferUsageFlags                    usage_flags;
 669         VkCommandBufferLevel                         level;
 670         struct radeon_winsys_cs *cs;
 671         struct radv_cmd_state state;
 672
 673         uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
 674         uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
 675         VkShaderStageFlags push_constant_stages;
 676
 677         struct radv_cmd_buffer_upload upload;
 678
 679         bool record_fail;
 680 };
 681
 682 struct radv_image;
 683
 684 void si_init_config(struct radv_physical_device *physical_device,
 685                     struct radv_cmd_buffer *cmd_buffer);
 686 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
 687                        int count, const VkViewport *viewports);
 688 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
 689                        int count, const VkRect2D *scissors);
 690 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
 691 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
 692 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
 693                            uint64_t src_va, uint64_t dest_va,
 694                            uint64_t size);
 695 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 696                             uint64_t size, unsigned value);
 697 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
 698 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 699                               struct radv_descriptor_set *set,
 700                               unsigned idx);
 701 bool
 702 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 703                              unsigned size,
 704                              unsigned alignment,
 705                              unsigned *out_offset,
 706                              void **ptr);
 707 void
 708 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
 709                             const struct radv_subpass *subpass,
 710                             bool transitions);
 711 bool
 712 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 713                             unsigned size, unsigned alignmnet,
 714                             const void *data, unsigned *out_offset);
 715 void
 716 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
 717 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
 718 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
 719 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 720 unsigned radv_cayman_get_maxdist(int log_samples);
 721 void radv_device_init_msaa(struct radv_device *device);
 722 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 723                                struct radv_image *image,
 724                                VkClearDepthStencilValue ds_clear_value,
 725                                VkImageAspectFlags aspects);
 726 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 727                                struct radv_image *image,
 728                                int idx,
 729                                uint32_t color_values[2]);
 730 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
 731                       struct radeon_winsys_bo *bo,
 732                       uint64_t offset, uint64_t size, uint32_t value);
 733
 734 /*
 735  * Takes x,y,z as exact numbers of invocations, instead of blocks.
 736  *
 737  * Limitations: Can't call normal dispatch functions without binding or rebinding
 738  *              the compute pipeline.
 739  */
 740 void radv_unaligned_dispatch(
 741         struct radv_cmd_buffer                      *cmd_buffer,
 742         uint32_t                                    x,
 743         uint32_t                                    y,
 744         uint32_t                                    z);
 745
 746 struct radv_event {
 747         struct radeon_winsys_bo *bo;
 748         uint64_t *map;
 749 };
 750
 751 struct nir_shader;
 752
 753 struct radv_shader_module {
 754         struct nir_shader *                          nir;
 755         unsigned char                                sha1[20];
 756         uint32_t                                     size;
 757         char                                         data[0];
 758 };
 759
 760 union ac_shader_variant_key;
 761
 762 void
 763 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
 764                  const char *entrypoint,
 765                  const VkSpecializationInfo *spec_info,
 766                  const struct radv_pipeline_layout *layout,
 767                  const union ac_shader_variant_key *key);
 768
 769 static inline gl_shader_stage
 770 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
 771 {
 772         assert(__builtin_popcount(vk_stage) == 1);
 773         return ffs(vk_stage) - 1;
 774 }
 775
 776 static inline VkShaderStageFlagBits
 777 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
 778 {
 779         return (1 << mesa_stage);
 780 }
 781
 782 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
 783
 784 #define radv_foreach_stage(stage, stage_bits)                           \
 785         for (gl_shader_stage stage,                                     \
 786                      __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
 787              stage = __builtin_ffs(__tmp) - 1, __tmp;                   \
 788              __tmp &= ~(1 << (stage)))
 789
 790 struct radv_shader_variant {
 791         uint32_t ref_count;
 792
 793         struct radeon_winsys_bo *bo;
 794         struct ac_shader_config config;
 795         struct ac_shader_variant_info info;
 796         unsigned rsrc1;
 797         unsigned rsrc2;
 798         uint32_t code_size;
 799 };
 800
 801 struct radv_depth_stencil_state {
 802         uint32_t db_depth_control;
 803         uint32_t db_stencil_control;
 804         uint32_t db_render_control;
 805         uint32_t db_render_override2;
 806 };
 807
 808 struct radv_blend_state {
 809         uint32_t cb_color_control;
 810         uint32_t cb_target_mask;
 811         uint32_t sx_mrt0_blend_opt[8];
 812         uint32_t cb_blend_control[8];
 813
 814         uint32_t spi_shader_col_format;
 815         uint32_t cb_shader_mask;
 816         uint32_t db_alpha_to_mask;
 817 };
 818
 819 unsigned radv_format_meta_fs_key(VkFormat format);
 820
 821 struct radv_raster_state {
 822         uint32_t pa_cl_clip_cntl;
 823         uint32_t pa_cl_vs_out_cntl;
 824         uint32_t spi_interp_control;
 825         uint32_t pa_su_point_size;
 826         uint32_t pa_su_point_minmax;
 827         uint32_t pa_su_line_cntl;
 828         uint32_t pa_su_vtx_cntl;
 829         uint32_t pa_su_sc_mode_cntl;
 830 };
 831
 832 struct radv_multisample_state {
 833         uint32_t db_eqaa;
 834         uint32_t pa_sc_line_cntl;
 835         uint32_t pa_sc_mode_cntl_0;
 836         uint32_t pa_sc_mode_cntl_1;
 837         uint32_t pa_sc_aa_config;
 838         uint32_t pa_sc_aa_mask[2];
 839         unsigned num_samples;
 840 };
 841
 842 struct radv_pipeline {
 843         struct radv_device *                          device;
 844         uint32_t                                     dynamic_state_mask;
 845         struct radv_dynamic_state                     dynamic_state;
 846
 847         struct radv_pipeline_layout *                 layout;
 848
 849         bool                                         needs_data_cache;
 850
 851         struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
 852         VkShaderStageFlags                           active_stages;
 853
 854         uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
 855         uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
 856         uint32_t va_binding[MAX_VERTEX_ATTRIBS];
 857         uint32_t va_offset[MAX_VERTEX_ATTRIBS];
 858         uint32_t num_vertex_attribs;
 859         uint32_t                                     binding_stride[MAX_VBS];
 860
 861         union {
 862                 struct {
 863                         struct radv_blend_state blend;
 864                         struct radv_depth_stencil_state ds;
 865                         struct radv_raster_state raster;
 866                         struct radv_multisample_state ms;
 867                         unsigned prim;
 868                         unsigned gs_out;
 869                         bool prim_restart_enable;
 870                 } graphics;
 871         };
 872 };
 873
 874 struct radv_graphics_pipeline_create_info {
 875         bool use_rectlist;
 876         bool db_depth_clear;
 877         bool db_stencil_clear;
 878         bool db_depth_disable_expclear;
 879         bool db_stencil_disable_expclear;
 880         bool db_flush_depth_inplace;
 881         bool db_flush_stencil_inplace;
 882         bool db_resummarize;
 883         uint32_t custom_blend_mode;
 884 };
 885
 886 VkResult
 887 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
 888                    struct radv_pipeline_cache *cache,
 889                    const VkGraphicsPipelineCreateInfo *pCreateInfo,
 890                    const struct radv_graphics_pipeline_create_info *extra,
 891                    const VkAllocationCallbacks *alloc);
 892
 893 VkResult
 894 radv_graphics_pipeline_create(VkDevice device,
 895                               VkPipelineCache cache,
 896                               const VkGraphicsPipelineCreateInfo *pCreateInfo,
 897                               const struct radv_graphics_pipeline_create_info *extra,
 898                               const VkAllocationCallbacks *alloc,
 899                               VkPipeline *pPipeline);
 900
 901 struct vk_format_description;
 902 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
 903                                           int first_non_void);
 904 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
 905                                          int first_non_void);
 906 uint32_t radv_translate_colorformat(VkFormat format);
 907 uint32_t radv_translate_color_numformat(VkFormat format,
 908                                         const struct vk_format_description *desc,
 909                                         int first_non_void);
 910 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
 911 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
 912 uint32_t radv_translate_dbformat(VkFormat format);
 913 uint32_t radv_translate_tex_dataformat(VkFormat format,
 914                                        const struct vk_format_description *desc,
 915                                        int first_non_void);
 916 uint32_t radv_translate_tex_numformat(VkFormat format,
 917                                       const struct vk_format_description *desc,
 918                                       int first_non_void);
 919 bool radv_format_pack_clear_color(VkFormat format,
 920                                   uint32_t clear_vals[2],
 921                                   VkClearColorValue *value);
 922 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
 923
 924 struct radv_fmask_info {
 925         uint64_t offset;
 926         uint64_t size;
 927         unsigned alignment;
 928         unsigned pitch_in_pixels;
 929         unsigned bank_height;
 930         unsigned slice_tile_max;
 931         unsigned tile_mode_index;
 932 };
 933
 934 struct radv_cmask_info {
 935         uint64_t offset;
 936         uint64_t size;
 937         unsigned alignment;
 938         unsigned slice_tile_max;
 939         unsigned base_address_reg;
 940 };
 941
 942 struct r600_htile_info {
 943         uint64_t offset;
 944         uint64_t size;
 945         unsigned pitch;
 946         unsigned height;
 947         unsigned xalign;
 948         unsigned yalign;
 949 };
 950
 951 struct radv_image {
 952         VkImageType type;
 953         /* The original VkFormat provided by the client.  This may not match any
 954          * of the actual surface formats.
 955          */
 956         VkFormat vk_format;
 957         VkImageAspectFlags aspects;
 958         VkExtent3D extent;
 959         uint32_t levels;
 960         uint32_t array_size;
 961         uint32_t samples; /**< VkImageCreateInfo::samples */
 962         VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
 963         VkImageTiling tiling; /** VkImageCreateInfo::tiling */
 964
 965         VkDeviceSize size;
 966         uint32_t alignment;
 967
 968         /* Set when bound */
 969         struct radeon_winsys_bo *bo;
 970         VkDeviceSize offset;
 971         uint32_t dcc_offset;
 972         struct radeon_surf surface;
 973
 974         struct radv_fmask_info fmask;
 975         struct radv_cmask_info cmask;
 976         uint32_t clear_value_offset;
 977
 978         /* Depth buffer compression and fast clear. */
 979         struct r600_htile_info htile;
 980 };
 981
 982 bool radv_layout_has_htile(const struct radv_image *image,
 983                            VkImageLayout layout);
 984 bool radv_layout_is_htile_compressed(const struct radv_image *image,
 985                                      VkImageLayout layout);
 986 bool radv_layout_can_expclear(const struct radv_image *image,
 987                               VkImageLayout layout);
 988 bool radv_layout_has_cmask(const struct radv_image *image,
 989                            VkImageLayout layout);
 990 static inline uint32_t
 991 radv_get_layerCount(const struct radv_image *image,
 992                     const VkImageSubresourceRange *range)
 993 {
 994         return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
 995                 image->array_size - range->baseArrayLayer : range->layerCount;
 996 }
 997
 998 static inline uint32_t
 999 radv_get_levelCount(const struct radv_image *image,
1000                     const VkImageSubresourceRange *range)
1001 {
1002         return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1003                 image->levels - range->baseMipLevel : range->levelCount;
1004 }
1005
1006 struct radeon_bo_metadata;
1007 void
1008 radv_init_metadata(struct radv_device *device,
1009                    struct radv_image *image,
1010                    struct radeon_bo_metadata *metadata);
1011
1012 struct radv_image_view {
1013         struct radv_image *image; /**< VkImageViewCreateInfo::image */
1014         struct radeon_winsys_bo *bo;
1015
1016         VkImageViewType type;
1017         VkImageAspectFlags aspect_mask;
1018         VkFormat vk_format;
1019         uint32_t base_layer;
1020         uint32_t layer_count;
1021         uint32_t base_mip;
1022         VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1023
1024         uint32_t descriptor[8];
1025         uint32_t fmask_descriptor[8];
1026 };
1027
1028 struct radv_image_create_info {
1029         const VkImageCreateInfo *vk_info;
1030         uint32_t stride;
1031         bool scanout;
1032 };
1033
1034 VkResult radv_image_create(VkDevice _device,
1035                            const struct radv_image_create_info *info,
1036                            const VkAllocationCallbacks* alloc,
1037                            VkImage *pImage);
1038
1039 void radv_image_view_init(struct radv_image_view *view,
1040                           struct radv_device *device,
1041                           const VkImageViewCreateInfo* pCreateInfo,
1042                           struct radv_cmd_buffer *cmd_buffer,
1043                           VkImageUsageFlags usage_mask);
1044 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1045                                             struct radv_image *image, uint32_t micro_tile_mode);
1046 struct radv_buffer_view {
1047         struct radeon_winsys_bo *bo;
1048         VkFormat vk_format;
1049         uint64_t range; /**< VkBufferViewCreateInfo::range */
1050         uint32_t state[4];
1051 };
1052 void radv_buffer_view_init(struct radv_buffer_view *view,
1053                            struct radv_device *device,
1054                            const VkBufferViewCreateInfo* pCreateInfo,
1055                            struct radv_cmd_buffer *cmd_buffer);
1056
1057 static inline struct VkExtent3D
1058 radv_sanitize_image_extent(const VkImageType imageType,
1059                            const struct VkExtent3D imageExtent)
1060 {
1061         switch (imageType) {
1062         case VK_IMAGE_TYPE_1D:
1063                 return (VkExtent3D) { imageExtent.width, 1, 1 };
1064         case VK_IMAGE_TYPE_2D:
1065                 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1066         case VK_IMAGE_TYPE_3D:
1067                 return imageExtent;
1068         default:
1069                 unreachable("invalid image type");
1070         }
1071 }
1072
1073 static inline struct VkOffset3D
1074 radv_sanitize_image_offset(const VkImageType imageType,
1075                            const struct VkOffset3D imageOffset)
1076 {
1077         switch (imageType) {
1078         case VK_IMAGE_TYPE_1D:
1079                 return (VkOffset3D) { imageOffset.x, 0, 0 };
1080         case VK_IMAGE_TYPE_2D:
1081                 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1082         case VK_IMAGE_TYPE_3D:
1083                 return imageOffset;
1084         default:
1085                 unreachable("invalid image type");
1086         }
1087 }
1088
1089 struct radv_sampler {
1090         uint32_t state[4];
1091 };
1092
1093 struct radv_color_buffer_info {
1094         uint32_t cb_color_base;
1095         uint32_t cb_color_pitch;
1096         uint32_t cb_color_slice;
1097         uint32_t cb_color_view;
1098         uint32_t cb_color_info;
1099         uint32_t cb_color_attrib;
1100         uint32_t cb_dcc_control;
1101         uint32_t cb_color_cmask;
1102         uint32_t cb_color_cmask_slice;
1103         uint32_t cb_color_fmask;
1104         uint32_t cb_color_fmask_slice;
1105         uint32_t cb_clear_value0;
1106         uint32_t cb_clear_value1;
1107         uint32_t cb_dcc_base;
1108         uint32_t micro_tile_mode;
1109 };
1110
1111 struct radv_ds_buffer_info {
1112         uint32_t db_depth_info;
1113         uint32_t db_z_info;
1114         uint32_t db_stencil_info;
1115         uint32_t db_z_read_base;
1116         uint32_t db_stencil_read_base;
1117         uint32_t db_z_write_base;
1118         uint32_t db_stencil_write_base;
1119         uint32_t db_depth_view;
1120         uint32_t db_depth_size;
1121         uint32_t db_depth_slice;
1122         uint32_t db_htile_surface;
1123         uint32_t db_htile_data_base;
1124         uint32_t pa_su_poly_offset_db_fmt_cntl;
1125         float offset_scale;
1126 };
1127
1128 struct radv_attachment_info {
1129         union {
1130                 struct radv_color_buffer_info cb;
1131                 struct radv_ds_buffer_info ds;
1132         };
1133         struct radv_image_view *attachment;
1134 };
1135
1136 struct radv_framebuffer {
1137         uint32_t                                     width;
1138         uint32_t                                     height;
1139         uint32_t                                     layers;
1140
1141         uint32_t                                     attachment_count;
1142         struct radv_attachment_info                  attachments[0];
1143 };
1144
1145 struct radv_subpass_barrier {
1146         VkPipelineStageFlags src_stage_mask;
1147         VkAccessFlags        src_access_mask;
1148         VkAccessFlags        dst_access_mask;
1149 };
1150
1151 struct radv_subpass {
1152         uint32_t                                     input_count;
1153         VkAttachmentReference *                      input_attachments;
1154         uint32_t                                     color_count;
1155         VkAttachmentReference *                      color_attachments;
1156         VkAttachmentReference *                      resolve_attachments;
1157         VkAttachmentReference                        depth_stencil_attachment;
1158
1159         /** Subpass has at least one resolve attachment */
1160         bool                                         has_resolve;
1161
1162         struct radv_subpass_barrier                  start_barrier;
1163 };
1164
1165 struct radv_render_pass_attachment {
1166         VkFormat                                     format;
1167         uint32_t                                     samples;
1168         VkAttachmentLoadOp                           load_op;
1169         VkAttachmentLoadOp                           stencil_load_op;
1170         VkImageLayout                                initial_layout;
1171         VkImageLayout                                final_layout;
1172 };
1173
1174 struct radv_render_pass {
1175         uint32_t                                     attachment_count;
1176         uint32_t                                     subpass_count;
1177         VkAttachmentReference *                      subpass_attachments;
1178         struct radv_render_pass_attachment *         attachments;
1179         struct radv_subpass_barrier                  end_barrier;
1180         struct radv_subpass                          subpasses[0];
1181 };
1182
1183 VkResult radv_device_init_meta(struct radv_device *device);
1184 void radv_device_finish_meta(struct radv_device *device);
1185
1186 struct radv_query_pool {
1187         struct radeon_winsys_bo *bo;
1188         uint32_t stride;
1189         uint32_t availability_offset;
1190         char *ptr;
1191         VkQueryType type;
1192 };
1193
1194 VkResult
1195 radv_temp_descriptor_set_create(struct radv_device *device,
1196                                 struct radv_cmd_buffer *cmd_buffer,
1197                                 VkDescriptorSetLayout _layout,
1198                                 VkDescriptorSet *_set);
1199
1200 void
1201 radv_temp_descriptor_set_destroy(struct radv_device *device,
1202                                  VkDescriptorSet _set);
1203 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1204                            struct radv_image *image, uint32_t value);
1205 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1206                          struct radv_image *image, uint32_t value);
1207
1208 struct radv_fence {
1209         struct radeon_winsys_fence *fence;
1210         bool submitted;
1211         bool signalled;
1212 };
1213
1214 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)         \
1215                                                                 \
1216         static inline struct __radv_type *                      \
1217         __radv_type ## _from_handle(__VkType _handle)           \
1218         {                                                       \
1219                 return (struct __radv_type *) _handle;          \
1220         }                                                       \
1221                                                                 \
1222         static inline __VkType                                  \
1223         __radv_type ## _to_handle(struct __radv_type *_obj)     \
1224         {                                                       \
1225                 return (__VkType) _obj;                         \
1226         }
1227
1228 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType)         \
1229                                                                         \
1230         static inline struct __radv_type *                              \
1231         __radv_type ## _from_handle(__VkType _handle)                   \
1232         {                                                               \
1233                 return (struct __radv_type *)(uintptr_t) _handle;       \
1234         }                                                               \
1235                                                                         \
1236         static inline __VkType                                          \
1237         __radv_type ## _to_handle(struct __radv_type *_obj)             \
1238         {                                                               \
1239                 return (__VkType)(uintptr_t) _obj;                      \
1240         }
1241
1242 #define RADV_FROM_HANDLE(__radv_type, __name, __handle)                 \
1243         struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1244
1245 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1246 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1247 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1248 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1249 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1250
1251 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1252 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1253 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1254 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1255 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1256 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1257 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1258 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1259 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1260 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1261 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1262 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1263 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1264 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1265 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1266 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1267 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1268 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1269 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1270
1271 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType)                 \
1272                                                                         \
1273         static inline const __VkType *                                  \
1274         __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1275         {                                                               \
1276                 return (const __VkType *) __radv_obj;                   \
1277         }
1278
1279 #define RADV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name)       \
1280         const __VkType *__vk_name = radv_common_to_ ## __VkType(__common_name)
1281
1282 RADV_DEFINE_STRUCT_CASTS(radv_common, VkMemoryBarrier)
1283 RADV_DEFINE_STRUCT_CASTS(radv_common, VkBufferMemoryBarrier)
1284 RADV_DEFINE_STRUCT_CASTS(radv_common, VkImageMemoryBarrier)
1285
1286
1287 #endif /* RADV_PRIVATE_H */