2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
52 #include "vk_debug_report.h"
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60 #include "radv_extensions.h"
62 #include <llvm-c/TargetMachine.h>
64 /* Pre-declarations needed for WSI entrypoints */
67 typedef struct xcb_connection_t xcb_connection_t
;
68 typedef uint32_t xcb_visualid_t
;
69 typedef uint32_t xcb_window_t
;
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
76 #include "radv_entrypoints.h"
78 #include "wsi_common.h"
80 #define ATI_VENDOR_ID 0x1002
83 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_VIEWPORTS 16
86 #define MAX_SCISSORS 16
87 #define MAX_DISCARD_RECTANGLES 4
88 #define MAX_PUSH_CONSTANTS_SIZE 128
89 #define MAX_PUSH_DESCRIPTORS 32
90 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
91 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
92 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define RADV_MAX_DRM_DEVICES 8
98 #define NUM_DEPTH_CLEAR_PIPELINES 3
101 * This is the point we switch from using CP to compute shader
102 * for certain buffer operations.
104 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
108 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
115 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
116 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
117 RADV_MEM_TYPE_GTT_CACHED
,
121 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
123 static inline uint32_t
124 align_u32(uint32_t v
, uint32_t a
)
126 assert(a
!= 0 && a
== (a
& -a
));
127 return (v
+ a
- 1) & ~(a
- 1);
130 static inline uint32_t
131 align_u32_npot(uint32_t v
, uint32_t a
)
133 return (v
+ a
- 1) / a
* a
;
136 static inline uint64_t
137 align_u64(uint64_t v
, uint64_t a
)
139 assert(a
!= 0 && a
== (a
& -a
));
140 return (v
+ a
- 1) & ~(a
- 1);
143 static inline int32_t
144 align_i32(int32_t v
, int32_t a
)
146 assert(a
!= 0 && a
== (a
& -a
));
147 return (v
+ a
- 1) & ~(a
- 1);
150 /** Alignment must be a power of 2. */
152 radv_is_aligned(uintmax_t n
, uintmax_t a
)
154 assert(a
== (a
& -a
));
155 return (n
& (a
- 1)) == 0;
158 static inline uint32_t
159 round_up_u32(uint32_t v
, uint32_t a
)
161 return (v
+ a
- 1) / a
;
164 static inline uint64_t
165 round_up_u64(uint64_t v
, uint64_t a
)
167 return (v
+ a
- 1) / a
;
170 static inline uint32_t
171 radv_minify(uint32_t n
, uint32_t levels
)
173 if (unlikely(n
== 0))
176 return MAX2(n
>> levels
, 1);
179 radv_clamp_f(float f
, float min
, float max
)
192 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
194 if (*inout_mask
& clear_mask
) {
195 *inout_mask
&= ~clear_mask
;
202 #define for_each_bit(b, dword) \
203 for (uint32_t __dword = (dword); \
204 (b) = __builtin_ffs(__dword) - 1, __dword; \
205 __dword &= ~(1 << (b)))
207 #define typed_memcpy(dest, src, count) ({ \
208 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
209 memcpy((dest), (src), (count) * sizeof(*(src))); \
212 /* Whenever we generate an error, pass it through this function. Useful for
213 * debugging, where we can break on it. Only call at error site, not when
214 * propagating errors. Might be useful to plug in a stack trace here.
217 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
220 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
221 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
223 #define vk_error(error) error
224 #define vk_errorf(error, format, ...) error
227 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
228 radv_printflike(3, 4);
229 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
230 void radv_loge_v(const char *format
, va_list va
);
233 * Print a FINISHME message, including its source location.
235 #define radv_finishme(format, ...) \
237 static bool reported = false; \
239 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
244 /* A non-fatal assert. Useful for debugging. */
246 #define radv_assert(x) ({ \
247 if (unlikely(!(x))) \
248 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
251 #define radv_assert(x)
254 #define stub_return(v) \
256 radv_finishme("stub %s", __func__); \
262 radv_finishme("stub %s", __func__); \
266 void *radv_lookup_entrypoint_unchecked(const char *name
);
267 void *radv_lookup_entrypoint_checked(const char *name
,
268 uint32_t core_version
,
269 const struct radv_instance_extension_table
*instance
,
270 const struct radv_device_extension_table
*device
);
272 struct radv_physical_device
{
273 VK_LOADER_DATA _loader_data
;
275 struct radv_instance
* instance
;
277 struct radeon_winsys
*ws
;
278 struct radeon_info rad_info
;
280 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
281 uint8_t driver_uuid
[VK_UUID_SIZE
];
282 uint8_t device_uuid
[VK_UUID_SIZE
];
283 uint8_t cache_uuid
[VK_UUID_SIZE
];
286 struct wsi_device wsi_device
;
288 bool has_rbplus
; /* if RB+ register exist */
289 bool rbplus_allowed
; /* if RB+ is allowed */
290 bool has_clear_state
;
291 bool cpdma_prefetch_writes_memory
;
292 bool has_scissor_bug
;
294 /* This is the drivers on-disk cache used as a fallback as opposed to
295 * the pipeline cache defined by apps.
297 struct disk_cache
* disk_cache
;
299 VkPhysicalDeviceMemoryProperties memory_properties
;
300 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
302 struct radv_device_extension_table supported_extensions
;
305 struct radv_instance
{
306 VK_LOADER_DATA _loader_data
;
308 VkAllocationCallbacks alloc
;
311 int physicalDeviceCount
;
312 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
314 uint64_t debug_flags
;
315 uint64_t perftest_flags
;
317 struct vk_debug_report_instance debug_report_callbacks
;
319 struct radv_instance_extension_table enabled_extensions
;
322 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
323 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
325 bool radv_instance_extension_supported(const char *name
);
326 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
327 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
332 struct radv_pipeline_cache
{
333 struct radv_device
* device
;
334 pthread_mutex_t mutex
;
338 uint32_t kernel_count
;
339 struct cache_entry
** hash_table
;
342 VkAllocationCallbacks alloc
;
345 struct radv_pipeline_key
{
346 uint32_t instance_rate_inputs
;
347 unsigned tess_input_vertices
;
351 uint8_t log2_ps_iter_samples
;
352 uint8_t log2_num_samples
;
353 uint32_t multisample
: 1;
354 uint32_t has_multiview_view_index
: 1;
358 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
359 struct radv_device
*device
);
361 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
363 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
364 const void *data
, size_t size
);
366 struct radv_shader_variant
;
369 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
370 struct radv_pipeline_cache
*cache
,
371 const unsigned char *sha1
,
372 struct radv_shader_variant
**variants
);
375 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
376 struct radv_pipeline_cache
*cache
,
377 const unsigned char *sha1
,
378 struct radv_shader_variant
**variants
,
379 const void *const *codes
,
380 const unsigned *code_sizes
);
382 enum radv_blit_ds_layout
{
383 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
384 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
385 RADV_BLIT_DS_LAYOUT_COUNT
,
388 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
390 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
393 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
395 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
398 enum radv_meta_dst_layout
{
399 RADV_META_DST_LAYOUT_GENERAL
,
400 RADV_META_DST_LAYOUT_OPTIMAL
,
401 RADV_META_DST_LAYOUT_COUNT
,
404 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
406 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
409 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
411 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
414 struct radv_meta_state
{
415 VkAllocationCallbacks alloc
;
417 struct radv_pipeline_cache cache
;
420 * Use array element `i` for images with `2^i` samples.
423 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
424 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
426 VkRenderPass depthstencil_rp
;
427 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
428 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
429 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
430 } clear
[1 + MAX_SAMPLES_LOG2
];
432 VkPipelineLayout clear_color_p_layout
;
433 VkPipelineLayout clear_depth_p_layout
;
435 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
437 /** Pipeline that blits from a 1D image. */
438 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
440 /** Pipeline that blits from a 2D image. */
441 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
443 /** Pipeline that blits from a 3D image. */
444 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
446 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
447 VkPipeline depth_only_1d_pipeline
;
448 VkPipeline depth_only_2d_pipeline
;
449 VkPipeline depth_only_3d_pipeline
;
451 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
452 VkPipeline stencil_only_1d_pipeline
;
453 VkPipeline stencil_only_2d_pipeline
;
454 VkPipeline stencil_only_3d_pipeline
;
455 VkPipelineLayout pipeline_layout
;
456 VkDescriptorSetLayout ds_layout
;
460 VkRenderPass render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
462 VkPipelineLayout p_layouts
[3];
463 VkDescriptorSetLayout ds_layouts
[3];
464 VkPipeline pipelines
[3][NUM_META_FS_KEYS
];
466 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
467 VkPipeline depth_only_pipeline
[3];
469 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
470 VkPipeline stencil_only_pipeline
[3];
474 VkPipelineLayout img_p_layout
;
475 VkDescriptorSetLayout img_ds_layout
;
477 VkPipeline pipeline_3d
;
480 VkPipelineLayout img_p_layout
;
481 VkDescriptorSetLayout img_ds_layout
;
483 VkPipeline pipeline_3d
;
486 VkPipelineLayout img_p_layout
;
487 VkDescriptorSetLayout img_ds_layout
;
489 VkPipeline pipeline_3d
;
492 VkPipelineLayout img_p_layout
;
493 VkDescriptorSetLayout img_ds_layout
;
495 VkPipeline pipeline_3d
;
499 VkPipelineLayout p_layout
;
500 VkPipeline pipeline
[NUM_META_FS_KEYS
];
501 VkRenderPass pass
[NUM_META_FS_KEYS
];
505 VkDescriptorSetLayout ds_layout
;
506 VkPipelineLayout p_layout
;
509 VkPipeline i_pipeline
;
510 VkPipeline srgb_pipeline
;
511 } rc
[MAX_SAMPLES_LOG2
];
515 VkDescriptorSetLayout ds_layout
;
516 VkPipelineLayout p_layout
;
519 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
520 VkPipeline pipeline
[NUM_META_FS_KEYS
];
521 } rc
[MAX_SAMPLES_LOG2
];
525 VkPipelineLayout p_layout
;
526 VkPipeline decompress_pipeline
;
527 VkPipeline resummarize_pipeline
;
529 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
532 VkPipelineLayout p_layout
;
533 VkPipeline cmask_eliminate_pipeline
;
534 VkPipeline fmask_decompress_pipeline
;
535 VkPipeline dcc_decompress_pipeline
;
538 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
539 VkPipelineLayout dcc_decompress_compute_p_layout
;
540 VkPipeline dcc_decompress_compute_pipeline
;
544 VkPipelineLayout fill_p_layout
;
545 VkPipelineLayout copy_p_layout
;
546 VkDescriptorSetLayout fill_ds_layout
;
547 VkDescriptorSetLayout copy_ds_layout
;
548 VkPipeline fill_pipeline
;
549 VkPipeline copy_pipeline
;
553 VkDescriptorSetLayout ds_layout
;
554 VkPipelineLayout p_layout
;
555 VkPipeline occlusion_query_pipeline
;
556 VkPipeline pipeline_statistics_query_pipeline
;
561 #define RADV_QUEUE_GENERAL 0
562 #define RADV_QUEUE_COMPUTE 1
563 #define RADV_QUEUE_TRANSFER 2
565 #define RADV_MAX_QUEUE_FAMILIES 3
567 enum ring_type
radv_queue_family_to_ring(int f
);
570 VK_LOADER_DATA _loader_data
;
571 struct radv_device
* device
;
572 struct radeon_winsys_ctx
*hw_ctx
;
573 enum radeon_ctx_priority priority
;
574 uint32_t queue_family_index
;
576 VkDeviceQueueCreateFlags flags
;
578 uint32_t scratch_size
;
579 uint32_t compute_scratch_size
;
580 uint32_t esgs_ring_size
;
581 uint32_t gsvs_ring_size
;
583 bool has_sample_positions
;
585 struct radeon_winsys_bo
*scratch_bo
;
586 struct radeon_winsys_bo
*descriptor_bo
;
587 struct radeon_winsys_bo
*compute_scratch_bo
;
588 struct radeon_winsys_bo
*esgs_ring_bo
;
589 struct radeon_winsys_bo
*gsvs_ring_bo
;
590 struct radeon_winsys_bo
*tess_rings_bo
;
591 struct radeon_winsys_cs
*initial_preamble_cs
;
592 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
593 struct radeon_winsys_cs
*continue_preamble_cs
;
597 VK_LOADER_DATA _loader_data
;
599 VkAllocationCallbacks alloc
;
601 struct radv_instance
* instance
;
602 struct radeon_winsys
*ws
;
604 struct radv_meta_state meta_state
;
606 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
607 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
608 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
610 bool always_use_syncobj
;
611 bool llvm_supports_spill
;
612 bool has_distributed_tess
;
615 uint32_t tess_offchip_block_dw_size
;
616 uint32_t scratch_waves
;
617 uint32_t dispatch_initiator
;
619 uint32_t gs_table_depth
;
621 /* MSAA sample locations.
622 * The first index is the sample index.
623 * The second index is the coordinate: X, Y. */
624 float sample_locations_1x
[1][2];
625 float sample_locations_2x
[2][2];
626 float sample_locations_4x
[4][2];
627 float sample_locations_8x
[8][2];
628 float sample_locations_16x
[16][2];
631 uint32_t gfx_init_size_dw
;
632 struct radeon_winsys_bo
*gfx_init
;
634 struct radeon_winsys_bo
*trace_bo
;
635 uint32_t *trace_id_ptr
;
637 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
638 bool keep_shader_info
;
640 struct radv_physical_device
*physical_device
;
642 /* Backup in-memory cache to be used if the app doesn't provide one */
643 struct radv_pipeline_cache
* mem_cache
;
646 * use different counters so MSAA MRTs get consecutive surface indices,
647 * even if MASK is allocated in between.
649 uint32_t image_mrt_offset_counter
;
650 uint32_t fmask_mrt_offset_counter
;
651 struct list_head shader_slabs
;
652 mtx_t shader_slab_mutex
;
654 /* For detecting VM faults reported by dmesg. */
655 uint64_t dmesg_timestamp
;
657 struct radv_device_extension_table enabled_extensions
;
660 struct radv_device_memory
{
661 struct radeon_winsys_bo
*bo
;
662 /* for dedicated allocations */
663 struct radv_image
*image
;
664 struct radv_buffer
*buffer
;
666 VkDeviceSize map_size
;
672 struct radv_descriptor_range
{
677 struct radv_descriptor_set
{
678 const struct radv_descriptor_set_layout
*layout
;
681 struct radeon_winsys_bo
*bo
;
683 uint32_t *mapped_ptr
;
684 struct radv_descriptor_range
*dynamic_descriptors
;
686 struct radeon_winsys_bo
*descriptors
[0];
689 struct radv_push_descriptor_set
691 struct radv_descriptor_set set
;
695 struct radv_descriptor_pool_entry
{
698 struct radv_descriptor_set
*set
;
701 struct radv_descriptor_pool
{
702 struct radeon_winsys_bo
*bo
;
704 uint64_t current_offset
;
707 uint8_t *host_memory_base
;
708 uint8_t *host_memory_ptr
;
709 uint8_t *host_memory_end
;
711 uint32_t entry_count
;
712 uint32_t max_entry_count
;
713 struct radv_descriptor_pool_entry entries
[0];
716 struct radv_descriptor_update_template_entry
{
717 VkDescriptorType descriptor_type
;
719 /* The number of descriptors to update */
720 uint32_t descriptor_count
;
722 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
725 /* In dwords. Not valid/used for dynamic descriptors */
728 uint32_t buffer_offset
;
730 /* Only valid for combined image samplers and samplers */
731 uint16_t has_sampler
;
737 /* For push descriptors */
738 const uint32_t *immutable_samplers
;
741 struct radv_descriptor_update_template
{
742 uint32_t entry_count
;
743 VkPipelineBindPoint bind_point
;
744 struct radv_descriptor_update_template_entry entry
[0];
750 VkBufferUsageFlags usage
;
751 VkBufferCreateFlags flags
;
754 struct radeon_winsys_bo
* bo
;
760 enum radv_dynamic_state_bits
{
761 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
762 RADV_DYNAMIC_SCISSOR
= 1 << 1,
763 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
764 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
765 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
766 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
767 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
768 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
769 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
770 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
771 RADV_DYNAMIC_ALL
= (1 << 10) - 1,
774 enum radv_cmd_dirty_bits
{
775 /* Keep the dynamic state dirty bits in sync with
776 * enum radv_dynamic_state_bits */
777 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
778 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
779 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
780 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
781 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
782 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
783 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
784 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
785 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
786 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
787 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 10) - 1,
788 RADV_CMD_DIRTY_PIPELINE
= 1 << 10,
789 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 11,
790 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 12,
791 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 13,
794 enum radv_cmd_flush_bits
{
795 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
796 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
797 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
798 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
799 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
800 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
801 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
802 /* Same as above, but only writes back and doesn't invalidate */
803 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
804 /* Framebuffer caches */
805 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
806 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
807 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
808 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
809 /* Engine synchronization. */
810 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
811 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
812 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
813 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
815 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
816 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
817 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
818 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
821 struct radv_vertex_binding
{
822 struct radv_buffer
* buffer
;
826 struct radv_viewport_state
{
828 VkViewport viewports
[MAX_VIEWPORTS
];
831 struct radv_scissor_state
{
833 VkRect2D scissors
[MAX_SCISSORS
];
836 struct radv_discard_rectangle_state
{
838 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
841 struct radv_dynamic_state
{
843 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
844 * Defines the set of saved dynamic state.
848 struct radv_viewport_state viewport
;
850 struct radv_scissor_state scissor
;
860 float blend_constants
[4];
870 } stencil_compare_mask
;
875 } stencil_write_mask
;
882 struct radv_discard_rectangle_state discard_rectangle
;
885 extern const struct radv_dynamic_state default_dynamic_state
;
888 radv_get_debug_option_name(int id
);
891 radv_get_perftest_option_name(int id
);
894 * Attachment state when recording a renderpass instance.
896 * The clear value is valid only if there exists a pending clear.
898 struct radv_attachment_state
{
899 VkImageAspectFlags pending_clear_aspects
;
900 uint32_t cleared_views
;
901 VkClearValue clear_value
;
902 VkImageLayout current_layout
;
905 struct radv_descriptor_state
{
906 struct radv_descriptor_set
*sets
[MAX_SETS
];
909 struct radv_push_descriptor_set push_set
;
913 struct radv_cmd_state
{
914 /* Vertex descriptors */
915 bool vb_prefetch_dirty
;
922 struct radv_pipeline
* pipeline
;
923 struct radv_pipeline
* emitted_pipeline
;
924 struct radv_pipeline
* compute_pipeline
;
925 struct radv_pipeline
* emitted_compute_pipeline
;
926 struct radv_framebuffer
* framebuffer
;
927 struct radv_render_pass
* pass
;
928 const struct radv_subpass
* subpass
;
929 struct radv_dynamic_state dynamic
;
930 struct radv_attachment_state
* attachments
;
931 VkRect2D render_area
;
934 struct radv_buffer
*index_buffer
;
935 uint64_t index_offset
;
937 uint32_t max_index_count
;
939 int32_t last_index_type
;
941 int32_t last_primitive_reset_en
;
942 uint32_t last_primitive_reset_index
;
943 enum radv_cmd_flush_bits flush_bits
;
944 unsigned active_occlusion_queries
;
947 uint32_t last_ia_multi_vgt_param
;
949 uint32_t last_num_instances
;
950 uint32_t last_first_instance
;
951 uint32_t last_vertex_offset
;
954 struct radv_cmd_pool
{
955 VkAllocationCallbacks alloc
;
956 struct list_head cmd_buffers
;
957 struct list_head free_cmd_buffers
;
958 uint32_t queue_family_index
;
961 struct radv_cmd_buffer_upload
{
965 struct radeon_winsys_bo
*upload_bo
;
966 struct list_head list
;
969 enum radv_cmd_buffer_status
{
970 RADV_CMD_BUFFER_STATUS_INVALID
,
971 RADV_CMD_BUFFER_STATUS_INITIAL
,
972 RADV_CMD_BUFFER_STATUS_RECORDING
,
973 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
974 RADV_CMD_BUFFER_STATUS_PENDING
,
977 struct radv_cmd_buffer
{
978 VK_LOADER_DATA _loader_data
;
980 struct radv_device
* device
;
982 struct radv_cmd_pool
* pool
;
983 struct list_head pool_link
;
985 VkCommandBufferUsageFlags usage_flags
;
986 VkCommandBufferLevel level
;
987 enum radv_cmd_buffer_status status
;
988 struct radeon_winsys_cs
*cs
;
989 struct radv_cmd_state state
;
990 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
991 uint32_t queue_family_index
;
993 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
994 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
995 VkShaderStageFlags push_constant_stages
;
996 struct radv_descriptor_set meta_push_descriptors
;
998 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1000 struct radv_cmd_buffer_upload upload
;
1002 uint32_t scratch_size_needed
;
1003 uint32_t compute_scratch_size_needed
;
1004 uint32_t esgs_ring_size_needed
;
1005 uint32_t gsvs_ring_size_needed
;
1006 bool tess_rings_needed
;
1007 bool sample_positions_needed
;
1009 VkResult record_result
;
1011 int ring_offsets_idx
; /* just used for verification */
1012 uint32_t gfx9_fence_offset
;
1013 struct radeon_winsys_bo
*gfx9_fence_bo
;
1014 uint32_t gfx9_fence_idx
;
1017 * Whether a query pool has been resetted and we have to flush caches.
1019 bool pending_reset_query
;
1024 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1026 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
1027 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
1029 void cik_create_gfx_config(struct radv_device
*device
);
1031 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
1032 int count
, const VkViewport
*viewports
);
1033 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
1034 int count
, const VkRect2D
*scissors
,
1035 const VkViewport
*viewports
, bool can_use_guardband
);
1036 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1037 bool instanced_draw
, bool indirect_draw
,
1038 uint32_t draw_vertex_count
);
1039 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
1041 enum chip_class chip_class
,
1043 unsigned event
, unsigned event_flags
,
1047 uint32_t new_fence
);
1049 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
1051 uint64_t va
, uint32_t ref
,
1053 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
1054 enum chip_class chip_class
,
1055 uint32_t *fence_ptr
, uint64_t va
,
1057 enum radv_cmd_flush_bits flush_bits
);
1058 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1059 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
1060 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1061 uint64_t src_va
, uint64_t dest_va
,
1063 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1065 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1066 uint64_t size
, unsigned value
);
1067 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1069 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1072 unsigned *out_offset
,
1075 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1076 const struct radv_subpass
*subpass
,
1079 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1080 unsigned size
, unsigned alignmnet
,
1081 const void *data
, unsigned *out_offset
);
1083 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1084 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1085 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1086 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1087 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
1088 unsigned radv_cayman_get_maxdist(int log_samples
);
1089 void radv_device_init_msaa(struct radv_device
*device
);
1090 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1091 struct radv_image
*image
,
1092 VkClearDepthStencilValue ds_clear_value
,
1093 VkImageAspectFlags aspects
);
1094 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1095 struct radv_image
*image
,
1097 uint32_t color_values
[2]);
1098 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1099 struct radv_image
*image
,
1101 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1102 struct radeon_winsys_bo
*bo
,
1103 uint64_t offset
, uint64_t size
, uint32_t value
);
1104 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1105 bool radv_get_memory_fd(struct radv_device
*device
,
1106 struct radv_device_memory
*memory
,
1109 static inline struct radv_descriptor_state
*
1110 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1111 VkPipelineBindPoint bind_point
)
1113 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1114 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1115 return &cmd_buffer
->descriptors
[bind_point
];
1119 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1121 * Limitations: Can't call normal dispatch functions without binding or rebinding
1122 * the compute pipeline.
1124 void radv_unaligned_dispatch(
1125 struct radv_cmd_buffer
*cmd_buffer
,
1131 struct radeon_winsys_bo
*bo
;
1135 struct radv_shader_module
;
1137 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1138 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1139 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1141 radv_hash_shaders(unsigned char *hash
,
1142 const VkPipelineShaderStageCreateInfo
**stages
,
1143 const struct radv_pipeline_layout
*layout
,
1144 const struct radv_pipeline_key
*key
,
1147 static inline gl_shader_stage
1148 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1150 assert(__builtin_popcount(vk_stage
) == 1);
1151 return ffs(vk_stage
) - 1;
1154 static inline VkShaderStageFlagBits
1155 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1157 return (1 << mesa_stage
);
1160 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1162 #define radv_foreach_stage(stage, stage_bits) \
1163 for (gl_shader_stage stage, \
1164 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1165 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1166 __tmp &= ~(1 << (stage)))
1168 unsigned radv_format_meta_fs_key(VkFormat format
);
1170 struct radv_multisample_state
{
1172 uint32_t pa_sc_line_cntl
;
1173 uint32_t pa_sc_mode_cntl_0
;
1174 uint32_t pa_sc_mode_cntl_1
;
1175 uint32_t pa_sc_aa_config
;
1176 uint32_t pa_sc_aa_mask
[2];
1177 unsigned num_samples
;
1180 struct radv_prim_vertex_count
{
1185 struct radv_vertex_elements_info
{
1186 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1187 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1188 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1189 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1193 struct radv_ia_multi_vgt_param_helpers
{
1195 bool partial_es_wave
;
1196 uint8_t primgroup_size
;
1197 bool wd_switch_on_eop
;
1198 bool ia_switch_on_eoi
;
1199 bool partial_vs_wave
;
1202 #define SI_GS_PER_ES 128
1204 struct radv_pipeline
{
1205 struct radv_device
* device
;
1206 struct radv_dynamic_state dynamic_state
;
1208 struct radv_pipeline_layout
* layout
;
1210 bool needs_data_cache
;
1211 bool need_indirect_descriptor_sets
;
1212 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1213 struct radv_shader_variant
*gs_copy_shader
;
1214 VkShaderStageFlags active_stages
;
1216 struct radeon_winsys_cs cs
;
1218 struct radv_vertex_elements_info vertex_elements
;
1220 uint32_t binding_stride
[MAX_VBS
];
1222 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1225 struct radv_multisample_state ms
;
1226 uint32_t spi_baryc_cntl
;
1227 bool prim_restart_enable
;
1228 unsigned esgs_ring_size
;
1229 unsigned gsvs_ring_size
;
1230 uint32_t vtx_base_sgpr
;
1231 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1232 uint8_t vtx_emit_num
;
1233 struct radv_prim_vertex_count prim_vertex_count
;
1234 bool can_use_guardband
;
1235 uint32_t needed_dynamic_state
;
1240 unsigned scratch_bytes_per_wave
;
1243 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1245 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1248 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1250 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1253 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1254 gl_shader_stage stage
,
1257 struct radv_shader_variant
*radv_get_vertex_shader(struct radv_pipeline
*pipeline
);
1259 struct radv_graphics_pipeline_create_info
{
1261 bool db_depth_clear
;
1262 bool db_stencil_clear
;
1263 bool db_depth_disable_expclear
;
1264 bool db_stencil_disable_expclear
;
1265 bool db_flush_depth_inplace
;
1266 bool db_flush_stencil_inplace
;
1267 bool db_resummarize
;
1268 uint32_t custom_blend_mode
;
1272 radv_graphics_pipeline_create(VkDevice device
,
1273 VkPipelineCache cache
,
1274 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1275 const struct radv_graphics_pipeline_create_info
*extra
,
1276 const VkAllocationCallbacks
*alloc
,
1277 VkPipeline
*pPipeline
);
1279 struct vk_format_description
;
1280 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1281 int first_non_void
);
1282 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1283 int first_non_void
);
1284 uint32_t radv_translate_colorformat(VkFormat format
);
1285 uint32_t radv_translate_color_numformat(VkFormat format
,
1286 const struct vk_format_description
*desc
,
1287 int first_non_void
);
1288 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1289 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1290 uint32_t radv_translate_dbformat(VkFormat format
);
1291 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1292 const struct vk_format_description
*desc
,
1293 int first_non_void
);
1294 uint32_t radv_translate_tex_numformat(VkFormat format
,
1295 const struct vk_format_description
*desc
,
1296 int first_non_void
);
1297 bool radv_format_pack_clear_color(VkFormat format
,
1298 uint32_t clear_vals
[2],
1299 VkClearColorValue
*value
);
1300 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1301 bool radv_dcc_formats_compatible(VkFormat format1
,
1304 struct radv_fmask_info
{
1308 unsigned pitch_in_pixels
;
1309 unsigned bank_height
;
1310 unsigned slice_tile_max
;
1311 unsigned tile_mode_index
;
1312 unsigned tile_swizzle
;
1315 struct radv_cmask_info
{
1319 unsigned slice_tile_max
;
1324 /* The original VkFormat provided by the client. This may not match any
1325 * of the actual surface formats.
1328 VkImageAspectFlags aspects
;
1329 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1330 struct ac_surf_info info
;
1331 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1332 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1337 unsigned queue_family_mask
;
1341 /* Set when bound */
1342 struct radeon_winsys_bo
*bo
;
1343 VkDeviceSize offset
;
1344 uint64_t dcc_offset
;
1345 uint64_t htile_offset
;
1346 bool tc_compatible_htile
;
1347 struct radeon_surf surface
;
1349 struct radv_fmask_info fmask
;
1350 struct radv_cmask_info cmask
;
1351 uint64_t clear_value_offset
;
1352 uint64_t dcc_pred_offset
;
1354 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1355 VkDeviceMemory owned_memory
;
1358 /* Whether the image has a htile that is known consistent with the contents of
1360 bool radv_layout_has_htile(const struct radv_image
*image
,
1361 VkImageLayout layout
,
1362 unsigned queue_mask
);
1364 /* Whether the image has a htile that is known consistent with the contents of
1365 * the image and is allowed to be in compressed form.
1367 * If this is false reads that don't use the htile should be able to return
1370 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1371 VkImageLayout layout
,
1372 unsigned queue_mask
);
1374 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1375 VkImageLayout layout
,
1376 unsigned queue_mask
);
1378 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1379 VkImageLayout layout
,
1380 unsigned queue_mask
);
1383 radv_vi_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1385 return image
->surface
.dcc_size
&& level
< image
->surface
.num_dcc_levels
;
1389 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1391 return image
->surface
.htile_size
&& level
== 0;
1394 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1396 static inline uint32_t
1397 radv_get_layerCount(const struct radv_image
*image
,
1398 const VkImageSubresourceRange
*range
)
1400 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1401 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1404 static inline uint32_t
1405 radv_get_levelCount(const struct radv_image
*image
,
1406 const VkImageSubresourceRange
*range
)
1408 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1409 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1412 struct radeon_bo_metadata
;
1414 radv_init_metadata(struct radv_device
*device
,
1415 struct radv_image
*image
,
1416 struct radeon_bo_metadata
*metadata
);
1418 struct radv_image_view
{
1419 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1420 struct radeon_winsys_bo
*bo
;
1422 VkImageViewType type
;
1423 VkImageAspectFlags aspect_mask
;
1425 uint32_t base_layer
;
1426 uint32_t layer_count
;
1428 uint32_t level_count
;
1429 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1431 uint32_t descriptor
[16];
1433 /* Descriptor for use as a storage image as opposed to a sampled image.
1434 * This has a few differences for cube maps (e.g. type).
1436 uint32_t storage_descriptor
[16];
1439 struct radv_image_create_info
{
1440 const VkImageCreateInfo
*vk_info
;
1442 bool no_metadata_planes
;
1445 VkResult
radv_image_create(VkDevice _device
,
1446 const struct radv_image_create_info
*info
,
1447 const VkAllocationCallbacks
* alloc
,
1451 radv_image_from_gralloc(VkDevice device_h
,
1452 const VkImageCreateInfo
*base_info
,
1453 const VkNativeBufferANDROID
*gralloc_info
,
1454 const VkAllocationCallbacks
*alloc
,
1455 VkImage
*out_image_h
);
1457 void radv_image_view_init(struct radv_image_view
*view
,
1458 struct radv_device
*device
,
1459 const VkImageViewCreateInfo
* pCreateInfo
);
1461 struct radv_buffer_view
{
1462 struct radeon_winsys_bo
*bo
;
1464 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1467 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1468 struct radv_device
*device
,
1469 const VkBufferViewCreateInfo
* pCreateInfo
);
1471 static inline struct VkExtent3D
1472 radv_sanitize_image_extent(const VkImageType imageType
,
1473 const struct VkExtent3D imageExtent
)
1475 switch (imageType
) {
1476 case VK_IMAGE_TYPE_1D
:
1477 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1478 case VK_IMAGE_TYPE_2D
:
1479 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1480 case VK_IMAGE_TYPE_3D
:
1483 unreachable("invalid image type");
1487 static inline struct VkOffset3D
1488 radv_sanitize_image_offset(const VkImageType imageType
,
1489 const struct VkOffset3D imageOffset
)
1491 switch (imageType
) {
1492 case VK_IMAGE_TYPE_1D
:
1493 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1494 case VK_IMAGE_TYPE_2D
:
1495 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1496 case VK_IMAGE_TYPE_3D
:
1499 unreachable("invalid image type");
1504 radv_image_extent_compare(const struct radv_image
*image
,
1505 const VkExtent3D
*extent
)
1507 if (extent
->width
!= image
->info
.width
||
1508 extent
->height
!= image
->info
.height
||
1509 extent
->depth
!= image
->info
.depth
)
1514 struct radv_sampler
{
1518 struct radv_color_buffer_info
{
1519 uint64_t cb_color_base
;
1520 uint64_t cb_color_cmask
;
1521 uint64_t cb_color_fmask
;
1522 uint64_t cb_dcc_base
;
1523 uint32_t cb_color_pitch
;
1524 uint32_t cb_color_slice
;
1525 uint32_t cb_color_view
;
1526 uint32_t cb_color_info
;
1527 uint32_t cb_color_attrib
;
1528 uint32_t cb_color_attrib2
;
1529 uint32_t cb_dcc_control
;
1530 uint32_t cb_color_cmask_slice
;
1531 uint32_t cb_color_fmask_slice
;
1534 struct radv_ds_buffer_info
{
1535 uint64_t db_z_read_base
;
1536 uint64_t db_stencil_read_base
;
1537 uint64_t db_z_write_base
;
1538 uint64_t db_stencil_write_base
;
1539 uint64_t db_htile_data_base
;
1540 uint32_t db_depth_info
;
1542 uint32_t db_stencil_info
;
1543 uint32_t db_depth_view
;
1544 uint32_t db_depth_size
;
1545 uint32_t db_depth_slice
;
1546 uint32_t db_htile_surface
;
1547 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1548 uint32_t db_z_info2
;
1549 uint32_t db_stencil_info2
;
1553 struct radv_attachment_info
{
1555 struct radv_color_buffer_info cb
;
1556 struct radv_ds_buffer_info ds
;
1558 struct radv_image_view
*attachment
;
1561 struct radv_framebuffer
{
1566 uint32_t attachment_count
;
1567 struct radv_attachment_info attachments
[0];
1570 struct radv_subpass_barrier
{
1571 VkPipelineStageFlags src_stage_mask
;
1572 VkAccessFlags src_access_mask
;
1573 VkAccessFlags dst_access_mask
;
1576 struct radv_subpass
{
1577 uint32_t input_count
;
1578 uint32_t color_count
;
1579 VkAttachmentReference
* input_attachments
;
1580 VkAttachmentReference
* color_attachments
;
1581 VkAttachmentReference
* resolve_attachments
;
1582 VkAttachmentReference depth_stencil_attachment
;
1584 /** Subpass has at least one resolve attachment */
1587 struct radv_subpass_barrier start_barrier
;
1592 struct radv_render_pass_attachment
{
1595 VkAttachmentLoadOp load_op
;
1596 VkAttachmentLoadOp stencil_load_op
;
1597 VkImageLayout initial_layout
;
1598 VkImageLayout final_layout
;
1602 struct radv_render_pass
{
1603 uint32_t attachment_count
;
1604 uint32_t subpass_count
;
1605 VkAttachmentReference
* subpass_attachments
;
1606 struct radv_render_pass_attachment
* attachments
;
1607 struct radv_subpass_barrier end_barrier
;
1608 struct radv_subpass subpasses
[0];
1611 VkResult
radv_device_init_meta(struct radv_device
*device
);
1612 void radv_device_finish_meta(struct radv_device
*device
);
1614 struct radv_query_pool
{
1615 struct radeon_winsys_bo
*bo
;
1617 uint32_t availability_offset
;
1621 uint32_t pipeline_stats_mask
;
1624 struct radv_semaphore
{
1625 /* use a winsys sem for non-exportable */
1626 struct radeon_winsys_sem
*sem
;
1628 uint32_t temp_syncobj
;
1631 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1633 const VkSemaphore
*wait_sems
,
1634 int num_signal_sems
,
1635 const VkSemaphore
*signal_sems
,
1637 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1639 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1640 VkPipelineBindPoint bind_point
,
1641 struct radv_descriptor_set
*set
,
1645 radv_update_descriptor_sets(struct radv_device
*device
,
1646 struct radv_cmd_buffer
*cmd_buffer
,
1647 VkDescriptorSet overrideSet
,
1648 uint32_t descriptorWriteCount
,
1649 const VkWriteDescriptorSet
*pDescriptorWrites
,
1650 uint32_t descriptorCopyCount
,
1651 const VkCopyDescriptorSet
*pDescriptorCopies
);
1654 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1655 struct radv_cmd_buffer
*cmd_buffer
,
1656 struct radv_descriptor_set
*set
,
1657 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1660 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1661 VkPipelineBindPoint pipelineBindPoint
,
1662 VkPipelineLayout _layout
,
1664 uint32_t descriptorWriteCount
,
1665 const VkWriteDescriptorSet
*pDescriptorWrites
);
1667 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1668 struct radv_image
*image
, uint32_t value
);
1669 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1670 struct radv_image
*image
, uint32_t value
);
1673 struct radeon_winsys_fence
*fence
;
1678 uint32_t temp_syncobj
;
1681 /* radv_nir_to_llvm.c */
1682 struct radv_shader_variant_info
;
1683 struct radv_nir_compiler_options
;
1685 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm
,
1686 struct nir_shader
*geom_shader
,
1687 struct ac_shader_binary
*binary
,
1688 struct ac_shader_config
*config
,
1689 struct radv_shader_variant_info
*shader_info
,
1690 const struct radv_nir_compiler_options
*option
);
1692 void radv_compile_nir_shader(LLVMTargetMachineRef tm
,
1693 struct ac_shader_binary
*binary
,
1694 struct ac_shader_config
*config
,
1695 struct radv_shader_variant_info
*shader_info
,
1696 struct nir_shader
*const *nir
,
1698 const struct radv_nir_compiler_options
*options
);
1700 /* radv_shader_info.h */
1701 struct radv_shader_info
;
1703 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
1704 const struct radv_nir_compiler_options
*options
,
1705 struct radv_shader_info
*info
);
1707 struct radeon_winsys_sem
;
1709 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1711 static inline struct __radv_type * \
1712 __radv_type ## _from_handle(__VkType _handle) \
1714 return (struct __radv_type *) _handle; \
1717 static inline __VkType \
1718 __radv_type ## _to_handle(struct __radv_type *_obj) \
1720 return (__VkType) _obj; \
1723 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1725 static inline struct __radv_type * \
1726 __radv_type ## _from_handle(__VkType _handle) \
1728 return (struct __radv_type *)(uintptr_t) _handle; \
1731 static inline __VkType \
1732 __radv_type ## _to_handle(struct __radv_type *_obj) \
1734 return (__VkType)(uintptr_t) _obj; \
1737 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1738 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1740 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1741 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1742 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1743 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1744 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1746 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1747 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1748 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1749 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1750 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1751 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1752 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1753 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1754 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1755 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1756 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1757 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1758 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1759 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1760 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1761 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1762 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1763 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1764 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1765 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1766 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1768 #endif /* RADV_PRIVATE_H */