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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102 #define MAX_SO_STREAMS 4
103 #define MAX_SO_BUFFERS 4
104 #define MAX_SO_OUTPUTS 64
105
106 #define NUM_DEPTH_CLEAR_PIPELINES 3
107
108 /*
109 * This is the point we switch from using CP to compute shader
110 * for certain buffer operations.
111 */
112 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113
114 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
115
116 enum radv_mem_heap {
117 RADV_MEM_HEAP_VRAM,
118 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
119 RADV_MEM_HEAP_GTT,
120 RADV_MEM_HEAP_COUNT
121 };
122
123 enum radv_mem_type {
124 RADV_MEM_TYPE_VRAM,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
127 RADV_MEM_TYPE_GTT_CACHED,
128 RADV_MEM_TYPE_COUNT
129 };
130
131 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
132
133 static inline uint32_t
134 align_u32(uint32_t v, uint32_t a)
135 {
136 assert(a != 0 && a == (a & -a));
137 return (v + a - 1) & ~(a - 1);
138 }
139
140 static inline uint32_t
141 align_u32_npot(uint32_t v, uint32_t a)
142 {
143 return (v + a - 1) / a * a;
144 }
145
146 static inline uint64_t
147 align_u64(uint64_t v, uint64_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 static inline int32_t
154 align_i32(int32_t v, int32_t a)
155 {
156 assert(a != 0 && a == (a & -a));
157 return (v + a - 1) & ~(a - 1);
158 }
159
160 /** Alignment must be a power of 2. */
161 static inline bool
162 radv_is_aligned(uintmax_t n, uintmax_t a)
163 {
164 assert(a == (a & -a));
165 return (n & (a - 1)) == 0;
166 }
167
168 static inline uint32_t
169 round_up_u32(uint32_t v, uint32_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint64_t
175 round_up_u64(uint64_t v, uint64_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint32_t
181 radv_minify(uint32_t n, uint32_t levels)
182 {
183 if (unlikely(n == 0))
184 return 0;
185 else
186 return MAX2(n >> levels, 1);
187 }
188 static inline float
189 radv_clamp_f(float f, float min, float max)
190 {
191 assert(min < max);
192
193 if (f > max)
194 return max;
195 else if (f < min)
196 return min;
197 else
198 return f;
199 }
200
201 static inline bool
202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
203 {
204 if (*inout_mask & clear_mask) {
205 *inout_mask &= ~clear_mask;
206 return true;
207 } else {
208 return false;
209 }
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Whenever we generate an error, pass it through this function. Useful for
223 * debugging, where we can break on it. Only call at error site, not when
224 * propagating errors. Might be useful to plug in a stack trace here.
225 */
226
227 struct radv_instance;
228
229 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
230
231 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
232 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
233
234 void __radv_finishme(const char *file, int line, const char *format, ...)
235 radv_printflike(3, 4);
236 void radv_loge(const char *format, ...) radv_printflike(1, 2);
237 void radv_loge_v(const char *format, va_list va);
238 void radv_logi(const char *format, ...) radv_printflike(1, 2);
239 void radv_logi_v(const char *format, va_list va);
240
241 /**
242 * Print a FINISHME message, including its source location.
243 */
244 #define radv_finishme(format, ...) \
245 do { \
246 static bool reported = false; \
247 if (!reported) { \
248 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 reported = true; \
250 } \
251 } while (0)
252
253 /* A non-fatal assert. Useful for debugging. */
254 #ifdef DEBUG
255 #define radv_assert(x) ({ \
256 if (unlikely(!(x))) \
257 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
258 })
259 #else
260 #define radv_assert(x)
261 #endif
262
263 #define stub_return(v) \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return (v); \
267 } while (0)
268
269 #define stub() \
270 do { \
271 radv_finishme("stub %s", __func__); \
272 return; \
273 } while (0)
274
275 void *radv_lookup_entrypoint_unchecked(const char *name);
276 void *radv_lookup_entrypoint_checked(const char *name,
277 uint32_t core_version,
278 const struct radv_instance_extension_table *instance,
279 const struct radv_device_extension_table *device);
280
281 struct radv_physical_device {
282 VK_LOADER_DATA _loader_data;
283
284 struct radv_instance * instance;
285
286 struct radeon_winsys *ws;
287 struct radeon_info rad_info;
288 char path[20];
289 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
290 uint8_t driver_uuid[VK_UUID_SIZE];
291 uint8_t device_uuid[VK_UUID_SIZE];
292 uint8_t cache_uuid[VK_UUID_SIZE];
293
294 int local_fd;
295 int master_fd;
296 struct wsi_device wsi_device;
297
298 bool has_rbplus; /* if RB+ register exist */
299 bool rbplus_allowed; /* if RB+ is allowed */
300 bool has_clear_state;
301 bool cpdma_prefetch_writes_memory;
302 bool has_scissor_bug;
303
304 bool has_out_of_order_rast;
305 bool out_of_order_rast_allowed;
306
307 /* Whether DCC should be enabled for MSAA textures. */
308 bool dcc_msaa_allowed;
309
310 /* This is the drivers on-disk cache used as a fallback as opposed to
311 * the pipeline cache defined by apps.
312 */
313 struct disk_cache * disk_cache;
314
315 VkPhysicalDeviceMemoryProperties memory_properties;
316 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
317
318 drmPciBusInfo bus_info;
319
320 struct radv_device_extension_table supported_extensions;
321 };
322
323 struct radv_instance {
324 VK_LOADER_DATA _loader_data;
325
326 VkAllocationCallbacks alloc;
327
328 uint32_t apiVersion;
329 int physicalDeviceCount;
330 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
331
332 uint64_t debug_flags;
333 uint64_t perftest_flags;
334
335 struct vk_debug_report_instance debug_report_callbacks;
336
337 struct radv_instance_extension_table enabled_extensions;
338 };
339
340 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
341 void radv_finish_wsi(struct radv_physical_device *physical_device);
342
343 bool radv_instance_extension_supported(const char *name);
344 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
345 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
346 const char *name);
347
348 struct cache_entry;
349
350 struct radv_pipeline_cache {
351 struct radv_device * device;
352 pthread_mutex_t mutex;
353
354 uint32_t total_size;
355 uint32_t table_size;
356 uint32_t kernel_count;
357 struct cache_entry ** hash_table;
358 bool modified;
359
360 VkAllocationCallbacks alloc;
361 };
362
363 struct radv_pipeline_key {
364 uint32_t instance_rate_inputs;
365 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
366 uint64_t vertex_alpha_adjust;
367 unsigned tess_input_vertices;
368 uint32_t col_format;
369 uint32_t is_int8;
370 uint32_t is_int10;
371 uint8_t log2_ps_iter_samples;
372 uint8_t num_samples;
373 uint32_t has_multiview_view_index : 1;
374 uint32_t optimisations_disabled : 1;
375 };
376
377 void
378 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
379 struct radv_device *device);
380 void
381 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
382 bool
383 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
384 const void *data, size_t size);
385
386 struct radv_shader_variant;
387
388 bool
389 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
390 struct radv_pipeline_cache *cache,
391 const unsigned char *sha1,
392 struct radv_shader_variant **variants);
393
394 void
395 radv_pipeline_cache_insert_shaders(struct radv_device *device,
396 struct radv_pipeline_cache *cache,
397 const unsigned char *sha1,
398 struct radv_shader_variant **variants,
399 const void *const *codes,
400 const unsigned *code_sizes);
401
402 enum radv_blit_ds_layout {
403 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
404 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
405 RADV_BLIT_DS_LAYOUT_COUNT,
406 };
407
408 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
409 {
410 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
411 }
412
413 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
414 {
415 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
416 }
417
418 enum radv_meta_dst_layout {
419 RADV_META_DST_LAYOUT_GENERAL,
420 RADV_META_DST_LAYOUT_OPTIMAL,
421 RADV_META_DST_LAYOUT_COUNT,
422 };
423
424 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
425 {
426 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
427 }
428
429 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
430 {
431 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
432 }
433
434 struct radv_meta_state {
435 VkAllocationCallbacks alloc;
436
437 struct radv_pipeline_cache cache;
438
439 /*
440 * For on-demand pipeline creation, makes sure that
441 * only one thread tries to build a pipeline at the same time.
442 */
443 mtx_t mtx;
444
445 /**
446 * Use array element `i` for images with `2^i` samples.
447 */
448 struct {
449 VkRenderPass render_pass[NUM_META_FS_KEYS];
450 VkPipeline color_pipelines[NUM_META_FS_KEYS];
451
452 VkRenderPass depthstencil_rp;
453 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
454 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
455 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
456 } clear[1 + MAX_SAMPLES_LOG2];
457
458 VkPipelineLayout clear_color_p_layout;
459 VkPipelineLayout clear_depth_p_layout;
460
461 /* Optimized compute fast HTILE clear for stencil or depth only. */
462 VkPipeline clear_htile_mask_pipeline;
463 VkPipelineLayout clear_htile_mask_p_layout;
464 VkDescriptorSetLayout clear_htile_mask_ds_layout;
465
466 struct {
467 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
468
469 /** Pipeline that blits from a 1D image. */
470 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
471
472 /** Pipeline that blits from a 2D image. */
473 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
474
475 /** Pipeline that blits from a 3D image. */
476 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
477
478 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
479 VkPipeline depth_only_1d_pipeline;
480 VkPipeline depth_only_2d_pipeline;
481 VkPipeline depth_only_3d_pipeline;
482
483 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
484 VkPipeline stencil_only_1d_pipeline;
485 VkPipeline stencil_only_2d_pipeline;
486 VkPipeline stencil_only_3d_pipeline;
487 VkPipelineLayout pipeline_layout;
488 VkDescriptorSetLayout ds_layout;
489 } blit;
490
491 struct {
492 VkPipelineLayout p_layouts[5];
493 VkDescriptorSetLayout ds_layouts[5];
494 VkPipeline pipelines[5][NUM_META_FS_KEYS];
495
496 VkPipeline depth_only_pipeline[5];
497
498 VkPipeline stencil_only_pipeline[5];
499 } blit2d[1 + MAX_SAMPLES_LOG2];
500
501 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
502 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
503 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
504
505 struct {
506 VkPipelineLayout img_p_layout;
507 VkDescriptorSetLayout img_ds_layout;
508 VkPipeline pipeline;
509 VkPipeline pipeline_3d;
510 } itob;
511 struct {
512 VkPipelineLayout img_p_layout;
513 VkDescriptorSetLayout img_ds_layout;
514 VkPipeline pipeline;
515 VkPipeline pipeline_3d;
516 } btoi;
517 struct {
518 VkPipelineLayout img_p_layout;
519 VkDescriptorSetLayout img_ds_layout;
520 VkPipeline pipeline;
521 } btoi_r32g32b32;
522 struct {
523 VkPipelineLayout img_p_layout;
524 VkDescriptorSetLayout img_ds_layout;
525 VkPipeline pipeline;
526 VkPipeline pipeline_3d;
527 } itoi;
528 struct {
529 VkPipelineLayout img_p_layout;
530 VkDescriptorSetLayout img_ds_layout;
531 VkPipeline pipeline;
532 } itoi_r32g32b32;
533 struct {
534 VkPipelineLayout img_p_layout;
535 VkDescriptorSetLayout img_ds_layout;
536 VkPipeline pipeline;
537 VkPipeline pipeline_3d;
538 } cleari;
539 struct {
540 VkPipelineLayout img_p_layout;
541 VkDescriptorSetLayout img_ds_layout;
542 VkPipeline pipeline;
543 } cleari_r32g32b32;
544
545 struct {
546 VkPipelineLayout p_layout;
547 VkPipeline pipeline[NUM_META_FS_KEYS];
548 VkRenderPass pass[NUM_META_FS_KEYS];
549 } resolve;
550
551 struct {
552 VkDescriptorSetLayout ds_layout;
553 VkPipelineLayout p_layout;
554 struct {
555 VkPipeline pipeline;
556 VkPipeline i_pipeline;
557 VkPipeline srgb_pipeline;
558 } rc[MAX_SAMPLES_LOG2];
559 } resolve_compute;
560
561 struct {
562 VkDescriptorSetLayout ds_layout;
563 VkPipelineLayout p_layout;
564
565 struct {
566 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
567 VkPipeline pipeline[NUM_META_FS_KEYS];
568 } rc[MAX_SAMPLES_LOG2];
569 } resolve_fragment;
570
571 struct {
572 VkPipelineLayout p_layout;
573 VkPipeline decompress_pipeline;
574 VkPipeline resummarize_pipeline;
575 VkRenderPass pass;
576 } depth_decomp[1 + MAX_SAMPLES_LOG2];
577
578 struct {
579 VkPipelineLayout p_layout;
580 VkPipeline cmask_eliminate_pipeline;
581 VkPipeline fmask_decompress_pipeline;
582 VkPipeline dcc_decompress_pipeline;
583 VkRenderPass pass;
584
585 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
586 VkPipelineLayout dcc_decompress_compute_p_layout;
587 VkPipeline dcc_decompress_compute_pipeline;
588 } fast_clear_flush;
589
590 struct {
591 VkPipelineLayout fill_p_layout;
592 VkPipelineLayout copy_p_layout;
593 VkDescriptorSetLayout fill_ds_layout;
594 VkDescriptorSetLayout copy_ds_layout;
595 VkPipeline fill_pipeline;
596 VkPipeline copy_pipeline;
597 } buffer;
598
599 struct {
600 VkDescriptorSetLayout ds_layout;
601 VkPipelineLayout p_layout;
602 VkPipeline occlusion_query_pipeline;
603 VkPipeline pipeline_statistics_query_pipeline;
604 VkPipeline tfb_query_pipeline;
605 } query;
606
607 struct {
608 VkDescriptorSetLayout ds_layout;
609 VkPipelineLayout p_layout;
610 VkPipeline pipeline[MAX_SAMPLES_LOG2];
611 } fmask_expand;
612 };
613
614 /* queue types */
615 #define RADV_QUEUE_GENERAL 0
616 #define RADV_QUEUE_COMPUTE 1
617 #define RADV_QUEUE_TRANSFER 2
618
619 #define RADV_MAX_QUEUE_FAMILIES 3
620
621 enum ring_type radv_queue_family_to_ring(int f);
622
623 struct radv_queue {
624 VK_LOADER_DATA _loader_data;
625 struct radv_device * device;
626 struct radeon_winsys_ctx *hw_ctx;
627 enum radeon_ctx_priority priority;
628 uint32_t queue_family_index;
629 int queue_idx;
630 VkDeviceQueueCreateFlags flags;
631
632 uint32_t scratch_size;
633 uint32_t compute_scratch_size;
634 uint32_t esgs_ring_size;
635 uint32_t gsvs_ring_size;
636 bool has_tess_rings;
637 bool has_sample_positions;
638
639 struct radeon_winsys_bo *scratch_bo;
640 struct radeon_winsys_bo *descriptor_bo;
641 struct radeon_winsys_bo *compute_scratch_bo;
642 struct radeon_winsys_bo *esgs_ring_bo;
643 struct radeon_winsys_bo *gsvs_ring_bo;
644 struct radeon_winsys_bo *tess_rings_bo;
645 struct radeon_cmdbuf *initial_preamble_cs;
646 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
647 struct radeon_cmdbuf *continue_preamble_cs;
648 };
649
650 struct radv_bo_list {
651 struct radv_winsys_bo_list list;
652 unsigned capacity;
653 pthread_mutex_t mutex;
654 };
655
656 struct radv_device {
657 VK_LOADER_DATA _loader_data;
658
659 VkAllocationCallbacks alloc;
660
661 struct radv_instance * instance;
662 struct radeon_winsys *ws;
663
664 struct radv_meta_state meta_state;
665
666 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
667 int queue_count[RADV_MAX_QUEUE_FAMILIES];
668 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
669
670 bool always_use_syncobj;
671 bool has_distributed_tess;
672 bool pbb_allowed;
673 bool dfsm_allowed;
674 uint32_t tess_offchip_block_dw_size;
675 uint32_t scratch_waves;
676 uint32_t dispatch_initiator;
677
678 uint32_t gs_table_depth;
679
680 /* MSAA sample locations.
681 * The first index is the sample index.
682 * The second index is the coordinate: X, Y. */
683 float sample_locations_1x[1][2];
684 float sample_locations_2x[2][2];
685 float sample_locations_4x[4][2];
686 float sample_locations_8x[8][2];
687 float sample_locations_16x[16][2];
688
689 /* CIK and later */
690 uint32_t gfx_init_size_dw;
691 struct radeon_winsys_bo *gfx_init;
692
693 struct radeon_winsys_bo *trace_bo;
694 uint32_t *trace_id_ptr;
695
696 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
697 bool keep_shader_info;
698
699 struct radv_physical_device *physical_device;
700
701 /* Backup in-memory cache to be used if the app doesn't provide one */
702 struct radv_pipeline_cache * mem_cache;
703
704 /*
705 * use different counters so MSAA MRTs get consecutive surface indices,
706 * even if MASK is allocated in between.
707 */
708 uint32_t image_mrt_offset_counter;
709 uint32_t fmask_mrt_offset_counter;
710 struct list_head shader_slabs;
711 mtx_t shader_slab_mutex;
712
713 /* For detecting VM faults reported by dmesg. */
714 uint64_t dmesg_timestamp;
715
716 struct radv_device_extension_table enabled_extensions;
717
718 /* Whether the driver uses a global BO list. */
719 bool use_global_bo_list;
720
721 struct radv_bo_list bo_list;
722
723 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
724 int force_aniso;
725 };
726
727 struct radv_device_memory {
728 struct radeon_winsys_bo *bo;
729 /* for dedicated allocations */
730 struct radv_image *image;
731 struct radv_buffer *buffer;
732 uint32_t type_index;
733 VkDeviceSize map_size;
734 void * map;
735 void * user_ptr;
736 };
737
738
739 struct radv_descriptor_range {
740 uint64_t va;
741 uint32_t size;
742 };
743
744 struct radv_descriptor_set {
745 const struct radv_descriptor_set_layout *layout;
746 uint32_t size;
747
748 struct radeon_winsys_bo *bo;
749 uint64_t va;
750 uint32_t *mapped_ptr;
751 struct radv_descriptor_range *dynamic_descriptors;
752
753 struct radeon_winsys_bo *descriptors[0];
754 };
755
756 struct radv_push_descriptor_set
757 {
758 struct radv_descriptor_set set;
759 uint32_t capacity;
760 };
761
762 struct radv_descriptor_pool_entry {
763 uint32_t offset;
764 uint32_t size;
765 struct radv_descriptor_set *set;
766 };
767
768 struct radv_descriptor_pool {
769 struct radeon_winsys_bo *bo;
770 uint8_t *mapped_ptr;
771 uint64_t current_offset;
772 uint64_t size;
773
774 uint8_t *host_memory_base;
775 uint8_t *host_memory_ptr;
776 uint8_t *host_memory_end;
777
778 uint32_t entry_count;
779 uint32_t max_entry_count;
780 struct radv_descriptor_pool_entry entries[0];
781 };
782
783 struct radv_descriptor_update_template_entry {
784 VkDescriptorType descriptor_type;
785
786 /* The number of descriptors to update */
787 uint32_t descriptor_count;
788
789 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
790 uint32_t dst_offset;
791
792 /* In dwords. Not valid/used for dynamic descriptors */
793 uint32_t dst_stride;
794
795 uint32_t buffer_offset;
796
797 /* Only valid for combined image samplers and samplers */
798 uint16_t has_sampler;
799
800 /* In bytes */
801 size_t src_offset;
802 size_t src_stride;
803
804 /* For push descriptors */
805 const uint32_t *immutable_samplers;
806 };
807
808 struct radv_descriptor_update_template {
809 uint32_t entry_count;
810 VkPipelineBindPoint bind_point;
811 struct radv_descriptor_update_template_entry entry[0];
812 };
813
814 struct radv_buffer {
815 VkDeviceSize size;
816
817 VkBufferUsageFlags usage;
818 VkBufferCreateFlags flags;
819
820 /* Set when bound */
821 struct radeon_winsys_bo * bo;
822 VkDeviceSize offset;
823
824 bool shareable;
825 };
826
827 enum radv_dynamic_state_bits {
828 RADV_DYNAMIC_VIEWPORT = 1 << 0,
829 RADV_DYNAMIC_SCISSOR = 1 << 1,
830 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
831 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
832 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
833 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
834 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
835 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
836 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
837 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
838 RADV_DYNAMIC_ALL = (1 << 10) - 1,
839 };
840
841 enum radv_cmd_dirty_bits {
842 /* Keep the dynamic state dirty bits in sync with
843 * enum radv_dynamic_state_bits */
844 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
845 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
846 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
847 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
848 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
849 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
850 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
851 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
852 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
853 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
854 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
855 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
856 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
857 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
858 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
859 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
860 };
861
862 enum radv_cmd_flush_bits {
863 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
864 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
865 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
866 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
867 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
868 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
869 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
870 /* Same as above, but only writes back and doesn't invalidate */
871 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
872 /* Framebuffer caches */
873 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
874 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
875 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
876 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
877 /* Engine synchronization. */
878 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
879 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
880 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
881 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
882 /* Pipeline query controls. */
883 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
884 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
885 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
886
887 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
888 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
889 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
890 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
891 };
892
893 struct radv_vertex_binding {
894 struct radv_buffer * buffer;
895 VkDeviceSize offset;
896 };
897
898 struct radv_streamout_binding {
899 struct radv_buffer *buffer;
900 VkDeviceSize offset;
901 VkDeviceSize size;
902 };
903
904 struct radv_streamout_state {
905 /* Mask of bound streamout buffers. */
906 uint8_t enabled_mask;
907
908 /* External state that comes from the last vertex stage, it must be
909 * set explicitely when binding a new graphics pipeline.
910 */
911 uint16_t stride_in_dw[MAX_SO_BUFFERS];
912 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
913
914 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
915 uint32_t hw_enabled_mask;
916
917 /* State of VGT_STRMOUT_(CONFIG|EN) */
918 bool streamout_enabled;
919 };
920
921 struct radv_viewport_state {
922 uint32_t count;
923 VkViewport viewports[MAX_VIEWPORTS];
924 };
925
926 struct radv_scissor_state {
927 uint32_t count;
928 VkRect2D scissors[MAX_SCISSORS];
929 };
930
931 struct radv_discard_rectangle_state {
932 uint32_t count;
933 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
934 };
935
936 struct radv_dynamic_state {
937 /**
938 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
939 * Defines the set of saved dynamic state.
940 */
941 uint32_t mask;
942
943 struct radv_viewport_state viewport;
944
945 struct radv_scissor_state scissor;
946
947 float line_width;
948
949 struct {
950 float bias;
951 float clamp;
952 float slope;
953 } depth_bias;
954
955 float blend_constants[4];
956
957 struct {
958 float min;
959 float max;
960 } depth_bounds;
961
962 struct {
963 uint32_t front;
964 uint32_t back;
965 } stencil_compare_mask;
966
967 struct {
968 uint32_t front;
969 uint32_t back;
970 } stencil_write_mask;
971
972 struct {
973 uint32_t front;
974 uint32_t back;
975 } stencil_reference;
976
977 struct radv_discard_rectangle_state discard_rectangle;
978 };
979
980 extern const struct radv_dynamic_state default_dynamic_state;
981
982 const char *
983 radv_get_debug_option_name(int id);
984
985 const char *
986 radv_get_perftest_option_name(int id);
987
988 /**
989 * Attachment state when recording a renderpass instance.
990 *
991 * The clear value is valid only if there exists a pending clear.
992 */
993 struct radv_attachment_state {
994 VkImageAspectFlags pending_clear_aspects;
995 uint32_t cleared_views;
996 VkClearValue clear_value;
997 VkImageLayout current_layout;
998 };
999
1000 struct radv_descriptor_state {
1001 struct radv_descriptor_set *sets[MAX_SETS];
1002 uint32_t dirty;
1003 uint32_t valid;
1004 struct radv_push_descriptor_set push_set;
1005 bool push_dirty;
1006 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1007 };
1008
1009 struct radv_cmd_state {
1010 /* Vertex descriptors */
1011 uint64_t vb_va;
1012 unsigned vb_size;
1013
1014 bool predicating;
1015 uint32_t dirty;
1016
1017 uint32_t prefetch_L2_mask;
1018
1019 struct radv_pipeline * pipeline;
1020 struct radv_pipeline * emitted_pipeline;
1021 struct radv_pipeline * compute_pipeline;
1022 struct radv_pipeline * emitted_compute_pipeline;
1023 struct radv_framebuffer * framebuffer;
1024 struct radv_render_pass * pass;
1025 const struct radv_subpass * subpass;
1026 struct radv_dynamic_state dynamic;
1027 struct radv_attachment_state * attachments;
1028 struct radv_streamout_state streamout;
1029 VkRect2D render_area;
1030
1031 /* Index buffer */
1032 struct radv_buffer *index_buffer;
1033 uint64_t index_offset;
1034 uint32_t index_type;
1035 uint32_t max_index_count;
1036 uint64_t index_va;
1037 int32_t last_index_type;
1038
1039 int32_t last_primitive_reset_en;
1040 uint32_t last_primitive_reset_index;
1041 enum radv_cmd_flush_bits flush_bits;
1042 unsigned active_occlusion_queries;
1043 bool perfect_occlusion_queries_enabled;
1044 unsigned active_pipeline_queries;
1045 float offset_scale;
1046 uint32_t trace_id;
1047 uint32_t last_ia_multi_vgt_param;
1048
1049 uint32_t last_num_instances;
1050 uint32_t last_first_instance;
1051 uint32_t last_vertex_offset;
1052
1053 /* Whether CP DMA is busy/idle. */
1054 bool dma_is_busy;
1055
1056 /* Conditional rendering info. */
1057 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1058 uint64_t predication_va;
1059 };
1060
1061 struct radv_cmd_pool {
1062 VkAllocationCallbacks alloc;
1063 struct list_head cmd_buffers;
1064 struct list_head free_cmd_buffers;
1065 uint32_t queue_family_index;
1066 };
1067
1068 struct radv_cmd_buffer_upload {
1069 uint8_t *map;
1070 unsigned offset;
1071 uint64_t size;
1072 struct radeon_winsys_bo *upload_bo;
1073 struct list_head list;
1074 };
1075
1076 enum radv_cmd_buffer_status {
1077 RADV_CMD_BUFFER_STATUS_INVALID,
1078 RADV_CMD_BUFFER_STATUS_INITIAL,
1079 RADV_CMD_BUFFER_STATUS_RECORDING,
1080 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1081 RADV_CMD_BUFFER_STATUS_PENDING,
1082 };
1083
1084 struct radv_cmd_buffer {
1085 VK_LOADER_DATA _loader_data;
1086
1087 struct radv_device * device;
1088
1089 struct radv_cmd_pool * pool;
1090 struct list_head pool_link;
1091
1092 VkCommandBufferUsageFlags usage_flags;
1093 VkCommandBufferLevel level;
1094 enum radv_cmd_buffer_status status;
1095 struct radeon_cmdbuf *cs;
1096 struct radv_cmd_state state;
1097 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1098 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1099 uint32_t queue_family_index;
1100
1101 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1102 VkShaderStageFlags push_constant_stages;
1103 struct radv_descriptor_set meta_push_descriptors;
1104
1105 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1106
1107 struct radv_cmd_buffer_upload upload;
1108
1109 uint32_t scratch_size_needed;
1110 uint32_t compute_scratch_size_needed;
1111 uint32_t esgs_ring_size_needed;
1112 uint32_t gsvs_ring_size_needed;
1113 bool tess_rings_needed;
1114 bool sample_positions_needed;
1115
1116 VkResult record_result;
1117
1118 uint32_t gfx9_fence_offset;
1119 struct radeon_winsys_bo *gfx9_fence_bo;
1120 uint32_t gfx9_fence_idx;
1121 uint64_t gfx9_eop_bug_va;
1122
1123 /**
1124 * Whether a query pool has been resetted and we have to flush caches.
1125 */
1126 bool pending_reset_query;
1127 };
1128
1129 struct radv_image;
1130
1131 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1132
1133 void si_emit_graphics(struct radv_physical_device *physical_device,
1134 struct radeon_cmdbuf *cs);
1135 void si_emit_compute(struct radv_physical_device *physical_device,
1136 struct radeon_cmdbuf *cs);
1137
1138 void cik_create_gfx_config(struct radv_device *device);
1139
1140 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1141 int count, const VkViewport *viewports);
1142 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1143 int count, const VkRect2D *scissors,
1144 const VkViewport *viewports, bool can_use_guardband);
1145 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1146 bool instanced_draw, bool indirect_draw,
1147 uint32_t draw_vertex_count);
1148 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1149 enum chip_class chip_class,
1150 bool is_mec,
1151 unsigned event, unsigned event_flags,
1152 unsigned data_sel,
1153 uint64_t va,
1154 uint32_t old_fence,
1155 uint32_t new_fence,
1156 uint64_t gfx9_eop_bug_va);
1157
1158 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1159 uint32_t ref, uint32_t mask);
1160 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1161 enum chip_class chip_class,
1162 uint32_t *fence_ptr, uint64_t va,
1163 bool is_mec,
1164 enum radv_cmd_flush_bits flush_bits,
1165 uint64_t gfx9_eop_bug_va);
1166 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1167 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1168 bool inverted, uint64_t va);
1169 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1170 uint64_t src_va, uint64_t dest_va,
1171 uint64_t size);
1172 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1173 unsigned size);
1174 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1175 uint64_t size, unsigned value);
1176 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1177
1178 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1179 bool
1180 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1181 unsigned size,
1182 unsigned alignment,
1183 unsigned *out_offset,
1184 void **ptr);
1185 void
1186 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1187 const struct radv_subpass *subpass,
1188 bool transitions);
1189 bool
1190 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1191 unsigned size, unsigned alignmnet,
1192 const void *data, unsigned *out_offset);
1193
1194 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1195 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1196 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1197 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1198 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1199 unsigned radv_cayman_get_maxdist(int log_samples);
1200 void radv_device_init_msaa(struct radv_device *device);
1201
1202 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1203 struct radv_image *image,
1204 VkClearDepthStencilValue ds_clear_value,
1205 VkImageAspectFlags aspects);
1206
1207 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1208 struct radv_image *image,
1209 int cb_idx,
1210 uint32_t color_values[2]);
1211
1212 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1213 struct radv_image *image, bool value);
1214
1215 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1216 struct radv_image *image, bool value);
1217
1218 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1219 struct radeon_winsys_bo *bo,
1220 uint64_t offset, uint64_t size, uint32_t value);
1221 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1222 bool radv_get_memory_fd(struct radv_device *device,
1223 struct radv_device_memory *memory,
1224 int *pFD);
1225
1226 static inline void
1227 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1228 unsigned sh_offset, unsigned pointer_count,
1229 bool use_32bit_pointers)
1230 {
1231 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1232 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1233 }
1234
1235 static inline void
1236 radv_emit_shader_pointer_body(struct radv_device *device,
1237 struct radeon_cmdbuf *cs,
1238 uint64_t va, bool use_32bit_pointers)
1239 {
1240 radeon_emit(cs, va);
1241
1242 if (use_32bit_pointers) {
1243 assert(va == 0 ||
1244 (va >> 32) == device->physical_device->rad_info.address32_hi);
1245 } else {
1246 radeon_emit(cs, va >> 32);
1247 }
1248 }
1249
1250 static inline void
1251 radv_emit_shader_pointer(struct radv_device *device,
1252 struct radeon_cmdbuf *cs,
1253 uint32_t sh_offset, uint64_t va, bool global)
1254 {
1255 bool use_32bit_pointers = !global;
1256
1257 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1258 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1259 }
1260
1261 static inline struct radv_descriptor_state *
1262 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1263 VkPipelineBindPoint bind_point)
1264 {
1265 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1266 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1267 return &cmd_buffer->descriptors[bind_point];
1268 }
1269
1270 /*
1271 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1272 *
1273 * Limitations: Can't call normal dispatch functions without binding or rebinding
1274 * the compute pipeline.
1275 */
1276 void radv_unaligned_dispatch(
1277 struct radv_cmd_buffer *cmd_buffer,
1278 uint32_t x,
1279 uint32_t y,
1280 uint32_t z);
1281
1282 struct radv_event {
1283 struct radeon_winsys_bo *bo;
1284 uint64_t *map;
1285 };
1286
1287 struct radv_shader_module;
1288
1289 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1290 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1291 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1292 void
1293 radv_hash_shaders(unsigned char *hash,
1294 const VkPipelineShaderStageCreateInfo **stages,
1295 const struct radv_pipeline_layout *layout,
1296 const struct radv_pipeline_key *key,
1297 uint32_t flags);
1298
1299 static inline gl_shader_stage
1300 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1301 {
1302 assert(__builtin_popcount(vk_stage) == 1);
1303 return ffs(vk_stage) - 1;
1304 }
1305
1306 static inline VkShaderStageFlagBits
1307 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1308 {
1309 return (1 << mesa_stage);
1310 }
1311
1312 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1313
1314 #define radv_foreach_stage(stage, stage_bits) \
1315 for (gl_shader_stage stage, \
1316 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1317 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1318 __tmp &= ~(1 << (stage)))
1319
1320 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1321 unsigned radv_format_meta_fs_key(VkFormat format);
1322
1323 struct radv_multisample_state {
1324 uint32_t db_eqaa;
1325 uint32_t pa_sc_line_cntl;
1326 uint32_t pa_sc_mode_cntl_0;
1327 uint32_t pa_sc_mode_cntl_1;
1328 uint32_t pa_sc_aa_config;
1329 uint32_t pa_sc_aa_mask[2];
1330 unsigned num_samples;
1331 };
1332
1333 struct radv_prim_vertex_count {
1334 uint8_t min;
1335 uint8_t incr;
1336 };
1337
1338 struct radv_vertex_elements_info {
1339 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1340 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1341 uint32_t binding[MAX_VERTEX_ATTRIBS];
1342 uint32_t offset[MAX_VERTEX_ATTRIBS];
1343 uint32_t count;
1344 };
1345
1346 struct radv_ia_multi_vgt_param_helpers {
1347 uint32_t base;
1348 bool partial_es_wave;
1349 uint8_t primgroup_size;
1350 bool wd_switch_on_eop;
1351 bool ia_switch_on_eoi;
1352 bool partial_vs_wave;
1353 };
1354
1355 #define SI_GS_PER_ES 128
1356
1357 struct radv_pipeline {
1358 struct radv_device * device;
1359 struct radv_dynamic_state dynamic_state;
1360
1361 struct radv_pipeline_layout * layout;
1362
1363 bool need_indirect_descriptor_sets;
1364 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1365 struct radv_shader_variant *gs_copy_shader;
1366 VkShaderStageFlags active_stages;
1367
1368 struct radeon_cmdbuf cs;
1369
1370 struct radv_vertex_elements_info vertex_elements;
1371
1372 uint32_t binding_stride[MAX_VBS];
1373
1374 uint32_t user_data_0[MESA_SHADER_STAGES];
1375 union {
1376 struct {
1377 struct radv_multisample_state ms;
1378 uint32_t spi_baryc_cntl;
1379 bool prim_restart_enable;
1380 unsigned esgs_ring_size;
1381 unsigned gsvs_ring_size;
1382 uint32_t vtx_base_sgpr;
1383 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1384 uint8_t vtx_emit_num;
1385 struct radv_prim_vertex_count prim_vertex_count;
1386 bool can_use_guardband;
1387 uint32_t needed_dynamic_state;
1388 bool disable_out_of_order_rast_for_occlusion;
1389
1390 /* Used for rbplus */
1391 uint32_t col_format;
1392 uint32_t cb_target_mask;
1393 } graphics;
1394 };
1395
1396 unsigned max_waves;
1397 unsigned scratch_bytes_per_wave;
1398
1399 /* Not NULL if graphics pipeline uses streamout. */
1400 struct radv_shader_variant *streamout_shader;
1401 };
1402
1403 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1404 {
1405 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1406 }
1407
1408 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1409 {
1410 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1411 }
1412
1413 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1414 gl_shader_stage stage,
1415 int idx);
1416
1417 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1418 gl_shader_stage stage);
1419
1420 struct radv_graphics_pipeline_create_info {
1421 bool use_rectlist;
1422 bool db_depth_clear;
1423 bool db_stencil_clear;
1424 bool db_depth_disable_expclear;
1425 bool db_stencil_disable_expclear;
1426 bool db_flush_depth_inplace;
1427 bool db_flush_stencil_inplace;
1428 bool db_resummarize;
1429 uint32_t custom_blend_mode;
1430 };
1431
1432 VkResult
1433 radv_graphics_pipeline_create(VkDevice device,
1434 VkPipelineCache cache,
1435 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1436 const struct radv_graphics_pipeline_create_info *extra,
1437 const VkAllocationCallbacks *alloc,
1438 VkPipeline *pPipeline);
1439
1440 struct vk_format_description;
1441 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1442 int first_non_void);
1443 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1444 int first_non_void);
1445 uint32_t radv_translate_colorformat(VkFormat format);
1446 uint32_t radv_translate_color_numformat(VkFormat format,
1447 const struct vk_format_description *desc,
1448 int first_non_void);
1449 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1450 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1451 uint32_t radv_translate_dbformat(VkFormat format);
1452 uint32_t radv_translate_tex_dataformat(VkFormat format,
1453 const struct vk_format_description *desc,
1454 int first_non_void);
1455 uint32_t radv_translate_tex_numformat(VkFormat format,
1456 const struct vk_format_description *desc,
1457 int first_non_void);
1458 bool radv_format_pack_clear_color(VkFormat format,
1459 uint32_t clear_vals[2],
1460 VkClearColorValue *value);
1461 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1462 bool radv_dcc_formats_compatible(VkFormat format1,
1463 VkFormat format2);
1464
1465 struct radv_fmask_info {
1466 uint64_t offset;
1467 uint64_t size;
1468 unsigned alignment;
1469 unsigned pitch_in_pixels;
1470 unsigned bank_height;
1471 unsigned slice_tile_max;
1472 unsigned tile_mode_index;
1473 unsigned tile_swizzle;
1474 };
1475
1476 struct radv_cmask_info {
1477 uint64_t offset;
1478 uint64_t size;
1479 unsigned alignment;
1480 unsigned slice_tile_max;
1481 };
1482
1483 struct radv_image {
1484 VkImageType type;
1485 /* The original VkFormat provided by the client. This may not match any
1486 * of the actual surface formats.
1487 */
1488 VkFormat vk_format;
1489 VkImageAspectFlags aspects;
1490 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1491 struct ac_surf_info info;
1492 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1493 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1494
1495 VkDeviceSize size;
1496 uint32_t alignment;
1497
1498 unsigned queue_family_mask;
1499 bool exclusive;
1500 bool shareable;
1501
1502 /* Set when bound */
1503 struct radeon_winsys_bo *bo;
1504 VkDeviceSize offset;
1505 uint64_t dcc_offset;
1506 uint64_t htile_offset;
1507 bool tc_compatible_htile;
1508 struct radeon_surf surface;
1509
1510 struct radv_fmask_info fmask;
1511 struct radv_cmask_info cmask;
1512 uint64_t clear_value_offset;
1513 uint64_t fce_pred_offset;
1514 uint64_t dcc_pred_offset;
1515
1516 /*
1517 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1518 * stored at this offset is UINT_MAX, the driver will emit
1519 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1520 * SET_CONTEXT_REG packet.
1521 */
1522 uint64_t tc_compat_zrange_offset;
1523
1524 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1525 VkDeviceMemory owned_memory;
1526 };
1527
1528 /* Whether the image has a htile that is known consistent with the contents of
1529 * the image. */
1530 bool radv_layout_has_htile(const struct radv_image *image,
1531 VkImageLayout layout,
1532 unsigned queue_mask);
1533
1534 /* Whether the image has a htile that is known consistent with the contents of
1535 * the image and is allowed to be in compressed form.
1536 *
1537 * If this is false reads that don't use the htile should be able to return
1538 * correct results.
1539 */
1540 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1541 VkImageLayout layout,
1542 unsigned queue_mask);
1543
1544 bool radv_layout_can_fast_clear(const struct radv_image *image,
1545 VkImageLayout layout,
1546 unsigned queue_mask);
1547
1548 bool radv_layout_dcc_compressed(const struct radv_image *image,
1549 VkImageLayout layout,
1550 unsigned queue_mask);
1551
1552 /**
1553 * Return whether the image has CMASK metadata for color surfaces.
1554 */
1555 static inline bool
1556 radv_image_has_cmask(const struct radv_image *image)
1557 {
1558 return image->cmask.size;
1559 }
1560
1561 /**
1562 * Return whether the image has FMASK metadata for color surfaces.
1563 */
1564 static inline bool
1565 radv_image_has_fmask(const struct radv_image *image)
1566 {
1567 return image->fmask.size;
1568 }
1569
1570 /**
1571 * Return whether the image has DCC metadata for color surfaces.
1572 */
1573 static inline bool
1574 radv_image_has_dcc(const struct radv_image *image)
1575 {
1576 return image->surface.dcc_size;
1577 }
1578
1579 /**
1580 * Return whether DCC metadata is enabled for a level.
1581 */
1582 static inline bool
1583 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1584 {
1585 return radv_image_has_dcc(image) &&
1586 level < image->surface.num_dcc_levels;
1587 }
1588
1589 /**
1590 * Return whether the image has CB metadata.
1591 */
1592 static inline bool
1593 radv_image_has_CB_metadata(const struct radv_image *image)
1594 {
1595 return radv_image_has_cmask(image) ||
1596 radv_image_has_fmask(image) ||
1597 radv_image_has_dcc(image);
1598 }
1599
1600 /**
1601 * Return whether the image has HTILE metadata for depth surfaces.
1602 */
1603 static inline bool
1604 radv_image_has_htile(const struct radv_image *image)
1605 {
1606 return image->surface.htile_size;
1607 }
1608
1609 /**
1610 * Return whether HTILE metadata is enabled for a level.
1611 */
1612 static inline bool
1613 radv_htile_enabled(const struct radv_image *image, unsigned level)
1614 {
1615 return radv_image_has_htile(image) && level == 0;
1616 }
1617
1618 /**
1619 * Return whether the image is TC-compatible HTILE.
1620 */
1621 static inline bool
1622 radv_image_is_tc_compat_htile(const struct radv_image *image)
1623 {
1624 return radv_image_has_htile(image) && image->tc_compatible_htile;
1625 }
1626
1627 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1628
1629 static inline uint32_t
1630 radv_get_layerCount(const struct radv_image *image,
1631 const VkImageSubresourceRange *range)
1632 {
1633 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1634 image->info.array_size - range->baseArrayLayer : range->layerCount;
1635 }
1636
1637 static inline uint32_t
1638 radv_get_levelCount(const struct radv_image *image,
1639 const VkImageSubresourceRange *range)
1640 {
1641 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1642 image->info.levels - range->baseMipLevel : range->levelCount;
1643 }
1644
1645 struct radeon_bo_metadata;
1646 void
1647 radv_init_metadata(struct radv_device *device,
1648 struct radv_image *image,
1649 struct radeon_bo_metadata *metadata);
1650
1651 struct radv_image_view {
1652 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1653 struct radeon_winsys_bo *bo;
1654
1655 VkImageViewType type;
1656 VkImageAspectFlags aspect_mask;
1657 VkFormat vk_format;
1658 uint32_t base_layer;
1659 uint32_t layer_count;
1660 uint32_t base_mip;
1661 uint32_t level_count;
1662 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1663
1664 uint32_t descriptor[16];
1665
1666 /* Descriptor for use as a storage image as opposed to a sampled image.
1667 * This has a few differences for cube maps (e.g. type).
1668 */
1669 uint32_t storage_descriptor[16];
1670 };
1671
1672 struct radv_image_create_info {
1673 const VkImageCreateInfo *vk_info;
1674 bool scanout;
1675 bool no_metadata_planes;
1676 };
1677
1678 VkResult radv_image_create(VkDevice _device,
1679 const struct radv_image_create_info *info,
1680 const VkAllocationCallbacks* alloc,
1681 VkImage *pImage);
1682
1683 VkResult
1684 radv_image_from_gralloc(VkDevice device_h,
1685 const VkImageCreateInfo *base_info,
1686 const VkNativeBufferANDROID *gralloc_info,
1687 const VkAllocationCallbacks *alloc,
1688 VkImage *out_image_h);
1689
1690 void radv_image_view_init(struct radv_image_view *view,
1691 struct radv_device *device,
1692 const VkImageViewCreateInfo* pCreateInfo);
1693
1694 struct radv_buffer_view {
1695 struct radeon_winsys_bo *bo;
1696 VkFormat vk_format;
1697 uint64_t range; /**< VkBufferViewCreateInfo::range */
1698 uint32_t state[4];
1699 };
1700 void radv_buffer_view_init(struct radv_buffer_view *view,
1701 struct radv_device *device,
1702 const VkBufferViewCreateInfo* pCreateInfo);
1703
1704 static inline struct VkExtent3D
1705 radv_sanitize_image_extent(const VkImageType imageType,
1706 const struct VkExtent3D imageExtent)
1707 {
1708 switch (imageType) {
1709 case VK_IMAGE_TYPE_1D:
1710 return (VkExtent3D) { imageExtent.width, 1, 1 };
1711 case VK_IMAGE_TYPE_2D:
1712 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1713 case VK_IMAGE_TYPE_3D:
1714 return imageExtent;
1715 default:
1716 unreachable("invalid image type");
1717 }
1718 }
1719
1720 static inline struct VkOffset3D
1721 radv_sanitize_image_offset(const VkImageType imageType,
1722 const struct VkOffset3D imageOffset)
1723 {
1724 switch (imageType) {
1725 case VK_IMAGE_TYPE_1D:
1726 return (VkOffset3D) { imageOffset.x, 0, 0 };
1727 case VK_IMAGE_TYPE_2D:
1728 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1729 case VK_IMAGE_TYPE_3D:
1730 return imageOffset;
1731 default:
1732 unreachable("invalid image type");
1733 }
1734 }
1735
1736 static inline bool
1737 radv_image_extent_compare(const struct radv_image *image,
1738 const VkExtent3D *extent)
1739 {
1740 if (extent->width != image->info.width ||
1741 extent->height != image->info.height ||
1742 extent->depth != image->info.depth)
1743 return false;
1744 return true;
1745 }
1746
1747 struct radv_sampler {
1748 uint32_t state[4];
1749 };
1750
1751 struct radv_color_buffer_info {
1752 uint64_t cb_color_base;
1753 uint64_t cb_color_cmask;
1754 uint64_t cb_color_fmask;
1755 uint64_t cb_dcc_base;
1756 uint32_t cb_color_pitch;
1757 uint32_t cb_color_slice;
1758 uint32_t cb_color_view;
1759 uint32_t cb_color_info;
1760 uint32_t cb_color_attrib;
1761 uint32_t cb_color_attrib2;
1762 uint32_t cb_dcc_control;
1763 uint32_t cb_color_cmask_slice;
1764 uint32_t cb_color_fmask_slice;
1765 };
1766
1767 struct radv_ds_buffer_info {
1768 uint64_t db_z_read_base;
1769 uint64_t db_stencil_read_base;
1770 uint64_t db_z_write_base;
1771 uint64_t db_stencil_write_base;
1772 uint64_t db_htile_data_base;
1773 uint32_t db_depth_info;
1774 uint32_t db_z_info;
1775 uint32_t db_stencil_info;
1776 uint32_t db_depth_view;
1777 uint32_t db_depth_size;
1778 uint32_t db_depth_slice;
1779 uint32_t db_htile_surface;
1780 uint32_t pa_su_poly_offset_db_fmt_cntl;
1781 uint32_t db_z_info2;
1782 uint32_t db_stencil_info2;
1783 float offset_scale;
1784 };
1785
1786 struct radv_attachment_info {
1787 union {
1788 struct radv_color_buffer_info cb;
1789 struct radv_ds_buffer_info ds;
1790 };
1791 struct radv_image_view *attachment;
1792 };
1793
1794 struct radv_framebuffer {
1795 uint32_t width;
1796 uint32_t height;
1797 uint32_t layers;
1798
1799 uint32_t attachment_count;
1800 struct radv_attachment_info attachments[0];
1801 };
1802
1803 struct radv_subpass_barrier {
1804 VkPipelineStageFlags src_stage_mask;
1805 VkAccessFlags src_access_mask;
1806 VkAccessFlags dst_access_mask;
1807 };
1808
1809 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1810 const struct radv_subpass_barrier *barrier);
1811
1812 struct radv_subpass_attachment {
1813 uint32_t attachment;
1814 VkImageLayout layout;
1815 };
1816
1817 struct radv_subpass {
1818 uint32_t input_count;
1819 uint32_t color_count;
1820 struct radv_subpass_attachment * input_attachments;
1821 struct radv_subpass_attachment * color_attachments;
1822 struct radv_subpass_attachment * resolve_attachments;
1823 struct radv_subpass_attachment depth_stencil_attachment;
1824
1825 /** Subpass has at least one resolve attachment */
1826 bool has_resolve;
1827
1828 struct radv_subpass_barrier start_barrier;
1829
1830 uint32_t view_mask;
1831 VkSampleCountFlagBits max_sample_count;
1832 };
1833
1834 struct radv_render_pass_attachment {
1835 VkFormat format;
1836 uint32_t samples;
1837 VkAttachmentLoadOp load_op;
1838 VkAttachmentLoadOp stencil_load_op;
1839 VkImageLayout initial_layout;
1840 VkImageLayout final_layout;
1841 uint32_t view_mask;
1842 };
1843
1844 struct radv_render_pass {
1845 uint32_t attachment_count;
1846 uint32_t subpass_count;
1847 struct radv_subpass_attachment * subpass_attachments;
1848 struct radv_render_pass_attachment * attachments;
1849 struct radv_subpass_barrier end_barrier;
1850 struct radv_subpass subpasses[0];
1851 };
1852
1853 VkResult radv_device_init_meta(struct radv_device *device);
1854 void radv_device_finish_meta(struct radv_device *device);
1855
1856 struct radv_query_pool {
1857 struct radeon_winsys_bo *bo;
1858 uint32_t stride;
1859 uint32_t availability_offset;
1860 uint64_t size;
1861 char *ptr;
1862 VkQueryType type;
1863 uint32_t pipeline_stats_mask;
1864 };
1865
1866 struct radv_semaphore {
1867 /* use a winsys sem for non-exportable */
1868 struct radeon_winsys_sem *sem;
1869 uint32_t syncobj;
1870 uint32_t temp_syncobj;
1871 };
1872
1873 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1874 VkPipelineBindPoint bind_point,
1875 struct radv_descriptor_set *set,
1876 unsigned idx);
1877
1878 void
1879 radv_update_descriptor_sets(struct radv_device *device,
1880 struct radv_cmd_buffer *cmd_buffer,
1881 VkDescriptorSet overrideSet,
1882 uint32_t descriptorWriteCount,
1883 const VkWriteDescriptorSet *pDescriptorWrites,
1884 uint32_t descriptorCopyCount,
1885 const VkCopyDescriptorSet *pDescriptorCopies);
1886
1887 void
1888 radv_update_descriptor_set_with_template(struct radv_device *device,
1889 struct radv_cmd_buffer *cmd_buffer,
1890 struct radv_descriptor_set *set,
1891 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1892 const void *pData);
1893
1894 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1895 VkPipelineBindPoint pipelineBindPoint,
1896 VkPipelineLayout _layout,
1897 uint32_t set,
1898 uint32_t descriptorWriteCount,
1899 const VkWriteDescriptorSet *pDescriptorWrites);
1900
1901 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1902 struct radv_image *image, uint32_t value);
1903
1904 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
1905 struct radv_image *image);
1906
1907 struct radv_fence {
1908 struct radeon_winsys_fence *fence;
1909 struct wsi_fence *fence_wsi;
1910 bool submitted;
1911 bool signalled;
1912
1913 uint32_t syncobj;
1914 uint32_t temp_syncobj;
1915 };
1916
1917 /* radv_nir_to_llvm.c */
1918 struct radv_shader_variant_info;
1919 struct radv_nir_compiler_options;
1920
1921 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1922 struct nir_shader *geom_shader,
1923 struct ac_shader_binary *binary,
1924 struct ac_shader_config *config,
1925 struct radv_shader_variant_info *shader_info,
1926 const struct radv_nir_compiler_options *option);
1927
1928 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1929 struct ac_shader_binary *binary,
1930 struct ac_shader_config *config,
1931 struct radv_shader_variant_info *shader_info,
1932 struct nir_shader *const *nir,
1933 int nir_count,
1934 const struct radv_nir_compiler_options *options);
1935
1936 /* radv_shader_info.h */
1937 struct radv_shader_info;
1938
1939 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1940 const struct radv_nir_compiler_options *options,
1941 struct radv_shader_info *info);
1942
1943 struct radeon_winsys_sem;
1944
1945 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1946 \
1947 static inline struct __radv_type * \
1948 __radv_type ## _from_handle(__VkType _handle) \
1949 { \
1950 return (struct __radv_type *) _handle; \
1951 } \
1952 \
1953 static inline __VkType \
1954 __radv_type ## _to_handle(struct __radv_type *_obj) \
1955 { \
1956 return (__VkType) _obj; \
1957 }
1958
1959 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1960 \
1961 static inline struct __radv_type * \
1962 __radv_type ## _from_handle(__VkType _handle) \
1963 { \
1964 return (struct __radv_type *)(uintptr_t) _handle; \
1965 } \
1966 \
1967 static inline __VkType \
1968 __radv_type ## _to_handle(struct __radv_type *_obj) \
1969 { \
1970 return (__VkType)(uintptr_t) _obj; \
1971 }
1972
1973 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1974 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1975
1976 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1977 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1978 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1979 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1980 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1981
1982 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1983 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1984 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1985 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1986 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1987 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1988 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1989 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1990 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1991 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1992 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1993 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1994 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1995 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1996 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1997 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1998 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1999 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2000 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2001 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2002 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2003
2004 #endif /* RADV_PRIVATE_H */