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c50e4016222964c0efb058c57d3a81df01444c29
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_IMAGES 8
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
84 #define NUM_META_FS_KEYS 11
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 #define radv_noreturn __attribute__((__noreturn__))
89 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
90
91 static inline uint32_t
92 align_u32(uint32_t v, uint32_t a)
93 {
94 assert(a != 0 && a == (a & -a));
95 return (v + a - 1) & ~(a - 1);
96 }
97
98 static inline uint32_t
99 align_u32_npot(uint32_t v, uint32_t a)
100 {
101 return (v + a - 1) / a * a;
102 }
103
104 static inline uint64_t
105 align_u64(uint64_t v, uint64_t a)
106 {
107 assert(a != 0 && a == (a & -a));
108 return (v + a - 1) & ~(a - 1);
109 }
110
111 static inline int32_t
112 align_i32(int32_t v, int32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 /** Alignment must be a power of 2. */
119 static inline bool
120 radv_is_aligned(uintmax_t n, uintmax_t a)
121 {
122 assert(a == (a & -a));
123 return (n & (a - 1)) == 0;
124 }
125
126 static inline uint32_t
127 round_up_u32(uint32_t v, uint32_t a)
128 {
129 return (v + a - 1) / a;
130 }
131
132 static inline uint64_t
133 round_up_u64(uint64_t v, uint64_t a)
134 {
135 return (v + a - 1) / a;
136 }
137
138 static inline uint32_t
139 radv_minify(uint32_t n, uint32_t levels)
140 {
141 if (unlikely(n == 0))
142 return 0;
143 else
144 return MAX2(n >> levels, 1);
145 }
146 static inline float
147 radv_clamp_f(float f, float min, float max)
148 {
149 assert(min < max);
150
151 if (f > max)
152 return max;
153 else if (f < min)
154 return min;
155 else
156 return f;
157 }
158
159 static inline bool
160 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
161 {
162 if (*inout_mask & clear_mask) {
163 *inout_mask &= ~clear_mask;
164 return true;
165 } else {
166 return false;
167 }
168 }
169
170 #define for_each_bit(b, dword) \
171 for (uint32_t __dword = (dword); \
172 (b) = __builtin_ffs(__dword) - 1, __dword; \
173 __dword &= ~(1 << (b)))
174
175 #define typed_memcpy(dest, src, count) ({ \
176 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
177 memcpy((dest), (src), (count) * sizeof(*(src))); \
178 })
179
180 #define zero(x) (memset(&(x), 0, sizeof(x)))
181
182 /* Define no kernel as 1, since that's an illegal offset for a kernel */
183 #define NO_KERNEL 1
184
185 struct radv_common {
186 VkStructureType sType;
187 const void* pNext;
188 };
189
190 /* Whenever we generate an error, pass it through this function. Useful for
191 * debugging, where we can break on it. Only call at error site, not when
192 * propagating errors. Might be useful to plug in a stack trace here.
193 */
194
195 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
196
197 #ifdef DEBUG
198 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
199 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
200 #else
201 #define vk_error(error) error
202 #define vk_errorf(error, format, ...) error
203 #endif
204
205 void __radv_finishme(const char *file, int line, const char *format, ...)
206 radv_printflike(3, 4);
207 void radv_loge(const char *format, ...) radv_printflike(1, 2);
208 void radv_loge_v(const char *format, va_list va);
209
210 /**
211 * Print a FINISHME message, including its source location.
212 */
213 #define radv_finishme(format, ...) \
214 do { \
215 static bool reported = false; \
216 if (!reported) { \
217 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
218 reported = true; \
219 } \
220 } while (0)
221
222 /* A non-fatal assert. Useful for debugging. */
223 #ifdef DEBUG
224 #define radv_assert(x) ({ \
225 if (unlikely(!(x))) \
226 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
227 })
228 #else
229 #define radv_assert(x)
230 #endif
231
232 void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
233 void radv_abortfv(const char *format, va_list va) radv_noreturn;
234
235 #define stub_return(v) \
236 do { \
237 radv_finishme("stub %s", __func__); \
238 return (v); \
239 } while (0)
240
241 #define stub() \
242 do { \
243 radv_finishme("stub %s", __func__); \
244 return; \
245 } while (0)
246
247 void *radv_resolve_entrypoint(uint32_t index);
248 void *radv_lookup_entrypoint(const char *name);
249
250 extern struct radv_dispatch_table dtable;
251
252 struct radv_physical_device {
253 VK_LOADER_DATA _loader_data;
254
255 struct radv_instance * instance;
256
257 struct radeon_winsys *ws;
258 struct radeon_info rad_info;
259 uint32_t chipset_id;
260 char path[20];
261 const char * name;
262 uint64_t aperture_size;
263 int cmd_parser_version;
264 uint32_t pci_vendor_id;
265 uint32_t pci_device_id;
266
267 uint8_t uuid[VK_UUID_SIZE];
268
269 struct wsi_device wsi_device;
270 };
271
272 struct radv_instance {
273 VK_LOADER_DATA _loader_data;
274
275 VkAllocationCallbacks alloc;
276
277 uint32_t apiVersion;
278 int physicalDeviceCount;
279 struct radv_physical_device physicalDevice;
280 };
281
282 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
283 void radv_finish_wsi(struct radv_physical_device *physical_device);
284
285 struct cache_entry;
286
287 struct radv_pipeline_cache {
288 struct radv_device * device;
289 pthread_mutex_t mutex;
290
291 uint32_t total_size;
292 uint32_t table_size;
293 uint32_t kernel_count;
294 struct cache_entry ** hash_table;
295 bool modified;
296
297 VkAllocationCallbacks alloc;
298 };
299
300 void
301 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
302 struct radv_device *device);
303 void
304 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
305 void
306 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
307 const void *data, size_t size);
308
309 struct radv_shader_variant *
310 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
311 struct radv_pipeline_cache *cache,
312 const unsigned char *sha1);
313
314 struct radv_shader_variant *
315 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
316 const unsigned char *sha1,
317 struct radv_shader_variant *variant,
318 const void *code, unsigned code_size);
319
320 void radv_shader_variant_destroy(struct radv_device *device,
321 struct radv_shader_variant *variant);
322
323 struct radv_meta_state {
324 VkAllocationCallbacks alloc;
325
326 struct radv_pipeline_cache cache;
327
328 /**
329 * Use array element `i` for images with `2^i` samples.
330 */
331 struct {
332 VkRenderPass render_pass[NUM_META_FS_KEYS];
333 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
334
335 VkRenderPass depth_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
336 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
337 VkRenderPass stencil_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
338 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
339 VkRenderPass depthstencil_rp[NUM_DEPTH_CLEAR_PIPELINES];
340 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
341 } clear[1 + MAX_SAMPLES_LOG2];
342
343 struct {
344 VkRenderPass render_pass[NUM_META_FS_KEYS];
345
346 /** Pipeline that blits from a 1D image. */
347 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
348
349 /** Pipeline that blits from a 2D image. */
350 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
351
352 /** Pipeline that blits from a 3D image. */
353 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
354
355 VkRenderPass depth_only_rp;
356 VkPipeline depth_only_1d_pipeline;
357 VkPipeline depth_only_2d_pipeline;
358 VkPipeline depth_only_3d_pipeline;
359
360 VkRenderPass stencil_only_rp;
361 VkPipeline stencil_only_1d_pipeline;
362 VkPipeline stencil_only_2d_pipeline;
363 VkPipeline stencil_only_3d_pipeline;
364 VkPipelineLayout pipeline_layout;
365 VkDescriptorSetLayout ds_layout;
366 } blit;
367
368 struct {
369 VkRenderPass render_passes[NUM_META_FS_KEYS];
370
371 VkPipelineLayout p_layouts[2];
372 VkDescriptorSetLayout ds_layouts[2];
373 VkPipeline pipelines[2][NUM_META_FS_KEYS];
374
375 VkRenderPass depth_only_rp;
376 VkPipeline depth_only_pipeline[2];
377
378 VkRenderPass stencil_only_rp;
379 VkPipeline stencil_only_pipeline[2];
380 } blit2d;
381
382 struct {
383 VkPipelineLayout img_p_layout;
384 VkDescriptorSetLayout img_ds_layout;
385 VkPipeline pipeline;
386 } itob;
387 struct {
388 VkRenderPass render_pass;
389 VkPipelineLayout img_p_layout;
390 VkDescriptorSetLayout img_ds_layout;
391 VkPipeline pipeline;
392 } btoi;
393
394 struct {
395 VkPipeline pipeline;
396 VkRenderPass pass;
397 } resolve;
398
399 struct {
400 VkDescriptorSetLayout ds_layout;
401 VkPipelineLayout p_layout;
402 struct {
403 VkPipeline pipeline;
404 VkPipeline i_pipeline;
405 } rc[MAX_SAMPLES_LOG2];
406 } resolve_compute;
407
408 struct {
409 VkPipeline decompress_pipeline;
410 VkPipeline resummarize_pipeline;
411 VkRenderPass pass;
412 } depth_decomp;
413
414 struct {
415 VkPipeline cmask_eliminate_pipeline;
416 VkPipeline fmask_decompress_pipeline;
417 VkRenderPass pass;
418 } fast_clear_flush;
419
420 struct {
421 VkPipelineLayout fill_p_layout;
422 VkPipelineLayout copy_p_layout;
423 VkDescriptorSetLayout fill_ds_layout;
424 VkDescriptorSetLayout copy_ds_layout;
425 VkPipeline fill_pipeline;
426 VkPipeline copy_pipeline;
427 } buffer;
428 };
429
430 struct radv_queue {
431 VK_LOADER_DATA _loader_data;
432
433 struct radv_device * device;
434
435 struct radv_state_pool * pool;
436 };
437
438 struct radv_device {
439 VK_LOADER_DATA _loader_data;
440
441 VkAllocationCallbacks alloc;
442
443 struct radv_instance * instance;
444 struct radeon_winsys *ws;
445 struct radeon_winsys_ctx *hw_ctx;
446
447 struct radv_meta_state meta_state;
448 struct radv_queue queue;
449 struct radeon_winsys_cs *empty_cs;
450
451 bool allow_fast_clears;
452 bool allow_dcc;
453 bool shader_stats_dump;
454
455 /* MSAA sample locations.
456 * The first index is the sample index.
457 * The second index is the coordinate: X, Y. */
458 float sample_locations_1x[1][2];
459 float sample_locations_2x[2][2];
460 float sample_locations_4x[4][2];
461 float sample_locations_8x[8][2];
462 float sample_locations_16x[16][2];
463 };
464
465 struct radv_device_memory {
466 struct radeon_winsys_bo *bo;
467 uint32_t type_index;
468 VkDeviceSize map_size;
469 void * map;
470 };
471
472
473 struct radv_descriptor_range {
474 uint64_t va;
475 uint32_t size;
476 };
477
478 struct radv_descriptor_set {
479 const struct radv_descriptor_set_layout *layout;
480 struct list_head descriptor_pool;
481 uint32_t size;
482
483 struct radv_buffer_view *buffer_views;
484 struct radeon_winsys_bo *bo;
485 uint64_t va;
486 uint32_t *mapped_ptr;
487 struct radv_descriptor_range *dynamic_descriptors;
488 struct radeon_winsys_bo *descriptors[0];
489 };
490
491 struct radv_descriptor_pool_free_node {
492 int next;
493 uint32_t offset;
494 uint32_t size;
495 };
496
497 struct radv_descriptor_pool {
498 struct list_head descriptor_sets;
499
500 struct radeon_winsys_bo *bo;
501 uint8_t *mapped_ptr;
502 uint64_t current_offset;
503 uint64_t size;
504
505 int free_list;
506 int full_list;
507 uint32_t max_sets;
508 struct radv_descriptor_pool_free_node free_nodes[];
509 };
510
511 struct radv_buffer {
512 struct radv_device * device;
513 VkDeviceSize size;
514
515 VkBufferUsageFlags usage;
516
517 /* Set when bound */
518 struct radeon_winsys_bo * bo;
519 VkDeviceSize offset;
520 };
521
522
523 enum radv_cmd_dirty_bits {
524 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
525 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
526 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
527 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
528 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
529 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
530 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
531 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
532 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
533 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
534 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
535 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
536 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
537 };
538 typedef uint32_t radv_cmd_dirty_mask_t;
539
540 enum radv_cmd_flush_bits {
541 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
542 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
543 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
544 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
545 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
546 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
547 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
548 /* Framebuffer caches */
549 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
550 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
551 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
552 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
553 /* Engine synchronization. */
554 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
555 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
556 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
557 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
558
559 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
560 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
561 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
562 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
563 };
564
565 struct radv_vertex_binding {
566 struct radv_buffer * buffer;
567 VkDeviceSize offset;
568 };
569
570 struct radv_dynamic_state {
571 struct {
572 uint32_t count;
573 VkViewport viewports[MAX_VIEWPORTS];
574 } viewport;
575
576 struct {
577 uint32_t count;
578 VkRect2D scissors[MAX_SCISSORS];
579 } scissor;
580
581 float line_width;
582
583 struct {
584 float bias;
585 float clamp;
586 float slope;
587 } depth_bias;
588
589 float blend_constants[4];
590
591 struct {
592 float min;
593 float max;
594 } depth_bounds;
595
596 struct {
597 uint32_t front;
598 uint32_t back;
599 } stencil_compare_mask;
600
601 struct {
602 uint32_t front;
603 uint32_t back;
604 } stencil_write_mask;
605
606 struct {
607 uint32_t front;
608 uint32_t back;
609 } stencil_reference;
610 };
611
612 extern const struct radv_dynamic_state default_dynamic_state;
613
614 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
615 const struct radv_dynamic_state *src,
616 uint32_t copy_mask);
617 /**
618 * Attachment state when recording a renderpass instance.
619 *
620 * The clear value is valid only if there exists a pending clear.
621 */
622 struct radv_attachment_state {
623 VkImageAspectFlags pending_clear_aspects;
624 VkClearValue clear_value;
625 VkImageLayout current_layout;
626 };
627
628 struct radv_cmd_state {
629 uint32_t vb_dirty;
630 bool vertex_descriptors_dirty;
631 radv_cmd_dirty_mask_t dirty;
632
633 struct radv_pipeline * pipeline;
634 struct radv_pipeline * emitted_pipeline;
635 struct radv_pipeline * compute_pipeline;
636 struct radv_pipeline * emitted_compute_pipeline;
637 struct radv_framebuffer * framebuffer;
638 struct radv_render_pass * pass;
639 const struct radv_subpass * subpass;
640 struct radv_dynamic_state dynamic;
641 struct radv_vertex_binding vertex_bindings[MAX_VBS];
642 struct radv_descriptor_set * descriptors[MAX_SETS];
643 struct radv_attachment_state * attachments;
644 VkRect2D render_area;
645 struct radv_buffer * index_buffer;
646 uint32_t index_type;
647 uint32_t index_offset;
648 uint32_t last_primitive_reset_index;
649 enum radv_cmd_flush_bits flush_bits;
650 unsigned active_occlusion_queries;
651 float offset_scale;
652 uint32_t descriptors_dirty;
653 };
654 struct radv_cmd_pool {
655 VkAllocationCallbacks alloc;
656 struct list_head cmd_buffers;
657 };
658
659 struct radv_cmd_buffer_upload {
660 uint8_t *map;
661 unsigned offset;
662 uint64_t size;
663 struct radeon_winsys_bo *upload_bo;
664 struct list_head list;
665 };
666
667 struct radv_cmd_buffer {
668 VK_LOADER_DATA _loader_data;
669
670 struct radv_device * device;
671
672 struct radv_cmd_pool * pool;
673 struct list_head pool_link;
674
675 VkCommandBufferUsageFlags usage_flags;
676 VkCommandBufferLevel level;
677 struct radeon_winsys_cs *cs;
678 struct radv_cmd_state state;
679
680 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
681 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
682 VkShaderStageFlags push_constant_stages;
683
684 struct radv_cmd_buffer_upload upload;
685
686 bool record_fail;
687 };
688
689 struct radv_image;
690
691 void si_init_config(struct radv_physical_device *physical_device,
692 struct radv_cmd_buffer *cmd_buffer);
693 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
694 int count, const VkViewport *viewports);
695 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
696 int count, const VkRect2D *scissors);
697 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
698 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
699 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
700 uint64_t src_va, uint64_t dest_va,
701 uint64_t size);
702 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
703 uint64_t size, unsigned value);
704 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
705 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
706 struct radv_descriptor_set *set,
707 unsigned idx);
708 bool
709 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
710 unsigned size,
711 unsigned alignment,
712 unsigned *out_offset,
713 void **ptr);
714 void
715 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
716 const struct radv_subpass *subpass,
717 bool transitions);
718 bool
719 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
720 unsigned size, unsigned alignmnet,
721 const void *data, unsigned *out_offset);
722 void
723 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
724 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
725 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
726 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
727 unsigned radv_cayman_get_maxdist(int log_samples);
728 void radv_device_init_msaa(struct radv_device *device);
729 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
730 struct radv_image *image,
731 VkClearDepthStencilValue ds_clear_value,
732 VkImageAspectFlags aspects);
733 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
734 struct radv_image *image,
735 int idx,
736 uint32_t color_values[2]);
737 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
738 struct radeon_winsys_bo *bo,
739 uint64_t offset, uint64_t size, uint32_t value);
740
741 /*
742 * Takes x,y,z as exact numbers of invocations, instead of blocks.
743 *
744 * Limitations: Can't call normal dispatch functions without binding or rebinding
745 * the compute pipeline.
746 */
747 void radv_unaligned_dispatch(
748 struct radv_cmd_buffer *cmd_buffer,
749 uint32_t x,
750 uint32_t y,
751 uint32_t z);
752
753 struct radv_event {
754 struct radeon_winsys_bo *bo;
755 uint64_t *map;
756 };
757
758 struct nir_shader;
759
760 struct radv_shader_module {
761 struct nir_shader * nir;
762 unsigned char sha1[20];
763 uint32_t size;
764 char data[0];
765 };
766
767 union ac_shader_variant_key;
768
769 void
770 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
771 const char *entrypoint,
772 const VkSpecializationInfo *spec_info,
773 const struct radv_pipeline_layout *layout,
774 const union ac_shader_variant_key *key);
775
776 static inline gl_shader_stage
777 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
778 {
779 assert(__builtin_popcount(vk_stage) == 1);
780 return ffs(vk_stage) - 1;
781 }
782
783 static inline VkShaderStageFlagBits
784 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
785 {
786 return (1 << mesa_stage);
787 }
788
789 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
790
791 #define radv_foreach_stage(stage, stage_bits) \
792 for (gl_shader_stage stage, \
793 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
794 stage = __builtin_ffs(__tmp) - 1, __tmp; \
795 __tmp &= ~(1 << (stage)))
796
797 struct radv_shader_variant {
798 uint32_t ref_count;
799
800 struct radeon_winsys_bo *bo;
801 struct ac_shader_config config;
802 struct ac_shader_variant_info info;
803 unsigned rsrc1;
804 unsigned rsrc2;
805 uint32_t code_size;
806 };
807
808 struct radv_depth_stencil_state {
809 uint32_t db_depth_control;
810 uint32_t db_stencil_control;
811 uint32_t db_render_control;
812 uint32_t db_render_override2;
813 };
814
815 struct radv_blend_state {
816 uint32_t cb_color_control;
817 uint32_t cb_target_mask;
818 uint32_t sx_mrt0_blend_opt[8];
819 uint32_t cb_blend_control[8];
820
821 uint32_t spi_shader_col_format;
822 uint32_t cb_shader_mask;
823 uint32_t db_alpha_to_mask;
824 };
825
826 unsigned radv_format_meta_fs_key(VkFormat format);
827
828 struct radv_raster_state {
829 uint32_t pa_cl_clip_cntl;
830 uint32_t pa_cl_vs_out_cntl;
831 uint32_t spi_interp_control;
832 uint32_t pa_su_point_size;
833 uint32_t pa_su_point_minmax;
834 uint32_t pa_su_line_cntl;
835 uint32_t pa_su_vtx_cntl;
836 uint32_t pa_su_sc_mode_cntl;
837 };
838
839 struct radv_multisample_state {
840 uint32_t db_eqaa;
841 uint32_t pa_sc_line_cntl;
842 uint32_t pa_sc_mode_cntl_0;
843 uint32_t pa_sc_mode_cntl_1;
844 uint32_t pa_sc_aa_config;
845 uint32_t pa_sc_aa_mask[2];
846 unsigned num_samples;
847 };
848
849 struct radv_pipeline {
850 struct radv_device * device;
851 uint32_t dynamic_state_mask;
852 struct radv_dynamic_state dynamic_state;
853
854 struct radv_pipeline_layout * layout;
855
856 bool needs_data_cache;
857
858 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
859 VkShaderStageFlags active_stages;
860
861 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
862 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
863 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
864 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
865 uint32_t num_vertex_attribs;
866 uint32_t binding_stride[MAX_VBS];
867
868 union {
869 struct {
870 struct radv_blend_state blend;
871 struct radv_depth_stencil_state ds;
872 struct radv_raster_state raster;
873 struct radv_multisample_state ms;
874 unsigned prim;
875 unsigned gs_out;
876 bool prim_restart_enable;
877 } graphics;
878 };
879 };
880
881 struct radv_graphics_pipeline_create_info {
882 bool use_rectlist;
883 bool db_depth_clear;
884 bool db_stencil_clear;
885 bool db_depth_disable_expclear;
886 bool db_stencil_disable_expclear;
887 bool db_flush_depth_inplace;
888 bool db_flush_stencil_inplace;
889 bool db_resummarize;
890 uint32_t custom_blend_mode;
891 };
892
893 VkResult
894 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
895 struct radv_pipeline_cache *cache,
896 const VkGraphicsPipelineCreateInfo *pCreateInfo,
897 const struct radv_graphics_pipeline_create_info *extra,
898 const VkAllocationCallbacks *alloc);
899
900 VkResult
901 radv_graphics_pipeline_create(VkDevice device,
902 VkPipelineCache cache,
903 const VkGraphicsPipelineCreateInfo *pCreateInfo,
904 const struct radv_graphics_pipeline_create_info *extra,
905 const VkAllocationCallbacks *alloc,
906 VkPipeline *pPipeline);
907
908 struct vk_format_description;
909 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
910 int first_non_void);
911 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
912 int first_non_void);
913 uint32_t radv_translate_colorformat(VkFormat format);
914 uint32_t radv_translate_color_numformat(VkFormat format,
915 const struct vk_format_description *desc,
916 int first_non_void);
917 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
918 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
919 uint32_t radv_translate_dbformat(VkFormat format);
920 uint32_t radv_translate_tex_dataformat(VkFormat format,
921 const struct vk_format_description *desc,
922 int first_non_void);
923 uint32_t radv_translate_tex_numformat(VkFormat format,
924 const struct vk_format_description *desc,
925 int first_non_void);
926 bool radv_format_pack_clear_color(VkFormat format,
927 uint32_t clear_vals[2],
928 VkClearColorValue *value);
929 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
930
931 struct radv_fmask_info {
932 uint64_t offset;
933 uint64_t size;
934 unsigned alignment;
935 unsigned pitch_in_pixels;
936 unsigned bank_height;
937 unsigned slice_tile_max;
938 unsigned tile_mode_index;
939 };
940
941 struct radv_cmask_info {
942 uint64_t offset;
943 uint64_t size;
944 unsigned alignment;
945 unsigned slice_tile_max;
946 unsigned base_address_reg;
947 };
948
949 struct r600_htile_info {
950 uint64_t offset;
951 uint64_t size;
952 unsigned pitch;
953 unsigned height;
954 unsigned xalign;
955 unsigned yalign;
956 };
957
958 struct radv_image {
959 VkImageType type;
960 /* The original VkFormat provided by the client. This may not match any
961 * of the actual surface formats.
962 */
963 VkFormat vk_format;
964 VkImageAspectFlags aspects;
965 VkExtent3D extent;
966 uint32_t levels;
967 uint32_t array_size;
968 uint32_t samples; /**< VkImageCreateInfo::samples */
969 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
970 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
971
972 VkDeviceSize size;
973 uint32_t alignment;
974
975 /* Set when bound */
976 struct radeon_winsys_bo *bo;
977 VkDeviceSize offset;
978 uint32_t dcc_offset;
979 struct radeon_surf surface;
980
981 struct radv_fmask_info fmask;
982 struct radv_cmask_info cmask;
983 uint32_t clear_value_offset;
984
985 /* Depth buffer compression and fast clear. */
986 struct r600_htile_info htile;
987 };
988
989 bool radv_layout_has_htile(const struct radv_image *image,
990 VkImageLayout layout);
991 bool radv_layout_is_htile_compressed(const struct radv_image *image,
992 VkImageLayout layout);
993 bool radv_layout_can_expclear(const struct radv_image *image,
994 VkImageLayout layout);
995 bool radv_layout_has_cmask(const struct radv_image *image,
996 VkImageLayout layout);
997 static inline uint32_t
998 radv_get_layerCount(const struct radv_image *image,
999 const VkImageSubresourceRange *range)
1000 {
1001 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1002 image->array_size - range->baseArrayLayer : range->layerCount;
1003 }
1004
1005 static inline uint32_t
1006 radv_get_levelCount(const struct radv_image *image,
1007 const VkImageSubresourceRange *range)
1008 {
1009 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1010 image->levels - range->baseMipLevel : range->levelCount;
1011 }
1012
1013 struct radeon_bo_metadata;
1014 void
1015 radv_init_metadata(struct radv_device *device,
1016 struct radv_image *image,
1017 struct radeon_bo_metadata *metadata);
1018
1019 struct radv_image_view {
1020 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1021 struct radeon_winsys_bo *bo;
1022
1023 VkImageViewType type;
1024 VkImageAspectFlags aspect_mask;
1025 VkFormat vk_format;
1026 uint32_t base_layer;
1027 uint32_t layer_count;
1028 uint32_t base_mip;
1029 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1030
1031 uint32_t descriptor[8];
1032 uint32_t fmask_descriptor[8];
1033 };
1034
1035 struct radv_image_create_info {
1036 const VkImageCreateInfo *vk_info;
1037 uint32_t stride;
1038 bool scanout;
1039 };
1040
1041 VkResult radv_image_create(VkDevice _device,
1042 const struct radv_image_create_info *info,
1043 const VkAllocationCallbacks* alloc,
1044 VkImage *pImage);
1045
1046 void radv_image_view_init(struct radv_image_view *view,
1047 struct radv_device *device,
1048 const VkImageViewCreateInfo* pCreateInfo,
1049 struct radv_cmd_buffer *cmd_buffer,
1050 VkImageUsageFlags usage_mask);
1051 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1052 struct radv_image *image, uint32_t micro_tile_mode);
1053 struct radv_buffer_view {
1054 struct radeon_winsys_bo *bo;
1055 VkFormat vk_format;
1056 uint64_t range; /**< VkBufferViewCreateInfo::range */
1057 uint32_t state[4];
1058 };
1059 void radv_buffer_view_init(struct radv_buffer_view *view,
1060 struct radv_device *device,
1061 const VkBufferViewCreateInfo* pCreateInfo,
1062 struct radv_cmd_buffer *cmd_buffer);
1063
1064 static inline struct VkExtent3D
1065 radv_sanitize_image_extent(const VkImageType imageType,
1066 const struct VkExtent3D imageExtent)
1067 {
1068 switch (imageType) {
1069 case VK_IMAGE_TYPE_1D:
1070 return (VkExtent3D) { imageExtent.width, 1, 1 };
1071 case VK_IMAGE_TYPE_2D:
1072 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1073 case VK_IMAGE_TYPE_3D:
1074 return imageExtent;
1075 default:
1076 unreachable("invalid image type");
1077 }
1078 }
1079
1080 static inline struct VkOffset3D
1081 radv_sanitize_image_offset(const VkImageType imageType,
1082 const struct VkOffset3D imageOffset)
1083 {
1084 switch (imageType) {
1085 case VK_IMAGE_TYPE_1D:
1086 return (VkOffset3D) { imageOffset.x, 0, 0 };
1087 case VK_IMAGE_TYPE_2D:
1088 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1089 case VK_IMAGE_TYPE_3D:
1090 return imageOffset;
1091 default:
1092 unreachable("invalid image type");
1093 }
1094 }
1095
1096 struct radv_sampler {
1097 uint32_t state[4];
1098 };
1099
1100 struct radv_color_buffer_info {
1101 uint32_t cb_color_base;
1102 uint32_t cb_color_pitch;
1103 uint32_t cb_color_slice;
1104 uint32_t cb_color_view;
1105 uint32_t cb_color_info;
1106 uint32_t cb_color_attrib;
1107 uint32_t cb_dcc_control;
1108 uint32_t cb_color_cmask;
1109 uint32_t cb_color_cmask_slice;
1110 uint32_t cb_color_fmask;
1111 uint32_t cb_color_fmask_slice;
1112 uint32_t cb_clear_value0;
1113 uint32_t cb_clear_value1;
1114 uint32_t cb_dcc_base;
1115 uint32_t micro_tile_mode;
1116 };
1117
1118 struct radv_ds_buffer_info {
1119 uint32_t db_depth_info;
1120 uint32_t db_z_info;
1121 uint32_t db_stencil_info;
1122 uint32_t db_z_read_base;
1123 uint32_t db_stencil_read_base;
1124 uint32_t db_z_write_base;
1125 uint32_t db_stencil_write_base;
1126 uint32_t db_depth_view;
1127 uint32_t db_depth_size;
1128 uint32_t db_depth_slice;
1129 uint32_t db_htile_surface;
1130 uint32_t db_htile_data_base;
1131 uint32_t pa_su_poly_offset_db_fmt_cntl;
1132 float offset_scale;
1133 };
1134
1135 struct radv_attachment_info {
1136 union {
1137 struct radv_color_buffer_info cb;
1138 struct radv_ds_buffer_info ds;
1139 };
1140 struct radv_image_view *attachment;
1141 };
1142
1143 struct radv_framebuffer {
1144 uint32_t width;
1145 uint32_t height;
1146 uint32_t layers;
1147
1148 uint32_t attachment_count;
1149 struct radv_attachment_info attachments[0];
1150 };
1151
1152 struct radv_subpass_barrier {
1153 VkPipelineStageFlags src_stage_mask;
1154 VkAccessFlags src_access_mask;
1155 VkAccessFlags dst_access_mask;
1156 };
1157
1158 struct radv_subpass {
1159 uint32_t input_count;
1160 VkAttachmentReference * input_attachments;
1161 uint32_t color_count;
1162 VkAttachmentReference * color_attachments;
1163 VkAttachmentReference * resolve_attachments;
1164 VkAttachmentReference depth_stencil_attachment;
1165
1166 /** Subpass has at least one resolve attachment */
1167 bool has_resolve;
1168
1169 struct radv_subpass_barrier start_barrier;
1170 };
1171
1172 struct radv_render_pass_attachment {
1173 VkFormat format;
1174 uint32_t samples;
1175 VkAttachmentLoadOp load_op;
1176 VkAttachmentLoadOp stencil_load_op;
1177 VkImageLayout initial_layout;
1178 VkImageLayout final_layout;
1179 };
1180
1181 struct radv_render_pass {
1182 uint32_t attachment_count;
1183 uint32_t subpass_count;
1184 VkAttachmentReference * subpass_attachments;
1185 struct radv_render_pass_attachment * attachments;
1186 struct radv_subpass_barrier end_barrier;
1187 struct radv_subpass subpasses[0];
1188 };
1189
1190 VkResult radv_device_init_meta(struct radv_device *device);
1191 void radv_device_finish_meta(struct radv_device *device);
1192
1193 struct radv_query_pool {
1194 struct radeon_winsys_bo *bo;
1195 uint32_t stride;
1196 uint32_t availability_offset;
1197 char *ptr;
1198 VkQueryType type;
1199 };
1200
1201 VkResult
1202 radv_temp_descriptor_set_create(struct radv_device *device,
1203 struct radv_cmd_buffer *cmd_buffer,
1204 VkDescriptorSetLayout _layout,
1205 VkDescriptorSet *_set);
1206
1207 void
1208 radv_temp_descriptor_set_destroy(struct radv_device *device,
1209 VkDescriptorSet _set);
1210 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1211 struct radv_image *image, uint32_t value);
1212 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1213 struct radv_image *image, uint32_t value);
1214
1215 struct radv_fence {
1216 struct radeon_winsys_fence *fence;
1217 bool submitted;
1218 bool signalled;
1219 };
1220
1221 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1222 \
1223 static inline struct __radv_type * \
1224 __radv_type ## _from_handle(__VkType _handle) \
1225 { \
1226 return (struct __radv_type *) _handle; \
1227 } \
1228 \
1229 static inline __VkType \
1230 __radv_type ## _to_handle(struct __radv_type *_obj) \
1231 { \
1232 return (__VkType) _obj; \
1233 }
1234
1235 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1236 \
1237 static inline struct __radv_type * \
1238 __radv_type ## _from_handle(__VkType _handle) \
1239 { \
1240 return (struct __radv_type *)(uintptr_t) _handle; \
1241 } \
1242 \
1243 static inline __VkType \
1244 __radv_type ## _to_handle(struct __radv_type *_obj) \
1245 { \
1246 return (__VkType)(uintptr_t) _obj; \
1247 }
1248
1249 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1250 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1251
1252 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1253 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1254 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1255 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1256 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1257
1258 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1259 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1260 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1261 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1262 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1263 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1264 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1265 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1266 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1267 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1268 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1269 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1270 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1271 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1272 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1273 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1274 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1275 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1276 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1277
1278 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1279 \
1280 static inline const __VkType * \
1281 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1282 { \
1283 return (const __VkType *) __radv_obj; \
1284 }
1285
1286 #define RADV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1287 const __VkType *__vk_name = radv_common_to_ ## __VkType(__common_name)
1288
1289 RADV_DEFINE_STRUCT_CASTS(radv_common, VkMemoryBarrier)
1290 RADV_DEFINE_STRUCT_CASTS(radv_common, VkBufferMemoryBarrier)
1291 RADV_DEFINE_STRUCT_CASTS(radv_common, VkImageMemoryBarrier)
1292
1293
1294 #endif /* RADV_PRIVATE_H */