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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280
281 VkPhysicalDeviceMemoryProperties memory_properties;
282 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 uint64_t perftest_flags;
296 };
297
298 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
299 void radv_finish_wsi(struct radv_physical_device *physical_device);
300
301 bool radv_instance_extension_supported(const char *name);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
303 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
304 const char *name);
305
306 struct cache_entry;
307
308 struct radv_pipeline_cache {
309 struct radv_device * device;
310 pthread_mutex_t mutex;
311
312 uint32_t total_size;
313 uint32_t table_size;
314 uint32_t kernel_count;
315 struct cache_entry ** hash_table;
316 bool modified;
317
318 VkAllocationCallbacks alloc;
319 };
320
321 struct radv_pipeline_key {
322 uint32_t instance_rate_inputs;
323 unsigned tess_input_vertices;
324 uint32_t col_format;
325 uint32_t is_int8;
326 uint32_t is_int10;
327 uint32_t multisample : 1;
328 uint32_t has_multiview_view_index : 1;
329 };
330
331 void
332 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
333 struct radv_device *device);
334 void
335 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
336 void
337 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
338 const void *data, size_t size);
339
340 struct radv_shader_variant;
341
342 bool
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
344 struct radv_pipeline_cache *cache,
345 const unsigned char *sha1,
346 struct radv_shader_variant **variants);
347
348 void
349 radv_pipeline_cache_insert_shaders(struct radv_device *device,
350 struct radv_pipeline_cache *cache,
351 const unsigned char *sha1,
352 struct radv_shader_variant **variants,
353 const void *const *codes,
354 const unsigned *code_sizes);
355
356 enum radv_blit_ds_layout {
357 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
358 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
359 RADV_BLIT_DS_LAYOUT_COUNT,
360 };
361
362 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
363 {
364 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
365 }
366
367 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
368 {
369 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
370 }
371
372 struct radv_meta_state {
373 VkAllocationCallbacks alloc;
374
375 struct radv_pipeline_cache cache;
376
377 /**
378 * Use array element `i` for images with `2^i` samples.
379 */
380 struct {
381 VkRenderPass render_pass[NUM_META_FS_KEYS];
382 VkPipeline color_pipelines[NUM_META_FS_KEYS];
383
384 VkRenderPass depthstencil_rp;
385 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
386 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
387 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
388 } clear[1 + MAX_SAMPLES_LOG2];
389
390 VkPipelineLayout clear_color_p_layout;
391 VkPipelineLayout clear_depth_p_layout;
392 struct {
393 VkRenderPass render_pass[NUM_META_FS_KEYS];
394
395 /** Pipeline that blits from a 1D image. */
396 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
397
398 /** Pipeline that blits from a 2D image. */
399 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
400
401 /** Pipeline that blits from a 3D image. */
402 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
403
404 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
405 VkPipeline depth_only_1d_pipeline;
406 VkPipeline depth_only_2d_pipeline;
407 VkPipeline depth_only_3d_pipeline;
408
409 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
410 VkPipeline stencil_only_1d_pipeline;
411 VkPipeline stencil_only_2d_pipeline;
412 VkPipeline stencil_only_3d_pipeline;
413 VkPipelineLayout pipeline_layout;
414 VkDescriptorSetLayout ds_layout;
415 } blit;
416
417 struct {
418 VkRenderPass render_passes[NUM_META_FS_KEYS];
419
420 VkPipelineLayout p_layouts[3];
421 VkDescriptorSetLayout ds_layouts[3];
422 VkPipeline pipelines[3][NUM_META_FS_KEYS];
423
424 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
425 VkPipeline depth_only_pipeline[3];
426
427 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
428 VkPipeline stencil_only_pipeline[3];
429 } blit2d;
430
431 struct {
432 VkPipelineLayout img_p_layout;
433 VkDescriptorSetLayout img_ds_layout;
434 VkPipeline pipeline;
435 VkPipeline pipeline_3d;
436 } itob;
437 struct {
438 VkPipelineLayout img_p_layout;
439 VkDescriptorSetLayout img_ds_layout;
440 VkPipeline pipeline;
441 VkPipeline pipeline_3d;
442 } btoi;
443 struct {
444 VkPipelineLayout img_p_layout;
445 VkDescriptorSetLayout img_ds_layout;
446 VkPipeline pipeline;
447 VkPipeline pipeline_3d;
448 } itoi;
449 struct {
450 VkPipelineLayout img_p_layout;
451 VkDescriptorSetLayout img_ds_layout;
452 VkPipeline pipeline;
453 VkPipeline pipeline_3d;
454 } cleari;
455
456 struct {
457 VkPipelineLayout p_layout;
458 VkPipeline pipeline;
459 VkRenderPass pass;
460 } resolve;
461
462 struct {
463 VkDescriptorSetLayout ds_layout;
464 VkPipelineLayout p_layout;
465 struct {
466 VkPipeline pipeline;
467 VkPipeline i_pipeline;
468 VkPipeline srgb_pipeline;
469 } rc[MAX_SAMPLES_LOG2];
470 } resolve_compute;
471
472 struct {
473 VkDescriptorSetLayout ds_layout;
474 VkPipelineLayout p_layout;
475
476 struct {
477 VkRenderPass render_pass[NUM_META_FS_KEYS];
478 VkPipeline pipeline[NUM_META_FS_KEYS];
479 } rc[MAX_SAMPLES_LOG2];
480 } resolve_fragment;
481
482 struct {
483 VkPipelineLayout p_layout;
484 VkPipeline decompress_pipeline;
485 VkPipeline resummarize_pipeline;
486 VkRenderPass pass;
487 } depth_decomp[1 + MAX_SAMPLES_LOG2];
488
489 struct {
490 VkPipelineLayout p_layout;
491 VkPipeline cmask_eliminate_pipeline;
492 VkPipeline fmask_decompress_pipeline;
493 VkPipeline dcc_decompress_pipeline;
494 VkRenderPass pass;
495
496 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
497 VkPipelineLayout dcc_decompress_compute_p_layout;
498 VkPipeline dcc_decompress_compute_pipeline;
499 } fast_clear_flush;
500
501 struct {
502 VkPipelineLayout fill_p_layout;
503 VkPipelineLayout copy_p_layout;
504 VkDescriptorSetLayout fill_ds_layout;
505 VkDescriptorSetLayout copy_ds_layout;
506 VkPipeline fill_pipeline;
507 VkPipeline copy_pipeline;
508 } buffer;
509
510 struct {
511 VkDescriptorSetLayout ds_layout;
512 VkPipelineLayout p_layout;
513 VkPipeline occlusion_query_pipeline;
514 VkPipeline pipeline_statistics_query_pipeline;
515 } query;
516 };
517
518 /* queue types */
519 #define RADV_QUEUE_GENERAL 0
520 #define RADV_QUEUE_COMPUTE 1
521 #define RADV_QUEUE_TRANSFER 2
522
523 #define RADV_MAX_QUEUE_FAMILIES 3
524
525 enum ring_type radv_queue_family_to_ring(int f);
526
527 struct radv_queue {
528 VK_LOADER_DATA _loader_data;
529 struct radv_device * device;
530 struct radeon_winsys_ctx *hw_ctx;
531 enum radeon_ctx_priority priority;
532 uint32_t queue_family_index;
533 int queue_idx;
534
535 uint32_t scratch_size;
536 uint32_t compute_scratch_size;
537 uint32_t esgs_ring_size;
538 uint32_t gsvs_ring_size;
539 bool has_tess_rings;
540 bool has_sample_positions;
541
542 struct radeon_winsys_bo *scratch_bo;
543 struct radeon_winsys_bo *descriptor_bo;
544 struct radeon_winsys_bo *compute_scratch_bo;
545 struct radeon_winsys_bo *esgs_ring_bo;
546 struct radeon_winsys_bo *gsvs_ring_bo;
547 struct radeon_winsys_bo *tess_factor_ring_bo;
548 struct radeon_winsys_bo *tess_offchip_ring_bo;
549 struct radeon_winsys_cs *initial_preamble_cs;
550 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
551 struct radeon_winsys_cs *continue_preamble_cs;
552 };
553
554 struct radv_device {
555 VK_LOADER_DATA _loader_data;
556
557 VkAllocationCallbacks alloc;
558
559 struct radv_instance * instance;
560 struct radeon_winsys *ws;
561
562 struct radv_meta_state meta_state;
563
564 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
565 int queue_count[RADV_MAX_QUEUE_FAMILIES];
566 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
567
568 bool llvm_supports_spill;
569 bool has_distributed_tess;
570 bool dfsm_allowed;
571 uint32_t tess_offchip_block_dw_size;
572 uint32_t scratch_waves;
573 uint32_t dispatch_initiator;
574
575 uint32_t gs_table_depth;
576
577 /* MSAA sample locations.
578 * The first index is the sample index.
579 * The second index is the coordinate: X, Y. */
580 float sample_locations_1x[1][2];
581 float sample_locations_2x[2][2];
582 float sample_locations_4x[4][2];
583 float sample_locations_8x[8][2];
584 float sample_locations_16x[16][2];
585
586 /* CIK and later */
587 uint32_t gfx_init_size_dw;
588 struct radeon_winsys_bo *gfx_init;
589
590 struct radeon_winsys_bo *trace_bo;
591 uint32_t *trace_id_ptr;
592
593 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
594 bool keep_shader_info;
595
596 struct radv_physical_device *physical_device;
597
598 /* Backup in-memory cache to be used if the app doesn't provide one */
599 struct radv_pipeline_cache * mem_cache;
600
601 /*
602 * use different counters so MSAA MRTs get consecutive surface indices,
603 * even if MASK is allocated in between.
604 */
605 uint32_t image_mrt_offset_counter;
606 uint32_t fmask_mrt_offset_counter;
607 struct list_head shader_slabs;
608 mtx_t shader_slab_mutex;
609
610 /* For detecting VM faults reported by dmesg. */
611 uint64_t dmesg_timestamp;
612 };
613
614 struct radv_device_memory {
615 struct radeon_winsys_bo *bo;
616 /* for dedicated allocations */
617 struct radv_image *image;
618 struct radv_buffer *buffer;
619 uint32_t type_index;
620 VkDeviceSize map_size;
621 void * map;
622 };
623
624
625 struct radv_descriptor_range {
626 uint64_t va;
627 uint32_t size;
628 };
629
630 struct radv_descriptor_set {
631 const struct radv_descriptor_set_layout *layout;
632 uint32_t size;
633
634 struct radeon_winsys_bo *bo;
635 uint64_t va;
636 uint32_t *mapped_ptr;
637 struct radv_descriptor_range *dynamic_descriptors;
638
639 struct radeon_winsys_bo *descriptors[0];
640 };
641
642 struct radv_push_descriptor_set
643 {
644 struct radv_descriptor_set set;
645 uint32_t capacity;
646 };
647
648 struct radv_descriptor_pool_entry {
649 uint32_t offset;
650 uint32_t size;
651 struct radv_descriptor_set *set;
652 };
653
654 struct radv_descriptor_pool {
655 struct radeon_winsys_bo *bo;
656 uint8_t *mapped_ptr;
657 uint64_t current_offset;
658 uint64_t size;
659
660 uint8_t *host_memory_base;
661 uint8_t *host_memory_ptr;
662 uint8_t *host_memory_end;
663
664 uint32_t entry_count;
665 uint32_t max_entry_count;
666 struct radv_descriptor_pool_entry entries[0];
667 };
668
669 struct radv_descriptor_update_template_entry {
670 VkDescriptorType descriptor_type;
671
672 /* The number of descriptors to update */
673 uint32_t descriptor_count;
674
675 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
676 uint32_t dst_offset;
677
678 /* In dwords. Not valid/used for dynamic descriptors */
679 uint32_t dst_stride;
680
681 uint32_t buffer_offset;
682
683 /* Only valid for combined image samplers and samplers */
684 uint16_t has_sampler;
685
686 /* In bytes */
687 size_t src_offset;
688 size_t src_stride;
689
690 /* For push descriptors */
691 const uint32_t *immutable_samplers;
692 };
693
694 struct radv_descriptor_update_template {
695 uint32_t entry_count;
696 struct radv_descriptor_update_template_entry entry[0];
697 };
698
699 struct radv_buffer {
700 struct radv_device * device;
701 VkDeviceSize size;
702
703 VkBufferUsageFlags usage;
704 VkBufferCreateFlags flags;
705
706 /* Set when bound */
707 struct radeon_winsys_bo * bo;
708 VkDeviceSize offset;
709
710 bool shareable;
711 };
712
713
714 enum radv_cmd_dirty_bits {
715 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
716 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
717 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
718 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
719 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
720 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
721 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
722 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
723 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
724 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
725 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
726 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
727 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
728 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
729 };
730
731 enum radv_cmd_flush_bits {
732 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
733 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
734 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
735 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
736 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
737 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
738 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
739 /* Same as above, but only writes back and doesn't invalidate */
740 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
741 /* Framebuffer caches */
742 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
743 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
744 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
745 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
746 /* Engine synchronization. */
747 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
748 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
749 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
750 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
751
752 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
753 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
754 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
755 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
756 };
757
758 struct radv_vertex_binding {
759 struct radv_buffer * buffer;
760 VkDeviceSize offset;
761 };
762
763 struct radv_viewport_state {
764 uint32_t count;
765 VkViewport viewports[MAX_VIEWPORTS];
766 };
767
768 struct radv_scissor_state {
769 uint32_t count;
770 VkRect2D scissors[MAX_SCISSORS];
771 };
772
773 struct radv_dynamic_state {
774 /**
775 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
776 * Defines the set of saved dynamic state.
777 */
778 uint32_t mask;
779
780 struct radv_viewport_state viewport;
781
782 struct radv_scissor_state scissor;
783
784 float line_width;
785
786 struct {
787 float bias;
788 float clamp;
789 float slope;
790 } depth_bias;
791
792 float blend_constants[4];
793
794 struct {
795 float min;
796 float max;
797 } depth_bounds;
798
799 struct {
800 uint32_t front;
801 uint32_t back;
802 } stencil_compare_mask;
803
804 struct {
805 uint32_t front;
806 uint32_t back;
807 } stencil_write_mask;
808
809 struct {
810 uint32_t front;
811 uint32_t back;
812 } stencil_reference;
813 };
814
815 extern const struct radv_dynamic_state default_dynamic_state;
816
817 const char *
818 radv_get_debug_option_name(int id);
819
820 const char *
821 radv_get_perftest_option_name(int id);
822
823 /**
824 * Attachment state when recording a renderpass instance.
825 *
826 * The clear value is valid only if there exists a pending clear.
827 */
828 struct radv_attachment_state {
829 VkImageAspectFlags pending_clear_aspects;
830 uint32_t cleared_views;
831 VkClearValue clear_value;
832 VkImageLayout current_layout;
833 };
834
835 struct radv_cmd_state {
836 /* Vertex descriptors */
837 bool vb_prefetch_dirty;
838 uint64_t vb_va;
839 unsigned vb_size;
840
841 bool push_descriptors_dirty;
842 bool predicating;
843 uint32_t dirty;
844
845 struct radv_pipeline * pipeline;
846 struct radv_pipeline * emitted_pipeline;
847 struct radv_pipeline * compute_pipeline;
848 struct radv_pipeline * emitted_compute_pipeline;
849 struct radv_framebuffer * framebuffer;
850 struct radv_render_pass * pass;
851 const struct radv_subpass * subpass;
852 struct radv_dynamic_state dynamic;
853 struct radv_attachment_state * attachments;
854 VkRect2D render_area;
855
856 /* Index buffer */
857 struct radv_buffer *index_buffer;
858 uint64_t index_offset;
859 uint32_t index_type;
860 uint32_t max_index_count;
861 uint64_t index_va;
862 int32_t last_index_type;
863
864 int32_t last_primitive_reset_en;
865 uint32_t last_primitive_reset_index;
866 enum radv_cmd_flush_bits flush_bits;
867 unsigned active_occlusion_queries;
868 float offset_scale;
869 uint32_t descriptors_dirty;
870 uint32_t valid_descriptors;
871 uint32_t trace_id;
872 uint32_t last_ia_multi_vgt_param;
873 };
874
875 struct radv_cmd_pool {
876 VkAllocationCallbacks alloc;
877 struct list_head cmd_buffers;
878 struct list_head free_cmd_buffers;
879 uint32_t queue_family_index;
880 };
881
882 struct radv_cmd_buffer_upload {
883 uint8_t *map;
884 unsigned offset;
885 uint64_t size;
886 struct radeon_winsys_bo *upload_bo;
887 struct list_head list;
888 };
889
890 enum radv_cmd_buffer_status {
891 RADV_CMD_BUFFER_STATUS_INVALID,
892 RADV_CMD_BUFFER_STATUS_INITIAL,
893 RADV_CMD_BUFFER_STATUS_RECORDING,
894 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
895 RADV_CMD_BUFFER_STATUS_PENDING,
896 };
897
898 struct radv_cmd_buffer {
899 VK_LOADER_DATA _loader_data;
900
901 struct radv_device * device;
902
903 struct radv_cmd_pool * pool;
904 struct list_head pool_link;
905
906 VkCommandBufferUsageFlags usage_flags;
907 VkCommandBufferLevel level;
908 enum radv_cmd_buffer_status status;
909 struct radeon_winsys_cs *cs;
910 struct radv_cmd_state state;
911 struct radv_vertex_binding vertex_bindings[MAX_VBS];
912 uint32_t queue_family_index;
913
914 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
915 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
916 VkShaderStageFlags push_constant_stages;
917 struct radv_push_descriptor_set push_descriptors;
918 struct radv_descriptor_set meta_push_descriptors;
919 struct radv_descriptor_set *descriptors[MAX_SETS];
920
921 struct radv_cmd_buffer_upload upload;
922
923 uint32_t scratch_size_needed;
924 uint32_t compute_scratch_size_needed;
925 uint32_t esgs_ring_size_needed;
926 uint32_t gsvs_ring_size_needed;
927 bool tess_rings_needed;
928 bool sample_positions_needed;
929
930 VkResult record_result;
931
932 int ring_offsets_idx; /* just used for verification */
933 uint32_t gfx9_fence_offset;
934 struct radeon_winsys_bo *gfx9_fence_bo;
935 uint32_t gfx9_fence_idx;
936 };
937
938 struct radv_image;
939
940 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
941
942 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
943 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
944
945 void cik_create_gfx_config(struct radv_device *device);
946
947 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
948 int count, const VkViewport *viewports);
949 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
950 int count, const VkRect2D *scissors,
951 const VkViewport *viewports, bool can_use_guardband);
952 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
953 bool instanced_draw, bool indirect_draw,
954 uint32_t draw_vertex_count);
955 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
956 bool predicated,
957 enum chip_class chip_class,
958 bool is_mec,
959 unsigned event, unsigned event_flags,
960 unsigned data_sel,
961 uint64_t va,
962 uint32_t old_fence,
963 uint32_t new_fence);
964
965 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
966 bool predicated,
967 uint64_t va, uint32_t ref,
968 uint32_t mask);
969 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
970 bool predicated,
971 enum chip_class chip_class,
972 uint32_t *fence_ptr, uint64_t va,
973 bool is_mec,
974 enum radv_cmd_flush_bits flush_bits);
975 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
976 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
977 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
978 uint64_t src_va, uint64_t dest_va,
979 uint64_t size);
980 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
981 unsigned size);
982 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
983 uint64_t size, unsigned value);
984 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
985 bool
986 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
987 unsigned size,
988 unsigned alignment,
989 unsigned *out_offset,
990 void **ptr);
991 void
992 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
993 const struct radv_subpass *subpass,
994 bool transitions);
995 bool
996 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
997 unsigned size, unsigned alignmnet,
998 const void *data, unsigned *out_offset);
999
1000 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1001 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1002 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1003 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1004 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1005 unsigned radv_cayman_get_maxdist(int log_samples);
1006 void radv_device_init_msaa(struct radv_device *device);
1007 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1008 struct radv_image *image,
1009 VkClearDepthStencilValue ds_clear_value,
1010 VkImageAspectFlags aspects);
1011 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1012 struct radv_image *image,
1013 int idx,
1014 uint32_t color_values[2]);
1015 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1016 struct radv_image *image,
1017 bool value);
1018 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1019 struct radeon_winsys_bo *bo,
1020 uint64_t offset, uint64_t size, uint32_t value);
1021 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1022 bool radv_get_memory_fd(struct radv_device *device,
1023 struct radv_device_memory *memory,
1024 int *pFD);
1025
1026 /*
1027 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1028 *
1029 * Limitations: Can't call normal dispatch functions without binding or rebinding
1030 * the compute pipeline.
1031 */
1032 void radv_unaligned_dispatch(
1033 struct radv_cmd_buffer *cmd_buffer,
1034 uint32_t x,
1035 uint32_t y,
1036 uint32_t z);
1037
1038 struct radv_event {
1039 struct radeon_winsys_bo *bo;
1040 uint64_t *map;
1041 };
1042
1043 struct radv_shader_module;
1044
1045 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1046 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1047 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1048 void
1049 radv_hash_shaders(unsigned char *hash,
1050 const VkPipelineShaderStageCreateInfo **stages,
1051 const struct radv_pipeline_layout *layout,
1052 const struct radv_pipeline_key *key,
1053 uint32_t flags);
1054
1055 static inline gl_shader_stage
1056 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1057 {
1058 assert(__builtin_popcount(vk_stage) == 1);
1059 return ffs(vk_stage) - 1;
1060 }
1061
1062 static inline VkShaderStageFlagBits
1063 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1064 {
1065 return (1 << mesa_stage);
1066 }
1067
1068 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1069
1070 #define radv_foreach_stage(stage, stage_bits) \
1071 for (gl_shader_stage stage, \
1072 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1073 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1074 __tmp &= ~(1 << (stage)))
1075
1076 struct radv_depth_stencil_state {
1077 uint32_t db_depth_control;
1078 uint32_t db_stencil_control;
1079 uint32_t db_render_control;
1080 uint32_t db_render_override2;
1081 };
1082
1083 struct radv_blend_state {
1084 uint32_t cb_color_control;
1085 uint32_t cb_target_mask;
1086 uint32_t sx_mrt_blend_opt[8];
1087 uint32_t cb_blend_control[8];
1088
1089 uint32_t spi_shader_col_format;
1090 uint32_t cb_shader_mask;
1091 uint32_t db_alpha_to_mask;
1092 };
1093
1094 unsigned radv_format_meta_fs_key(VkFormat format);
1095
1096 struct radv_raster_state {
1097 uint32_t pa_cl_clip_cntl;
1098 uint32_t spi_interp_control;
1099 uint32_t pa_su_vtx_cntl;
1100 uint32_t pa_su_sc_mode_cntl;
1101 };
1102
1103 struct radv_multisample_state {
1104 uint32_t db_eqaa;
1105 uint32_t pa_sc_line_cntl;
1106 uint32_t pa_sc_mode_cntl_0;
1107 uint32_t pa_sc_mode_cntl_1;
1108 uint32_t pa_sc_aa_config;
1109 uint32_t pa_sc_aa_mask[2];
1110 unsigned num_samples;
1111 };
1112
1113 struct radv_prim_vertex_count {
1114 uint8_t min;
1115 uint8_t incr;
1116 };
1117
1118 struct radv_tessellation_state {
1119 uint32_t ls_hs_config;
1120 uint32_t tcs_in_layout;
1121 uint32_t tcs_out_layout;
1122 uint32_t tcs_out_offsets;
1123 uint32_t offchip_layout;
1124 unsigned num_patches;
1125 unsigned lds_size;
1126 unsigned num_tcs_input_cp;
1127 uint32_t tf_param;
1128 };
1129
1130 struct radv_gs_state {
1131 uint32_t vgt_gs_onchip_cntl;
1132 uint32_t vgt_gs_max_prims_per_subgroup;
1133 uint32_t vgt_esgs_ring_itemsize;
1134 uint32_t lds_size;
1135 };
1136
1137 struct radv_vertex_elements_info {
1138 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1139 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1140 uint32_t binding[MAX_VERTEX_ATTRIBS];
1141 uint32_t offset[MAX_VERTEX_ATTRIBS];
1142 uint32_t count;
1143 };
1144
1145 struct radv_vs_state {
1146 uint32_t pa_cl_vs_out_cntl;
1147 uint32_t spi_shader_pos_format;
1148 uint32_t spi_vs_out_config;
1149 uint32_t vgt_reuse_off;
1150 };
1151
1152 #define SI_GS_PER_ES 128
1153
1154 struct radv_pipeline {
1155 struct radv_device * device;
1156 struct radv_dynamic_state dynamic_state;
1157
1158 struct radv_pipeline_layout * layout;
1159
1160 bool needs_data_cache;
1161 bool need_indirect_descriptor_sets;
1162 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1163 struct radv_shader_variant *gs_copy_shader;
1164 VkShaderStageFlags active_stages;
1165
1166 struct radv_vertex_elements_info vertex_elements;
1167
1168 uint32_t binding_stride[MAX_VBS];
1169
1170 uint32_t user_data_0[MESA_SHADER_STAGES];
1171 union {
1172 struct {
1173 struct radv_blend_state blend;
1174 struct radv_depth_stencil_state ds;
1175 struct radv_raster_state raster;
1176 struct radv_multisample_state ms;
1177 struct radv_tessellation_state tess;
1178 struct radv_gs_state gs;
1179 struct radv_vs_state vs;
1180 uint32_t db_shader_control;
1181 uint32_t shader_z_format;
1182 unsigned prim;
1183 unsigned gs_out;
1184 uint32_t vgt_gs_mode;
1185 bool vgt_primitiveid_en;
1186 bool prim_restart_enable;
1187 bool partial_es_wave;
1188 uint8_t primgroup_size;
1189 unsigned esgs_ring_size;
1190 unsigned gsvs_ring_size;
1191 uint32_t ps_input_cntl[32];
1192 uint32_t ps_input_cntl_num;
1193 uint32_t vgt_shader_stages_en;
1194 uint32_t vtx_base_sgpr;
1195 uint32_t base_ia_multi_vgt_param;
1196 bool wd_switch_on_eop;
1197 bool ia_switch_on_eoi;
1198 bool partial_vs_wave;
1199 uint8_t vtx_emit_num;
1200 uint32_t vtx_reuse_depth;
1201 struct radv_prim_vertex_count prim_vertex_count;
1202 bool can_use_guardband;
1203 } graphics;
1204 };
1205
1206 unsigned max_waves;
1207 unsigned scratch_bytes_per_wave;
1208 };
1209
1210 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1211 {
1212 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1213 }
1214
1215 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1216 {
1217 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1218 }
1219
1220 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1221 gl_shader_stage stage,
1222 int idx);
1223
1224 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1225
1226 struct radv_graphics_pipeline_create_info {
1227 bool use_rectlist;
1228 bool db_depth_clear;
1229 bool db_stencil_clear;
1230 bool db_depth_disable_expclear;
1231 bool db_stencil_disable_expclear;
1232 bool db_flush_depth_inplace;
1233 bool db_flush_stencil_inplace;
1234 bool db_resummarize;
1235 uint32_t custom_blend_mode;
1236 };
1237
1238 VkResult
1239 radv_graphics_pipeline_create(VkDevice device,
1240 VkPipelineCache cache,
1241 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1242 const struct radv_graphics_pipeline_create_info *extra,
1243 const VkAllocationCallbacks *alloc,
1244 VkPipeline *pPipeline);
1245
1246 struct vk_format_description;
1247 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1248 int first_non_void);
1249 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1250 int first_non_void);
1251 uint32_t radv_translate_colorformat(VkFormat format);
1252 uint32_t radv_translate_color_numformat(VkFormat format,
1253 const struct vk_format_description *desc,
1254 int first_non_void);
1255 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1256 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1257 uint32_t radv_translate_dbformat(VkFormat format);
1258 uint32_t radv_translate_tex_dataformat(VkFormat format,
1259 const struct vk_format_description *desc,
1260 int first_non_void);
1261 uint32_t radv_translate_tex_numformat(VkFormat format,
1262 const struct vk_format_description *desc,
1263 int first_non_void);
1264 bool radv_format_pack_clear_color(VkFormat format,
1265 uint32_t clear_vals[2],
1266 VkClearColorValue *value);
1267 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1268 bool radv_dcc_formats_compatible(VkFormat format1,
1269 VkFormat format2);
1270
1271 struct radv_fmask_info {
1272 uint64_t offset;
1273 uint64_t size;
1274 unsigned alignment;
1275 unsigned pitch_in_pixels;
1276 unsigned bank_height;
1277 unsigned slice_tile_max;
1278 unsigned tile_mode_index;
1279 unsigned tile_swizzle;
1280 };
1281
1282 struct radv_cmask_info {
1283 uint64_t offset;
1284 uint64_t size;
1285 unsigned alignment;
1286 unsigned slice_tile_max;
1287 };
1288
1289 struct radv_image {
1290 VkImageType type;
1291 /* The original VkFormat provided by the client. This may not match any
1292 * of the actual surface formats.
1293 */
1294 VkFormat vk_format;
1295 VkImageAspectFlags aspects;
1296 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1297 struct ac_surf_info info;
1298 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1299 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1300
1301 VkDeviceSize size;
1302 uint32_t alignment;
1303
1304 unsigned queue_family_mask;
1305 bool exclusive;
1306 bool shareable;
1307
1308 /* Set when bound */
1309 struct radeon_winsys_bo *bo;
1310 VkDeviceSize offset;
1311 uint64_t dcc_offset;
1312 uint64_t htile_offset;
1313 bool tc_compatible_htile;
1314 struct radeon_surf surface;
1315
1316 struct radv_fmask_info fmask;
1317 struct radv_cmask_info cmask;
1318 uint64_t clear_value_offset;
1319 uint64_t dcc_pred_offset;
1320 };
1321
1322 /* Whether the image has a htile that is known consistent with the contents of
1323 * the image. */
1324 bool radv_layout_has_htile(const struct radv_image *image,
1325 VkImageLayout layout,
1326 unsigned queue_mask);
1327
1328 /* Whether the image has a htile that is known consistent with the contents of
1329 * the image and is allowed to be in compressed form.
1330 *
1331 * If this is false reads that don't use the htile should be able to return
1332 * correct results.
1333 */
1334 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1335 VkImageLayout layout,
1336 unsigned queue_mask);
1337
1338 bool radv_layout_can_fast_clear(const struct radv_image *image,
1339 VkImageLayout layout,
1340 unsigned queue_mask);
1341
1342 static inline bool
1343 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1344 {
1345 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1346 }
1347
1348 static inline bool
1349 radv_htile_enabled(const struct radv_image *image, unsigned level)
1350 {
1351 return image->surface.htile_size && level == 0;
1352 }
1353
1354 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1355
1356 static inline uint32_t
1357 radv_get_layerCount(const struct radv_image *image,
1358 const VkImageSubresourceRange *range)
1359 {
1360 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1361 image->info.array_size - range->baseArrayLayer : range->layerCount;
1362 }
1363
1364 static inline uint32_t
1365 radv_get_levelCount(const struct radv_image *image,
1366 const VkImageSubresourceRange *range)
1367 {
1368 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1369 image->info.levels - range->baseMipLevel : range->levelCount;
1370 }
1371
1372 struct radeon_bo_metadata;
1373 void
1374 radv_init_metadata(struct radv_device *device,
1375 struct radv_image *image,
1376 struct radeon_bo_metadata *metadata);
1377
1378 struct radv_image_view {
1379 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1380 struct radeon_winsys_bo *bo;
1381
1382 VkImageViewType type;
1383 VkImageAspectFlags aspect_mask;
1384 VkFormat vk_format;
1385 uint32_t base_layer;
1386 uint32_t layer_count;
1387 uint32_t base_mip;
1388 uint32_t level_count;
1389 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1390
1391 uint32_t descriptor[16];
1392
1393 /* Descriptor for use as a storage image as opposed to a sampled image.
1394 * This has a few differences for cube maps (e.g. type).
1395 */
1396 uint32_t storage_descriptor[16];
1397 };
1398
1399 struct radv_image_create_info {
1400 const VkImageCreateInfo *vk_info;
1401 bool scanout;
1402 };
1403
1404 VkResult radv_image_create(VkDevice _device,
1405 const struct radv_image_create_info *info,
1406 const VkAllocationCallbacks* alloc,
1407 VkImage *pImage);
1408
1409 void radv_image_view_init(struct radv_image_view *view,
1410 struct radv_device *device,
1411 const VkImageViewCreateInfo* pCreateInfo);
1412
1413 struct radv_buffer_view {
1414 struct radeon_winsys_bo *bo;
1415 VkFormat vk_format;
1416 uint64_t range; /**< VkBufferViewCreateInfo::range */
1417 uint32_t state[4];
1418 };
1419 void radv_buffer_view_init(struct radv_buffer_view *view,
1420 struct radv_device *device,
1421 const VkBufferViewCreateInfo* pCreateInfo);
1422
1423 static inline struct VkExtent3D
1424 radv_sanitize_image_extent(const VkImageType imageType,
1425 const struct VkExtent3D imageExtent)
1426 {
1427 switch (imageType) {
1428 case VK_IMAGE_TYPE_1D:
1429 return (VkExtent3D) { imageExtent.width, 1, 1 };
1430 case VK_IMAGE_TYPE_2D:
1431 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1432 case VK_IMAGE_TYPE_3D:
1433 return imageExtent;
1434 default:
1435 unreachable("invalid image type");
1436 }
1437 }
1438
1439 static inline struct VkOffset3D
1440 radv_sanitize_image_offset(const VkImageType imageType,
1441 const struct VkOffset3D imageOffset)
1442 {
1443 switch (imageType) {
1444 case VK_IMAGE_TYPE_1D:
1445 return (VkOffset3D) { imageOffset.x, 0, 0 };
1446 case VK_IMAGE_TYPE_2D:
1447 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1448 case VK_IMAGE_TYPE_3D:
1449 return imageOffset;
1450 default:
1451 unreachable("invalid image type");
1452 }
1453 }
1454
1455 static inline bool
1456 radv_image_extent_compare(const struct radv_image *image,
1457 const VkExtent3D *extent)
1458 {
1459 if (extent->width != image->info.width ||
1460 extent->height != image->info.height ||
1461 extent->depth != image->info.depth)
1462 return false;
1463 return true;
1464 }
1465
1466 struct radv_sampler {
1467 uint32_t state[4];
1468 };
1469
1470 struct radv_color_buffer_info {
1471 uint64_t cb_color_base;
1472 uint64_t cb_color_cmask;
1473 uint64_t cb_color_fmask;
1474 uint64_t cb_dcc_base;
1475 uint32_t cb_color_pitch;
1476 uint32_t cb_color_slice;
1477 uint32_t cb_color_view;
1478 uint32_t cb_color_info;
1479 uint32_t cb_color_attrib;
1480 uint32_t cb_color_attrib2;
1481 uint32_t cb_dcc_control;
1482 uint32_t cb_color_cmask_slice;
1483 uint32_t cb_color_fmask_slice;
1484 uint32_t cb_clear_value0;
1485 uint32_t cb_clear_value1;
1486 };
1487
1488 struct radv_ds_buffer_info {
1489 uint64_t db_z_read_base;
1490 uint64_t db_stencil_read_base;
1491 uint64_t db_z_write_base;
1492 uint64_t db_stencil_write_base;
1493 uint64_t db_htile_data_base;
1494 uint32_t db_depth_info;
1495 uint32_t db_z_info;
1496 uint32_t db_stencil_info;
1497 uint32_t db_depth_view;
1498 uint32_t db_depth_size;
1499 uint32_t db_depth_slice;
1500 uint32_t db_htile_surface;
1501 uint32_t pa_su_poly_offset_db_fmt_cntl;
1502 uint32_t db_z_info2;
1503 uint32_t db_stencil_info2;
1504 float offset_scale;
1505 };
1506
1507 struct radv_attachment_info {
1508 union {
1509 struct radv_color_buffer_info cb;
1510 struct radv_ds_buffer_info ds;
1511 };
1512 struct radv_image_view *attachment;
1513 };
1514
1515 struct radv_framebuffer {
1516 uint32_t width;
1517 uint32_t height;
1518 uint32_t layers;
1519
1520 uint32_t attachment_count;
1521 struct radv_attachment_info attachments[0];
1522 };
1523
1524 struct radv_subpass_barrier {
1525 VkPipelineStageFlags src_stage_mask;
1526 VkAccessFlags src_access_mask;
1527 VkAccessFlags dst_access_mask;
1528 };
1529
1530 struct radv_subpass {
1531 uint32_t input_count;
1532 uint32_t color_count;
1533 VkAttachmentReference * input_attachments;
1534 VkAttachmentReference * color_attachments;
1535 VkAttachmentReference * resolve_attachments;
1536 VkAttachmentReference depth_stencil_attachment;
1537
1538 /** Subpass has at least one resolve attachment */
1539 bool has_resolve;
1540
1541 struct radv_subpass_barrier start_barrier;
1542
1543 uint32_t view_mask;
1544 };
1545
1546 struct radv_render_pass_attachment {
1547 VkFormat format;
1548 uint32_t samples;
1549 VkAttachmentLoadOp load_op;
1550 VkAttachmentLoadOp stencil_load_op;
1551 VkImageLayout initial_layout;
1552 VkImageLayout final_layout;
1553 uint32_t view_mask;
1554 };
1555
1556 struct radv_render_pass {
1557 uint32_t attachment_count;
1558 uint32_t subpass_count;
1559 VkAttachmentReference * subpass_attachments;
1560 struct radv_render_pass_attachment * attachments;
1561 struct radv_subpass_barrier end_barrier;
1562 struct radv_subpass subpasses[0];
1563 };
1564
1565 VkResult radv_device_init_meta(struct radv_device *device);
1566 void radv_device_finish_meta(struct radv_device *device);
1567
1568 struct radv_query_pool {
1569 struct radeon_winsys_bo *bo;
1570 uint32_t stride;
1571 uint32_t availability_offset;
1572 char *ptr;
1573 VkQueryType type;
1574 uint32_t pipeline_stats_mask;
1575 };
1576
1577 struct radv_semaphore {
1578 /* use a winsys sem for non-exportable */
1579 struct radeon_winsys_sem *sem;
1580 uint32_t syncobj;
1581 uint32_t temp_syncobj;
1582 };
1583
1584 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1585 int num_wait_sems,
1586 const VkSemaphore *wait_sems,
1587 int num_signal_sems,
1588 const VkSemaphore *signal_sems,
1589 VkFence fence);
1590 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1591
1592 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1593 struct radv_descriptor_set *set,
1594 unsigned idx);
1595
1596 void
1597 radv_update_descriptor_sets(struct radv_device *device,
1598 struct radv_cmd_buffer *cmd_buffer,
1599 VkDescriptorSet overrideSet,
1600 uint32_t descriptorWriteCount,
1601 const VkWriteDescriptorSet *pDescriptorWrites,
1602 uint32_t descriptorCopyCount,
1603 const VkCopyDescriptorSet *pDescriptorCopies);
1604
1605 void
1606 radv_update_descriptor_set_with_template(struct radv_device *device,
1607 struct radv_cmd_buffer *cmd_buffer,
1608 struct radv_descriptor_set *set,
1609 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1610 const void *pData);
1611
1612 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1613 VkPipelineBindPoint pipelineBindPoint,
1614 VkPipelineLayout _layout,
1615 uint32_t set,
1616 uint32_t descriptorWriteCount,
1617 const VkWriteDescriptorSet *pDescriptorWrites);
1618
1619 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1620 struct radv_image *image, uint32_t value);
1621 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1622 struct radv_image *image, uint32_t value);
1623
1624 struct radv_fence {
1625 struct radeon_winsys_fence *fence;
1626 bool submitted;
1627 bool signalled;
1628
1629 uint32_t syncobj;
1630 uint32_t temp_syncobj;
1631 };
1632
1633 struct radeon_winsys_sem;
1634
1635 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1636 \
1637 static inline struct __radv_type * \
1638 __radv_type ## _from_handle(__VkType _handle) \
1639 { \
1640 return (struct __radv_type *) _handle; \
1641 } \
1642 \
1643 static inline __VkType \
1644 __radv_type ## _to_handle(struct __radv_type *_obj) \
1645 { \
1646 return (__VkType) _obj; \
1647 }
1648
1649 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1650 \
1651 static inline struct __radv_type * \
1652 __radv_type ## _from_handle(__VkType _handle) \
1653 { \
1654 return (struct __radv_type *)(uintptr_t) _handle; \
1655 } \
1656 \
1657 static inline __VkType \
1658 __radv_type ## _to_handle(struct __radv_type *_obj) \
1659 { \
1660 return (__VkType)(uintptr_t) _obj; \
1661 }
1662
1663 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1664 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1665
1666 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1667 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1668 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1669 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1670 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1671
1672 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1673 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1674 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1675 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1676 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1677 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1678 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1679 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1680 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1681 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1682 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1683 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1684 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1685 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1686 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1687 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1688 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1689 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1690 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1691 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1692 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1693
1694 #endif /* RADV_PRIVATE_H */