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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102 #define MAX_SO_STREAMS 4
103 #define MAX_SO_BUFFERS 4
104 #define MAX_SO_OUTPUTS 64
105
106 #define NUM_DEPTH_CLEAR_PIPELINES 3
107
108 /*
109 * This is the point we switch from using CP to compute shader
110 * for certain buffer operations.
111 */
112 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113
114 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
115
116 enum radv_mem_heap {
117 RADV_MEM_HEAP_VRAM,
118 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
119 RADV_MEM_HEAP_GTT,
120 RADV_MEM_HEAP_COUNT
121 };
122
123 enum radv_mem_type {
124 RADV_MEM_TYPE_VRAM,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
127 RADV_MEM_TYPE_GTT_CACHED,
128 RADV_MEM_TYPE_COUNT
129 };
130
131 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
132
133 static inline uint32_t
134 align_u32(uint32_t v, uint32_t a)
135 {
136 assert(a != 0 && a == (a & -a));
137 return (v + a - 1) & ~(a - 1);
138 }
139
140 static inline uint32_t
141 align_u32_npot(uint32_t v, uint32_t a)
142 {
143 return (v + a - 1) / a * a;
144 }
145
146 static inline uint64_t
147 align_u64(uint64_t v, uint64_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 static inline int32_t
154 align_i32(int32_t v, int32_t a)
155 {
156 assert(a != 0 && a == (a & -a));
157 return (v + a - 1) & ~(a - 1);
158 }
159
160 /** Alignment must be a power of 2. */
161 static inline bool
162 radv_is_aligned(uintmax_t n, uintmax_t a)
163 {
164 assert(a == (a & -a));
165 return (n & (a - 1)) == 0;
166 }
167
168 static inline uint32_t
169 round_up_u32(uint32_t v, uint32_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint64_t
175 round_up_u64(uint64_t v, uint64_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint32_t
181 radv_minify(uint32_t n, uint32_t levels)
182 {
183 if (unlikely(n == 0))
184 return 0;
185 else
186 return MAX2(n >> levels, 1);
187 }
188 static inline float
189 radv_clamp_f(float f, float min, float max)
190 {
191 assert(min < max);
192
193 if (f > max)
194 return max;
195 else if (f < min)
196 return min;
197 else
198 return f;
199 }
200
201 static inline bool
202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
203 {
204 if (*inout_mask & clear_mask) {
205 *inout_mask &= ~clear_mask;
206 return true;
207 } else {
208 return false;
209 }
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Whenever we generate an error, pass it through this function. Useful for
223 * debugging, where we can break on it. Only call at error site, not when
224 * propagating errors. Might be useful to plug in a stack trace here.
225 */
226
227 struct radv_instance;
228
229 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
230
231 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
232 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
233
234 void __radv_finishme(const char *file, int line, const char *format, ...)
235 radv_printflike(3, 4);
236 void radv_loge(const char *format, ...) radv_printflike(1, 2);
237 void radv_loge_v(const char *format, va_list va);
238 void radv_logi(const char *format, ...) radv_printflike(1, 2);
239 void radv_logi_v(const char *format, va_list va);
240
241 /**
242 * Print a FINISHME message, including its source location.
243 */
244 #define radv_finishme(format, ...) \
245 do { \
246 static bool reported = false; \
247 if (!reported) { \
248 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 reported = true; \
250 } \
251 } while (0)
252
253 /* A non-fatal assert. Useful for debugging. */
254 #ifdef DEBUG
255 #define radv_assert(x) ({ \
256 if (unlikely(!(x))) \
257 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
258 })
259 #else
260 #define radv_assert(x)
261 #endif
262
263 #define stub_return(v) \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return (v); \
267 } while (0)
268
269 #define stub() \
270 do { \
271 radv_finishme("stub %s", __func__); \
272 return; \
273 } while (0)
274
275 void *radv_lookup_entrypoint_unchecked(const char *name);
276 void *radv_lookup_entrypoint_checked(const char *name,
277 uint32_t core_version,
278 const struct radv_instance_extension_table *instance,
279 const struct radv_device_extension_table *device);
280
281 struct radv_physical_device {
282 VK_LOADER_DATA _loader_data;
283
284 struct radv_instance * instance;
285
286 struct radeon_winsys *ws;
287 struct radeon_info rad_info;
288 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
289 uint8_t driver_uuid[VK_UUID_SIZE];
290 uint8_t device_uuid[VK_UUID_SIZE];
291 uint8_t cache_uuid[VK_UUID_SIZE];
292
293 int local_fd;
294 int master_fd;
295 struct wsi_device wsi_device;
296
297 bool has_rbplus; /* if RB+ register exist */
298 bool rbplus_allowed; /* if RB+ is allowed */
299 bool has_clear_state;
300 bool cpdma_prefetch_writes_memory;
301 bool has_scissor_bug;
302
303 bool has_out_of_order_rast;
304 bool out_of_order_rast_allowed;
305
306 /* Whether DCC should be enabled for MSAA textures. */
307 bool dcc_msaa_allowed;
308
309 /* Whether LOAD_CONTEXT_REG packets are supported. */
310 bool has_load_ctx_reg_pkt;
311
312 /* This is the drivers on-disk cache used as a fallback as opposed to
313 * the pipeline cache defined by apps.
314 */
315 struct disk_cache * disk_cache;
316
317 VkPhysicalDeviceMemoryProperties memory_properties;
318 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
319
320 drmPciBusInfo bus_info;
321
322 struct radv_device_extension_table supported_extensions;
323 };
324
325 struct radv_instance {
326 VK_LOADER_DATA _loader_data;
327
328 VkAllocationCallbacks alloc;
329
330 uint32_t apiVersion;
331 int physicalDeviceCount;
332 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
333
334 uint64_t debug_flags;
335 uint64_t perftest_flags;
336
337 struct vk_debug_report_instance debug_report_callbacks;
338
339 struct radv_instance_extension_table enabled_extensions;
340 };
341
342 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
343 void radv_finish_wsi(struct radv_physical_device *physical_device);
344
345 bool radv_instance_extension_supported(const char *name);
346 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
347 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
348 const char *name);
349
350 struct cache_entry;
351
352 struct radv_pipeline_cache {
353 struct radv_device * device;
354 pthread_mutex_t mutex;
355
356 uint32_t total_size;
357 uint32_t table_size;
358 uint32_t kernel_count;
359 struct cache_entry ** hash_table;
360 bool modified;
361
362 VkAllocationCallbacks alloc;
363 };
364
365 struct radv_pipeline_key {
366 uint32_t instance_rate_inputs;
367 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
368 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
369 uint64_t vertex_alpha_adjust;
370 unsigned tess_input_vertices;
371 uint32_t col_format;
372 uint32_t is_int8;
373 uint32_t is_int10;
374 uint8_t log2_ps_iter_samples;
375 uint8_t num_samples;
376 uint32_t has_multiview_view_index : 1;
377 uint32_t optimisations_disabled : 1;
378 };
379
380 void
381 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
382 struct radv_device *device);
383 void
384 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
385 bool
386 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
387 const void *data, size_t size);
388
389 struct radv_shader_variant;
390
391 bool
392 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
393 struct radv_pipeline_cache *cache,
394 const unsigned char *sha1,
395 struct radv_shader_variant **variants);
396
397 void
398 radv_pipeline_cache_insert_shaders(struct radv_device *device,
399 struct radv_pipeline_cache *cache,
400 const unsigned char *sha1,
401 struct radv_shader_variant **variants,
402 const void *const *codes,
403 const unsigned *code_sizes);
404
405 enum radv_blit_ds_layout {
406 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
407 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
408 RADV_BLIT_DS_LAYOUT_COUNT,
409 };
410
411 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
412 {
413 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
414 }
415
416 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
417 {
418 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
419 }
420
421 enum radv_meta_dst_layout {
422 RADV_META_DST_LAYOUT_GENERAL,
423 RADV_META_DST_LAYOUT_OPTIMAL,
424 RADV_META_DST_LAYOUT_COUNT,
425 };
426
427 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
428 {
429 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
430 }
431
432 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
433 {
434 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
435 }
436
437 struct radv_meta_state {
438 VkAllocationCallbacks alloc;
439
440 struct radv_pipeline_cache cache;
441
442 /*
443 * For on-demand pipeline creation, makes sure that
444 * only one thread tries to build a pipeline at the same time.
445 */
446 mtx_t mtx;
447
448 /**
449 * Use array element `i` for images with `2^i` samples.
450 */
451 struct {
452 VkRenderPass render_pass[NUM_META_FS_KEYS];
453 VkPipeline color_pipelines[NUM_META_FS_KEYS];
454
455 VkRenderPass depthstencil_rp;
456 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
457 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
458 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
459 } clear[1 + MAX_SAMPLES_LOG2];
460
461 VkPipelineLayout clear_color_p_layout;
462 VkPipelineLayout clear_depth_p_layout;
463
464 /* Optimized compute fast HTILE clear for stencil or depth only. */
465 VkPipeline clear_htile_mask_pipeline;
466 VkPipelineLayout clear_htile_mask_p_layout;
467 VkDescriptorSetLayout clear_htile_mask_ds_layout;
468
469 struct {
470 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
471
472 /** Pipeline that blits from a 1D image. */
473 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
474
475 /** Pipeline that blits from a 2D image. */
476 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
477
478 /** Pipeline that blits from a 3D image. */
479 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
480
481 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
482 VkPipeline depth_only_1d_pipeline;
483 VkPipeline depth_only_2d_pipeline;
484 VkPipeline depth_only_3d_pipeline;
485
486 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
487 VkPipeline stencil_only_1d_pipeline;
488 VkPipeline stencil_only_2d_pipeline;
489 VkPipeline stencil_only_3d_pipeline;
490 VkPipelineLayout pipeline_layout;
491 VkDescriptorSetLayout ds_layout;
492 } blit;
493
494 struct {
495 VkPipelineLayout p_layouts[5];
496 VkDescriptorSetLayout ds_layouts[5];
497 VkPipeline pipelines[5][NUM_META_FS_KEYS];
498
499 VkPipeline depth_only_pipeline[5];
500
501 VkPipeline stencil_only_pipeline[5];
502 } blit2d[1 + MAX_SAMPLES_LOG2];
503
504 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
505 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
506 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
507
508 struct {
509 VkPipelineLayout img_p_layout;
510 VkDescriptorSetLayout img_ds_layout;
511 VkPipeline pipeline;
512 VkPipeline pipeline_3d;
513 } itob;
514 struct {
515 VkPipelineLayout img_p_layout;
516 VkDescriptorSetLayout img_ds_layout;
517 VkPipeline pipeline;
518 VkPipeline pipeline_3d;
519 } btoi;
520 struct {
521 VkPipelineLayout img_p_layout;
522 VkDescriptorSetLayout img_ds_layout;
523 VkPipeline pipeline;
524 } btoi_r32g32b32;
525 struct {
526 VkPipelineLayout img_p_layout;
527 VkDescriptorSetLayout img_ds_layout;
528 VkPipeline pipeline;
529 VkPipeline pipeline_3d;
530 } itoi;
531 struct {
532 VkPipelineLayout img_p_layout;
533 VkDescriptorSetLayout img_ds_layout;
534 VkPipeline pipeline;
535 } itoi_r32g32b32;
536 struct {
537 VkPipelineLayout img_p_layout;
538 VkDescriptorSetLayout img_ds_layout;
539 VkPipeline pipeline;
540 VkPipeline pipeline_3d;
541 } cleari;
542 struct {
543 VkPipelineLayout img_p_layout;
544 VkDescriptorSetLayout img_ds_layout;
545 VkPipeline pipeline;
546 } cleari_r32g32b32;
547
548 struct {
549 VkPipelineLayout p_layout;
550 VkPipeline pipeline[NUM_META_FS_KEYS];
551 VkRenderPass pass[NUM_META_FS_KEYS];
552 } resolve;
553
554 struct {
555 VkDescriptorSetLayout ds_layout;
556 VkPipelineLayout p_layout;
557 struct {
558 VkPipeline pipeline;
559 VkPipeline i_pipeline;
560 VkPipeline srgb_pipeline;
561 } rc[MAX_SAMPLES_LOG2];
562 } resolve_compute;
563
564 struct {
565 VkDescriptorSetLayout ds_layout;
566 VkPipelineLayout p_layout;
567
568 struct {
569 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
570 VkPipeline pipeline[NUM_META_FS_KEYS];
571 } rc[MAX_SAMPLES_LOG2];
572 } resolve_fragment;
573
574 struct {
575 VkPipelineLayout p_layout;
576 VkPipeline decompress_pipeline;
577 VkPipeline resummarize_pipeline;
578 VkRenderPass pass;
579 } depth_decomp[1 + MAX_SAMPLES_LOG2];
580
581 struct {
582 VkPipelineLayout p_layout;
583 VkPipeline cmask_eliminate_pipeline;
584 VkPipeline fmask_decompress_pipeline;
585 VkPipeline dcc_decompress_pipeline;
586 VkRenderPass pass;
587
588 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
589 VkPipelineLayout dcc_decompress_compute_p_layout;
590 VkPipeline dcc_decompress_compute_pipeline;
591 } fast_clear_flush;
592
593 struct {
594 VkPipelineLayout fill_p_layout;
595 VkPipelineLayout copy_p_layout;
596 VkDescriptorSetLayout fill_ds_layout;
597 VkDescriptorSetLayout copy_ds_layout;
598 VkPipeline fill_pipeline;
599 VkPipeline copy_pipeline;
600 } buffer;
601
602 struct {
603 VkDescriptorSetLayout ds_layout;
604 VkPipelineLayout p_layout;
605 VkPipeline occlusion_query_pipeline;
606 VkPipeline pipeline_statistics_query_pipeline;
607 VkPipeline tfb_query_pipeline;
608 } query;
609
610 struct {
611 VkDescriptorSetLayout ds_layout;
612 VkPipelineLayout p_layout;
613 VkPipeline pipeline[MAX_SAMPLES_LOG2];
614 } fmask_expand;
615 };
616
617 /* queue types */
618 #define RADV_QUEUE_GENERAL 0
619 #define RADV_QUEUE_COMPUTE 1
620 #define RADV_QUEUE_TRANSFER 2
621
622 #define RADV_MAX_QUEUE_FAMILIES 3
623
624 enum ring_type radv_queue_family_to_ring(int f);
625
626 struct radv_queue {
627 VK_LOADER_DATA _loader_data;
628 struct radv_device * device;
629 struct radeon_winsys_ctx *hw_ctx;
630 enum radeon_ctx_priority priority;
631 uint32_t queue_family_index;
632 int queue_idx;
633 VkDeviceQueueCreateFlags flags;
634
635 uint32_t scratch_size;
636 uint32_t compute_scratch_size;
637 uint32_t esgs_ring_size;
638 uint32_t gsvs_ring_size;
639 bool has_tess_rings;
640 bool has_sample_positions;
641
642 struct radeon_winsys_bo *scratch_bo;
643 struct radeon_winsys_bo *descriptor_bo;
644 struct radeon_winsys_bo *compute_scratch_bo;
645 struct radeon_winsys_bo *esgs_ring_bo;
646 struct radeon_winsys_bo *gsvs_ring_bo;
647 struct radeon_winsys_bo *tess_rings_bo;
648 struct radeon_cmdbuf *initial_preamble_cs;
649 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
650 struct radeon_cmdbuf *continue_preamble_cs;
651 };
652
653 struct radv_bo_list {
654 struct radv_winsys_bo_list list;
655 unsigned capacity;
656 pthread_mutex_t mutex;
657 };
658
659 struct radv_device {
660 VK_LOADER_DATA _loader_data;
661
662 VkAllocationCallbacks alloc;
663
664 struct radv_instance * instance;
665 struct radeon_winsys *ws;
666
667 struct radv_meta_state meta_state;
668
669 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
670 int queue_count[RADV_MAX_QUEUE_FAMILIES];
671 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
672
673 bool always_use_syncobj;
674 bool has_distributed_tess;
675 bool pbb_allowed;
676 bool dfsm_allowed;
677 uint32_t tess_offchip_block_dw_size;
678 uint32_t scratch_waves;
679 uint32_t dispatch_initiator;
680
681 uint32_t gs_table_depth;
682
683 /* MSAA sample locations.
684 * The first index is the sample index.
685 * The second index is the coordinate: X, Y. */
686 float sample_locations_1x[1][2];
687 float sample_locations_2x[2][2];
688 float sample_locations_4x[4][2];
689 float sample_locations_8x[8][2];
690 float sample_locations_16x[16][2];
691
692 /* CIK and later */
693 uint32_t gfx_init_size_dw;
694 struct radeon_winsys_bo *gfx_init;
695
696 struct radeon_winsys_bo *trace_bo;
697 uint32_t *trace_id_ptr;
698
699 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
700 bool keep_shader_info;
701
702 struct radv_physical_device *physical_device;
703
704 /* Backup in-memory cache to be used if the app doesn't provide one */
705 struct radv_pipeline_cache * mem_cache;
706
707 /*
708 * use different counters so MSAA MRTs get consecutive surface indices,
709 * even if MASK is allocated in between.
710 */
711 uint32_t image_mrt_offset_counter;
712 uint32_t fmask_mrt_offset_counter;
713 struct list_head shader_slabs;
714 mtx_t shader_slab_mutex;
715
716 /* For detecting VM faults reported by dmesg. */
717 uint64_t dmesg_timestamp;
718
719 struct radv_device_extension_table enabled_extensions;
720
721 /* Whether the driver uses a global BO list. */
722 bool use_global_bo_list;
723
724 struct radv_bo_list bo_list;
725
726 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
727 int force_aniso;
728 };
729
730 struct radv_device_memory {
731 struct radeon_winsys_bo *bo;
732 /* for dedicated allocations */
733 struct radv_image *image;
734 struct radv_buffer *buffer;
735 uint32_t type_index;
736 VkDeviceSize map_size;
737 void * map;
738 void * user_ptr;
739 };
740
741
742 struct radv_descriptor_range {
743 uint64_t va;
744 uint32_t size;
745 };
746
747 struct radv_descriptor_set {
748 const struct radv_descriptor_set_layout *layout;
749 uint32_t size;
750
751 struct radeon_winsys_bo *bo;
752 uint64_t va;
753 uint32_t *mapped_ptr;
754 struct radv_descriptor_range *dynamic_descriptors;
755
756 struct radeon_winsys_bo *descriptors[0];
757 };
758
759 struct radv_push_descriptor_set
760 {
761 struct radv_descriptor_set set;
762 uint32_t capacity;
763 };
764
765 struct radv_descriptor_pool_entry {
766 uint32_t offset;
767 uint32_t size;
768 struct radv_descriptor_set *set;
769 };
770
771 struct radv_descriptor_pool {
772 struct radeon_winsys_bo *bo;
773 uint8_t *mapped_ptr;
774 uint64_t current_offset;
775 uint64_t size;
776
777 uint8_t *host_memory_base;
778 uint8_t *host_memory_ptr;
779 uint8_t *host_memory_end;
780
781 uint32_t entry_count;
782 uint32_t max_entry_count;
783 struct radv_descriptor_pool_entry entries[0];
784 };
785
786 struct radv_descriptor_update_template_entry {
787 VkDescriptorType descriptor_type;
788
789 /* The number of descriptors to update */
790 uint32_t descriptor_count;
791
792 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
793 uint32_t dst_offset;
794
795 /* In dwords. Not valid/used for dynamic descriptors */
796 uint32_t dst_stride;
797
798 uint32_t buffer_offset;
799
800 /* Only valid for combined image samplers and samplers */
801 uint16_t has_sampler;
802
803 /* In bytes */
804 size_t src_offset;
805 size_t src_stride;
806
807 /* For push descriptors */
808 const uint32_t *immutable_samplers;
809 };
810
811 struct radv_descriptor_update_template {
812 uint32_t entry_count;
813 VkPipelineBindPoint bind_point;
814 struct radv_descriptor_update_template_entry entry[0];
815 };
816
817 struct radv_buffer {
818 VkDeviceSize size;
819
820 VkBufferUsageFlags usage;
821 VkBufferCreateFlags flags;
822
823 /* Set when bound */
824 struct radeon_winsys_bo * bo;
825 VkDeviceSize offset;
826
827 bool shareable;
828 };
829
830 enum radv_dynamic_state_bits {
831 RADV_DYNAMIC_VIEWPORT = 1 << 0,
832 RADV_DYNAMIC_SCISSOR = 1 << 1,
833 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
834 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
835 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
836 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
837 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
838 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
839 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
840 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
841 RADV_DYNAMIC_ALL = (1 << 10) - 1,
842 };
843
844 enum radv_cmd_dirty_bits {
845 /* Keep the dynamic state dirty bits in sync with
846 * enum radv_dynamic_state_bits */
847 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
848 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
849 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
850 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
851 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
852 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
853 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
854 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
855 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
856 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
857 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
858 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
859 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
860 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
861 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
862 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
863 };
864
865 enum radv_cmd_flush_bits {
866 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
867 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
868 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
869 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
870 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
871 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
872 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
873 /* Same as above, but only writes back and doesn't invalidate */
874 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
875 /* Framebuffer caches */
876 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
877 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
878 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
879 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
880 /* Engine synchronization. */
881 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
882 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
883 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
884 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
885 /* Pipeline query controls. */
886 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
887 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
888 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
889
890 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
891 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
892 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
893 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
894 };
895
896 struct radv_vertex_binding {
897 struct radv_buffer * buffer;
898 VkDeviceSize offset;
899 };
900
901 struct radv_streamout_binding {
902 struct radv_buffer *buffer;
903 VkDeviceSize offset;
904 VkDeviceSize size;
905 };
906
907 struct radv_streamout_state {
908 /* Mask of bound streamout buffers. */
909 uint8_t enabled_mask;
910
911 /* External state that comes from the last vertex stage, it must be
912 * set explicitely when binding a new graphics pipeline.
913 */
914 uint16_t stride_in_dw[MAX_SO_BUFFERS];
915 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
916
917 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
918 uint32_t hw_enabled_mask;
919
920 /* State of VGT_STRMOUT_(CONFIG|EN) */
921 bool streamout_enabled;
922 };
923
924 struct radv_viewport_state {
925 uint32_t count;
926 VkViewport viewports[MAX_VIEWPORTS];
927 };
928
929 struct radv_scissor_state {
930 uint32_t count;
931 VkRect2D scissors[MAX_SCISSORS];
932 };
933
934 struct radv_discard_rectangle_state {
935 uint32_t count;
936 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
937 };
938
939 struct radv_dynamic_state {
940 /**
941 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
942 * Defines the set of saved dynamic state.
943 */
944 uint32_t mask;
945
946 struct radv_viewport_state viewport;
947
948 struct radv_scissor_state scissor;
949
950 float line_width;
951
952 struct {
953 float bias;
954 float clamp;
955 float slope;
956 } depth_bias;
957
958 float blend_constants[4];
959
960 struct {
961 float min;
962 float max;
963 } depth_bounds;
964
965 struct {
966 uint32_t front;
967 uint32_t back;
968 } stencil_compare_mask;
969
970 struct {
971 uint32_t front;
972 uint32_t back;
973 } stencil_write_mask;
974
975 struct {
976 uint32_t front;
977 uint32_t back;
978 } stencil_reference;
979
980 struct radv_discard_rectangle_state discard_rectangle;
981 };
982
983 extern const struct radv_dynamic_state default_dynamic_state;
984
985 const char *
986 radv_get_debug_option_name(int id);
987
988 const char *
989 radv_get_perftest_option_name(int id);
990
991 /**
992 * Attachment state when recording a renderpass instance.
993 *
994 * The clear value is valid only if there exists a pending clear.
995 */
996 struct radv_attachment_state {
997 VkImageAspectFlags pending_clear_aspects;
998 uint32_t cleared_views;
999 VkClearValue clear_value;
1000 VkImageLayout current_layout;
1001 };
1002
1003 struct radv_descriptor_state {
1004 struct radv_descriptor_set *sets[MAX_SETS];
1005 uint32_t dirty;
1006 uint32_t valid;
1007 struct radv_push_descriptor_set push_set;
1008 bool push_dirty;
1009 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1010 };
1011
1012 struct radv_cmd_state {
1013 /* Vertex descriptors */
1014 uint64_t vb_va;
1015 unsigned vb_size;
1016
1017 bool predicating;
1018 uint32_t dirty;
1019
1020 uint32_t prefetch_L2_mask;
1021
1022 struct radv_pipeline * pipeline;
1023 struct radv_pipeline * emitted_pipeline;
1024 struct radv_pipeline * compute_pipeline;
1025 struct radv_pipeline * emitted_compute_pipeline;
1026 struct radv_framebuffer * framebuffer;
1027 struct radv_render_pass * pass;
1028 const struct radv_subpass * subpass;
1029 struct radv_dynamic_state dynamic;
1030 struct radv_attachment_state * attachments;
1031 struct radv_streamout_state streamout;
1032 VkRect2D render_area;
1033
1034 /* Index buffer */
1035 struct radv_buffer *index_buffer;
1036 uint64_t index_offset;
1037 uint32_t index_type;
1038 uint32_t max_index_count;
1039 uint64_t index_va;
1040 int32_t last_index_type;
1041
1042 int32_t last_primitive_reset_en;
1043 uint32_t last_primitive_reset_index;
1044 enum radv_cmd_flush_bits flush_bits;
1045 unsigned active_occlusion_queries;
1046 bool perfect_occlusion_queries_enabled;
1047 unsigned active_pipeline_queries;
1048 float offset_scale;
1049 uint32_t trace_id;
1050 uint32_t last_ia_multi_vgt_param;
1051
1052 uint32_t last_num_instances;
1053 uint32_t last_first_instance;
1054 uint32_t last_vertex_offset;
1055
1056 /* Whether CP DMA is busy/idle. */
1057 bool dma_is_busy;
1058
1059 /* Conditional rendering info. */
1060 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1061 uint64_t predication_va;
1062
1063 bool context_roll_without_scissor_emitted;
1064 };
1065
1066 struct radv_cmd_pool {
1067 VkAllocationCallbacks alloc;
1068 struct list_head cmd_buffers;
1069 struct list_head free_cmd_buffers;
1070 uint32_t queue_family_index;
1071 };
1072
1073 struct radv_cmd_buffer_upload {
1074 uint8_t *map;
1075 unsigned offset;
1076 uint64_t size;
1077 struct radeon_winsys_bo *upload_bo;
1078 struct list_head list;
1079 };
1080
1081 enum radv_cmd_buffer_status {
1082 RADV_CMD_BUFFER_STATUS_INVALID,
1083 RADV_CMD_BUFFER_STATUS_INITIAL,
1084 RADV_CMD_BUFFER_STATUS_RECORDING,
1085 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1086 RADV_CMD_BUFFER_STATUS_PENDING,
1087 };
1088
1089 struct radv_cmd_buffer {
1090 VK_LOADER_DATA _loader_data;
1091
1092 struct radv_device * device;
1093
1094 struct radv_cmd_pool * pool;
1095 struct list_head pool_link;
1096
1097 VkCommandBufferUsageFlags usage_flags;
1098 VkCommandBufferLevel level;
1099 enum radv_cmd_buffer_status status;
1100 struct radeon_cmdbuf *cs;
1101 struct radv_cmd_state state;
1102 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1103 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1104 uint32_t queue_family_index;
1105
1106 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1107 VkShaderStageFlags push_constant_stages;
1108 struct radv_descriptor_set meta_push_descriptors;
1109
1110 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1111
1112 struct radv_cmd_buffer_upload upload;
1113
1114 uint32_t scratch_size_needed;
1115 uint32_t compute_scratch_size_needed;
1116 uint32_t esgs_ring_size_needed;
1117 uint32_t gsvs_ring_size_needed;
1118 bool tess_rings_needed;
1119 bool sample_positions_needed;
1120
1121 VkResult record_result;
1122
1123 uint64_t gfx9_fence_va;
1124 uint32_t gfx9_fence_idx;
1125 uint64_t gfx9_eop_bug_va;
1126
1127 /**
1128 * Whether a query pool has been resetted and we have to flush caches.
1129 */
1130 bool pending_reset_query;
1131 };
1132
1133 struct radv_image;
1134
1135 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1136
1137 void si_emit_graphics(struct radv_physical_device *physical_device,
1138 struct radeon_cmdbuf *cs);
1139 void si_emit_compute(struct radv_physical_device *physical_device,
1140 struct radeon_cmdbuf *cs);
1141
1142 void cik_create_gfx_config(struct radv_device *device);
1143
1144 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1145 int count, const VkViewport *viewports);
1146 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1147 int count, const VkRect2D *scissors,
1148 const VkViewport *viewports, bool can_use_guardband);
1149 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1150 bool instanced_draw, bool indirect_draw,
1151 uint32_t draw_vertex_count);
1152 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1153 enum chip_class chip_class,
1154 bool is_mec,
1155 unsigned event, unsigned event_flags,
1156 unsigned data_sel,
1157 uint64_t va,
1158 uint32_t new_fence,
1159 uint64_t gfx9_eop_bug_va);
1160
1161 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1162 uint32_t ref, uint32_t mask);
1163 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1164 enum chip_class chip_class,
1165 uint32_t *fence_ptr, uint64_t va,
1166 bool is_mec,
1167 enum radv_cmd_flush_bits flush_bits,
1168 uint64_t gfx9_eop_bug_va);
1169 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1170 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1171 bool inverted, uint64_t va);
1172 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1173 uint64_t src_va, uint64_t dest_va,
1174 uint64_t size);
1175 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1176 unsigned size);
1177 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1178 uint64_t size, unsigned value);
1179 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1180
1181 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1182 bool
1183 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1184 unsigned size,
1185 unsigned alignment,
1186 unsigned *out_offset,
1187 void **ptr);
1188 void
1189 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1190 const struct radv_subpass *subpass);
1191 bool
1192 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1193 unsigned size, unsigned alignmnet,
1194 const void *data, unsigned *out_offset);
1195
1196 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1197 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1198 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1199 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1200 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1201 unsigned radv_cayman_get_maxdist(int log_samples);
1202 void radv_device_init_msaa(struct radv_device *device);
1203
1204 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1205 struct radv_image *image,
1206 VkClearDepthStencilValue ds_clear_value,
1207 VkImageAspectFlags aspects);
1208
1209 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1210 struct radv_image *image,
1211 int cb_idx,
1212 uint32_t color_values[2]);
1213
1214 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1215 struct radv_image *image, bool value);
1216
1217 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1218 struct radv_image *image, bool value);
1219
1220 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1221 struct radeon_winsys_bo *bo,
1222 uint64_t offset, uint64_t size, uint32_t value);
1223 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1224 bool radv_get_memory_fd(struct radv_device *device,
1225 struct radv_device_memory *memory,
1226 int *pFD);
1227
1228 static inline void
1229 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1230 unsigned sh_offset, unsigned pointer_count,
1231 bool use_32bit_pointers)
1232 {
1233 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1234 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1235 }
1236
1237 static inline void
1238 radv_emit_shader_pointer_body(struct radv_device *device,
1239 struct radeon_cmdbuf *cs,
1240 uint64_t va, bool use_32bit_pointers)
1241 {
1242 radeon_emit(cs, va);
1243
1244 if (use_32bit_pointers) {
1245 assert(va == 0 ||
1246 (va >> 32) == device->physical_device->rad_info.address32_hi);
1247 } else {
1248 radeon_emit(cs, va >> 32);
1249 }
1250 }
1251
1252 static inline void
1253 radv_emit_shader_pointer(struct radv_device *device,
1254 struct radeon_cmdbuf *cs,
1255 uint32_t sh_offset, uint64_t va, bool global)
1256 {
1257 bool use_32bit_pointers = !global;
1258
1259 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1260 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1261 }
1262
1263 static inline struct radv_descriptor_state *
1264 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1265 VkPipelineBindPoint bind_point)
1266 {
1267 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1268 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1269 return &cmd_buffer->descriptors[bind_point];
1270 }
1271
1272 /*
1273 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1274 *
1275 * Limitations: Can't call normal dispatch functions without binding or rebinding
1276 * the compute pipeline.
1277 */
1278 void radv_unaligned_dispatch(
1279 struct radv_cmd_buffer *cmd_buffer,
1280 uint32_t x,
1281 uint32_t y,
1282 uint32_t z);
1283
1284 struct radv_event {
1285 struct radeon_winsys_bo *bo;
1286 uint64_t *map;
1287 };
1288
1289 struct radv_shader_module;
1290
1291 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1292 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1293 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1294 void
1295 radv_hash_shaders(unsigned char *hash,
1296 const VkPipelineShaderStageCreateInfo **stages,
1297 const struct radv_pipeline_layout *layout,
1298 const struct radv_pipeline_key *key,
1299 uint32_t flags);
1300
1301 static inline gl_shader_stage
1302 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1303 {
1304 assert(__builtin_popcount(vk_stage) == 1);
1305 return ffs(vk_stage) - 1;
1306 }
1307
1308 static inline VkShaderStageFlagBits
1309 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1310 {
1311 return (1 << mesa_stage);
1312 }
1313
1314 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1315
1316 #define radv_foreach_stage(stage, stage_bits) \
1317 for (gl_shader_stage stage, \
1318 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1319 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1320 __tmp &= ~(1 << (stage)))
1321
1322 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1323 unsigned radv_format_meta_fs_key(VkFormat format);
1324
1325 struct radv_multisample_state {
1326 uint32_t db_eqaa;
1327 uint32_t pa_sc_line_cntl;
1328 uint32_t pa_sc_mode_cntl_0;
1329 uint32_t pa_sc_mode_cntl_1;
1330 uint32_t pa_sc_aa_config;
1331 uint32_t pa_sc_aa_mask[2];
1332 unsigned num_samples;
1333 };
1334
1335 struct radv_prim_vertex_count {
1336 uint8_t min;
1337 uint8_t incr;
1338 };
1339
1340 struct radv_vertex_elements_info {
1341 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1342 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1343 uint32_t binding[MAX_VERTEX_ATTRIBS];
1344 uint32_t offset[MAX_VERTEX_ATTRIBS];
1345 uint32_t count;
1346 };
1347
1348 struct radv_ia_multi_vgt_param_helpers {
1349 uint32_t base;
1350 bool partial_es_wave;
1351 uint8_t primgroup_size;
1352 bool wd_switch_on_eop;
1353 bool ia_switch_on_eoi;
1354 bool partial_vs_wave;
1355 };
1356
1357 #define SI_GS_PER_ES 128
1358
1359 struct radv_pipeline {
1360 struct radv_device * device;
1361 struct radv_dynamic_state dynamic_state;
1362
1363 struct radv_pipeline_layout * layout;
1364
1365 bool need_indirect_descriptor_sets;
1366 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1367 struct radv_shader_variant *gs_copy_shader;
1368 VkShaderStageFlags active_stages;
1369
1370 struct radeon_cmdbuf cs;
1371 uint32_t ctx_cs_hash;
1372 struct radeon_cmdbuf ctx_cs;
1373
1374 struct radv_vertex_elements_info vertex_elements;
1375
1376 uint32_t binding_stride[MAX_VBS];
1377
1378 uint32_t user_data_0[MESA_SHADER_STAGES];
1379 union {
1380 struct {
1381 struct radv_multisample_state ms;
1382 uint32_t spi_baryc_cntl;
1383 bool prim_restart_enable;
1384 unsigned esgs_ring_size;
1385 unsigned gsvs_ring_size;
1386 uint32_t vtx_base_sgpr;
1387 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1388 uint8_t vtx_emit_num;
1389 struct radv_prim_vertex_count prim_vertex_count;
1390 bool can_use_guardband;
1391 uint32_t needed_dynamic_state;
1392 bool disable_out_of_order_rast_for_occlusion;
1393
1394 /* Used for rbplus */
1395 uint32_t col_format;
1396 uint32_t cb_target_mask;
1397 } graphics;
1398 };
1399
1400 unsigned max_waves;
1401 unsigned scratch_bytes_per_wave;
1402
1403 /* Not NULL if graphics pipeline uses streamout. */
1404 struct radv_shader_variant *streamout_shader;
1405 };
1406
1407 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1408 {
1409 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1410 }
1411
1412 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1413 {
1414 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1415 }
1416
1417 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1418 gl_shader_stage stage,
1419 int idx);
1420
1421 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1422 gl_shader_stage stage);
1423
1424 struct radv_graphics_pipeline_create_info {
1425 bool use_rectlist;
1426 bool db_depth_clear;
1427 bool db_stencil_clear;
1428 bool db_depth_disable_expclear;
1429 bool db_stencil_disable_expclear;
1430 bool db_flush_depth_inplace;
1431 bool db_flush_stencil_inplace;
1432 bool db_resummarize;
1433 uint32_t custom_blend_mode;
1434 };
1435
1436 VkResult
1437 radv_graphics_pipeline_create(VkDevice device,
1438 VkPipelineCache cache,
1439 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1440 const struct radv_graphics_pipeline_create_info *extra,
1441 const VkAllocationCallbacks *alloc,
1442 VkPipeline *pPipeline);
1443
1444 struct vk_format_description;
1445 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1446 int first_non_void);
1447 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1448 int first_non_void);
1449 uint32_t radv_translate_colorformat(VkFormat format);
1450 uint32_t radv_translate_color_numformat(VkFormat format,
1451 const struct vk_format_description *desc,
1452 int first_non_void);
1453 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1454 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1455 uint32_t radv_translate_dbformat(VkFormat format);
1456 uint32_t radv_translate_tex_dataformat(VkFormat format,
1457 const struct vk_format_description *desc,
1458 int first_non_void);
1459 uint32_t radv_translate_tex_numformat(VkFormat format,
1460 const struct vk_format_description *desc,
1461 int first_non_void);
1462 bool radv_format_pack_clear_color(VkFormat format,
1463 uint32_t clear_vals[2],
1464 VkClearColorValue *value);
1465 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1466 bool radv_dcc_formats_compatible(VkFormat format1,
1467 VkFormat format2);
1468
1469 struct radv_fmask_info {
1470 uint64_t offset;
1471 uint64_t size;
1472 unsigned alignment;
1473 unsigned pitch_in_pixels;
1474 unsigned bank_height;
1475 unsigned slice_tile_max;
1476 unsigned tile_mode_index;
1477 unsigned tile_swizzle;
1478 };
1479
1480 struct radv_cmask_info {
1481 uint64_t offset;
1482 uint64_t size;
1483 unsigned alignment;
1484 unsigned slice_tile_max;
1485 };
1486
1487 struct radv_image {
1488 VkImageType type;
1489 /* The original VkFormat provided by the client. This may not match any
1490 * of the actual surface formats.
1491 */
1492 VkFormat vk_format;
1493 VkImageAspectFlags aspects;
1494 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1495 struct ac_surf_info info;
1496 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1497 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1498
1499 VkDeviceSize size;
1500 uint32_t alignment;
1501
1502 unsigned queue_family_mask;
1503 bool exclusive;
1504 bool shareable;
1505
1506 /* Set when bound */
1507 struct radeon_winsys_bo *bo;
1508 VkDeviceSize offset;
1509 uint64_t dcc_offset;
1510 uint64_t htile_offset;
1511 bool tc_compatible_htile;
1512 struct radeon_surf surface;
1513
1514 struct radv_fmask_info fmask;
1515 struct radv_cmask_info cmask;
1516 uint64_t clear_value_offset;
1517 uint64_t fce_pred_offset;
1518 uint64_t dcc_pred_offset;
1519
1520 /*
1521 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1522 * stored at this offset is UINT_MAX, the driver will emit
1523 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1524 * SET_CONTEXT_REG packet.
1525 */
1526 uint64_t tc_compat_zrange_offset;
1527
1528 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1529 VkDeviceMemory owned_memory;
1530 };
1531
1532 /* Whether the image has a htile that is known consistent with the contents of
1533 * the image. */
1534 bool radv_layout_has_htile(const struct radv_image *image,
1535 VkImageLayout layout,
1536 unsigned queue_mask);
1537
1538 /* Whether the image has a htile that is known consistent with the contents of
1539 * the image and is allowed to be in compressed form.
1540 *
1541 * If this is false reads that don't use the htile should be able to return
1542 * correct results.
1543 */
1544 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1545 VkImageLayout layout,
1546 unsigned queue_mask);
1547
1548 bool radv_layout_can_fast_clear(const struct radv_image *image,
1549 VkImageLayout layout,
1550 unsigned queue_mask);
1551
1552 bool radv_layout_dcc_compressed(const struct radv_image *image,
1553 VkImageLayout layout,
1554 unsigned queue_mask);
1555
1556 /**
1557 * Return whether the image has CMASK metadata for color surfaces.
1558 */
1559 static inline bool
1560 radv_image_has_cmask(const struct radv_image *image)
1561 {
1562 return image->cmask.size;
1563 }
1564
1565 /**
1566 * Return whether the image has FMASK metadata for color surfaces.
1567 */
1568 static inline bool
1569 radv_image_has_fmask(const struct radv_image *image)
1570 {
1571 return image->fmask.size;
1572 }
1573
1574 /**
1575 * Return whether the image has DCC metadata for color surfaces.
1576 */
1577 static inline bool
1578 radv_image_has_dcc(const struct radv_image *image)
1579 {
1580 return image->surface.dcc_size;
1581 }
1582
1583 /**
1584 * Return whether DCC metadata is enabled for a level.
1585 */
1586 static inline bool
1587 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1588 {
1589 return radv_image_has_dcc(image) &&
1590 level < image->surface.num_dcc_levels;
1591 }
1592
1593 /**
1594 * Return whether the image has CB metadata.
1595 */
1596 static inline bool
1597 radv_image_has_CB_metadata(const struct radv_image *image)
1598 {
1599 return radv_image_has_cmask(image) ||
1600 radv_image_has_fmask(image) ||
1601 radv_image_has_dcc(image);
1602 }
1603
1604 /**
1605 * Return whether the image has HTILE metadata for depth surfaces.
1606 */
1607 static inline bool
1608 radv_image_has_htile(const struct radv_image *image)
1609 {
1610 return image->surface.htile_size;
1611 }
1612
1613 /**
1614 * Return whether HTILE metadata is enabled for a level.
1615 */
1616 static inline bool
1617 radv_htile_enabled(const struct radv_image *image, unsigned level)
1618 {
1619 return radv_image_has_htile(image) && level == 0;
1620 }
1621
1622 /**
1623 * Return whether the image is TC-compatible HTILE.
1624 */
1625 static inline bool
1626 radv_image_is_tc_compat_htile(const struct radv_image *image)
1627 {
1628 return radv_image_has_htile(image) && image->tc_compatible_htile;
1629 }
1630
1631 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1632
1633 static inline uint32_t
1634 radv_get_layerCount(const struct radv_image *image,
1635 const VkImageSubresourceRange *range)
1636 {
1637 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1638 image->info.array_size - range->baseArrayLayer : range->layerCount;
1639 }
1640
1641 static inline uint32_t
1642 radv_get_levelCount(const struct radv_image *image,
1643 const VkImageSubresourceRange *range)
1644 {
1645 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1646 image->info.levels - range->baseMipLevel : range->levelCount;
1647 }
1648
1649 struct radeon_bo_metadata;
1650 void
1651 radv_init_metadata(struct radv_device *device,
1652 struct radv_image *image,
1653 struct radeon_bo_metadata *metadata);
1654
1655 struct radv_image_view {
1656 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1657 struct radeon_winsys_bo *bo;
1658
1659 VkImageViewType type;
1660 VkImageAspectFlags aspect_mask;
1661 VkFormat vk_format;
1662 uint32_t base_layer;
1663 uint32_t layer_count;
1664 uint32_t base_mip;
1665 uint32_t level_count;
1666 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1667
1668 uint32_t descriptor[16];
1669
1670 /* Descriptor for use as a storage image as opposed to a sampled image.
1671 * This has a few differences for cube maps (e.g. type).
1672 */
1673 uint32_t storage_descriptor[16];
1674 };
1675
1676 struct radv_image_create_info {
1677 const VkImageCreateInfo *vk_info;
1678 bool scanout;
1679 bool no_metadata_planes;
1680 };
1681
1682 VkResult radv_image_create(VkDevice _device,
1683 const struct radv_image_create_info *info,
1684 const VkAllocationCallbacks* alloc,
1685 VkImage *pImage);
1686
1687 VkResult
1688 radv_image_from_gralloc(VkDevice device_h,
1689 const VkImageCreateInfo *base_info,
1690 const VkNativeBufferANDROID *gralloc_info,
1691 const VkAllocationCallbacks *alloc,
1692 VkImage *out_image_h);
1693
1694 void radv_image_view_init(struct radv_image_view *view,
1695 struct radv_device *device,
1696 const VkImageViewCreateInfo* pCreateInfo);
1697
1698 struct radv_buffer_view {
1699 struct radeon_winsys_bo *bo;
1700 VkFormat vk_format;
1701 uint64_t range; /**< VkBufferViewCreateInfo::range */
1702 uint32_t state[4];
1703 };
1704 void radv_buffer_view_init(struct radv_buffer_view *view,
1705 struct radv_device *device,
1706 const VkBufferViewCreateInfo* pCreateInfo);
1707
1708 static inline struct VkExtent3D
1709 radv_sanitize_image_extent(const VkImageType imageType,
1710 const struct VkExtent3D imageExtent)
1711 {
1712 switch (imageType) {
1713 case VK_IMAGE_TYPE_1D:
1714 return (VkExtent3D) { imageExtent.width, 1, 1 };
1715 case VK_IMAGE_TYPE_2D:
1716 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1717 case VK_IMAGE_TYPE_3D:
1718 return imageExtent;
1719 default:
1720 unreachable("invalid image type");
1721 }
1722 }
1723
1724 static inline struct VkOffset3D
1725 radv_sanitize_image_offset(const VkImageType imageType,
1726 const struct VkOffset3D imageOffset)
1727 {
1728 switch (imageType) {
1729 case VK_IMAGE_TYPE_1D:
1730 return (VkOffset3D) { imageOffset.x, 0, 0 };
1731 case VK_IMAGE_TYPE_2D:
1732 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1733 case VK_IMAGE_TYPE_3D:
1734 return imageOffset;
1735 default:
1736 unreachable("invalid image type");
1737 }
1738 }
1739
1740 static inline bool
1741 radv_image_extent_compare(const struct radv_image *image,
1742 const VkExtent3D *extent)
1743 {
1744 if (extent->width != image->info.width ||
1745 extent->height != image->info.height ||
1746 extent->depth != image->info.depth)
1747 return false;
1748 return true;
1749 }
1750
1751 struct radv_sampler {
1752 uint32_t state[4];
1753 };
1754
1755 struct radv_color_buffer_info {
1756 uint64_t cb_color_base;
1757 uint64_t cb_color_cmask;
1758 uint64_t cb_color_fmask;
1759 uint64_t cb_dcc_base;
1760 uint32_t cb_color_pitch;
1761 uint32_t cb_color_slice;
1762 uint32_t cb_color_view;
1763 uint32_t cb_color_info;
1764 uint32_t cb_color_attrib;
1765 uint32_t cb_color_attrib2;
1766 uint32_t cb_dcc_control;
1767 uint32_t cb_color_cmask_slice;
1768 uint32_t cb_color_fmask_slice;
1769 };
1770
1771 struct radv_ds_buffer_info {
1772 uint64_t db_z_read_base;
1773 uint64_t db_stencil_read_base;
1774 uint64_t db_z_write_base;
1775 uint64_t db_stencil_write_base;
1776 uint64_t db_htile_data_base;
1777 uint32_t db_depth_info;
1778 uint32_t db_z_info;
1779 uint32_t db_stencil_info;
1780 uint32_t db_depth_view;
1781 uint32_t db_depth_size;
1782 uint32_t db_depth_slice;
1783 uint32_t db_htile_surface;
1784 uint32_t pa_su_poly_offset_db_fmt_cntl;
1785 uint32_t db_z_info2;
1786 uint32_t db_stencil_info2;
1787 float offset_scale;
1788 };
1789
1790 struct radv_attachment_info {
1791 union {
1792 struct radv_color_buffer_info cb;
1793 struct radv_ds_buffer_info ds;
1794 };
1795 struct radv_image_view *attachment;
1796 };
1797
1798 struct radv_framebuffer {
1799 uint32_t width;
1800 uint32_t height;
1801 uint32_t layers;
1802
1803 uint32_t attachment_count;
1804 struct radv_attachment_info attachments[0];
1805 };
1806
1807 struct radv_subpass_barrier {
1808 VkPipelineStageFlags src_stage_mask;
1809 VkAccessFlags src_access_mask;
1810 VkAccessFlags dst_access_mask;
1811 };
1812
1813 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1814 const struct radv_subpass_barrier *barrier);
1815
1816 struct radv_subpass_attachment {
1817 uint32_t attachment;
1818 VkImageLayout layout;
1819 };
1820
1821 struct radv_subpass {
1822 uint32_t attachment_count;
1823 struct radv_subpass_attachment * attachments;
1824
1825 uint32_t input_count;
1826 uint32_t color_count;
1827 struct radv_subpass_attachment * input_attachments;
1828 struct radv_subpass_attachment * color_attachments;
1829 struct radv_subpass_attachment * resolve_attachments;
1830 struct radv_subpass_attachment * depth_stencil_attachment;
1831
1832 /** Subpass has at least one resolve attachment */
1833 bool has_resolve;
1834
1835 /** Subpass has at least one color attachment */
1836 bool has_color_att;
1837
1838 struct radv_subpass_barrier start_barrier;
1839
1840 uint32_t view_mask;
1841 VkSampleCountFlagBits max_sample_count;
1842 };
1843
1844 struct radv_render_pass_attachment {
1845 VkFormat format;
1846 uint32_t samples;
1847 VkAttachmentLoadOp load_op;
1848 VkAttachmentLoadOp stencil_load_op;
1849 VkImageLayout initial_layout;
1850 VkImageLayout final_layout;
1851
1852 /* The subpass id in which the attachment will be used last. */
1853 uint32_t last_subpass_idx;
1854 };
1855
1856 struct radv_render_pass {
1857 uint32_t attachment_count;
1858 uint32_t subpass_count;
1859 struct radv_subpass_attachment * subpass_attachments;
1860 struct radv_render_pass_attachment * attachments;
1861 struct radv_subpass_barrier end_barrier;
1862 struct radv_subpass subpasses[0];
1863 };
1864
1865 VkResult radv_device_init_meta(struct radv_device *device);
1866 void radv_device_finish_meta(struct radv_device *device);
1867
1868 struct radv_query_pool {
1869 struct radeon_winsys_bo *bo;
1870 uint32_t stride;
1871 uint32_t availability_offset;
1872 uint64_t size;
1873 char *ptr;
1874 VkQueryType type;
1875 uint32_t pipeline_stats_mask;
1876 };
1877
1878 struct radv_semaphore {
1879 /* use a winsys sem for non-exportable */
1880 struct radeon_winsys_sem *sem;
1881 uint32_t syncobj;
1882 uint32_t temp_syncobj;
1883 };
1884
1885 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1886 VkPipelineBindPoint bind_point,
1887 struct radv_descriptor_set *set,
1888 unsigned idx);
1889
1890 void
1891 radv_update_descriptor_sets(struct radv_device *device,
1892 struct radv_cmd_buffer *cmd_buffer,
1893 VkDescriptorSet overrideSet,
1894 uint32_t descriptorWriteCount,
1895 const VkWriteDescriptorSet *pDescriptorWrites,
1896 uint32_t descriptorCopyCount,
1897 const VkCopyDescriptorSet *pDescriptorCopies);
1898
1899 void
1900 radv_update_descriptor_set_with_template(struct radv_device *device,
1901 struct radv_cmd_buffer *cmd_buffer,
1902 struct radv_descriptor_set *set,
1903 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1904 const void *pData);
1905
1906 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1907 VkPipelineBindPoint pipelineBindPoint,
1908 VkPipelineLayout _layout,
1909 uint32_t set,
1910 uint32_t descriptorWriteCount,
1911 const VkWriteDescriptorSet *pDescriptorWrites);
1912
1913 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1914 struct radv_image *image, uint32_t value);
1915
1916 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
1917 struct radv_image *image);
1918
1919 struct radv_fence {
1920 struct radeon_winsys_fence *fence;
1921 struct wsi_fence *fence_wsi;
1922 bool submitted;
1923 bool signalled;
1924
1925 uint32_t syncobj;
1926 uint32_t temp_syncobj;
1927 };
1928
1929 /* radv_nir_to_llvm.c */
1930 struct radv_shader_variant_info;
1931 struct radv_nir_compiler_options;
1932
1933 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1934 struct nir_shader *geom_shader,
1935 struct ac_shader_binary *binary,
1936 struct ac_shader_config *config,
1937 struct radv_shader_variant_info *shader_info,
1938 const struct radv_nir_compiler_options *option);
1939
1940 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1941 struct ac_shader_binary *binary,
1942 struct ac_shader_config *config,
1943 struct radv_shader_variant_info *shader_info,
1944 struct nir_shader *const *nir,
1945 int nir_count,
1946 const struct radv_nir_compiler_options *options);
1947
1948 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
1949 const struct nir_shader *nir);
1950
1951 /* radv_shader_info.h */
1952 struct radv_shader_info;
1953
1954 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1955 const struct radv_nir_compiler_options *options,
1956 struct radv_shader_info *info);
1957
1958 void radv_nir_shader_info_init(struct radv_shader_info *info);
1959
1960 struct radeon_winsys_sem;
1961
1962 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1963 \
1964 static inline struct __radv_type * \
1965 __radv_type ## _from_handle(__VkType _handle) \
1966 { \
1967 return (struct __radv_type *) _handle; \
1968 } \
1969 \
1970 static inline __VkType \
1971 __radv_type ## _to_handle(struct __radv_type *_obj) \
1972 { \
1973 return (__VkType) _obj; \
1974 }
1975
1976 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1977 \
1978 static inline struct __radv_type * \
1979 __radv_type ## _from_handle(__VkType _handle) \
1980 { \
1981 return (struct __radv_type *)(uintptr_t) _handle; \
1982 } \
1983 \
1984 static inline __VkType \
1985 __radv_type ## _to_handle(struct __radv_type *_obj) \
1986 { \
1987 return (__VkType)(uintptr_t) _obj; \
1988 }
1989
1990 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1991 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1992
1993 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1994 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1995 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1996 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1997 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1998
1999 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2000 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2001 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2002 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2003 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2004 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2005 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2006 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2007 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2008 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2009 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2010 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2011 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2012 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2013 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2014 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2015 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2016 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2017 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2018 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2019 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2020
2021 #endif /* RADV_PRIVATE_H */