2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
53 #include "vk_debug_report.h"
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "radv_descriptor_set.h"
62 #include "radv_extensions.h"
65 #include <llvm-c/TargetMachine.h>
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vk_icd.h>
77 #include <vulkan/vk_android_native_buffer.h>
79 #include "radv_entrypoints.h"
81 #include "wsi_common.h"
83 #define ATI_VENDOR_ID 0x1002
86 #define MAX_VERTEX_ATTRIBS 32
88 #define MAX_VIEWPORTS 16
89 #define MAX_SCISSORS 16
90 #define MAX_DISCARD_RECTANGLES 4
91 #define MAX_PUSH_CONSTANTS_SIZE 128
92 #define MAX_PUSH_DESCRIPTORS 32
93 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
94 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
95 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
96 #define MAX_SAMPLES_LOG2 4
97 #define NUM_META_FS_KEYS 13
98 #define RADV_MAX_DRM_DEVICES 8
101 #define NUM_DEPTH_CLEAR_PIPELINES 3
104 * This is the point we switch from using CP to compute shader
105 * for certain buffer operations.
107 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
111 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
118 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
119 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
120 RADV_MEM_TYPE_GTT_CACHED
,
124 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
126 static inline uint32_t
127 align_u32(uint32_t v
, uint32_t a
)
129 assert(a
!= 0 && a
== (a
& -a
));
130 return (v
+ a
- 1) & ~(a
- 1);
133 static inline uint32_t
134 align_u32_npot(uint32_t v
, uint32_t a
)
136 return (v
+ a
- 1) / a
* a
;
139 static inline uint64_t
140 align_u64(uint64_t v
, uint64_t a
)
142 assert(a
!= 0 && a
== (a
& -a
));
143 return (v
+ a
- 1) & ~(a
- 1);
146 static inline int32_t
147 align_i32(int32_t v
, int32_t a
)
149 assert(a
!= 0 && a
== (a
& -a
));
150 return (v
+ a
- 1) & ~(a
- 1);
153 /** Alignment must be a power of 2. */
155 radv_is_aligned(uintmax_t n
, uintmax_t a
)
157 assert(a
== (a
& -a
));
158 return (n
& (a
- 1)) == 0;
161 static inline uint32_t
162 round_up_u32(uint32_t v
, uint32_t a
)
164 return (v
+ a
- 1) / a
;
167 static inline uint64_t
168 round_up_u64(uint64_t v
, uint64_t a
)
170 return (v
+ a
- 1) / a
;
173 static inline uint32_t
174 radv_minify(uint32_t n
, uint32_t levels
)
176 if (unlikely(n
== 0))
179 return MAX2(n
>> levels
, 1);
182 radv_clamp_f(float f
, float min
, float max
)
195 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
197 if (*inout_mask
& clear_mask
) {
198 *inout_mask
&= ~clear_mask
;
205 #define for_each_bit(b, dword) \
206 for (uint32_t __dword = (dword); \
207 (b) = __builtin_ffs(__dword) - 1, __dword; \
208 __dword &= ~(1 << (b)))
210 #define typed_memcpy(dest, src, count) ({ \
211 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
212 memcpy((dest), (src), (count) * sizeof(*(src))); \
215 /* Whenever we generate an error, pass it through this function. Useful for
216 * debugging, where we can break on it. Only call at error site, not when
217 * propagating errors. Might be useful to plug in a stack trace here.
220 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
223 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
224 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
226 #define vk_error(error) error
227 #define vk_errorf(error, format, ...) error
230 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
231 radv_printflike(3, 4);
232 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
233 void radv_loge_v(const char *format
, va_list va
);
236 * Print a FINISHME message, including its source location.
238 #define radv_finishme(format, ...) \
240 static bool reported = false; \
242 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
247 /* A non-fatal assert. Useful for debugging. */
249 #define radv_assert(x) ({ \
250 if (unlikely(!(x))) \
251 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
254 #define radv_assert(x)
257 #define stub_return(v) \
259 radv_finishme("stub %s", __func__); \
265 radv_finishme("stub %s", __func__); \
269 void *radv_lookup_entrypoint_unchecked(const char *name
);
270 void *radv_lookup_entrypoint_checked(const char *name
,
271 uint32_t core_version
,
272 const struct radv_instance_extension_table
*instance
,
273 const struct radv_device_extension_table
*device
);
275 struct radv_physical_device
{
276 VK_LOADER_DATA _loader_data
;
278 struct radv_instance
* instance
;
280 struct radeon_winsys
*ws
;
281 struct radeon_info rad_info
;
283 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
284 uint8_t driver_uuid
[VK_UUID_SIZE
];
285 uint8_t device_uuid
[VK_UUID_SIZE
];
286 uint8_t cache_uuid
[VK_UUID_SIZE
];
289 struct wsi_device wsi_device
;
291 bool has_rbplus
; /* if RB+ register exist */
292 bool rbplus_allowed
; /* if RB+ is allowed */
293 bool has_clear_state
;
294 bool cpdma_prefetch_writes_memory
;
295 bool has_scissor_bug
;
297 bool has_out_of_order_rast
;
298 bool out_of_order_rast_allowed
;
300 /* Whether DCC should be enabled for MSAA textures. */
301 bool dcc_msaa_allowed
;
303 /* This is the drivers on-disk cache used as a fallback as opposed to
304 * the pipeline cache defined by apps.
306 struct disk_cache
* disk_cache
;
308 VkPhysicalDeviceMemoryProperties memory_properties
;
309 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
311 struct radv_device_extension_table supported_extensions
;
314 struct radv_instance
{
315 VK_LOADER_DATA _loader_data
;
317 VkAllocationCallbacks alloc
;
320 int physicalDeviceCount
;
321 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
323 uint64_t debug_flags
;
324 uint64_t perftest_flags
;
326 struct vk_debug_report_instance debug_report_callbacks
;
328 struct radv_instance_extension_table enabled_extensions
;
331 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
332 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
334 bool radv_instance_extension_supported(const char *name
);
335 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
336 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
341 struct radv_pipeline_cache
{
342 struct radv_device
* device
;
343 pthread_mutex_t mutex
;
347 uint32_t kernel_count
;
348 struct cache_entry
** hash_table
;
351 VkAllocationCallbacks alloc
;
354 struct radv_pipeline_key
{
355 uint32_t instance_rate_inputs
;
356 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
357 uint64_t vertex_alpha_adjust
;
358 unsigned tess_input_vertices
;
362 uint8_t log2_ps_iter_samples
;
363 uint8_t log2_num_samples
;
364 uint32_t multisample
: 1;
365 uint32_t has_multiview_view_index
: 1;
366 uint32_t optimisations_disabled
: 1;
370 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
371 struct radv_device
*device
);
373 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
375 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
376 const void *data
, size_t size
);
378 struct radv_shader_variant
;
381 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
382 struct radv_pipeline_cache
*cache
,
383 const unsigned char *sha1
,
384 struct radv_shader_variant
**variants
);
387 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
388 struct radv_pipeline_cache
*cache
,
389 const unsigned char *sha1
,
390 struct radv_shader_variant
**variants
,
391 const void *const *codes
,
392 const unsigned *code_sizes
);
394 enum radv_blit_ds_layout
{
395 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
396 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
397 RADV_BLIT_DS_LAYOUT_COUNT
,
400 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
402 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
405 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
407 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
410 enum radv_meta_dst_layout
{
411 RADV_META_DST_LAYOUT_GENERAL
,
412 RADV_META_DST_LAYOUT_OPTIMAL
,
413 RADV_META_DST_LAYOUT_COUNT
,
416 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
418 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
421 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
423 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
426 struct radv_meta_state
{
427 VkAllocationCallbacks alloc
;
429 struct radv_pipeline_cache cache
;
432 * Use array element `i` for images with `2^i` samples.
435 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
436 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
438 VkRenderPass depthstencil_rp
;
439 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
440 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
441 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
442 } clear
[1 + MAX_SAMPLES_LOG2
];
444 VkPipelineLayout clear_color_p_layout
;
445 VkPipelineLayout clear_depth_p_layout
;
447 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
449 /** Pipeline that blits from a 1D image. */
450 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
452 /** Pipeline that blits from a 2D image. */
453 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
455 /** Pipeline that blits from a 3D image. */
456 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
458 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
459 VkPipeline depth_only_1d_pipeline
;
460 VkPipeline depth_only_2d_pipeline
;
461 VkPipeline depth_only_3d_pipeline
;
463 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
464 VkPipeline stencil_only_1d_pipeline
;
465 VkPipeline stencil_only_2d_pipeline
;
466 VkPipeline stencil_only_3d_pipeline
;
467 VkPipelineLayout pipeline_layout
;
468 VkDescriptorSetLayout ds_layout
;
472 VkPipelineLayout p_layouts
[5];
473 VkDescriptorSetLayout ds_layouts
[5];
474 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
476 VkPipeline depth_only_pipeline
[5];
478 VkPipeline stencil_only_pipeline
[5];
479 } blit2d
[1 + MAX_SAMPLES_LOG2
];
481 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
482 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
483 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
486 VkPipelineLayout img_p_layout
;
487 VkDescriptorSetLayout img_ds_layout
;
489 VkPipeline pipeline_3d
;
492 VkPipelineLayout img_p_layout
;
493 VkDescriptorSetLayout img_ds_layout
;
495 VkPipeline pipeline_3d
;
498 VkPipelineLayout img_p_layout
;
499 VkDescriptorSetLayout img_ds_layout
;
501 VkPipeline pipeline_3d
;
504 VkPipelineLayout img_p_layout
;
505 VkDescriptorSetLayout img_ds_layout
;
507 VkPipeline pipeline_3d
;
511 VkPipelineLayout p_layout
;
512 VkPipeline pipeline
[NUM_META_FS_KEYS
];
513 VkRenderPass pass
[NUM_META_FS_KEYS
];
517 VkDescriptorSetLayout ds_layout
;
518 VkPipelineLayout p_layout
;
521 VkPipeline i_pipeline
;
522 VkPipeline srgb_pipeline
;
523 } rc
[MAX_SAMPLES_LOG2
];
527 VkDescriptorSetLayout ds_layout
;
528 VkPipelineLayout p_layout
;
531 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
532 VkPipeline pipeline
[NUM_META_FS_KEYS
];
533 } rc
[MAX_SAMPLES_LOG2
];
537 VkPipelineLayout p_layout
;
538 VkPipeline decompress_pipeline
;
539 VkPipeline resummarize_pipeline
;
541 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
544 VkPipelineLayout p_layout
;
545 VkPipeline cmask_eliminate_pipeline
;
546 VkPipeline fmask_decompress_pipeline
;
547 VkPipeline dcc_decompress_pipeline
;
550 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
551 VkPipelineLayout dcc_decompress_compute_p_layout
;
552 VkPipeline dcc_decompress_compute_pipeline
;
556 VkPipelineLayout fill_p_layout
;
557 VkPipelineLayout copy_p_layout
;
558 VkDescriptorSetLayout fill_ds_layout
;
559 VkDescriptorSetLayout copy_ds_layout
;
560 VkPipeline fill_pipeline
;
561 VkPipeline copy_pipeline
;
565 VkDescriptorSetLayout ds_layout
;
566 VkPipelineLayout p_layout
;
567 VkPipeline occlusion_query_pipeline
;
568 VkPipeline pipeline_statistics_query_pipeline
;
573 #define RADV_QUEUE_GENERAL 0
574 #define RADV_QUEUE_COMPUTE 1
575 #define RADV_QUEUE_TRANSFER 2
577 #define RADV_MAX_QUEUE_FAMILIES 3
579 enum ring_type
radv_queue_family_to_ring(int f
);
582 VK_LOADER_DATA _loader_data
;
583 struct radv_device
* device
;
584 struct radeon_winsys_ctx
*hw_ctx
;
585 enum radeon_ctx_priority priority
;
586 uint32_t queue_family_index
;
588 VkDeviceQueueCreateFlags flags
;
590 uint32_t scratch_size
;
591 uint32_t compute_scratch_size
;
592 uint32_t esgs_ring_size
;
593 uint32_t gsvs_ring_size
;
595 bool has_sample_positions
;
597 struct radeon_winsys_bo
*scratch_bo
;
598 struct radeon_winsys_bo
*descriptor_bo
;
599 struct radeon_winsys_bo
*compute_scratch_bo
;
600 struct radeon_winsys_bo
*esgs_ring_bo
;
601 struct radeon_winsys_bo
*gsvs_ring_bo
;
602 struct radeon_winsys_bo
*tess_rings_bo
;
603 struct radeon_winsys_cs
*initial_preamble_cs
;
604 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
605 struct radeon_winsys_cs
*continue_preamble_cs
;
608 struct radv_bo_list
{
609 struct radv_winsys_bo_list list
;
611 pthread_mutex_t mutex
;
615 VK_LOADER_DATA _loader_data
;
617 VkAllocationCallbacks alloc
;
619 struct radv_instance
* instance
;
620 struct radeon_winsys
*ws
;
622 struct radv_meta_state meta_state
;
624 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
625 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
626 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
628 bool always_use_syncobj
;
629 bool has_distributed_tess
;
632 uint32_t tess_offchip_block_dw_size
;
633 uint32_t scratch_waves
;
634 uint32_t dispatch_initiator
;
636 uint32_t gs_table_depth
;
638 /* MSAA sample locations.
639 * The first index is the sample index.
640 * The second index is the coordinate: X, Y. */
641 float sample_locations_1x
[1][2];
642 float sample_locations_2x
[2][2];
643 float sample_locations_4x
[4][2];
644 float sample_locations_8x
[8][2];
645 float sample_locations_16x
[16][2];
648 uint32_t gfx_init_size_dw
;
649 struct radeon_winsys_bo
*gfx_init
;
651 struct radeon_winsys_bo
*trace_bo
;
652 uint32_t *trace_id_ptr
;
654 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
655 bool keep_shader_info
;
657 struct radv_physical_device
*physical_device
;
659 /* Backup in-memory cache to be used if the app doesn't provide one */
660 struct radv_pipeline_cache
* mem_cache
;
663 * use different counters so MSAA MRTs get consecutive surface indices,
664 * even if MASK is allocated in between.
666 uint32_t image_mrt_offset_counter
;
667 uint32_t fmask_mrt_offset_counter
;
668 struct list_head shader_slabs
;
669 mtx_t shader_slab_mutex
;
671 /* For detecting VM faults reported by dmesg. */
672 uint64_t dmesg_timestamp
;
674 struct radv_device_extension_table enabled_extensions
;
676 /* Whether the driver uses a global BO list. */
677 bool use_global_bo_list
;
679 struct radv_bo_list bo_list
;
682 struct radv_device_memory
{
683 struct radeon_winsys_bo
*bo
;
684 /* for dedicated allocations */
685 struct radv_image
*image
;
686 struct radv_buffer
*buffer
;
688 VkDeviceSize map_size
;
694 struct radv_descriptor_range
{
699 struct radv_descriptor_set
{
700 const struct radv_descriptor_set_layout
*layout
;
703 struct radeon_winsys_bo
*bo
;
705 uint32_t *mapped_ptr
;
706 struct radv_descriptor_range
*dynamic_descriptors
;
708 struct radeon_winsys_bo
*descriptors
[0];
711 struct radv_push_descriptor_set
713 struct radv_descriptor_set set
;
717 struct radv_descriptor_pool_entry
{
720 struct radv_descriptor_set
*set
;
723 struct radv_descriptor_pool
{
724 struct radeon_winsys_bo
*bo
;
726 uint64_t current_offset
;
729 uint8_t *host_memory_base
;
730 uint8_t *host_memory_ptr
;
731 uint8_t *host_memory_end
;
733 uint32_t entry_count
;
734 uint32_t max_entry_count
;
735 struct radv_descriptor_pool_entry entries
[0];
738 struct radv_descriptor_update_template_entry
{
739 VkDescriptorType descriptor_type
;
741 /* The number of descriptors to update */
742 uint32_t descriptor_count
;
744 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
747 /* In dwords. Not valid/used for dynamic descriptors */
750 uint32_t buffer_offset
;
752 /* Only valid for combined image samplers and samplers */
753 uint16_t has_sampler
;
759 /* For push descriptors */
760 const uint32_t *immutable_samplers
;
763 struct radv_descriptor_update_template
{
764 uint32_t entry_count
;
765 VkPipelineBindPoint bind_point
;
766 struct radv_descriptor_update_template_entry entry
[0];
772 VkBufferUsageFlags usage
;
773 VkBufferCreateFlags flags
;
776 struct radeon_winsys_bo
* bo
;
782 enum radv_dynamic_state_bits
{
783 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
784 RADV_DYNAMIC_SCISSOR
= 1 << 1,
785 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
786 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
787 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
788 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
789 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
790 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
791 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
792 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
793 RADV_DYNAMIC_ALL
= (1 << 10) - 1,
796 enum radv_cmd_dirty_bits
{
797 /* Keep the dynamic state dirty bits in sync with
798 * enum radv_dynamic_state_bits */
799 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
800 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
801 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
802 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
803 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
804 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
805 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
806 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
807 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
808 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
809 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 10) - 1,
810 RADV_CMD_DIRTY_PIPELINE
= 1 << 10,
811 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 11,
812 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 12,
813 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 13,
816 enum radv_cmd_flush_bits
{
817 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
818 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
819 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
820 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
821 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
822 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
823 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
824 /* Same as above, but only writes back and doesn't invalidate */
825 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
826 /* Framebuffer caches */
827 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
828 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
829 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
830 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
831 /* Engine synchronization. */
832 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
833 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
834 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
835 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
837 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
838 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
839 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
840 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
843 struct radv_vertex_binding
{
844 struct radv_buffer
* buffer
;
848 struct radv_viewport_state
{
850 VkViewport viewports
[MAX_VIEWPORTS
];
853 struct radv_scissor_state
{
855 VkRect2D scissors
[MAX_SCISSORS
];
858 struct radv_discard_rectangle_state
{
860 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
863 struct radv_dynamic_state
{
865 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
866 * Defines the set of saved dynamic state.
870 struct radv_viewport_state viewport
;
872 struct radv_scissor_state scissor
;
882 float blend_constants
[4];
892 } stencil_compare_mask
;
897 } stencil_write_mask
;
904 struct radv_discard_rectangle_state discard_rectangle
;
907 extern const struct radv_dynamic_state default_dynamic_state
;
910 radv_get_debug_option_name(int id
);
913 radv_get_perftest_option_name(int id
);
916 * Attachment state when recording a renderpass instance.
918 * The clear value is valid only if there exists a pending clear.
920 struct radv_attachment_state
{
921 VkImageAspectFlags pending_clear_aspects
;
922 uint32_t cleared_views
;
923 VkClearValue clear_value
;
924 VkImageLayout current_layout
;
927 struct radv_descriptor_state
{
928 struct radv_descriptor_set
*sets
[MAX_SETS
];
931 struct radv_push_descriptor_set push_set
;
935 struct radv_cmd_state
{
936 /* Vertex descriptors */
943 uint32_t prefetch_L2_mask
;
945 struct radv_pipeline
* pipeline
;
946 struct radv_pipeline
* emitted_pipeline
;
947 struct radv_pipeline
* compute_pipeline
;
948 struct radv_pipeline
* emitted_compute_pipeline
;
949 struct radv_framebuffer
* framebuffer
;
950 struct radv_render_pass
* pass
;
951 const struct radv_subpass
* subpass
;
952 struct radv_dynamic_state dynamic
;
953 struct radv_attachment_state
* attachments
;
954 VkRect2D render_area
;
957 struct radv_buffer
*index_buffer
;
958 uint64_t index_offset
;
960 uint32_t max_index_count
;
962 int32_t last_index_type
;
964 int32_t last_primitive_reset_en
;
965 uint32_t last_primitive_reset_index
;
966 enum radv_cmd_flush_bits flush_bits
;
967 unsigned active_occlusion_queries
;
968 bool perfect_occlusion_queries_enabled
;
971 uint32_t last_ia_multi_vgt_param
;
973 uint32_t last_num_instances
;
974 uint32_t last_first_instance
;
975 uint32_t last_vertex_offset
;
978 struct radv_cmd_pool
{
979 VkAllocationCallbacks alloc
;
980 struct list_head cmd_buffers
;
981 struct list_head free_cmd_buffers
;
982 uint32_t queue_family_index
;
985 struct radv_cmd_buffer_upload
{
989 struct radeon_winsys_bo
*upload_bo
;
990 struct list_head list
;
993 enum radv_cmd_buffer_status
{
994 RADV_CMD_BUFFER_STATUS_INVALID
,
995 RADV_CMD_BUFFER_STATUS_INITIAL
,
996 RADV_CMD_BUFFER_STATUS_RECORDING
,
997 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
998 RADV_CMD_BUFFER_STATUS_PENDING
,
1001 struct radv_cmd_buffer
{
1002 VK_LOADER_DATA _loader_data
;
1004 struct radv_device
* device
;
1006 struct radv_cmd_pool
* pool
;
1007 struct list_head pool_link
;
1009 VkCommandBufferUsageFlags usage_flags
;
1010 VkCommandBufferLevel level
;
1011 enum radv_cmd_buffer_status status
;
1012 struct radeon_winsys_cs
*cs
;
1013 struct radv_cmd_state state
;
1014 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1015 uint32_t queue_family_index
;
1017 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1018 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1019 VkShaderStageFlags push_constant_stages
;
1020 struct radv_descriptor_set meta_push_descriptors
;
1022 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1024 struct radv_cmd_buffer_upload upload
;
1026 uint32_t scratch_size_needed
;
1027 uint32_t compute_scratch_size_needed
;
1028 uint32_t esgs_ring_size_needed
;
1029 uint32_t gsvs_ring_size_needed
;
1030 bool tess_rings_needed
;
1031 bool sample_positions_needed
;
1033 VkResult record_result
;
1035 int ring_offsets_idx
; /* just used for verification */
1036 uint32_t gfx9_fence_offset
;
1037 struct radeon_winsys_bo
*gfx9_fence_bo
;
1038 uint32_t gfx9_fence_idx
;
1041 * Whether a query pool has been resetted and we have to flush caches.
1043 bool pending_reset_query
;
1048 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1050 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
1051 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
1053 void cik_create_gfx_config(struct radv_device
*device
);
1055 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
1056 int count
, const VkViewport
*viewports
);
1057 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
1058 int count
, const VkRect2D
*scissors
,
1059 const VkViewport
*viewports
, bool can_use_guardband
);
1060 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1061 bool instanced_draw
, bool indirect_draw
,
1062 uint32_t draw_vertex_count
);
1063 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
1065 enum chip_class chip_class
,
1067 unsigned event
, unsigned event_flags
,
1071 uint32_t new_fence
);
1073 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
1075 uint64_t va
, uint32_t ref
,
1077 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
1078 enum chip_class chip_class
,
1079 uint32_t *fence_ptr
, uint64_t va
,
1081 enum radv_cmd_flush_bits flush_bits
);
1082 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1083 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
1084 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1085 uint64_t src_va
, uint64_t dest_va
,
1087 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1089 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1090 uint64_t size
, unsigned value
);
1091 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1093 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1096 unsigned *out_offset
,
1099 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1100 const struct radv_subpass
*subpass
,
1103 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1104 unsigned size
, unsigned alignmnet
,
1105 const void *data
, unsigned *out_offset
);
1107 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1108 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1109 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1110 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1111 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
1112 unsigned radv_cayman_get_maxdist(int log_samples
);
1113 void radv_device_init_msaa(struct radv_device
*device
);
1114 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1115 struct radv_image
*image
,
1116 VkClearDepthStencilValue ds_clear_value
,
1117 VkImageAspectFlags aspects
);
1118 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1119 struct radv_image
*image
,
1121 uint32_t color_values
[2]);
1122 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1123 struct radv_image
*image
,
1125 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1126 struct radeon_winsys_bo
*bo
,
1127 uint64_t offset
, uint64_t size
, uint32_t value
);
1128 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1129 bool radv_get_memory_fd(struct radv_device
*device
,
1130 struct radv_device_memory
*memory
,
1134 radv_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
1135 unsigned sh_offset
, bool use_32bit_pointers
)
1137 radeon_set_sh_reg_seq(cs
, sh_offset
, use_32bit_pointers
? 1 : 2);
1141 radv_emit_shader_pointer_body(struct radv_device
*device
,
1142 struct radeon_winsys_cs
*cs
,
1143 uint64_t va
, bool use_32bit_pointers
)
1145 radeon_emit(cs
, va
);
1147 if (use_32bit_pointers
) {
1149 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1151 radeon_emit(cs
, va
>> 32);
1156 radv_emit_shader_pointer(struct radv_device
*device
,
1157 struct radeon_winsys_cs
*cs
,
1158 uint32_t sh_offset
, uint64_t va
, bool global
)
1160 bool use_32bit_pointers
= HAVE_32BIT_POINTERS
&& !global
;
1162 radv_emit_shader_pointer_head(cs
, sh_offset
, use_32bit_pointers
);
1163 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1166 static inline struct radv_descriptor_state
*
1167 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1168 VkPipelineBindPoint bind_point
)
1170 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1171 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1172 return &cmd_buffer
->descriptors
[bind_point
];
1176 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1178 * Limitations: Can't call normal dispatch functions without binding or rebinding
1179 * the compute pipeline.
1181 void radv_unaligned_dispatch(
1182 struct radv_cmd_buffer
*cmd_buffer
,
1188 struct radeon_winsys_bo
*bo
;
1192 struct radv_shader_module
;
1194 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1195 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1196 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1198 radv_hash_shaders(unsigned char *hash
,
1199 const VkPipelineShaderStageCreateInfo
**stages
,
1200 const struct radv_pipeline_layout
*layout
,
1201 const struct radv_pipeline_key
*key
,
1204 static inline gl_shader_stage
1205 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1207 assert(__builtin_popcount(vk_stage
) == 1);
1208 return ffs(vk_stage
) - 1;
1211 static inline VkShaderStageFlagBits
1212 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1214 return (1 << mesa_stage
);
1217 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1219 #define radv_foreach_stage(stage, stage_bits) \
1220 for (gl_shader_stage stage, \
1221 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1222 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1223 __tmp &= ~(1 << (stage)))
1225 unsigned radv_format_meta_fs_key(VkFormat format
);
1227 struct radv_multisample_state
{
1229 uint32_t pa_sc_line_cntl
;
1230 uint32_t pa_sc_mode_cntl_0
;
1231 uint32_t pa_sc_mode_cntl_1
;
1232 uint32_t pa_sc_aa_config
;
1233 uint32_t pa_sc_aa_mask
[2];
1234 unsigned num_samples
;
1237 struct radv_prim_vertex_count
{
1242 struct radv_vertex_elements_info
{
1243 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1244 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1245 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1246 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1250 struct radv_ia_multi_vgt_param_helpers
{
1252 bool partial_es_wave
;
1253 uint8_t primgroup_size
;
1254 bool wd_switch_on_eop
;
1255 bool ia_switch_on_eoi
;
1256 bool partial_vs_wave
;
1259 #define SI_GS_PER_ES 128
1261 struct radv_pipeline
{
1262 struct radv_device
* device
;
1263 struct radv_dynamic_state dynamic_state
;
1265 struct radv_pipeline_layout
* layout
;
1267 bool need_indirect_descriptor_sets
;
1268 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1269 struct radv_shader_variant
*gs_copy_shader
;
1270 VkShaderStageFlags active_stages
;
1272 struct radeon_winsys_cs cs
;
1274 struct radv_vertex_elements_info vertex_elements
;
1276 uint32_t binding_stride
[MAX_VBS
];
1278 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1281 struct radv_multisample_state ms
;
1282 uint32_t spi_baryc_cntl
;
1283 bool prim_restart_enable
;
1284 unsigned esgs_ring_size
;
1285 unsigned gsvs_ring_size
;
1286 uint32_t vtx_base_sgpr
;
1287 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1288 uint8_t vtx_emit_num
;
1289 struct radv_prim_vertex_count prim_vertex_count
;
1290 bool can_use_guardband
;
1291 uint32_t needed_dynamic_state
;
1292 bool disable_out_of_order_rast_for_occlusion
;
1294 /* Used for rbplus */
1295 uint32_t col_format
;
1296 uint32_t cb_target_mask
;
1301 unsigned scratch_bytes_per_wave
;
1304 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1306 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1309 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1311 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1314 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1315 gl_shader_stage stage
,
1318 struct radv_shader_variant
*radv_get_vertex_shader(struct radv_pipeline
*pipeline
);
1320 struct radv_graphics_pipeline_create_info
{
1322 bool db_depth_clear
;
1323 bool db_stencil_clear
;
1324 bool db_depth_disable_expclear
;
1325 bool db_stencil_disable_expclear
;
1326 bool db_flush_depth_inplace
;
1327 bool db_flush_stencil_inplace
;
1328 bool db_resummarize
;
1329 uint32_t custom_blend_mode
;
1333 radv_graphics_pipeline_create(VkDevice device
,
1334 VkPipelineCache cache
,
1335 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1336 const struct radv_graphics_pipeline_create_info
*extra
,
1337 const VkAllocationCallbacks
*alloc
,
1338 VkPipeline
*pPipeline
);
1340 struct vk_format_description
;
1341 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1342 int first_non_void
);
1343 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1344 int first_non_void
);
1345 uint32_t radv_translate_colorformat(VkFormat format
);
1346 uint32_t radv_translate_color_numformat(VkFormat format
,
1347 const struct vk_format_description
*desc
,
1348 int first_non_void
);
1349 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1350 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1351 uint32_t radv_translate_dbformat(VkFormat format
);
1352 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1353 const struct vk_format_description
*desc
,
1354 int first_non_void
);
1355 uint32_t radv_translate_tex_numformat(VkFormat format
,
1356 const struct vk_format_description
*desc
,
1357 int first_non_void
);
1358 bool radv_format_pack_clear_color(VkFormat format
,
1359 uint32_t clear_vals
[2],
1360 VkClearColorValue
*value
);
1361 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1362 bool radv_dcc_formats_compatible(VkFormat format1
,
1365 struct radv_fmask_info
{
1369 unsigned pitch_in_pixels
;
1370 unsigned bank_height
;
1371 unsigned slice_tile_max
;
1372 unsigned tile_mode_index
;
1373 unsigned tile_swizzle
;
1376 struct radv_cmask_info
{
1380 unsigned slice_tile_max
;
1385 /* The original VkFormat provided by the client. This may not match any
1386 * of the actual surface formats.
1389 VkImageAspectFlags aspects
;
1390 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1391 struct ac_surf_info info
;
1392 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1393 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1398 unsigned queue_family_mask
;
1402 /* Set when bound */
1403 struct radeon_winsys_bo
*bo
;
1404 VkDeviceSize offset
;
1405 uint64_t dcc_offset
;
1406 uint64_t htile_offset
;
1407 bool tc_compatible_htile
;
1408 struct radeon_surf surface
;
1410 struct radv_fmask_info fmask
;
1411 struct radv_cmask_info cmask
;
1412 uint64_t clear_value_offset
;
1413 uint64_t dcc_pred_offset
;
1415 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1416 VkDeviceMemory owned_memory
;
1419 /* Whether the image has a htile that is known consistent with the contents of
1421 bool radv_layout_has_htile(const struct radv_image
*image
,
1422 VkImageLayout layout
,
1423 unsigned queue_mask
);
1425 /* Whether the image has a htile that is known consistent with the contents of
1426 * the image and is allowed to be in compressed form.
1428 * If this is false reads that don't use the htile should be able to return
1431 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1432 VkImageLayout layout
,
1433 unsigned queue_mask
);
1435 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1436 VkImageLayout layout
,
1437 unsigned queue_mask
);
1439 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1440 VkImageLayout layout
,
1441 unsigned queue_mask
);
1444 * Return whether the image has CMASK metadata for color surfaces.
1447 radv_image_has_cmask(const struct radv_image
*image
)
1449 return image
->cmask
.size
;
1453 * Return whether the image has FMASK metadata for color surfaces.
1456 radv_image_has_fmask(const struct radv_image
*image
)
1458 return image
->fmask
.size
;
1462 * Return whether the image has DCC metadata for color surfaces.
1465 radv_image_has_dcc(const struct radv_image
*image
)
1467 return image
->surface
.dcc_size
;
1471 * Return whether DCC metadata is enabled for a level.
1474 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1476 return radv_image_has_dcc(image
) &&
1477 level
< image
->surface
.num_dcc_levels
;
1481 * Return whether the image has HTILE metadata for depth surfaces.
1484 radv_image_has_htile(const struct radv_image
*image
)
1486 return image
->surface
.htile_size
;
1490 * Return whether HTILE metadata is enabled for a level.
1493 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1495 return radv_image_has_htile(image
) && level
== 0;
1499 * Return whether the image is TC-compatible HTILE.
1502 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1504 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1507 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1509 static inline uint32_t
1510 radv_get_layerCount(const struct radv_image
*image
,
1511 const VkImageSubresourceRange
*range
)
1513 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1514 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1517 static inline uint32_t
1518 radv_get_levelCount(const struct radv_image
*image
,
1519 const VkImageSubresourceRange
*range
)
1521 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1522 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1525 struct radeon_bo_metadata
;
1527 radv_init_metadata(struct radv_device
*device
,
1528 struct radv_image
*image
,
1529 struct radeon_bo_metadata
*metadata
);
1531 struct radv_image_view
{
1532 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1533 struct radeon_winsys_bo
*bo
;
1535 VkImageViewType type
;
1536 VkImageAspectFlags aspect_mask
;
1538 uint32_t base_layer
;
1539 uint32_t layer_count
;
1541 uint32_t level_count
;
1542 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1544 uint32_t descriptor
[16];
1546 /* Descriptor for use as a storage image as opposed to a sampled image.
1547 * This has a few differences for cube maps (e.g. type).
1549 uint32_t storage_descriptor
[16];
1552 struct radv_image_create_info
{
1553 const VkImageCreateInfo
*vk_info
;
1555 bool no_metadata_planes
;
1558 VkResult
radv_image_create(VkDevice _device
,
1559 const struct radv_image_create_info
*info
,
1560 const VkAllocationCallbacks
* alloc
,
1564 radv_image_from_gralloc(VkDevice device_h
,
1565 const VkImageCreateInfo
*base_info
,
1566 const VkNativeBufferANDROID
*gralloc_info
,
1567 const VkAllocationCallbacks
*alloc
,
1568 VkImage
*out_image_h
);
1570 void radv_image_view_init(struct radv_image_view
*view
,
1571 struct radv_device
*device
,
1572 const VkImageViewCreateInfo
* pCreateInfo
);
1574 struct radv_buffer_view
{
1575 struct radeon_winsys_bo
*bo
;
1577 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1580 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1581 struct radv_device
*device
,
1582 const VkBufferViewCreateInfo
* pCreateInfo
);
1584 static inline struct VkExtent3D
1585 radv_sanitize_image_extent(const VkImageType imageType
,
1586 const struct VkExtent3D imageExtent
)
1588 switch (imageType
) {
1589 case VK_IMAGE_TYPE_1D
:
1590 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1591 case VK_IMAGE_TYPE_2D
:
1592 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1593 case VK_IMAGE_TYPE_3D
:
1596 unreachable("invalid image type");
1600 static inline struct VkOffset3D
1601 radv_sanitize_image_offset(const VkImageType imageType
,
1602 const struct VkOffset3D imageOffset
)
1604 switch (imageType
) {
1605 case VK_IMAGE_TYPE_1D
:
1606 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1607 case VK_IMAGE_TYPE_2D
:
1608 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1609 case VK_IMAGE_TYPE_3D
:
1612 unreachable("invalid image type");
1617 radv_image_extent_compare(const struct radv_image
*image
,
1618 const VkExtent3D
*extent
)
1620 if (extent
->width
!= image
->info
.width
||
1621 extent
->height
!= image
->info
.height
||
1622 extent
->depth
!= image
->info
.depth
)
1627 struct radv_sampler
{
1631 struct radv_color_buffer_info
{
1632 uint64_t cb_color_base
;
1633 uint64_t cb_color_cmask
;
1634 uint64_t cb_color_fmask
;
1635 uint64_t cb_dcc_base
;
1636 uint32_t cb_color_pitch
;
1637 uint32_t cb_color_slice
;
1638 uint32_t cb_color_view
;
1639 uint32_t cb_color_info
;
1640 uint32_t cb_color_attrib
;
1641 uint32_t cb_color_attrib2
;
1642 uint32_t cb_dcc_control
;
1643 uint32_t cb_color_cmask_slice
;
1644 uint32_t cb_color_fmask_slice
;
1647 struct radv_ds_buffer_info
{
1648 uint64_t db_z_read_base
;
1649 uint64_t db_stencil_read_base
;
1650 uint64_t db_z_write_base
;
1651 uint64_t db_stencil_write_base
;
1652 uint64_t db_htile_data_base
;
1653 uint32_t db_depth_info
;
1655 uint32_t db_stencil_info
;
1656 uint32_t db_depth_view
;
1657 uint32_t db_depth_size
;
1658 uint32_t db_depth_slice
;
1659 uint32_t db_htile_surface
;
1660 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1661 uint32_t db_z_info2
;
1662 uint32_t db_stencil_info2
;
1666 struct radv_attachment_info
{
1668 struct radv_color_buffer_info cb
;
1669 struct radv_ds_buffer_info ds
;
1671 struct radv_image_view
*attachment
;
1674 struct radv_framebuffer
{
1679 uint32_t attachment_count
;
1680 struct radv_attachment_info attachments
[0];
1683 struct radv_subpass_barrier
{
1684 VkPipelineStageFlags src_stage_mask
;
1685 VkAccessFlags src_access_mask
;
1686 VkAccessFlags dst_access_mask
;
1689 struct radv_subpass
{
1690 uint32_t input_count
;
1691 uint32_t color_count
;
1692 VkAttachmentReference
* input_attachments
;
1693 VkAttachmentReference
* color_attachments
;
1694 VkAttachmentReference
* resolve_attachments
;
1695 VkAttachmentReference depth_stencil_attachment
;
1697 /** Subpass has at least one resolve attachment */
1700 struct radv_subpass_barrier start_barrier
;
1703 VkSampleCountFlagBits max_sample_count
;
1706 struct radv_render_pass_attachment
{
1709 VkAttachmentLoadOp load_op
;
1710 VkAttachmentLoadOp stencil_load_op
;
1711 VkImageLayout initial_layout
;
1712 VkImageLayout final_layout
;
1716 struct radv_render_pass
{
1717 uint32_t attachment_count
;
1718 uint32_t subpass_count
;
1719 VkAttachmentReference
* subpass_attachments
;
1720 struct radv_render_pass_attachment
* attachments
;
1721 struct radv_subpass_barrier end_barrier
;
1722 struct radv_subpass subpasses
[0];
1725 VkResult
radv_device_init_meta(struct radv_device
*device
);
1726 void radv_device_finish_meta(struct radv_device
*device
);
1728 struct radv_query_pool
{
1729 struct radeon_winsys_bo
*bo
;
1731 uint32_t availability_offset
;
1735 uint32_t pipeline_stats_mask
;
1738 struct radv_semaphore
{
1739 /* use a winsys sem for non-exportable */
1740 struct radeon_winsys_sem
*sem
;
1742 uint32_t temp_syncobj
;
1745 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1747 const VkSemaphore
*wait_sems
,
1748 int num_signal_sems
,
1749 const VkSemaphore
*signal_sems
,
1751 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1753 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1754 VkPipelineBindPoint bind_point
,
1755 struct radv_descriptor_set
*set
,
1759 radv_update_descriptor_sets(struct radv_device
*device
,
1760 struct radv_cmd_buffer
*cmd_buffer
,
1761 VkDescriptorSet overrideSet
,
1762 uint32_t descriptorWriteCount
,
1763 const VkWriteDescriptorSet
*pDescriptorWrites
,
1764 uint32_t descriptorCopyCount
,
1765 const VkCopyDescriptorSet
*pDescriptorCopies
);
1768 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1769 struct radv_cmd_buffer
*cmd_buffer
,
1770 struct radv_descriptor_set
*set
,
1771 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1774 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1775 VkPipelineBindPoint pipelineBindPoint
,
1776 VkPipelineLayout _layout
,
1778 uint32_t descriptorWriteCount
,
1779 const VkWriteDescriptorSet
*pDescriptorWrites
);
1781 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1782 struct radv_image
*image
, uint32_t value
);
1785 struct radeon_winsys_fence
*fence
;
1790 uint32_t temp_syncobj
;
1793 /* radv_nir_to_llvm.c */
1794 struct radv_shader_variant_info
;
1795 struct radv_nir_compiler_options
;
1797 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm
,
1798 struct nir_shader
*geom_shader
,
1799 struct ac_shader_binary
*binary
,
1800 struct ac_shader_config
*config
,
1801 struct radv_shader_variant_info
*shader_info
,
1802 const struct radv_nir_compiler_options
*option
);
1804 void radv_compile_nir_shader(LLVMTargetMachineRef tm
,
1805 struct ac_shader_binary
*binary
,
1806 struct ac_shader_config
*config
,
1807 struct radv_shader_variant_info
*shader_info
,
1808 struct nir_shader
*const *nir
,
1810 const struct radv_nir_compiler_options
*options
);
1812 /* radv_shader_info.h */
1813 struct radv_shader_info
;
1815 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
1816 const struct radv_nir_compiler_options
*options
,
1817 struct radv_shader_info
*info
);
1819 struct radeon_winsys_sem
;
1821 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1823 static inline struct __radv_type * \
1824 __radv_type ## _from_handle(__VkType _handle) \
1826 return (struct __radv_type *) _handle; \
1829 static inline __VkType \
1830 __radv_type ## _to_handle(struct __radv_type *_obj) \
1832 return (__VkType) _obj; \
1835 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1837 static inline struct __radv_type * \
1838 __radv_type ## _from_handle(__VkType _handle) \
1840 return (struct __radv_type *)(uintptr_t) _handle; \
1843 static inline __VkType \
1844 __radv_type ## _to_handle(struct __radv_type *_obj) \
1846 return (__VkType)(uintptr_t) _obj; \
1849 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1850 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1852 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1853 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1854 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1855 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1856 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1858 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1859 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1860 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1861 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1862 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1863 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1864 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1865 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1866 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1867 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1868 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1869 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1870 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1871 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1872 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1873 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1874 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1875 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1876 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1877 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1878 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1880 #endif /* RADV_PRIVATE_H */