2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
60 #include <llvm-c/TargetMachine.h>
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t
;
66 typedef uint32_t xcb_visualid_t
;
67 typedef uint32_t xcb_window_t
;
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
73 #include "radv_entrypoints.h"
75 #include "wsi_common.h"
77 #define ATI_VENDOR_ID 0x1002
80 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
105 RADV_MEM_TYPE_GTT_CACHED
,
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111 static inline uint32_t
112 align_u32(uint32_t v
, uint32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 static inline uint32_t
119 align_u32_npot(uint32_t v
, uint32_t a
)
121 return (v
+ a
- 1) / a
* a
;
124 static inline uint64_t
125 align_u64(uint64_t v
, uint64_t a
)
127 assert(a
!= 0 && a
== (a
& -a
));
128 return (v
+ a
- 1) & ~(a
- 1);
131 static inline int32_t
132 align_i32(int32_t v
, int32_t a
)
134 assert(a
!= 0 && a
== (a
& -a
));
135 return (v
+ a
- 1) & ~(a
- 1);
138 /** Alignment must be a power of 2. */
140 radv_is_aligned(uintmax_t n
, uintmax_t a
)
142 assert(a
== (a
& -a
));
143 return (n
& (a
- 1)) == 0;
146 static inline uint32_t
147 round_up_u32(uint32_t v
, uint32_t a
)
149 return (v
+ a
- 1) / a
;
152 static inline uint64_t
153 round_up_u64(uint64_t v
, uint64_t a
)
155 return (v
+ a
- 1) / a
;
158 static inline uint32_t
159 radv_minify(uint32_t n
, uint32_t levels
)
161 if (unlikely(n
== 0))
164 return MAX2(n
>> levels
, 1);
167 radv_clamp_f(float f
, float min
, float max
)
180 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
182 if (*inout_mask
& clear_mask
) {
183 *inout_mask
&= ~clear_mask
;
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
205 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
215 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format
, va_list va
);
221 * Print a FINISHME message, including its source location.
223 #define radv_finishme(format, ...) \
225 static bool reported = false; \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
232 /* A non-fatal assert. Useful for debugging. */
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
239 #define radv_assert(x)
242 #define stub_return(v) \
244 radv_finishme("stub %s", __func__); \
250 radv_finishme("stub %s", __func__); \
254 void *radv_lookup_entrypoint(const char *name
);
256 struct radv_extensions
{
257 VkExtensionProperties
*ext_array
;
261 struct radv_physical_device
{
262 VK_LOADER_DATA _loader_data
;
264 struct radv_instance
* instance
;
266 struct radeon_winsys
*ws
;
267 struct radeon_info rad_info
;
270 uint8_t driver_uuid
[VK_UUID_SIZE
];
271 uint8_t device_uuid
[VK_UUID_SIZE
];
272 uint8_t cache_uuid
[VK_UUID_SIZE
];
275 struct wsi_device wsi_device
;
276 struct radv_extensions extensions
;
278 bool has_rbplus
; /* if RB+ register exist */
279 bool rbplus_allowed
; /* if RB+ is allowed */
282 /* This is the drivers on-disk cache used as a fallback as opposed to
283 * the pipeline cache defined by apps.
285 struct disk_cache
* disk_cache
;
288 struct radv_instance
{
289 VK_LOADER_DATA _loader_data
;
291 VkAllocationCallbacks alloc
;
294 int physicalDeviceCount
;
295 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
297 uint64_t debug_flags
;
298 uint64_t perftest_flags
;
301 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
302 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
306 struct radv_pipeline_cache
{
307 struct radv_device
* device
;
308 pthread_mutex_t mutex
;
312 uint32_t kernel_count
;
313 struct cache_entry
** hash_table
;
316 VkAllocationCallbacks alloc
;
320 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
321 struct radv_device
*device
);
323 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
325 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
326 const void *data
, size_t size
);
328 struct radv_shader_variant
*
329 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
330 struct radv_pipeline_cache
*cache
,
331 const unsigned char *sha1
);
333 struct radv_shader_variant
*
334 radv_pipeline_cache_insert_shader(struct radv_device
*device
,
335 struct radv_pipeline_cache
*cache
,
336 const unsigned char *sha1
,
337 struct radv_shader_variant
*variant
,
338 const void *code
, unsigned code_size
);
340 struct radv_meta_state
{
341 VkAllocationCallbacks alloc
;
343 struct radv_pipeline_cache cache
;
346 * Use array element `i` for images with `2^i` samples.
349 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
350 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
352 VkRenderPass depthstencil_rp
;
353 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
354 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
355 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
356 } clear
[1 + MAX_SAMPLES_LOG2
];
358 VkPipelineLayout clear_color_p_layout
;
359 VkPipelineLayout clear_depth_p_layout
;
361 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
363 /** Pipeline that blits from a 1D image. */
364 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
366 /** Pipeline that blits from a 2D image. */
367 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
369 /** Pipeline that blits from a 3D image. */
370 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
372 VkRenderPass depth_only_rp
;
373 VkPipeline depth_only_1d_pipeline
;
374 VkPipeline depth_only_2d_pipeline
;
375 VkPipeline depth_only_3d_pipeline
;
377 VkRenderPass stencil_only_rp
;
378 VkPipeline stencil_only_1d_pipeline
;
379 VkPipeline stencil_only_2d_pipeline
;
380 VkPipeline stencil_only_3d_pipeline
;
381 VkPipelineLayout pipeline_layout
;
382 VkDescriptorSetLayout ds_layout
;
386 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
388 VkPipelineLayout p_layouts
[2];
389 VkDescriptorSetLayout ds_layouts
[2];
390 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
392 VkRenderPass depth_only_rp
;
393 VkPipeline depth_only_pipeline
[2];
395 VkRenderPass stencil_only_rp
;
396 VkPipeline stencil_only_pipeline
[2];
400 VkPipelineLayout img_p_layout
;
401 VkDescriptorSetLayout img_ds_layout
;
405 VkPipelineLayout img_p_layout
;
406 VkDescriptorSetLayout img_ds_layout
;
410 VkPipelineLayout img_p_layout
;
411 VkDescriptorSetLayout img_ds_layout
;
415 VkPipelineLayout img_p_layout
;
416 VkDescriptorSetLayout img_ds_layout
;
426 VkDescriptorSetLayout ds_layout
;
427 VkPipelineLayout p_layout
;
430 VkPipeline i_pipeline
;
431 VkPipeline srgb_pipeline
;
432 } rc
[MAX_SAMPLES_LOG2
];
436 VkDescriptorSetLayout ds_layout
;
437 VkPipelineLayout p_layout
;
440 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
441 VkPipeline pipeline
[NUM_META_FS_KEYS
];
442 } rc
[MAX_SAMPLES_LOG2
];
446 VkPipeline decompress_pipeline
;
447 VkPipeline resummarize_pipeline
;
449 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
452 VkPipeline cmask_eliminate_pipeline
;
453 VkPipeline fmask_decompress_pipeline
;
458 VkPipelineLayout fill_p_layout
;
459 VkPipelineLayout copy_p_layout
;
460 VkDescriptorSetLayout fill_ds_layout
;
461 VkDescriptorSetLayout copy_ds_layout
;
462 VkPipeline fill_pipeline
;
463 VkPipeline copy_pipeline
;
467 VkDescriptorSetLayout ds_layout
;
468 VkPipelineLayout p_layout
;
469 VkPipeline occlusion_query_pipeline
;
470 VkPipeline pipeline_statistics_query_pipeline
;
475 #define RADV_QUEUE_GENERAL 0
476 #define RADV_QUEUE_COMPUTE 1
477 #define RADV_QUEUE_TRANSFER 2
479 #define RADV_MAX_QUEUE_FAMILIES 3
481 enum ring_type
radv_queue_family_to_ring(int f
);
484 VK_LOADER_DATA _loader_data
;
485 struct radv_device
* device
;
486 struct radeon_winsys_ctx
*hw_ctx
;
487 int queue_family_index
;
490 uint32_t scratch_size
;
491 uint32_t compute_scratch_size
;
492 uint32_t esgs_ring_size
;
493 uint32_t gsvs_ring_size
;
495 bool has_sample_positions
;
497 struct radeon_winsys_bo
*scratch_bo
;
498 struct radeon_winsys_bo
*descriptor_bo
;
499 struct radeon_winsys_bo
*compute_scratch_bo
;
500 struct radeon_winsys_bo
*esgs_ring_bo
;
501 struct radeon_winsys_bo
*gsvs_ring_bo
;
502 struct radeon_winsys_bo
*tess_factor_ring_bo
;
503 struct radeon_winsys_bo
*tess_offchip_ring_bo
;
504 struct radeon_winsys_cs
*initial_preamble_cs
;
505 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
506 struct radeon_winsys_cs
*continue_preamble_cs
;
510 VK_LOADER_DATA _loader_data
;
512 VkAllocationCallbacks alloc
;
514 struct radv_instance
* instance
;
515 struct radeon_winsys
*ws
;
517 struct radv_meta_state meta_state
;
519 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
520 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
521 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
523 bool llvm_supports_spill
;
524 bool has_distributed_tess
;
525 uint32_t tess_offchip_block_dw_size
;
526 uint32_t scratch_waves
;
528 uint32_t gs_table_depth
;
530 /* MSAA sample locations.
531 * The first index is the sample index.
532 * The second index is the coordinate: X, Y. */
533 float sample_locations_1x
[1][2];
534 float sample_locations_2x
[2][2];
535 float sample_locations_4x
[4][2];
536 float sample_locations_8x
[8][2];
537 float sample_locations_16x
[16][2];
540 uint32_t gfx_init_size_dw
;
541 struct radeon_winsys_bo
*gfx_init
;
543 struct radeon_winsys_bo
*trace_bo
;
544 uint32_t *trace_id_ptr
;
546 struct radv_physical_device
*physical_device
;
548 /* Backup in-memory cache to be used if the app doesn't provide one */
549 struct radv_pipeline_cache
* mem_cache
;
552 * use different counters so MSAA MRTs get consecutive surface indices,
553 * even if MASK is allocated in between.
555 uint32_t image_mrt_offset_counter
;
556 uint32_t fmask_mrt_offset_counter
;
557 struct list_head shader_slabs
;
558 mtx_t shader_slab_mutex
;
560 /* For detecting VM faults reported by dmesg. */
561 uint64_t dmesg_timestamp
;
564 struct radv_device_memory
{
565 struct radeon_winsys_bo
*bo
;
566 /* for dedicated allocations */
567 struct radv_image
*image
;
568 struct radv_buffer
*buffer
;
570 VkDeviceSize map_size
;
575 struct radv_descriptor_range
{
580 struct radv_descriptor_set
{
581 const struct radv_descriptor_set_layout
*layout
;
584 struct radeon_winsys_bo
*bo
;
586 uint32_t *mapped_ptr
;
587 struct radv_descriptor_range
*dynamic_descriptors
;
589 struct list_head vram_list
;
591 struct radeon_winsys_bo
*descriptors
[0];
594 struct radv_push_descriptor_set
596 struct radv_descriptor_set set
;
600 struct radv_descriptor_pool
{
601 struct radeon_winsys_bo
*bo
;
603 uint64_t current_offset
;
606 struct list_head vram_list
;
608 uint8_t *host_memory_base
;
609 uint8_t *host_memory_ptr
;
610 uint8_t *host_memory_end
;
613 struct radv_descriptor_update_template_entry
{
614 VkDescriptorType descriptor_type
;
616 /* The number of descriptors to update */
617 uint32_t descriptor_count
;
619 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
622 /* In dwords. Not valid/used for dynamic descriptors */
625 uint32_t buffer_offset
;
627 /* Only valid for combined image samplers and samplers */
628 uint16_t has_sampler
;
634 /* For push descriptors */
635 const uint32_t *immutable_samplers
;
638 struct radv_descriptor_update_template
{
639 uint32_t entry_count
;
640 struct radv_descriptor_update_template_entry entry
[0];
644 struct radv_device
* device
;
647 VkBufferUsageFlags usage
;
648 VkBufferCreateFlags flags
;
651 struct radeon_winsys_bo
* bo
;
656 enum radv_cmd_dirty_bits
{
657 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
658 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
659 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
660 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
661 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
662 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
663 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
664 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
665 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
666 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
667 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
668 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
669 RADV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
671 typedef uint32_t radv_cmd_dirty_mask_t
;
673 enum radv_cmd_flush_bits
{
674 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
675 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
676 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
677 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
678 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
679 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
680 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
681 /* Same as above, but only writes back and doesn't invalidate */
682 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
683 /* Framebuffer caches */
684 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
685 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
686 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
687 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
688 /* Engine synchronization. */
689 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
690 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
691 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
692 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
694 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
695 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
696 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
697 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
700 struct radv_vertex_binding
{
701 struct radv_buffer
* buffer
;
705 struct radv_viewport_state
{
707 VkViewport viewports
[MAX_VIEWPORTS
];
710 struct radv_scissor_state
{
712 VkRect2D scissors
[MAX_SCISSORS
];
715 struct radv_dynamic_state
{
716 struct radv_viewport_state viewport
;
718 struct radv_scissor_state scissor
;
728 float blend_constants
[4];
738 } stencil_compare_mask
;
743 } stencil_write_mask
;
751 extern const struct radv_dynamic_state default_dynamic_state
;
754 radv_get_debug_option_name(int id
);
757 radv_get_perftest_option_name(int id
);
760 * Attachment state when recording a renderpass instance.
762 * The clear value is valid only if there exists a pending clear.
764 struct radv_attachment_state
{
765 VkImageAspectFlags pending_clear_aspects
;
766 uint32_t cleared_views
;
767 VkClearValue clear_value
;
768 VkImageLayout current_layout
;
771 struct radv_cmd_state
{
773 radv_cmd_dirty_mask_t dirty
;
774 bool push_descriptors_dirty
;
777 struct radv_pipeline
* pipeline
;
778 struct radv_pipeline
* emitted_pipeline
;
779 struct radv_pipeline
* compute_pipeline
;
780 struct radv_pipeline
* emitted_compute_pipeline
;
781 struct radv_framebuffer
* framebuffer
;
782 struct radv_render_pass
* pass
;
783 const struct radv_subpass
* subpass
;
784 struct radv_dynamic_state dynamic
;
785 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
786 struct radv_descriptor_set
* descriptors
[MAX_SETS
];
787 struct radv_attachment_state
* attachments
;
788 VkRect2D render_area
;
790 uint32_t max_index_count
;
792 int32_t last_primitive_reset_en
;
793 uint32_t last_primitive_reset_index
;
794 enum radv_cmd_flush_bits flush_bits
;
795 unsigned active_occlusion_queries
;
797 uint32_t descriptors_dirty
;
799 uint32_t last_ia_multi_vgt_param
;
802 struct radv_cmd_pool
{
803 VkAllocationCallbacks alloc
;
804 struct list_head cmd_buffers
;
805 struct list_head free_cmd_buffers
;
806 uint32_t queue_family_index
;
809 struct radv_cmd_buffer_upload
{
813 struct radeon_winsys_bo
*upload_bo
;
814 struct list_head list
;
817 struct radv_cmd_buffer
{
818 VK_LOADER_DATA _loader_data
;
820 struct radv_device
* device
;
822 struct radv_cmd_pool
* pool
;
823 struct list_head pool_link
;
825 VkCommandBufferUsageFlags usage_flags
;
826 VkCommandBufferLevel level
;
827 struct radeon_winsys_cs
*cs
;
828 struct radv_cmd_state state
;
829 uint32_t queue_family_index
;
831 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
832 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
833 VkShaderStageFlags push_constant_stages
;
834 struct radv_push_descriptor_set push_descriptors
;
835 struct radv_descriptor_set meta_push_descriptors
;
837 struct radv_cmd_buffer_upload upload
;
839 uint32_t scratch_size_needed
;
840 uint32_t compute_scratch_size_needed
;
841 uint32_t esgs_ring_size_needed
;
842 uint32_t gsvs_ring_size_needed
;
843 bool tess_rings_needed
;
844 bool sample_positions_needed
;
846 VkResult record_result
;
848 int ring_offsets_idx
; /* just used for verification */
849 uint32_t gfx9_fence_offset
;
850 struct radeon_winsys_bo
*gfx9_fence_bo
;
851 uint32_t gfx9_fence_idx
;
856 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
858 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
859 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
861 void cik_create_gfx_config(struct radv_device
*device
);
863 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
864 int count
, const VkViewport
*viewports
);
865 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
866 int count
, const VkRect2D
*scissors
,
867 const VkViewport
*viewports
, bool can_use_guardband
);
868 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
869 bool instanced_draw
, bool indirect_draw
,
870 uint32_t draw_vertex_count
);
871 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
873 enum chip_class chip_class
,
875 unsigned event
, unsigned event_flags
,
881 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
883 uint64_t va
, uint32_t ref
,
885 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
887 enum chip_class chip_class
,
888 uint32_t *fence_ptr
, uint64_t va
,
890 enum radv_cmd_flush_bits flush_bits
);
891 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
892 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
893 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
894 uint64_t src_va
, uint64_t dest_va
,
896 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
898 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
899 uint64_t size
, unsigned value
);
900 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
901 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
902 struct radv_descriptor_set
*set
,
905 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
908 unsigned *out_offset
,
911 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
912 const struct radv_subpass
*subpass
,
915 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
916 unsigned size
, unsigned alignmnet
,
917 const void *data
, unsigned *out_offset
);
919 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
920 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
921 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
922 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
923 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
924 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
925 unsigned radv_cayman_get_maxdist(int log_samples
);
926 void radv_device_init_msaa(struct radv_device
*device
);
927 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
928 struct radv_image
*image
,
929 VkClearDepthStencilValue ds_clear_value
,
930 VkImageAspectFlags aspects
);
931 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
932 struct radv_image
*image
,
934 uint32_t color_values
[2]);
935 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
936 struct radv_image
*image
,
938 void radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
939 struct radeon_winsys_bo
*bo
,
940 uint64_t offset
, uint64_t size
, uint32_t value
);
941 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
942 bool radv_get_memory_fd(struct radv_device
*device
,
943 struct radv_device_memory
*memory
,
946 * Takes x,y,z as exact numbers of invocations, instead of blocks.
948 * Limitations: Can't call normal dispatch functions without binding or rebinding
949 * the compute pipeline.
951 void radv_unaligned_dispatch(
952 struct radv_cmd_buffer
*cmd_buffer
,
958 struct radeon_winsys_bo
*bo
;
962 struct radv_shader_module
;
963 struct ac_shader_variant_key
;
966 radv_hash_shader(unsigned char *hash
, struct radv_shader_module
*module
,
967 const char *entrypoint
,
968 const VkSpecializationInfo
*spec_info
,
969 const struct radv_pipeline_layout
*layout
,
970 const struct ac_shader_variant_key
*key
,
971 uint32_t is_geom_copy_shader
);
973 static inline gl_shader_stage
974 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
976 assert(__builtin_popcount(vk_stage
) == 1);
977 return ffs(vk_stage
) - 1;
980 static inline VkShaderStageFlagBits
981 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
983 return (1 << mesa_stage
);
986 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
988 #define radv_foreach_stage(stage, stage_bits) \
989 for (gl_shader_stage stage, \
990 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
991 stage = __builtin_ffs(__tmp) - 1, __tmp; \
992 __tmp &= ~(1 << (stage)))
994 struct radv_depth_stencil_state
{
995 uint32_t db_depth_control
;
996 uint32_t db_stencil_control
;
997 uint32_t db_render_control
;
998 uint32_t db_render_override2
;
1001 struct radv_blend_state
{
1002 uint32_t cb_color_control
;
1003 uint32_t cb_target_mask
;
1004 uint32_t sx_mrt_blend_opt
[8];
1005 uint32_t cb_blend_control
[8];
1007 uint32_t spi_shader_col_format
;
1008 uint32_t cb_shader_mask
;
1009 uint32_t db_alpha_to_mask
;
1012 unsigned radv_format_meta_fs_key(VkFormat format
);
1014 struct radv_raster_state
{
1015 uint32_t pa_cl_clip_cntl
;
1016 uint32_t spi_interp_control
;
1017 uint32_t pa_su_vtx_cntl
;
1018 uint32_t pa_su_sc_mode_cntl
;
1021 struct radv_multisample_state
{
1023 uint32_t pa_sc_line_cntl
;
1024 uint32_t pa_sc_mode_cntl_0
;
1025 uint32_t pa_sc_mode_cntl_1
;
1026 uint32_t pa_sc_aa_config
;
1027 uint32_t pa_sc_aa_mask
[2];
1028 unsigned num_samples
;
1031 struct radv_prim_vertex_count
{
1036 struct radv_tessellation_state
{
1037 uint32_t ls_hs_config
;
1038 uint32_t tcs_in_layout
;
1039 uint32_t tcs_out_layout
;
1040 uint32_t tcs_out_offsets
;
1041 uint32_t offchip_layout
;
1042 unsigned num_patches
;
1044 unsigned num_tcs_input_cp
;
1048 struct radv_vertex_elements_info
{
1049 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1050 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1051 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1052 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1056 #define SI_GS_PER_ES 128
1058 struct radv_pipeline
{
1059 struct radv_device
* device
;
1060 uint32_t dynamic_state_mask
;
1061 struct radv_dynamic_state dynamic_state
;
1063 struct radv_pipeline_layout
* layout
;
1065 bool needs_data_cache
;
1066 bool need_indirect_descriptor_sets
;
1067 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1068 struct radv_shader_variant
*gs_copy_shader
;
1069 VkShaderStageFlags active_stages
;
1071 struct radv_vertex_elements_info vertex_elements
;
1073 uint32_t binding_stride
[MAX_VBS
];
1077 struct radv_blend_state blend
;
1078 struct radv_depth_stencil_state ds
;
1079 struct radv_raster_state raster
;
1080 struct radv_multisample_state ms
;
1081 struct radv_tessellation_state tess
;
1082 uint32_t db_shader_control
;
1083 uint32_t shader_z_format
;
1086 uint32_t vgt_gs_mode
;
1087 bool vgt_primitiveid_en
;
1088 bool prim_restart_enable
;
1089 bool partial_es_wave
;
1090 uint8_t primgroup_size
;
1091 unsigned esgs_ring_size
;
1092 unsigned gsvs_ring_size
;
1093 uint32_t ps_input_cntl
[32];
1094 uint32_t ps_input_cntl_num
;
1095 uint32_t pa_cl_vs_out_cntl
;
1096 uint32_t vgt_shader_stages_en
;
1097 uint32_t vtx_base_sgpr
;
1098 uint32_t base_ia_multi_vgt_param
;
1099 bool wd_switch_on_eop
;
1100 bool ia_switch_on_eoi
;
1101 bool partial_vs_wave
;
1102 uint8_t vtx_emit_num
;
1103 uint32_t vtx_reuse_depth
;
1104 struct radv_prim_vertex_count prim_vertex_count
;
1105 bool can_use_guardband
;
1110 unsigned scratch_bytes_per_wave
;
1113 static inline bool radv_pipeline_has_gs(struct radv_pipeline
*pipeline
)
1115 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1118 static inline bool radv_pipeline_has_tess(struct radv_pipeline
*pipeline
)
1120 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ? true : false;
1123 struct ac_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1124 gl_shader_stage stage
,
1127 struct radv_graphics_pipeline_create_info
{
1129 bool db_depth_clear
;
1130 bool db_stencil_clear
;
1131 bool db_depth_disable_expclear
;
1132 bool db_stencil_disable_expclear
;
1133 bool db_flush_depth_inplace
;
1134 bool db_flush_stencil_inplace
;
1135 bool db_resummarize
;
1136 uint32_t custom_blend_mode
;
1140 radv_graphics_pipeline_create(VkDevice device
,
1141 VkPipelineCache cache
,
1142 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1143 const struct radv_graphics_pipeline_create_info
*extra
,
1144 const VkAllocationCallbacks
*alloc
,
1145 VkPipeline
*pPipeline
);
1147 struct vk_format_description
;
1148 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1149 int first_non_void
);
1150 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1151 int first_non_void
);
1152 uint32_t radv_translate_colorformat(VkFormat format
);
1153 uint32_t radv_translate_color_numformat(VkFormat format
,
1154 const struct vk_format_description
*desc
,
1155 int first_non_void
);
1156 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1157 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1158 uint32_t radv_translate_dbformat(VkFormat format
);
1159 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1160 const struct vk_format_description
*desc
,
1161 int first_non_void
);
1162 uint32_t radv_translate_tex_numformat(VkFormat format
,
1163 const struct vk_format_description
*desc
,
1164 int first_non_void
);
1165 bool radv_format_pack_clear_color(VkFormat format
,
1166 uint32_t clear_vals
[2],
1167 VkClearColorValue
*value
);
1168 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1169 bool radv_dcc_formats_compatible(VkFormat format1
,
1172 struct radv_fmask_info
{
1176 unsigned pitch_in_pixels
;
1177 unsigned bank_height
;
1178 unsigned slice_tile_max
;
1179 unsigned tile_mode_index
;
1180 unsigned tile_swizzle
;
1183 struct radv_cmask_info
{
1187 unsigned slice_tile_max
;
1188 unsigned base_address_reg
;
1191 struct r600_htile_info
{
1202 /* The original VkFormat provided by the client. This may not match any
1203 * of the actual surface formats.
1206 VkImageAspectFlags aspects
;
1207 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1208 struct ac_surf_info info
;
1209 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1210 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1215 unsigned queue_family_mask
;
1219 /* Set when bound */
1220 struct radeon_winsys_bo
*bo
;
1221 VkDeviceSize offset
;
1222 uint32_t dcc_offset
;
1223 uint32_t htile_offset
;
1224 bool tc_compatible_htile
;
1225 struct radeon_surf surface
;
1227 struct radv_fmask_info fmask
;
1228 struct radv_cmask_info cmask
;
1229 uint32_t clear_value_offset
;
1230 uint32_t dcc_pred_offset
;
1233 /* Whether the image has a htile that is known consistent with the contents of
1235 bool radv_layout_has_htile(const struct radv_image
*image
,
1236 VkImageLayout layout
,
1237 unsigned queue_mask
);
1239 /* Whether the image has a htile that is known consistent with the contents of
1240 * the image and is allowed to be in compressed form.
1242 * If this is false reads that don't use the htile should be able to return
1245 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1246 VkImageLayout layout
,
1247 unsigned queue_mask
);
1249 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1250 VkImageLayout layout
,
1251 unsigned queue_mask
);
1254 radv_vi_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1256 return image
->surface
.dcc_size
&& level
< image
->surface
.num_dcc_levels
;
1260 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1262 return image
->surface
.htile_size
&& level
== 0;
1265 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1267 static inline uint32_t
1268 radv_get_layerCount(const struct radv_image
*image
,
1269 const VkImageSubresourceRange
*range
)
1271 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1272 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1275 static inline uint32_t
1276 radv_get_levelCount(const struct radv_image
*image
,
1277 const VkImageSubresourceRange
*range
)
1279 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1280 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1283 struct radeon_bo_metadata
;
1285 radv_init_metadata(struct radv_device
*device
,
1286 struct radv_image
*image
,
1287 struct radeon_bo_metadata
*metadata
);
1289 struct radv_image_view
{
1290 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1291 struct radeon_winsys_bo
*bo
;
1293 VkImageViewType type
;
1294 VkImageAspectFlags aspect_mask
;
1296 uint32_t base_layer
;
1297 uint32_t layer_count
;
1299 uint32_t level_count
;
1300 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1302 uint32_t descriptor
[8];
1303 uint32_t fmask_descriptor
[8];
1305 /* Descriptor for use as a storage image as opposed to a sampled image.
1306 * This has a few differences for cube maps (e.g. type).
1308 uint32_t storage_descriptor
[8];
1309 uint32_t storage_fmask_descriptor
[8];
1312 struct radv_image_create_info
{
1313 const VkImageCreateInfo
*vk_info
;
1317 VkResult
radv_image_create(VkDevice _device
,
1318 const struct radv_image_create_info
*info
,
1319 const VkAllocationCallbacks
* alloc
,
1322 void radv_image_view_init(struct radv_image_view
*view
,
1323 struct radv_device
*device
,
1324 const VkImageViewCreateInfo
* pCreateInfo
);
1326 struct radv_buffer_view
{
1327 struct radeon_winsys_bo
*bo
;
1329 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1332 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1333 struct radv_device
*device
,
1334 const VkBufferViewCreateInfo
* pCreateInfo
);
1336 static inline struct VkExtent3D
1337 radv_sanitize_image_extent(const VkImageType imageType
,
1338 const struct VkExtent3D imageExtent
)
1340 switch (imageType
) {
1341 case VK_IMAGE_TYPE_1D
:
1342 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1343 case VK_IMAGE_TYPE_2D
:
1344 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1345 case VK_IMAGE_TYPE_3D
:
1348 unreachable("invalid image type");
1352 static inline struct VkOffset3D
1353 radv_sanitize_image_offset(const VkImageType imageType
,
1354 const struct VkOffset3D imageOffset
)
1356 switch (imageType
) {
1357 case VK_IMAGE_TYPE_1D
:
1358 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1359 case VK_IMAGE_TYPE_2D
:
1360 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1361 case VK_IMAGE_TYPE_3D
:
1364 unreachable("invalid image type");
1369 radv_image_extent_compare(const struct radv_image
*image
,
1370 const VkExtent3D
*extent
)
1372 if (extent
->width
!= image
->info
.width
||
1373 extent
->height
!= image
->info
.height
||
1374 extent
->depth
!= image
->info
.depth
)
1379 struct radv_sampler
{
1383 struct radv_color_buffer_info
{
1384 uint64_t cb_color_base
;
1385 uint64_t cb_color_cmask
;
1386 uint64_t cb_color_fmask
;
1387 uint64_t cb_dcc_base
;
1388 uint32_t cb_color_pitch
;
1389 uint32_t cb_color_slice
;
1390 uint32_t cb_color_view
;
1391 uint32_t cb_color_info
;
1392 uint32_t cb_color_attrib
;
1393 uint32_t cb_color_attrib2
;
1394 uint32_t cb_dcc_control
;
1395 uint32_t cb_color_cmask_slice
;
1396 uint32_t cb_color_fmask_slice
;
1397 uint32_t cb_clear_value0
;
1398 uint32_t cb_clear_value1
;
1399 uint32_t micro_tile_mode
;
1400 uint32_t gfx9_epitch
;
1403 struct radv_ds_buffer_info
{
1404 uint64_t db_z_read_base
;
1405 uint64_t db_stencil_read_base
;
1406 uint64_t db_z_write_base
;
1407 uint64_t db_stencil_write_base
;
1408 uint64_t db_htile_data_base
;
1409 uint32_t db_depth_info
;
1411 uint32_t db_stencil_info
;
1412 uint32_t db_depth_view
;
1413 uint32_t db_depth_size
;
1414 uint32_t db_depth_slice
;
1415 uint32_t db_htile_surface
;
1416 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1417 uint32_t db_z_info2
;
1418 uint32_t db_stencil_info2
;
1422 struct radv_attachment_info
{
1424 struct radv_color_buffer_info cb
;
1425 struct radv_ds_buffer_info ds
;
1427 struct radv_image_view
*attachment
;
1430 struct radv_framebuffer
{
1435 uint32_t attachment_count
;
1436 struct radv_attachment_info attachments
[0];
1439 struct radv_subpass_barrier
{
1440 VkPipelineStageFlags src_stage_mask
;
1441 VkAccessFlags src_access_mask
;
1442 VkAccessFlags dst_access_mask
;
1445 struct radv_subpass
{
1446 uint32_t input_count
;
1447 uint32_t color_count
;
1448 VkAttachmentReference
* input_attachments
;
1449 VkAttachmentReference
* color_attachments
;
1450 VkAttachmentReference
* resolve_attachments
;
1451 VkAttachmentReference depth_stencil_attachment
;
1453 /** Subpass has at least one resolve attachment */
1456 struct radv_subpass_barrier start_barrier
;
1461 struct radv_render_pass_attachment
{
1464 VkAttachmentLoadOp load_op
;
1465 VkAttachmentLoadOp stencil_load_op
;
1466 VkImageLayout initial_layout
;
1467 VkImageLayout final_layout
;
1471 struct radv_render_pass
{
1472 uint32_t attachment_count
;
1473 uint32_t subpass_count
;
1474 VkAttachmentReference
* subpass_attachments
;
1475 struct radv_render_pass_attachment
* attachments
;
1476 struct radv_subpass_barrier end_barrier
;
1477 struct radv_subpass subpasses
[0];
1480 VkResult
radv_device_init_meta(struct radv_device
*device
);
1481 void radv_device_finish_meta(struct radv_device
*device
);
1483 struct radv_query_pool
{
1484 struct radeon_winsys_bo
*bo
;
1486 uint32_t availability_offset
;
1489 uint32_t pipeline_stats_mask
;
1492 struct radv_semaphore
{
1493 /* use a winsys sem for non-exportable */
1494 struct radeon_winsys_sem
*sem
;
1496 uint32_t temp_syncobj
;
1499 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1501 const VkSemaphore
*wait_sems
,
1502 int num_signal_sems
,
1503 const VkSemaphore
*signal_sems
);
1504 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1507 radv_update_descriptor_sets(struct radv_device
*device
,
1508 struct radv_cmd_buffer
*cmd_buffer
,
1509 VkDescriptorSet overrideSet
,
1510 uint32_t descriptorWriteCount
,
1511 const VkWriteDescriptorSet
*pDescriptorWrites
,
1512 uint32_t descriptorCopyCount
,
1513 const VkCopyDescriptorSet
*pDescriptorCopies
);
1516 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1517 struct radv_cmd_buffer
*cmd_buffer
,
1518 struct radv_descriptor_set
*set
,
1519 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1522 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1523 VkPipelineBindPoint pipelineBindPoint
,
1524 VkPipelineLayout _layout
,
1526 uint32_t descriptorWriteCount
,
1527 const VkWriteDescriptorSet
*pDescriptorWrites
);
1529 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1530 struct radv_image
*image
, uint32_t value
);
1531 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1532 struct radv_image
*image
, uint32_t value
);
1535 struct radeon_winsys_fence
*fence
;
1540 struct radeon_winsys_sem
;
1542 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1544 static inline struct __radv_type * \
1545 __radv_type ## _from_handle(__VkType _handle) \
1547 return (struct __radv_type *) _handle; \
1550 static inline __VkType \
1551 __radv_type ## _to_handle(struct __radv_type *_obj) \
1553 return (__VkType) _obj; \
1556 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1558 static inline struct __radv_type * \
1559 __radv_type ## _from_handle(__VkType _handle) \
1561 return (struct __radv_type *)(uintptr_t) _handle; \
1564 static inline __VkType \
1565 __radv_type ## _to_handle(struct __radv_type *_obj) \
1567 return (__VkType)(uintptr_t) _obj; \
1570 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1571 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1573 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1574 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1575 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1576 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1577 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1579 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1580 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1581 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1582 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1583 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1584 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1585 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1586 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1587 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1588 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1589 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1590 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1591 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1592 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1593 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1594 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1595 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1596 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1597 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1598 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1599 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1601 #endif /* RADV_PRIVATE_H */