src/amd/vulkan/radv_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_PRIVATE_H
  29 #define RADV_PRIVATE_H
  30
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <stdbool.h>
  34 #include <pthread.h>
  35 #include <assert.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <valgrind.h>
  40 #include <memcheck.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x)
  44 #endif
  45
  46 #include <amdgpu.h>
  47 #include "compiler/shader_enums.h"
  48 #include "util/macros.h"
  49 #include "util/list.h"
  50 #include "util/vk_alloc.h"
  51 #include "main/macros.h"
  52
  53 #include "radv_radeon_winsys.h"
  54 #include "ac_binary.h"
  55 #include "ac_nir_to_llvm.h"
  56 #include "radv_descriptor_set.h"
  57
  58 #include <llvm-c/TargetMachine.h>
  59
  60 /* Pre-declarations needed for WSI entrypoints */
  61 struct wl_surface;
  62 struct wl_display;
  63 typedef struct xcb_connection_t xcb_connection_t;
  64 typedef uint32_t xcb_visualid_t;
  65 typedef uint32_t xcb_window_t;
  66
  67 #include <vulkan/vulkan.h>
  68 #include <vulkan/vulkan_intel.h>
  69 #include <vulkan/vk_icd.h>
  70
  71 #include "radv_entrypoints.h"
  72
  73 #include "wsi_common.h"
  74
  75 #define MAX_VBS         32
  76 #define MAX_VERTEX_ATTRIBS 32
  77 #define MAX_RTS          8
  78 #define MAX_VIEWPORTS   16
  79 #define MAX_SCISSORS    16
  80 #define MAX_PUSH_CONSTANTS_SIZE 128
  81 #define MAX_DYNAMIC_BUFFERS 16
  82 #define MAX_IMAGES 8
  83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
  84 #define NUM_META_FS_KEYS 11
  85
  86 #define NUM_DEPTH_CLEAR_PIPELINES 3
  87
  88 enum radv_mem_heap {
  89         RADV_MEM_HEAP_VRAM,
  90         RADV_MEM_HEAP_VRAM_CPU_ACCESS,
  91         RADV_MEM_HEAP_GTT,
  92         RADV_MEM_HEAP_COUNT
  93 };
  94
  95 enum radv_mem_type {
  96         RADV_MEM_TYPE_VRAM,
  97         RADV_MEM_TYPE_GTT_WRITE_COMBINE,
  98         RADV_MEM_TYPE_VRAM_CPU_ACCESS,
  99         RADV_MEM_TYPE_GTT_CACHED,
 100         RADV_MEM_TYPE_COUNT
 101 };
 102
 103 #define radv_noreturn __attribute__((__noreturn__))
 104 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 105
 106 static inline uint32_t
 107 align_u32(uint32_t v, uint32_t a)
 108 {
 109         assert(a != 0 && a == (a & -a));
 110         return (v + a - 1) & ~(a - 1);
 111 }
 112
 113 static inline uint32_t
 114 align_u32_npot(uint32_t v, uint32_t a)
 115 {
 116         return (v + a - 1) / a * a;
 117 }
 118
 119 static inline uint64_t
 120 align_u64(uint64_t v, uint64_t a)
 121 {
 122         assert(a != 0 && a == (a & -a));
 123         return (v + a - 1) & ~(a - 1);
 124 }
 125
 126 static inline int32_t
 127 align_i32(int32_t v, int32_t a)
 128 {
 129         assert(a != 0 && a == (a & -a));
 130         return (v + a - 1) & ~(a - 1);
 131 }
 132
 133 /** Alignment must be a power of 2. */
 134 static inline bool
 135 radv_is_aligned(uintmax_t n, uintmax_t a)
 136 {
 137         assert(a == (a & -a));
 138         return (n & (a - 1)) == 0;
 139 }
 140
 141 static inline uint32_t
 142 round_up_u32(uint32_t v, uint32_t a)
 143 {
 144         return (v + a - 1) / a;
 145 }
 146
 147 static inline uint64_t
 148 round_up_u64(uint64_t v, uint64_t a)
 149 {
 150         return (v + a - 1) / a;
 151 }
 152
 153 static inline uint32_t
 154 radv_minify(uint32_t n, uint32_t levels)
 155 {
 156         if (unlikely(n == 0))
 157                 return 0;
 158         else
 159                 return MAX2(n >> levels, 1);
 160 }
 161 static inline float
 162 radv_clamp_f(float f, float min, float max)
 163 {
 164         assert(min < max);
 165
 166         if (f > max)
 167                 return max;
 168         else if (f < min)
 169                 return min;
 170         else
 171                 return f;
 172 }
 173
 174 static inline bool
 175 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
 176 {
 177         if (*inout_mask & clear_mask) {
 178                 *inout_mask &= ~clear_mask;
 179                 return true;
 180         } else {
 181                 return false;
 182         }
 183 }
 184
 185 #define for_each_bit(b, dword)                          \
 186         for (uint32_t __dword = (dword);                \
 187              (b) = __builtin_ffs(__dword) - 1, __dword; \
 188              __dword &= ~(1 << (b)))
 189
 190 #define typed_memcpy(dest, src, count) ({                               \
 191                         STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
 192                         memcpy((dest), (src), (count) * sizeof(*(src))); \
 193                 })
 194
 195 #define zero(x) (memset(&(x), 0, sizeof(x)))
 196
 197 /* Whenever we generate an error, pass it through this function. Useful for
 198  * debugging, where we can break on it. Only call at error site, not when
 199  * propagating errors. Might be useful to plug in a stack trace here.
 200  */
 201
 202 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
 203
 204 #ifdef DEBUG
 205 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
 206 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
 207 #else
 208 #define vk_error(error) error
 209 #define vk_errorf(error, format, ...) error
 210 #endif
 211
 212 void __radv_finishme(const char *file, int line, const char *format, ...)
 213         radv_printflike(3, 4);
 214 void radv_loge(const char *format, ...) radv_printflike(1, 2);
 215 void radv_loge_v(const char *format, va_list va);
 216
 217 /**
 218  * Print a FINISHME message, including its source location.
 219  */
 220 #define radv_finishme(format, ...)                                      \
 221         do { \
 222                 static bool reported = false; \
 223                 if (!reported) { \
 224                         __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
 225                         reported = true; \
 226                 } \
 227         } while (0)
 228
 229 /* A non-fatal assert.  Useful for debugging. */
 230 #ifdef DEBUG
 231 #define radv_assert(x) ({                                               \
 232                         if (unlikely(!(x)))                             \
 233                                 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
 234                 })
 235 #else
 236 #define radv_assert(x)
 237 #endif
 238
 239 void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
 240 void radv_abortfv(const char *format, va_list va) radv_noreturn;
 241
 242 #define stub_return(v)                                  \
 243         do {                                            \
 244                 radv_finishme("stub %s", __func__);     \
 245                 return (v);                             \
 246         } while (0)
 247
 248 #define stub()                                          \
 249         do {                                            \
 250                 radv_finishme("stub %s", __func__);     \
 251                 return;                                 \
 252         } while (0)
 253
 254 void *radv_resolve_entrypoint(uint32_t index);
 255 void *radv_lookup_entrypoint(const char *name);
 256
 257 extern struct radv_dispatch_table dtable;
 258
 259 struct radv_physical_device {
 260         VK_LOADER_DATA                              _loader_data;
 261
 262         struct radv_instance *                       instance;
 263
 264         struct radeon_winsys *ws;
 265         struct radeon_info rad_info;
 266         uint32_t                                    chipset_id;
 267         char                                        path[20];
 268         const char *                                name;
 269         uint64_t                                    aperture_size;
 270         int                                         cmd_parser_version;
 271         uint32_t                    pci_vendor_id;
 272         uint32_t                    pci_device_id;
 273
 274         uint8_t                                     uuid[VK_UUID_SIZE];
 275
 276         struct wsi_device                       wsi_device;
 277 };
 278
 279 struct radv_instance {
 280         VK_LOADER_DATA                              _loader_data;
 281
 282         VkAllocationCallbacks                       alloc;
 283
 284         uint32_t                                    apiVersion;
 285         int                                         physicalDeviceCount;
 286         struct radv_physical_device                  physicalDevice;
 287 };
 288
 289 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
 290 void radv_finish_wsi(struct radv_physical_device *physical_device);
 291
 292 struct cache_entry;
 293
 294 struct radv_pipeline_cache {
 295         struct radv_device *                          device;
 296         pthread_mutex_t                              mutex;
 297
 298         uint32_t                                     total_size;
 299         uint32_t                                     table_size;
 300         uint32_t                                     kernel_count;
 301         struct cache_entry **                        hash_table;
 302         bool                                         modified;
 303
 304         VkAllocationCallbacks                        alloc;
 305 };
 306
 307 void
 308 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 309                          struct radv_device *device);
 310 void
 311 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
 312 void
 313 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 314                          const void *data, size_t size);
 315
 316 struct radv_shader_variant *
 317 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
 318                                                struct radv_pipeline_cache *cache,
 319                                                const unsigned char *sha1);
 320
 321 struct radv_shader_variant *
 322 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
 323                                   const unsigned char *sha1,
 324                                   struct radv_shader_variant *variant,
 325                                   const void *code, unsigned code_size);
 326
 327 void radv_shader_variant_destroy(struct radv_device *device,
 328                                  struct radv_shader_variant *variant);
 329
 330 struct radv_meta_state {
 331         VkAllocationCallbacks alloc;
 332
 333         struct radv_pipeline_cache cache;
 334
 335         /**
 336          * Use array element `i` for images with `2^i` samples.
 337          */
 338         struct {
 339                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 340                 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
 341
 342                 VkRenderPass depth_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
 343                 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 344                 VkRenderPass stencil_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
 345                 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 346                 VkRenderPass depthstencil_rp[NUM_DEPTH_CLEAR_PIPELINES];
 347                 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 348         } clear[1 + MAX_SAMPLES_LOG2];
 349
 350         struct {
 351                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 352
 353                 /** Pipeline that blits from a 1D image. */
 354                 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
 355
 356                 /** Pipeline that blits from a 2D image. */
 357                 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
 358
 359                 /** Pipeline that blits from a 3D image. */
 360                 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 361
 362                 VkRenderPass depth_only_rp;
 363                 VkPipeline depth_only_1d_pipeline;
 364                 VkPipeline depth_only_2d_pipeline;
 365                 VkPipeline depth_only_3d_pipeline;
 366
 367                 VkRenderPass stencil_only_rp;
 368                 VkPipeline stencil_only_1d_pipeline;
 369                 VkPipeline stencil_only_2d_pipeline;
 370                 VkPipeline stencil_only_3d_pipeline;
 371                 VkPipelineLayout                          pipeline_layout;
 372                 VkDescriptorSetLayout                     ds_layout;
 373         } blit;
 374
 375         struct {
 376                 VkRenderPass render_passes[NUM_META_FS_KEYS];
 377
 378                 VkPipelineLayout p_layouts[2];
 379                 VkDescriptorSetLayout ds_layouts[2];
 380                 VkPipeline pipelines[2][NUM_META_FS_KEYS];
 381
 382                 VkRenderPass depth_only_rp;
 383                 VkPipeline depth_only_pipeline[2];
 384
 385                 VkRenderPass stencil_only_rp;
 386                 VkPipeline stencil_only_pipeline[2];
 387         } blit2d;
 388
 389         struct {
 390                 VkPipelineLayout                          img_p_layout;
 391                 VkDescriptorSetLayout                     img_ds_layout;
 392                 VkPipeline pipeline;
 393         } itob;
 394         struct {
 395                 VkRenderPass render_pass;
 396                 VkPipelineLayout                          img_p_layout;
 397                 VkDescriptorSetLayout                     img_ds_layout;
 398                 VkPipeline pipeline;
 399         } btoi;
 400         struct {
 401                 VkPipelineLayout                          img_p_layout;
 402                 VkDescriptorSetLayout                     img_ds_layout;
 403                 VkPipeline pipeline;
 404         } itoi;
 405         struct {
 406                 VkPipelineLayout                          img_p_layout;
 407                 VkDescriptorSetLayout                     img_ds_layout;
 408                 VkPipeline pipeline;
 409         } cleari;
 410
 411         struct {
 412                 VkPipeline                                pipeline;
 413                 VkRenderPass                              pass;
 414         } resolve;
 415
 416         struct {
 417                 VkDescriptorSetLayout                     ds_layout;
 418                 VkPipelineLayout                          p_layout;
 419                 struct {
 420                         VkPipeline                                pipeline;
 421                         VkPipeline                                i_pipeline;
 422                 } rc[MAX_SAMPLES_LOG2];
 423         } resolve_compute;
 424
 425         struct {
 426                 VkPipeline                                decompress_pipeline;
 427                 VkPipeline                                resummarize_pipeline;
 428                 VkRenderPass                              pass;
 429         } depth_decomp;
 430
 431         struct {
 432                 VkPipeline                                cmask_eliminate_pipeline;
 433                 VkPipeline                                fmask_decompress_pipeline;
 434                 VkRenderPass                              pass;
 435         } fast_clear_flush;
 436
 437         struct {
 438                 VkPipelineLayout fill_p_layout;
 439                 VkPipelineLayout copy_p_layout;
 440                 VkDescriptorSetLayout fill_ds_layout;
 441                 VkDescriptorSetLayout copy_ds_layout;
 442                 VkPipeline fill_pipeline;
 443                 VkPipeline copy_pipeline;
 444         } buffer;
 445 };
 446
 447 /* queue types */
 448 #define RADV_QUEUE_GENERAL 0
 449 #define RADV_QUEUE_COMPUTE 1
 450 #define RADV_QUEUE_TRANSFER 2
 451
 452 #define RADV_MAX_QUEUE_FAMILIES 3
 453
 454 enum ring_type radv_queue_family_to_ring(int f);
 455
 456 struct radv_queue {
 457         VK_LOADER_DATA                              _loader_data;
 458         struct radv_device *                         device;
 459         int queue_family_index;
 460         int queue_idx;
 461 };
 462
 463 struct radv_device {
 464         VK_LOADER_DATA                              _loader_data;
 465
 466         VkAllocationCallbacks                       alloc;
 467
 468         struct radv_instance *                       instance;
 469         struct radeon_winsys *ws;
 470         struct radeon_winsys_ctx *hw_ctx;
 471
 472         struct radv_meta_state                       meta_state;
 473
 474         struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
 475         int queue_count[RADV_MAX_QUEUE_FAMILIES];
 476         struct radeon_winsys_cs *empty_cs;
 477
 478         bool allow_fast_clears;
 479         bool allow_dcc;
 480         bool shader_stats_dump;
 481
 482         /* MSAA sample locations.
 483          * The first index is the sample index.
 484          * The second index is the coordinate: X, Y. */
 485         float sample_locations_1x[1][2];
 486         float sample_locations_2x[2][2];
 487         float sample_locations_4x[4][2];
 488         float sample_locations_8x[8][2];
 489         float sample_locations_16x[16][2];
 490 };
 491
 492 struct radv_device_memory {
 493         struct radeon_winsys_bo                      *bo;
 494         uint32_t                                     type_index;
 495         VkDeviceSize                                 map_size;
 496         void *                                       map;
 497 };
 498
 499
 500 struct radv_descriptor_range {
 501         uint64_t va;
 502         uint32_t size;
 503 };
 504
 505 struct radv_descriptor_set {
 506         const struct radv_descriptor_set_layout *layout;
 507         struct list_head descriptor_pool;
 508         uint32_t size;
 509
 510         struct radv_buffer_view *buffer_views;
 511         struct radeon_winsys_bo *bo;
 512         uint64_t va;
 513         uint32_t *mapped_ptr;
 514         struct radv_descriptor_range *dynamic_descriptors;
 515         struct radeon_winsys_bo *descriptors[0];
 516 };
 517
 518 struct radv_descriptor_pool_free_node {
 519         int next;
 520         uint32_t offset;
 521         uint32_t size;
 522 };
 523
 524 struct radv_descriptor_pool {
 525         struct list_head descriptor_sets;
 526
 527         struct radeon_winsys_bo *bo;
 528         uint8_t *mapped_ptr;
 529         uint64_t current_offset;
 530         uint64_t size;
 531
 532         int free_list;
 533         int full_list;
 534         uint32_t max_sets;
 535         struct radv_descriptor_pool_free_node free_nodes[];
 536 };
 537
 538 struct radv_buffer {
 539         struct radv_device *                          device;
 540         VkDeviceSize                                 size;
 541
 542         VkBufferUsageFlags                           usage;
 543
 544         /* Set when bound */
 545         struct radeon_winsys_bo *                      bo;
 546         VkDeviceSize                                 offset;
 547 };
 548
 549
 550 enum radv_cmd_dirty_bits {
 551         RADV_CMD_DIRTY_DYNAMIC_VIEWPORT                  = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
 552         RADV_CMD_DIRTY_DYNAMIC_SCISSOR                   = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
 553         RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH                = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
 554         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS                = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
 555         RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS           = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
 556         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS              = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
 557         RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
 558         RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
 559         RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
 560         RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 9) - 1,
 561         RADV_CMD_DIRTY_PIPELINE                          = 1 << 9,
 562         RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 10,
 563         RADV_CMD_DIRTY_RENDER_TARGETS                    = 1 << 11,
 564 };
 565 typedef uint32_t radv_cmd_dirty_mask_t;
 566
 567 enum radv_cmd_flush_bits {
 568         RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
 569         /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
 570         RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
 571         /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
 572         RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
 573         /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
 574         RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
 575         /* Framebuffer caches */
 576         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
 577         RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
 578         RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
 579         RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
 580         /* Engine synchronization. */
 581         RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
 582         RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
 583         RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
 584         RADV_CMD_FLAG_VGT_FLUSH        = 1 << 11,
 585
 586         RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 587                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
 588                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 589                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
 590 };
 591
 592 struct radv_vertex_binding {
 593         struct radv_buffer *                          buffer;
 594         VkDeviceSize                                 offset;
 595 };
 596
 597 struct radv_dynamic_state {
 598         struct {
 599                 uint32_t                                  count;
 600                 VkViewport                                viewports[MAX_VIEWPORTS];
 601         } viewport;
 602
 603         struct {
 604                 uint32_t                                  count;
 605                 VkRect2D                                  scissors[MAX_SCISSORS];
 606         } scissor;
 607
 608         float                                        line_width;
 609
 610         struct {
 611                 float                                     bias;
 612                 float                                     clamp;
 613                 float                                     slope;
 614         } depth_bias;
 615
 616         float                                        blend_constants[4];
 617
 618         struct {
 619                 float                                     min;
 620                 float                                     max;
 621         } depth_bounds;
 622
 623         struct {
 624                 uint32_t                                  front;
 625                 uint32_t                                  back;
 626         } stencil_compare_mask;
 627
 628         struct {
 629                 uint32_t                                  front;
 630                 uint32_t                                  back;
 631         } stencil_write_mask;
 632
 633         struct {
 634                 uint32_t                                  front;
 635                 uint32_t                                  back;
 636         } stencil_reference;
 637 };
 638
 639 extern const struct radv_dynamic_state default_dynamic_state;
 640
 641 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
 642                              const struct radv_dynamic_state *src,
 643                              uint32_t copy_mask);
 644 /**
 645  * Attachment state when recording a renderpass instance.
 646  *
 647  * The clear value is valid only if there exists a pending clear.
 648  */
 649 struct radv_attachment_state {
 650         VkImageAspectFlags                           pending_clear_aspects;
 651         VkClearValue                                 clear_value;
 652         VkImageLayout                                current_layout;
 653 };
 654
 655 struct radv_cmd_state {
 656         uint32_t                                      vb_dirty;
 657         bool                                          vertex_descriptors_dirty;
 658         radv_cmd_dirty_mask_t                         dirty;
 659
 660         struct radv_pipeline *                        pipeline;
 661         struct radv_pipeline *                        emitted_pipeline;
 662         struct radv_pipeline *                        compute_pipeline;
 663         struct radv_pipeline *                        emitted_compute_pipeline;
 664         struct radv_framebuffer *                     framebuffer;
 665         struct radv_render_pass *                     pass;
 666         const struct radv_subpass *                         subpass;
 667         struct radv_dynamic_state                     dynamic;
 668         struct radv_vertex_binding                    vertex_bindings[MAX_VBS];
 669         struct radv_descriptor_set *                  descriptors[MAX_SETS];
 670         struct radv_attachment_state *                attachments;
 671         VkRect2D                                     render_area;
 672         struct radv_buffer *                         index_buffer;
 673         uint32_t                                     index_type;
 674         uint32_t                                     index_offset;
 675         uint32_t                                     last_primitive_reset_index;
 676         enum radv_cmd_flush_bits                     flush_bits;
 677         unsigned                                     active_occlusion_queries;
 678         float                                        offset_scale;
 679         uint32_t                                      descriptors_dirty;
 680 };
 681
 682 struct radv_cmd_pool {
 683         VkAllocationCallbacks                        alloc;
 684         struct list_head                             cmd_buffers;
 685         uint32_t queue_family_index;
 686 };
 687
 688 struct radv_cmd_buffer_upload {
 689         uint8_t *map;
 690         unsigned offset;
 691         uint64_t size;
 692         struct radeon_winsys_bo *upload_bo;
 693         struct list_head list;
 694 };
 695
 696 struct radv_cmd_buffer {
 697         VK_LOADER_DATA                               _loader_data;
 698
 699         struct radv_device *                          device;
 700
 701         struct radv_cmd_pool *                        pool;
 702         struct list_head                             pool_link;
 703
 704         VkCommandBufferUsageFlags                    usage_flags;
 705         VkCommandBufferLevel                         level;
 706         struct radeon_winsys_cs *cs;
 707         struct radv_cmd_state state;
 708         uint32_t queue_family_index;
 709
 710         uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
 711         uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
 712         VkShaderStageFlags push_constant_stages;
 713
 714         struct radv_cmd_buffer_upload upload;
 715
 716         bool record_fail;
 717 };
 718
 719 struct radv_image;
 720
 721 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
 722
 723 void si_init_compute(struct radv_physical_device *physical_device,
 724                      struct radv_cmd_buffer *cmd_buffer);
 725 void si_init_config(struct radv_physical_device *physical_device,
 726                     struct radv_cmd_buffer *cmd_buffer);
 727 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
 728                        int count, const VkViewport *viewports);
 729 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
 730                        int count, const VkRect2D *scissors);
 731 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
 732 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
 733 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
 734                            uint64_t src_va, uint64_t dest_va,
 735                            uint64_t size);
 736 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 737                             uint64_t size, unsigned value);
 738 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
 739 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 740                               struct radv_descriptor_set *set,
 741                               unsigned idx);
 742 bool
 743 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 744                              unsigned size,
 745                              unsigned alignment,
 746                              unsigned *out_offset,
 747                              void **ptr);
 748 void
 749 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
 750                             const struct radv_subpass *subpass,
 751                             bool transitions);
 752 bool
 753 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 754                             unsigned size, unsigned alignmnet,
 755                             const void *data, unsigned *out_offset);
 756 void
 757 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
 758 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
 759 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
 760 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 761 unsigned radv_cayman_get_maxdist(int log_samples);
 762 void radv_device_init_msaa(struct radv_device *device);
 763 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 764                                struct radv_image *image,
 765                                VkClearDepthStencilValue ds_clear_value,
 766                                VkImageAspectFlags aspects);
 767 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 768                                struct radv_image *image,
 769                                int idx,
 770                                uint32_t color_values[2]);
 771 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
 772                       struct radeon_winsys_bo *bo,
 773                       uint64_t offset, uint64_t size, uint32_t value);
 774
 775 /*
 776  * Takes x,y,z as exact numbers of invocations, instead of blocks.
 777  *
 778  * Limitations: Can't call normal dispatch functions without binding or rebinding
 779  *              the compute pipeline.
 780  */
 781 void radv_unaligned_dispatch(
 782         struct radv_cmd_buffer                      *cmd_buffer,
 783         uint32_t                                    x,
 784         uint32_t                                    y,
 785         uint32_t                                    z);
 786
 787 struct radv_event {
 788         struct radeon_winsys_bo *bo;
 789         uint64_t *map;
 790 };
 791
 792 struct nir_shader;
 793
 794 struct radv_shader_module {
 795         struct nir_shader *                          nir;
 796         unsigned char                                sha1[20];
 797         uint32_t                                     size;
 798         char                                         data[0];
 799 };
 800
 801 union ac_shader_variant_key;
 802
 803 void
 804 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
 805                  const char *entrypoint,
 806                  const VkSpecializationInfo *spec_info,
 807                  const struct radv_pipeline_layout *layout,
 808                  const union ac_shader_variant_key *key);
 809
 810 static inline gl_shader_stage
 811 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
 812 {
 813         assert(__builtin_popcount(vk_stage) == 1);
 814         return ffs(vk_stage) - 1;
 815 }
 816
 817 static inline VkShaderStageFlagBits
 818 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
 819 {
 820         return (1 << mesa_stage);
 821 }
 822
 823 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
 824
 825 #define radv_foreach_stage(stage, stage_bits)                           \
 826         for (gl_shader_stage stage,                                     \
 827                      __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
 828              stage = __builtin_ffs(__tmp) - 1, __tmp;                   \
 829              __tmp &= ~(1 << (stage)))
 830
 831 struct radv_shader_variant {
 832         uint32_t ref_count;
 833
 834         struct radeon_winsys_bo *bo;
 835         struct ac_shader_config config;
 836         struct ac_shader_variant_info info;
 837         unsigned rsrc1;
 838         unsigned rsrc2;
 839         uint32_t code_size;
 840 };
 841
 842 struct radv_depth_stencil_state {
 843         uint32_t db_depth_control;
 844         uint32_t db_stencil_control;
 845         uint32_t db_render_control;
 846         uint32_t db_render_override2;
 847 };
 848
 849 struct radv_blend_state {
 850         uint32_t cb_color_control;
 851         uint32_t cb_target_mask;
 852         uint32_t sx_mrt0_blend_opt[8];
 853         uint32_t cb_blend_control[8];
 854
 855         uint32_t spi_shader_col_format;
 856         uint32_t cb_shader_mask;
 857         uint32_t db_alpha_to_mask;
 858 };
 859
 860 unsigned radv_format_meta_fs_key(VkFormat format);
 861
 862 struct radv_raster_state {
 863         uint32_t pa_cl_clip_cntl;
 864         uint32_t pa_cl_vs_out_cntl;
 865         uint32_t spi_interp_control;
 866         uint32_t pa_su_point_size;
 867         uint32_t pa_su_point_minmax;
 868         uint32_t pa_su_line_cntl;
 869         uint32_t pa_su_vtx_cntl;
 870         uint32_t pa_su_sc_mode_cntl;
 871 };
 872
 873 struct radv_multisample_state {
 874         uint32_t db_eqaa;
 875         uint32_t pa_sc_line_cntl;
 876         uint32_t pa_sc_mode_cntl_0;
 877         uint32_t pa_sc_mode_cntl_1;
 878         uint32_t pa_sc_aa_config;
 879         uint32_t pa_sc_aa_mask[2];
 880         unsigned num_samples;
 881 };
 882
 883 struct radv_pipeline {
 884         struct radv_device *                          device;
 885         uint32_t                                     dynamic_state_mask;
 886         struct radv_dynamic_state                     dynamic_state;
 887
 888         struct radv_pipeline_layout *                 layout;
 889
 890         bool                                         needs_data_cache;
 891
 892         struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
 893         VkShaderStageFlags                           active_stages;
 894
 895         uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
 896         uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
 897         uint32_t va_binding[MAX_VERTEX_ATTRIBS];
 898         uint32_t va_offset[MAX_VERTEX_ATTRIBS];
 899         uint32_t num_vertex_attribs;
 900         uint32_t                                     binding_stride[MAX_VBS];
 901
 902         union {
 903                 struct {
 904                         struct radv_blend_state blend;
 905                         struct radv_depth_stencil_state ds;
 906                         struct radv_raster_state raster;
 907                         struct radv_multisample_state ms;
 908                         unsigned prim;
 909                         unsigned gs_out;
 910                         bool prim_restart_enable;
 911                 } graphics;
 912         };
 913 };
 914
 915 struct radv_graphics_pipeline_create_info {
 916         bool use_rectlist;
 917         bool db_depth_clear;
 918         bool db_stencil_clear;
 919         bool db_depth_disable_expclear;
 920         bool db_stencil_disable_expclear;
 921         bool db_flush_depth_inplace;
 922         bool db_flush_stencil_inplace;
 923         bool db_resummarize;
 924         uint32_t custom_blend_mode;
 925 };
 926
 927 VkResult
 928 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
 929                    struct radv_pipeline_cache *cache,
 930                    const VkGraphicsPipelineCreateInfo *pCreateInfo,
 931                    const struct radv_graphics_pipeline_create_info *extra,
 932                    const VkAllocationCallbacks *alloc);
 933
 934 VkResult
 935 radv_graphics_pipeline_create(VkDevice device,
 936                               VkPipelineCache cache,
 937                               const VkGraphicsPipelineCreateInfo *pCreateInfo,
 938                               const struct radv_graphics_pipeline_create_info *extra,
 939                               const VkAllocationCallbacks *alloc,
 940                               VkPipeline *pPipeline);
 941
 942 struct vk_format_description;
 943 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
 944                                           int first_non_void);
 945 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
 946                                          int first_non_void);
 947 uint32_t radv_translate_colorformat(VkFormat format);
 948 uint32_t radv_translate_color_numformat(VkFormat format,
 949                                         const struct vk_format_description *desc,
 950                                         int first_non_void);
 951 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
 952 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
 953 uint32_t radv_translate_dbformat(VkFormat format);
 954 uint32_t radv_translate_tex_dataformat(VkFormat format,
 955                                        const struct vk_format_description *desc,
 956                                        int first_non_void);
 957 uint32_t radv_translate_tex_numformat(VkFormat format,
 958                                       const struct vk_format_description *desc,
 959                                       int first_non_void);
 960 bool radv_format_pack_clear_color(VkFormat format,
 961                                   uint32_t clear_vals[2],
 962                                   VkClearColorValue *value);
 963 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
 964
 965 struct radv_fmask_info {
 966         uint64_t offset;
 967         uint64_t size;
 968         unsigned alignment;
 969         unsigned pitch_in_pixels;
 970         unsigned bank_height;
 971         unsigned slice_tile_max;
 972         unsigned tile_mode_index;
 973 };
 974
 975 struct radv_cmask_info {
 976         uint64_t offset;
 977         uint64_t size;
 978         unsigned alignment;
 979         unsigned slice_tile_max;
 980         unsigned base_address_reg;
 981 };
 982
 983 struct r600_htile_info {
 984         uint64_t offset;
 985         uint64_t size;
 986         unsigned pitch;
 987         unsigned height;
 988         unsigned xalign;
 989         unsigned yalign;
 990 };
 991
 992 struct radv_image {
 993         VkImageType type;
 994         /* The original VkFormat provided by the client.  This may not match any
 995          * of the actual surface formats.
 996          */
 997         VkFormat vk_format;
 998         VkImageAspectFlags aspects;
 999         VkExtent3D extent;
1000         uint32_t levels;
1001         uint32_t array_size;
1002         uint32_t samples; /**< VkImageCreateInfo::samples */
1003         VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1004         VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1005
1006         VkDeviceSize size;
1007         uint32_t alignment;
1008
1009         /* Set when bound */
1010         struct radeon_winsys_bo *bo;
1011         VkDeviceSize offset;
1012         uint32_t dcc_offset;
1013         struct radeon_surf surface;
1014
1015         struct radv_fmask_info fmask;
1016         struct radv_cmask_info cmask;
1017         uint32_t clear_value_offset;
1018
1019         /* Depth buffer compression and fast clear. */
1020         struct r600_htile_info htile;
1021 };
1022
1023 bool radv_layout_has_htile(const struct radv_image *image,
1024                            VkImageLayout layout);
1025 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1026                                      VkImageLayout layout);
1027 bool radv_layout_can_expclear(const struct radv_image *image,
1028                               VkImageLayout layout);
1029 bool radv_layout_has_cmask(const struct radv_image *image,
1030                            VkImageLayout layout);
1031 static inline uint32_t
1032 radv_get_layerCount(const struct radv_image *image,
1033                     const VkImageSubresourceRange *range)
1034 {
1035         return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1036                 image->array_size - range->baseArrayLayer : range->layerCount;
1037 }
1038
1039 static inline uint32_t
1040 radv_get_levelCount(const struct radv_image *image,
1041                     const VkImageSubresourceRange *range)
1042 {
1043         return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1044                 image->levels - range->baseMipLevel : range->levelCount;
1045 }
1046
1047 struct radeon_bo_metadata;
1048 void
1049 radv_init_metadata(struct radv_device *device,
1050                    struct radv_image *image,
1051                    struct radeon_bo_metadata *metadata);
1052
1053 struct radv_image_view {
1054         struct radv_image *image; /**< VkImageViewCreateInfo::image */
1055         struct radeon_winsys_bo *bo;
1056
1057         VkImageViewType type;
1058         VkImageAspectFlags aspect_mask;
1059         VkFormat vk_format;
1060         uint32_t base_layer;
1061         uint32_t layer_count;
1062         uint32_t base_mip;
1063         VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1064
1065         uint32_t descriptor[8];
1066         uint32_t fmask_descriptor[8];
1067 };
1068
1069 struct radv_image_create_info {
1070         const VkImageCreateInfo *vk_info;
1071         uint32_t stride;
1072         bool scanout;
1073 };
1074
1075 VkResult radv_image_create(VkDevice _device,
1076                            const struct radv_image_create_info *info,
1077                            const VkAllocationCallbacks* alloc,
1078                            VkImage *pImage);
1079
1080 void radv_image_view_init(struct radv_image_view *view,
1081                           struct radv_device *device,
1082                           const VkImageViewCreateInfo* pCreateInfo,
1083                           struct radv_cmd_buffer *cmd_buffer,
1084                           VkImageUsageFlags usage_mask);
1085 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1086                                             struct radv_image *image, uint32_t micro_tile_mode);
1087 struct radv_buffer_view {
1088         struct radeon_winsys_bo *bo;
1089         VkFormat vk_format;
1090         uint64_t range; /**< VkBufferViewCreateInfo::range */
1091         uint32_t state[4];
1092 };
1093 void radv_buffer_view_init(struct radv_buffer_view *view,
1094                            struct radv_device *device,
1095                            const VkBufferViewCreateInfo* pCreateInfo,
1096                            struct radv_cmd_buffer *cmd_buffer);
1097
1098 static inline struct VkExtent3D
1099 radv_sanitize_image_extent(const VkImageType imageType,
1100                            const struct VkExtent3D imageExtent)
1101 {
1102         switch (imageType) {
1103         case VK_IMAGE_TYPE_1D:
1104                 return (VkExtent3D) { imageExtent.width, 1, 1 };
1105         case VK_IMAGE_TYPE_2D:
1106                 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1107         case VK_IMAGE_TYPE_3D:
1108                 return imageExtent;
1109         default:
1110                 unreachable("invalid image type");
1111         }
1112 }
1113
1114 static inline struct VkOffset3D
1115 radv_sanitize_image_offset(const VkImageType imageType,
1116                            const struct VkOffset3D imageOffset)
1117 {
1118         switch (imageType) {
1119         case VK_IMAGE_TYPE_1D:
1120                 return (VkOffset3D) { imageOffset.x, 0, 0 };
1121         case VK_IMAGE_TYPE_2D:
1122                 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1123         case VK_IMAGE_TYPE_3D:
1124                 return imageOffset;
1125         default:
1126                 unreachable("invalid image type");
1127         }
1128 }
1129
1130 struct radv_sampler {
1131         uint32_t state[4];
1132 };
1133
1134 struct radv_color_buffer_info {
1135         uint32_t cb_color_base;
1136         uint32_t cb_color_pitch;
1137         uint32_t cb_color_slice;
1138         uint32_t cb_color_view;
1139         uint32_t cb_color_info;
1140         uint32_t cb_color_attrib;
1141         uint32_t cb_dcc_control;
1142         uint32_t cb_color_cmask;
1143         uint32_t cb_color_cmask_slice;
1144         uint32_t cb_color_fmask;
1145         uint32_t cb_color_fmask_slice;
1146         uint32_t cb_clear_value0;
1147         uint32_t cb_clear_value1;
1148         uint32_t cb_dcc_base;
1149         uint32_t micro_tile_mode;
1150 };
1151
1152 struct radv_ds_buffer_info {
1153         uint32_t db_depth_info;
1154         uint32_t db_z_info;
1155         uint32_t db_stencil_info;
1156         uint32_t db_z_read_base;
1157         uint32_t db_stencil_read_base;
1158         uint32_t db_z_write_base;
1159         uint32_t db_stencil_write_base;
1160         uint32_t db_depth_view;
1161         uint32_t db_depth_size;
1162         uint32_t db_depth_slice;
1163         uint32_t db_htile_surface;
1164         uint32_t db_htile_data_base;
1165         uint32_t pa_su_poly_offset_db_fmt_cntl;
1166         float offset_scale;
1167 };
1168
1169 struct radv_attachment_info {
1170         union {
1171                 struct radv_color_buffer_info cb;
1172                 struct radv_ds_buffer_info ds;
1173         };
1174         struct radv_image_view *attachment;
1175 };
1176
1177 struct radv_framebuffer {
1178         uint32_t                                     width;
1179         uint32_t                                     height;
1180         uint32_t                                     layers;
1181
1182         uint32_t                                     attachment_count;
1183         struct radv_attachment_info                  attachments[0];
1184 };
1185
1186 struct radv_subpass_barrier {
1187         VkPipelineStageFlags src_stage_mask;
1188         VkAccessFlags        src_access_mask;
1189         VkAccessFlags        dst_access_mask;
1190 };
1191
1192 struct radv_subpass {
1193         uint32_t                                     input_count;
1194         VkAttachmentReference *                      input_attachments;
1195         uint32_t                                     color_count;
1196         VkAttachmentReference *                      color_attachments;
1197         VkAttachmentReference *                      resolve_attachments;
1198         VkAttachmentReference                        depth_stencil_attachment;
1199
1200         /** Subpass has at least one resolve attachment */
1201         bool                                         has_resolve;
1202
1203         struct radv_subpass_barrier                  start_barrier;
1204 };
1205
1206 struct radv_render_pass_attachment {
1207         VkFormat                                     format;
1208         uint32_t                                     samples;
1209         VkAttachmentLoadOp                           load_op;
1210         VkAttachmentLoadOp                           stencil_load_op;
1211         VkImageLayout                                initial_layout;
1212         VkImageLayout                                final_layout;
1213 };
1214
1215 struct radv_render_pass {
1216         uint32_t                                     attachment_count;
1217         uint32_t                                     subpass_count;
1218         VkAttachmentReference *                      subpass_attachments;
1219         struct radv_render_pass_attachment *         attachments;
1220         struct radv_subpass_barrier                  end_barrier;
1221         struct radv_subpass                          subpasses[0];
1222 };
1223
1224 VkResult radv_device_init_meta(struct radv_device *device);
1225 void radv_device_finish_meta(struct radv_device *device);
1226
1227 struct radv_query_pool {
1228         struct radeon_winsys_bo *bo;
1229         uint32_t stride;
1230         uint32_t availability_offset;
1231         char *ptr;
1232         VkQueryType type;
1233 };
1234
1235 VkResult
1236 radv_temp_descriptor_set_create(struct radv_device *device,
1237                                 struct radv_cmd_buffer *cmd_buffer,
1238                                 VkDescriptorSetLayout _layout,
1239                                 VkDescriptorSet *_set);
1240
1241 void
1242 radv_temp_descriptor_set_destroy(struct radv_device *device,
1243                                  VkDescriptorSet _set);
1244 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1245                            struct radv_image *image, uint32_t value);
1246 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1247                          struct radv_image *image, uint32_t value);
1248
1249 struct radv_fence {
1250         struct radeon_winsys_fence *fence;
1251         bool submitted;
1252         bool signalled;
1253 };
1254
1255 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)         \
1256                                                                 \
1257         static inline struct __radv_type *                      \
1258         __radv_type ## _from_handle(__VkType _handle)           \
1259         {                                                       \
1260                 return (struct __radv_type *) _handle;          \
1261         }                                                       \
1262                                                                 \
1263         static inline __VkType                                  \
1264         __radv_type ## _to_handle(struct __radv_type *_obj)     \
1265         {                                                       \
1266                 return (__VkType) _obj;                         \
1267         }
1268
1269 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType)         \
1270                                                                         \
1271         static inline struct __radv_type *                              \
1272         __radv_type ## _from_handle(__VkType _handle)                   \
1273         {                                                               \
1274                 return (struct __radv_type *)(uintptr_t) _handle;       \
1275         }                                                               \
1276                                                                         \
1277         static inline __VkType                                          \
1278         __radv_type ## _to_handle(struct __radv_type *_obj)             \
1279         {                                                               \
1280                 return (__VkType)(uintptr_t) _obj;                      \
1281         }
1282
1283 #define RADV_FROM_HANDLE(__radv_type, __name, __handle)                 \
1284         struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1285
1286 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1287 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1288 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1289 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1290 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1291
1292 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1293 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1294 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1295 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1296 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1297 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1298 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1299 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1300 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1301 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1302 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1303 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1304 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1305 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1306 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1307 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1308 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1309 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1310 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1311
1312 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType)                 \
1313                                                                         \
1314         static inline const __VkType *                                  \
1315         __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1316         {                                                               \
1317                 return (const __VkType *) __radv_obj;                   \
1318         }
1319
1320 #endif /* RADV_PRIVATE_H */