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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_IMAGES 8
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
84 #define NUM_META_FS_KEYS 11
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 enum radv_mem_heap {
89 RADV_MEM_HEAP_VRAM,
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
91 RADV_MEM_HEAP_GTT,
92 RADV_MEM_HEAP_COUNT
93 };
94
95 enum radv_mem_type {
96 RADV_MEM_TYPE_VRAM,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
99 RADV_MEM_TYPE_GTT_CACHED,
100 RADV_MEM_TYPE_COUNT
101 };
102
103 #define radv_noreturn __attribute__((__noreturn__))
104 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105
106 static inline uint32_t
107 align_u32(uint32_t v, uint32_t a)
108 {
109 assert(a != 0 && a == (a & -a));
110 return (v + a - 1) & ~(a - 1);
111 }
112
113 static inline uint32_t
114 align_u32_npot(uint32_t v, uint32_t a)
115 {
116 return (v + a - 1) / a * a;
117 }
118
119 static inline uint64_t
120 align_u64(uint64_t v, uint64_t a)
121 {
122 assert(a != 0 && a == (a & -a));
123 return (v + a - 1) & ~(a - 1);
124 }
125
126 static inline int32_t
127 align_i32(int32_t v, int32_t a)
128 {
129 assert(a != 0 && a == (a & -a));
130 return (v + a - 1) & ~(a - 1);
131 }
132
133 /** Alignment must be a power of 2. */
134 static inline bool
135 radv_is_aligned(uintmax_t n, uintmax_t a)
136 {
137 assert(a == (a & -a));
138 return (n & (a - 1)) == 0;
139 }
140
141 static inline uint32_t
142 round_up_u32(uint32_t v, uint32_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint64_t
148 round_up_u64(uint64_t v, uint64_t a)
149 {
150 return (v + a - 1) / a;
151 }
152
153 static inline uint32_t
154 radv_minify(uint32_t n, uint32_t levels)
155 {
156 if (unlikely(n == 0))
157 return 0;
158 else
159 return MAX2(n >> levels, 1);
160 }
161 static inline float
162 radv_clamp_f(float f, float min, float max)
163 {
164 assert(min < max);
165
166 if (f > max)
167 return max;
168 else if (f < min)
169 return min;
170 else
171 return f;
172 }
173
174 static inline bool
175 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
176 {
177 if (*inout_mask & clear_mask) {
178 *inout_mask &= ~clear_mask;
179 return true;
180 } else {
181 return false;
182 }
183 }
184
185 #define for_each_bit(b, dword) \
186 for (uint32_t __dword = (dword); \
187 (b) = __builtin_ffs(__dword) - 1, __dword; \
188 __dword &= ~(1 << (b)))
189
190 #define typed_memcpy(dest, src, count) ({ \
191 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
192 memcpy((dest), (src), (count) * sizeof(*(src))); \
193 })
194
195 #define zero(x) (memset(&(x), 0, sizeof(x)))
196
197 /* Whenever we generate an error, pass it through this function. Useful for
198 * debugging, where we can break on it. Only call at error site, not when
199 * propagating errors. Might be useful to plug in a stack trace here.
200 */
201
202 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
203
204 #ifdef DEBUG
205 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
206 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
207 #else
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #endif
211
212 void __radv_finishme(const char *file, int line, const char *format, ...)
213 radv_printflike(3, 4);
214 void radv_loge(const char *format, ...) radv_printflike(1, 2);
215 void radv_loge_v(const char *format, va_list va);
216
217 /**
218 * Print a FINISHME message, including its source location.
219 */
220 #define radv_finishme(format, ...) \
221 do { \
222 static bool reported = false; \
223 if (!reported) { \
224 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
225 reported = true; \
226 } \
227 } while (0)
228
229 /* A non-fatal assert. Useful for debugging. */
230 #ifdef DEBUG
231 #define radv_assert(x) ({ \
232 if (unlikely(!(x))) \
233 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
234 })
235 #else
236 #define radv_assert(x)
237 #endif
238
239 void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
240 void radv_abortfv(const char *format, va_list va) radv_noreturn;
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_resolve_entrypoint(uint32_t index);
255 void *radv_lookup_entrypoint(const char *name);
256
257 extern struct radv_dispatch_table dtable;
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 uint32_t chipset_id;
267 char path[20];
268 const char * name;
269 uint64_t aperture_size;
270 int cmd_parser_version;
271 uint32_t pci_vendor_id;
272 uint32_t pci_device_id;
273
274 uint8_t uuid[VK_UUID_SIZE];
275
276 struct wsi_device wsi_device;
277 };
278
279 struct radv_instance {
280 VK_LOADER_DATA _loader_data;
281
282 VkAllocationCallbacks alloc;
283
284 uint32_t apiVersion;
285 int physicalDeviceCount;
286 struct radv_physical_device physicalDevice;
287 };
288
289 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
290 void radv_finish_wsi(struct radv_physical_device *physical_device);
291
292 struct cache_entry;
293
294 struct radv_pipeline_cache {
295 struct radv_device * device;
296 pthread_mutex_t mutex;
297
298 uint32_t total_size;
299 uint32_t table_size;
300 uint32_t kernel_count;
301 struct cache_entry ** hash_table;
302 bool modified;
303
304 VkAllocationCallbacks alloc;
305 };
306
307 void
308 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
309 struct radv_device *device);
310 void
311 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
312 void
313 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
314 const void *data, size_t size);
315
316 struct radv_shader_variant *
317 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
318 struct radv_pipeline_cache *cache,
319 const unsigned char *sha1);
320
321 struct radv_shader_variant *
322 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
323 const unsigned char *sha1,
324 struct radv_shader_variant *variant,
325 const void *code, unsigned code_size);
326
327 void radv_shader_variant_destroy(struct radv_device *device,
328 struct radv_shader_variant *variant);
329
330 struct radv_meta_state {
331 VkAllocationCallbacks alloc;
332
333 struct radv_pipeline_cache cache;
334
335 /**
336 * Use array element `i` for images with `2^i` samples.
337 */
338 struct {
339 VkRenderPass render_pass[NUM_META_FS_KEYS];
340 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
341
342 VkRenderPass depth_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
343 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
344 VkRenderPass stencil_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
345 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
346 VkRenderPass depthstencil_rp[NUM_DEPTH_CLEAR_PIPELINES];
347 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
348 } clear[1 + MAX_SAMPLES_LOG2];
349
350 struct {
351 VkRenderPass render_pass[NUM_META_FS_KEYS];
352
353 /** Pipeline that blits from a 1D image. */
354 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
355
356 /** Pipeline that blits from a 2D image. */
357 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
358
359 /** Pipeline that blits from a 3D image. */
360 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
361
362 VkRenderPass depth_only_rp;
363 VkPipeline depth_only_1d_pipeline;
364 VkPipeline depth_only_2d_pipeline;
365 VkPipeline depth_only_3d_pipeline;
366
367 VkRenderPass stencil_only_rp;
368 VkPipeline stencil_only_1d_pipeline;
369 VkPipeline stencil_only_2d_pipeline;
370 VkPipeline stencil_only_3d_pipeline;
371 VkPipelineLayout pipeline_layout;
372 VkDescriptorSetLayout ds_layout;
373 } blit;
374
375 struct {
376 VkRenderPass render_passes[NUM_META_FS_KEYS];
377
378 VkPipelineLayout p_layouts[2];
379 VkDescriptorSetLayout ds_layouts[2];
380 VkPipeline pipelines[2][NUM_META_FS_KEYS];
381
382 VkRenderPass depth_only_rp;
383 VkPipeline depth_only_pipeline[2];
384
385 VkRenderPass stencil_only_rp;
386 VkPipeline stencil_only_pipeline[2];
387 } blit2d;
388
389 struct {
390 VkPipelineLayout img_p_layout;
391 VkDescriptorSetLayout img_ds_layout;
392 VkPipeline pipeline;
393 } itob;
394 struct {
395 VkRenderPass render_pass;
396 VkPipelineLayout img_p_layout;
397 VkDescriptorSetLayout img_ds_layout;
398 VkPipeline pipeline;
399 } btoi;
400 struct {
401 VkPipelineLayout img_p_layout;
402 VkDescriptorSetLayout img_ds_layout;
403 VkPipeline pipeline;
404 } itoi;
405
406 struct {
407 VkPipeline pipeline;
408 VkRenderPass pass;
409 } resolve;
410
411 struct {
412 VkDescriptorSetLayout ds_layout;
413 VkPipelineLayout p_layout;
414 struct {
415 VkPipeline pipeline;
416 VkPipeline i_pipeline;
417 } rc[MAX_SAMPLES_LOG2];
418 } resolve_compute;
419
420 struct {
421 VkPipeline decompress_pipeline;
422 VkPipeline resummarize_pipeline;
423 VkRenderPass pass;
424 } depth_decomp;
425
426 struct {
427 VkPipeline cmask_eliminate_pipeline;
428 VkPipeline fmask_decompress_pipeline;
429 VkRenderPass pass;
430 } fast_clear_flush;
431
432 struct {
433 VkPipelineLayout fill_p_layout;
434 VkPipelineLayout copy_p_layout;
435 VkDescriptorSetLayout fill_ds_layout;
436 VkDescriptorSetLayout copy_ds_layout;
437 VkPipeline fill_pipeline;
438 VkPipeline copy_pipeline;
439 } buffer;
440 };
441
442 /* queue types */
443 #define RADV_QUEUE_GENERAL 0
444 #define RADV_QUEUE_COMPUTE 1
445 #define RADV_QUEUE_TRANSFER 2
446
447 #define RADV_MAX_QUEUE_FAMILIES 3
448
449 enum ring_type radv_queue_family_to_ring(int f);
450
451 struct radv_queue {
452 VK_LOADER_DATA _loader_data;
453 struct radv_device * device;
454 int queue_family_index;
455 int queue_idx;
456 };
457
458 struct radv_device {
459 VK_LOADER_DATA _loader_data;
460
461 VkAllocationCallbacks alloc;
462
463 struct radv_instance * instance;
464 struct radeon_winsys *ws;
465 struct radeon_winsys_ctx *hw_ctx;
466
467 struct radv_meta_state meta_state;
468
469 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
470 int queue_count[RADV_MAX_QUEUE_FAMILIES];
471 struct radeon_winsys_cs *empty_cs;
472
473 bool allow_fast_clears;
474 bool allow_dcc;
475 bool shader_stats_dump;
476
477 /* MSAA sample locations.
478 * The first index is the sample index.
479 * The second index is the coordinate: X, Y. */
480 float sample_locations_1x[1][2];
481 float sample_locations_2x[2][2];
482 float sample_locations_4x[4][2];
483 float sample_locations_8x[8][2];
484 float sample_locations_16x[16][2];
485 };
486
487 struct radv_device_memory {
488 struct radeon_winsys_bo *bo;
489 uint32_t type_index;
490 VkDeviceSize map_size;
491 void * map;
492 };
493
494
495 struct radv_descriptor_range {
496 uint64_t va;
497 uint32_t size;
498 };
499
500 struct radv_descriptor_set {
501 const struct radv_descriptor_set_layout *layout;
502 struct list_head descriptor_pool;
503 uint32_t size;
504
505 struct radv_buffer_view *buffer_views;
506 struct radeon_winsys_bo *bo;
507 uint64_t va;
508 uint32_t *mapped_ptr;
509 struct radv_descriptor_range *dynamic_descriptors;
510 struct radeon_winsys_bo *descriptors[0];
511 };
512
513 struct radv_descriptor_pool_free_node {
514 int next;
515 uint32_t offset;
516 uint32_t size;
517 };
518
519 struct radv_descriptor_pool {
520 struct list_head descriptor_sets;
521
522 struct radeon_winsys_bo *bo;
523 uint8_t *mapped_ptr;
524 uint64_t current_offset;
525 uint64_t size;
526
527 int free_list;
528 int full_list;
529 uint32_t max_sets;
530 struct radv_descriptor_pool_free_node free_nodes[];
531 };
532
533 struct radv_buffer {
534 struct radv_device * device;
535 VkDeviceSize size;
536
537 VkBufferUsageFlags usage;
538
539 /* Set when bound */
540 struct radeon_winsys_bo * bo;
541 VkDeviceSize offset;
542 };
543
544
545 enum radv_cmd_dirty_bits {
546 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
547 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
548 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
549 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
550 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
551 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
552 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
553 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
554 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
555 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
556 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
557 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
558 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
559 };
560 typedef uint32_t radv_cmd_dirty_mask_t;
561
562 enum radv_cmd_flush_bits {
563 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
564 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
565 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
566 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
567 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
568 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
569 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
570 /* Framebuffer caches */
571 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
572 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
573 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
574 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
575 /* Engine synchronization. */
576 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
577 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
578 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
579 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
580
581 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
582 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
583 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
584 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
585 };
586
587 struct radv_vertex_binding {
588 struct radv_buffer * buffer;
589 VkDeviceSize offset;
590 };
591
592 struct radv_dynamic_state {
593 struct {
594 uint32_t count;
595 VkViewport viewports[MAX_VIEWPORTS];
596 } viewport;
597
598 struct {
599 uint32_t count;
600 VkRect2D scissors[MAX_SCISSORS];
601 } scissor;
602
603 float line_width;
604
605 struct {
606 float bias;
607 float clamp;
608 float slope;
609 } depth_bias;
610
611 float blend_constants[4];
612
613 struct {
614 float min;
615 float max;
616 } depth_bounds;
617
618 struct {
619 uint32_t front;
620 uint32_t back;
621 } stencil_compare_mask;
622
623 struct {
624 uint32_t front;
625 uint32_t back;
626 } stencil_write_mask;
627
628 struct {
629 uint32_t front;
630 uint32_t back;
631 } stencil_reference;
632 };
633
634 extern const struct radv_dynamic_state default_dynamic_state;
635
636 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
637 const struct radv_dynamic_state *src,
638 uint32_t copy_mask);
639 /**
640 * Attachment state when recording a renderpass instance.
641 *
642 * The clear value is valid only if there exists a pending clear.
643 */
644 struct radv_attachment_state {
645 VkImageAspectFlags pending_clear_aspects;
646 VkClearValue clear_value;
647 VkImageLayout current_layout;
648 };
649
650 struct radv_cmd_state {
651 uint32_t vb_dirty;
652 bool vertex_descriptors_dirty;
653 radv_cmd_dirty_mask_t dirty;
654
655 struct radv_pipeline * pipeline;
656 struct radv_pipeline * emitted_pipeline;
657 struct radv_pipeline * compute_pipeline;
658 struct radv_pipeline * emitted_compute_pipeline;
659 struct radv_framebuffer * framebuffer;
660 struct radv_render_pass * pass;
661 const struct radv_subpass * subpass;
662 struct radv_dynamic_state dynamic;
663 struct radv_vertex_binding vertex_bindings[MAX_VBS];
664 struct radv_descriptor_set * descriptors[MAX_SETS];
665 struct radv_attachment_state * attachments;
666 VkRect2D render_area;
667 struct radv_buffer * index_buffer;
668 uint32_t index_type;
669 uint32_t index_offset;
670 uint32_t last_primitive_reset_index;
671 enum radv_cmd_flush_bits flush_bits;
672 unsigned active_occlusion_queries;
673 float offset_scale;
674 uint32_t descriptors_dirty;
675 };
676
677 struct radv_cmd_pool {
678 VkAllocationCallbacks alloc;
679 struct list_head cmd_buffers;
680 uint32_t queue_family_index;
681 };
682
683 struct radv_cmd_buffer_upload {
684 uint8_t *map;
685 unsigned offset;
686 uint64_t size;
687 struct radeon_winsys_bo *upload_bo;
688 struct list_head list;
689 };
690
691 struct radv_cmd_buffer {
692 VK_LOADER_DATA _loader_data;
693
694 struct radv_device * device;
695
696 struct radv_cmd_pool * pool;
697 struct list_head pool_link;
698
699 VkCommandBufferUsageFlags usage_flags;
700 VkCommandBufferLevel level;
701 struct radeon_winsys_cs *cs;
702 struct radv_cmd_state state;
703 uint32_t queue_family_index;
704
705 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
706 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
707 VkShaderStageFlags push_constant_stages;
708
709 struct radv_cmd_buffer_upload upload;
710
711 bool record_fail;
712 };
713
714 struct radv_image;
715
716 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
717
718 void si_init_config(struct radv_physical_device *physical_device,
719 struct radv_cmd_buffer *cmd_buffer);
720 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
721 int count, const VkViewport *viewports);
722 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
723 int count, const VkRect2D *scissors);
724 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
725 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
726 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
727 uint64_t src_va, uint64_t dest_va,
728 uint64_t size);
729 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
730 uint64_t size, unsigned value);
731 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
732 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
733 struct radv_descriptor_set *set,
734 unsigned idx);
735 bool
736 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
737 unsigned size,
738 unsigned alignment,
739 unsigned *out_offset,
740 void **ptr);
741 void
742 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
743 const struct radv_subpass *subpass,
744 bool transitions);
745 bool
746 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
747 unsigned size, unsigned alignmnet,
748 const void *data, unsigned *out_offset);
749 void
750 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
751 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
752 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
753 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
754 unsigned radv_cayman_get_maxdist(int log_samples);
755 void radv_device_init_msaa(struct radv_device *device);
756 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
757 struct radv_image *image,
758 VkClearDepthStencilValue ds_clear_value,
759 VkImageAspectFlags aspects);
760 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
761 struct radv_image *image,
762 int idx,
763 uint32_t color_values[2]);
764 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
765 struct radeon_winsys_bo *bo,
766 uint64_t offset, uint64_t size, uint32_t value);
767
768 /*
769 * Takes x,y,z as exact numbers of invocations, instead of blocks.
770 *
771 * Limitations: Can't call normal dispatch functions without binding or rebinding
772 * the compute pipeline.
773 */
774 void radv_unaligned_dispatch(
775 struct radv_cmd_buffer *cmd_buffer,
776 uint32_t x,
777 uint32_t y,
778 uint32_t z);
779
780 struct radv_event {
781 struct radeon_winsys_bo *bo;
782 uint64_t *map;
783 };
784
785 struct nir_shader;
786
787 struct radv_shader_module {
788 struct nir_shader * nir;
789 unsigned char sha1[20];
790 uint32_t size;
791 char data[0];
792 };
793
794 union ac_shader_variant_key;
795
796 void
797 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
798 const char *entrypoint,
799 const VkSpecializationInfo *spec_info,
800 const struct radv_pipeline_layout *layout,
801 const union ac_shader_variant_key *key);
802
803 static inline gl_shader_stage
804 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
805 {
806 assert(__builtin_popcount(vk_stage) == 1);
807 return ffs(vk_stage) - 1;
808 }
809
810 static inline VkShaderStageFlagBits
811 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
812 {
813 return (1 << mesa_stage);
814 }
815
816 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
817
818 #define radv_foreach_stage(stage, stage_bits) \
819 for (gl_shader_stage stage, \
820 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
821 stage = __builtin_ffs(__tmp) - 1, __tmp; \
822 __tmp &= ~(1 << (stage)))
823
824 struct radv_shader_variant {
825 uint32_t ref_count;
826
827 struct radeon_winsys_bo *bo;
828 struct ac_shader_config config;
829 struct ac_shader_variant_info info;
830 unsigned rsrc1;
831 unsigned rsrc2;
832 uint32_t code_size;
833 };
834
835 struct radv_depth_stencil_state {
836 uint32_t db_depth_control;
837 uint32_t db_stencil_control;
838 uint32_t db_render_control;
839 uint32_t db_render_override2;
840 };
841
842 struct radv_blend_state {
843 uint32_t cb_color_control;
844 uint32_t cb_target_mask;
845 uint32_t sx_mrt0_blend_opt[8];
846 uint32_t cb_blend_control[8];
847
848 uint32_t spi_shader_col_format;
849 uint32_t cb_shader_mask;
850 uint32_t db_alpha_to_mask;
851 };
852
853 unsigned radv_format_meta_fs_key(VkFormat format);
854
855 struct radv_raster_state {
856 uint32_t pa_cl_clip_cntl;
857 uint32_t pa_cl_vs_out_cntl;
858 uint32_t spi_interp_control;
859 uint32_t pa_su_point_size;
860 uint32_t pa_su_point_minmax;
861 uint32_t pa_su_line_cntl;
862 uint32_t pa_su_vtx_cntl;
863 uint32_t pa_su_sc_mode_cntl;
864 };
865
866 struct radv_multisample_state {
867 uint32_t db_eqaa;
868 uint32_t pa_sc_line_cntl;
869 uint32_t pa_sc_mode_cntl_0;
870 uint32_t pa_sc_mode_cntl_1;
871 uint32_t pa_sc_aa_config;
872 uint32_t pa_sc_aa_mask[2];
873 unsigned num_samples;
874 };
875
876 struct radv_pipeline {
877 struct radv_device * device;
878 uint32_t dynamic_state_mask;
879 struct radv_dynamic_state dynamic_state;
880
881 struct radv_pipeline_layout * layout;
882
883 bool needs_data_cache;
884
885 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
886 VkShaderStageFlags active_stages;
887
888 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
889 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
890 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
891 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
892 uint32_t num_vertex_attribs;
893 uint32_t binding_stride[MAX_VBS];
894
895 union {
896 struct {
897 struct radv_blend_state blend;
898 struct radv_depth_stencil_state ds;
899 struct radv_raster_state raster;
900 struct radv_multisample_state ms;
901 unsigned prim;
902 unsigned gs_out;
903 bool prim_restart_enable;
904 } graphics;
905 };
906 };
907
908 struct radv_graphics_pipeline_create_info {
909 bool use_rectlist;
910 bool db_depth_clear;
911 bool db_stencil_clear;
912 bool db_depth_disable_expclear;
913 bool db_stencil_disable_expclear;
914 bool db_flush_depth_inplace;
915 bool db_flush_stencil_inplace;
916 bool db_resummarize;
917 uint32_t custom_blend_mode;
918 };
919
920 VkResult
921 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
922 struct radv_pipeline_cache *cache,
923 const VkGraphicsPipelineCreateInfo *pCreateInfo,
924 const struct radv_graphics_pipeline_create_info *extra,
925 const VkAllocationCallbacks *alloc);
926
927 VkResult
928 radv_graphics_pipeline_create(VkDevice device,
929 VkPipelineCache cache,
930 const VkGraphicsPipelineCreateInfo *pCreateInfo,
931 const struct radv_graphics_pipeline_create_info *extra,
932 const VkAllocationCallbacks *alloc,
933 VkPipeline *pPipeline);
934
935 struct vk_format_description;
936 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
937 int first_non_void);
938 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
939 int first_non_void);
940 uint32_t radv_translate_colorformat(VkFormat format);
941 uint32_t radv_translate_color_numformat(VkFormat format,
942 const struct vk_format_description *desc,
943 int first_non_void);
944 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
945 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
946 uint32_t radv_translate_dbformat(VkFormat format);
947 uint32_t radv_translate_tex_dataformat(VkFormat format,
948 const struct vk_format_description *desc,
949 int first_non_void);
950 uint32_t radv_translate_tex_numformat(VkFormat format,
951 const struct vk_format_description *desc,
952 int first_non_void);
953 bool radv_format_pack_clear_color(VkFormat format,
954 uint32_t clear_vals[2],
955 VkClearColorValue *value);
956 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
957
958 struct radv_fmask_info {
959 uint64_t offset;
960 uint64_t size;
961 unsigned alignment;
962 unsigned pitch_in_pixels;
963 unsigned bank_height;
964 unsigned slice_tile_max;
965 unsigned tile_mode_index;
966 };
967
968 struct radv_cmask_info {
969 uint64_t offset;
970 uint64_t size;
971 unsigned alignment;
972 unsigned slice_tile_max;
973 unsigned base_address_reg;
974 };
975
976 struct r600_htile_info {
977 uint64_t offset;
978 uint64_t size;
979 unsigned pitch;
980 unsigned height;
981 unsigned xalign;
982 unsigned yalign;
983 };
984
985 struct radv_image {
986 VkImageType type;
987 /* The original VkFormat provided by the client. This may not match any
988 * of the actual surface formats.
989 */
990 VkFormat vk_format;
991 VkImageAspectFlags aspects;
992 VkExtent3D extent;
993 uint32_t levels;
994 uint32_t array_size;
995 uint32_t samples; /**< VkImageCreateInfo::samples */
996 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
997 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
998
999 VkDeviceSize size;
1000 uint32_t alignment;
1001
1002 /* Set when bound */
1003 struct radeon_winsys_bo *bo;
1004 VkDeviceSize offset;
1005 uint32_t dcc_offset;
1006 struct radeon_surf surface;
1007
1008 struct radv_fmask_info fmask;
1009 struct radv_cmask_info cmask;
1010 uint32_t clear_value_offset;
1011
1012 /* Depth buffer compression and fast clear. */
1013 struct r600_htile_info htile;
1014 };
1015
1016 bool radv_layout_has_htile(const struct radv_image *image,
1017 VkImageLayout layout);
1018 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1019 VkImageLayout layout);
1020 bool radv_layout_can_expclear(const struct radv_image *image,
1021 VkImageLayout layout);
1022 bool radv_layout_has_cmask(const struct radv_image *image,
1023 VkImageLayout layout);
1024 static inline uint32_t
1025 radv_get_layerCount(const struct radv_image *image,
1026 const VkImageSubresourceRange *range)
1027 {
1028 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1029 image->array_size - range->baseArrayLayer : range->layerCount;
1030 }
1031
1032 static inline uint32_t
1033 radv_get_levelCount(const struct radv_image *image,
1034 const VkImageSubresourceRange *range)
1035 {
1036 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1037 image->levels - range->baseMipLevel : range->levelCount;
1038 }
1039
1040 struct radeon_bo_metadata;
1041 void
1042 radv_init_metadata(struct radv_device *device,
1043 struct radv_image *image,
1044 struct radeon_bo_metadata *metadata);
1045
1046 struct radv_image_view {
1047 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1048 struct radeon_winsys_bo *bo;
1049
1050 VkImageViewType type;
1051 VkImageAspectFlags aspect_mask;
1052 VkFormat vk_format;
1053 uint32_t base_layer;
1054 uint32_t layer_count;
1055 uint32_t base_mip;
1056 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1057
1058 uint32_t descriptor[8];
1059 uint32_t fmask_descriptor[8];
1060 };
1061
1062 struct radv_image_create_info {
1063 const VkImageCreateInfo *vk_info;
1064 uint32_t stride;
1065 bool scanout;
1066 };
1067
1068 VkResult radv_image_create(VkDevice _device,
1069 const struct radv_image_create_info *info,
1070 const VkAllocationCallbacks* alloc,
1071 VkImage *pImage);
1072
1073 void radv_image_view_init(struct radv_image_view *view,
1074 struct radv_device *device,
1075 const VkImageViewCreateInfo* pCreateInfo,
1076 struct radv_cmd_buffer *cmd_buffer,
1077 VkImageUsageFlags usage_mask);
1078 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1079 struct radv_image *image, uint32_t micro_tile_mode);
1080 struct radv_buffer_view {
1081 struct radeon_winsys_bo *bo;
1082 VkFormat vk_format;
1083 uint64_t range; /**< VkBufferViewCreateInfo::range */
1084 uint32_t state[4];
1085 };
1086 void radv_buffer_view_init(struct radv_buffer_view *view,
1087 struct radv_device *device,
1088 const VkBufferViewCreateInfo* pCreateInfo,
1089 struct radv_cmd_buffer *cmd_buffer);
1090
1091 static inline struct VkExtent3D
1092 radv_sanitize_image_extent(const VkImageType imageType,
1093 const struct VkExtent3D imageExtent)
1094 {
1095 switch (imageType) {
1096 case VK_IMAGE_TYPE_1D:
1097 return (VkExtent3D) { imageExtent.width, 1, 1 };
1098 case VK_IMAGE_TYPE_2D:
1099 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1100 case VK_IMAGE_TYPE_3D:
1101 return imageExtent;
1102 default:
1103 unreachable("invalid image type");
1104 }
1105 }
1106
1107 static inline struct VkOffset3D
1108 radv_sanitize_image_offset(const VkImageType imageType,
1109 const struct VkOffset3D imageOffset)
1110 {
1111 switch (imageType) {
1112 case VK_IMAGE_TYPE_1D:
1113 return (VkOffset3D) { imageOffset.x, 0, 0 };
1114 case VK_IMAGE_TYPE_2D:
1115 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1116 case VK_IMAGE_TYPE_3D:
1117 return imageOffset;
1118 default:
1119 unreachable("invalid image type");
1120 }
1121 }
1122
1123 struct radv_sampler {
1124 uint32_t state[4];
1125 };
1126
1127 struct radv_color_buffer_info {
1128 uint32_t cb_color_base;
1129 uint32_t cb_color_pitch;
1130 uint32_t cb_color_slice;
1131 uint32_t cb_color_view;
1132 uint32_t cb_color_info;
1133 uint32_t cb_color_attrib;
1134 uint32_t cb_dcc_control;
1135 uint32_t cb_color_cmask;
1136 uint32_t cb_color_cmask_slice;
1137 uint32_t cb_color_fmask;
1138 uint32_t cb_color_fmask_slice;
1139 uint32_t cb_clear_value0;
1140 uint32_t cb_clear_value1;
1141 uint32_t cb_dcc_base;
1142 uint32_t micro_tile_mode;
1143 };
1144
1145 struct radv_ds_buffer_info {
1146 uint32_t db_depth_info;
1147 uint32_t db_z_info;
1148 uint32_t db_stencil_info;
1149 uint32_t db_z_read_base;
1150 uint32_t db_stencil_read_base;
1151 uint32_t db_z_write_base;
1152 uint32_t db_stencil_write_base;
1153 uint32_t db_depth_view;
1154 uint32_t db_depth_size;
1155 uint32_t db_depth_slice;
1156 uint32_t db_htile_surface;
1157 uint32_t db_htile_data_base;
1158 uint32_t pa_su_poly_offset_db_fmt_cntl;
1159 float offset_scale;
1160 };
1161
1162 struct radv_attachment_info {
1163 union {
1164 struct radv_color_buffer_info cb;
1165 struct radv_ds_buffer_info ds;
1166 };
1167 struct radv_image_view *attachment;
1168 };
1169
1170 struct radv_framebuffer {
1171 uint32_t width;
1172 uint32_t height;
1173 uint32_t layers;
1174
1175 uint32_t attachment_count;
1176 struct radv_attachment_info attachments[0];
1177 };
1178
1179 struct radv_subpass_barrier {
1180 VkPipelineStageFlags src_stage_mask;
1181 VkAccessFlags src_access_mask;
1182 VkAccessFlags dst_access_mask;
1183 };
1184
1185 struct radv_subpass {
1186 uint32_t input_count;
1187 VkAttachmentReference * input_attachments;
1188 uint32_t color_count;
1189 VkAttachmentReference * color_attachments;
1190 VkAttachmentReference * resolve_attachments;
1191 VkAttachmentReference depth_stencil_attachment;
1192
1193 /** Subpass has at least one resolve attachment */
1194 bool has_resolve;
1195
1196 struct radv_subpass_barrier start_barrier;
1197 };
1198
1199 struct radv_render_pass_attachment {
1200 VkFormat format;
1201 uint32_t samples;
1202 VkAttachmentLoadOp load_op;
1203 VkAttachmentLoadOp stencil_load_op;
1204 VkImageLayout initial_layout;
1205 VkImageLayout final_layout;
1206 };
1207
1208 struct radv_render_pass {
1209 uint32_t attachment_count;
1210 uint32_t subpass_count;
1211 VkAttachmentReference * subpass_attachments;
1212 struct radv_render_pass_attachment * attachments;
1213 struct radv_subpass_barrier end_barrier;
1214 struct radv_subpass subpasses[0];
1215 };
1216
1217 VkResult radv_device_init_meta(struct radv_device *device);
1218 void radv_device_finish_meta(struct radv_device *device);
1219
1220 struct radv_query_pool {
1221 struct radeon_winsys_bo *bo;
1222 uint32_t stride;
1223 uint32_t availability_offset;
1224 char *ptr;
1225 VkQueryType type;
1226 };
1227
1228 VkResult
1229 radv_temp_descriptor_set_create(struct radv_device *device,
1230 struct radv_cmd_buffer *cmd_buffer,
1231 VkDescriptorSetLayout _layout,
1232 VkDescriptorSet *_set);
1233
1234 void
1235 radv_temp_descriptor_set_destroy(struct radv_device *device,
1236 VkDescriptorSet _set);
1237 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1238 struct radv_image *image, uint32_t value);
1239 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1240 struct radv_image *image, uint32_t value);
1241
1242 struct radv_fence {
1243 struct radeon_winsys_fence *fence;
1244 bool submitted;
1245 bool signalled;
1246 };
1247
1248 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1249 \
1250 static inline struct __radv_type * \
1251 __radv_type ## _from_handle(__VkType _handle) \
1252 { \
1253 return (struct __radv_type *) _handle; \
1254 } \
1255 \
1256 static inline __VkType \
1257 __radv_type ## _to_handle(struct __radv_type *_obj) \
1258 { \
1259 return (__VkType) _obj; \
1260 }
1261
1262 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1263 \
1264 static inline struct __radv_type * \
1265 __radv_type ## _from_handle(__VkType _handle) \
1266 { \
1267 return (struct __radv_type *)(uintptr_t) _handle; \
1268 } \
1269 \
1270 static inline __VkType \
1271 __radv_type ## _to_handle(struct __radv_type *_obj) \
1272 { \
1273 return (__VkType)(uintptr_t) _obj; \
1274 }
1275
1276 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1277 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1278
1279 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1280 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1281 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1282 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1283 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1284
1285 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1286 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1287 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1288 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1289 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1290 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1291 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1292 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1293 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1294 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1295 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1296 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1297 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1298 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1299 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1300 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1301 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1302 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1303 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1304
1305 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1306 \
1307 static inline const __VkType * \
1308 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1309 { \
1310 return (const __VkType *) __radv_obj; \
1311 }
1312
1313 #endif /* RADV_PRIVATE_H */