projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: bump some base addresses to 64-bits.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_debug.h"
57 #include "radv_descriptor_set.h"
58
59 #include <llvm-c/TargetMachine.h>
60
61 /* Pre-declarations needed for WSI entrypoints */
62 struct wl_surface;
63 struct wl_display;
64 typedef struct xcb_connection_t xcb_connection_t;
65 typedef uint32_t xcb_visualid_t;
66 typedef uint32_t xcb_window_t;
67
68 #include <vulkan/vulkan.h>
69 #include <vulkan/vulkan_intel.h>
70 #include <vulkan/vk_icd.h>
71
72 #include "radv_entrypoints.h"
73
74 #include "wsi_common.h"
75
76 #define MAX_VBS 32
77 #define MAX_VERTEX_ATTRIBS 32
78 #define MAX_RTS 8
79 #define MAX_VIEWPORTS 16
80 #define MAX_SCISSORS 16
81 #define MAX_PUSH_CONSTANTS_SIZE 128
82 #define MAX_PUSH_DESCRIPTORS 32
83 #define MAX_DYNAMIC_BUFFERS 16
84 #define MAX_SAMPLES_LOG2 4
85 #define NUM_META_FS_KEYS 11
86 #define RADV_MAX_DRM_DEVICES 8
87
88 #define NUM_DEPTH_CLEAR_PIPELINES 3
89
90 enum radv_mem_heap {
91 RADV_MEM_HEAP_VRAM,
92 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
93 RADV_MEM_HEAP_GTT,
94 RADV_MEM_HEAP_COUNT
95 };
96
97 enum radv_mem_type {
98 RADV_MEM_TYPE_VRAM,
99 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
100 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
101 RADV_MEM_TYPE_GTT_CACHED,
102 RADV_MEM_TYPE_COUNT
103 };
104
105 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
106
107 static inline uint32_t
108 align_u32(uint32_t v, uint32_t a)
109 {
110 assert(a != 0 && a == (a & -a));
111 return (v + a - 1) & ~(a - 1);
112 }
113
114 static inline uint32_t
115 align_u32_npot(uint32_t v, uint32_t a)
116 {
117 return (v + a - 1) / a * a;
118 }
119
120 static inline uint64_t
121 align_u64(uint64_t v, uint64_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 static inline int32_t
128 align_i32(int32_t v, int32_t a)
129 {
130 assert(a != 0 && a == (a & -a));
131 return (v + a - 1) & ~(a - 1);
132 }
133
134 /** Alignment must be a power of 2. */
135 static inline bool
136 radv_is_aligned(uintmax_t n, uintmax_t a)
137 {
138 assert(a == (a & -a));
139 return (n & (a - 1)) == 0;
140 }
141
142 static inline uint32_t
143 round_up_u32(uint32_t v, uint32_t a)
144 {
145 return (v + a - 1) / a;
146 }
147
148 static inline uint64_t
149 round_up_u64(uint64_t v, uint64_t a)
150 {
151 return (v + a - 1) / a;
152 }
153
154 static inline uint32_t
155 radv_minify(uint32_t n, uint32_t levels)
156 {
157 if (unlikely(n == 0))
158 return 0;
159 else
160 return MAX2(n >> levels, 1);
161 }
162 static inline float
163 radv_clamp_f(float f, float min, float max)
164 {
165 assert(min < max);
166
167 if (f > max)
168 return max;
169 else if (f < min)
170 return min;
171 else
172 return f;
173 }
174
175 static inline bool
176 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
177 {
178 if (*inout_mask & clear_mask) {
179 *inout_mask &= ~clear_mask;
180 return true;
181 } else {
182 return false;
183 }
184 }
185
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
190
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
194 })
195
196 #define zero(x) (memset(&(x), 0, sizeof(x)))
197
198 /* Whenever we generate an error, pass it through this function. Useful for
199 * debugging, where we can break on it. Only call at error site, not when
200 * propagating errors. Might be useful to plug in a stack trace here.
201 */
202
203 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
204
205 #ifdef DEBUG
206 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
207 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #else
209 #define vk_error(error) error
210 #define vk_errorf(error, format, ...) error
211 #endif
212
213 void __radv_finishme(const char *file, int line, const char *format, ...)
214 radv_printflike(3, 4);
215 void radv_loge(const char *format, ...) radv_printflike(1, 2);
216 void radv_loge_v(const char *format, va_list va);
217
218 /**
219 * Print a FINISHME message, including its source location.
220 */
221 #define radv_finishme(format, ...) \
222 do { \
223 static bool reported = false; \
224 if (!reported) { \
225 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
226 reported = true; \
227 } \
228 } while (0)
229
230 /* A non-fatal assert. Useful for debugging. */
231 #ifdef DEBUG
232 #define radv_assert(x) ({ \
233 if (unlikely(!(x))) \
234 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
235 })
236 #else
237 #define radv_assert(x)
238 #endif
239
240 #define stub_return(v) \
241 do { \
242 radv_finishme("stub %s", __func__); \
243 return (v); \
244 } while (0)
245
246 #define stub() \
247 do { \
248 radv_finishme("stub %s", __func__); \
249 return; \
250 } while (0)
251
252 void *radv_lookup_entrypoint(const char *name);
253
254 struct radv_extensions {
255 VkExtensionProperties *ext_array;
256 uint32_t num_ext;
257 };
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 char path[20];
267 const char * name;
268 uint8_t uuid[VK_UUID_SIZE];
269
270 int local_fd;
271 struct wsi_device wsi_device;
272 struct radv_extensions extensions;
273 };
274
275 struct radv_instance {
276 VK_LOADER_DATA _loader_data;
277
278 VkAllocationCallbacks alloc;
279
280 uint32_t apiVersion;
281 int physicalDeviceCount;
282 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
283
284 uint64_t debug_flags;
285 };
286
287 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
288 void radv_finish_wsi(struct radv_physical_device *physical_device);
289
290 struct cache_entry;
291
292 struct radv_pipeline_cache {
293 struct radv_device * device;
294 pthread_mutex_t mutex;
295
296 uint32_t total_size;
297 uint32_t table_size;
298 uint32_t kernel_count;
299 struct cache_entry ** hash_table;
300 bool modified;
301
302 VkAllocationCallbacks alloc;
303 };
304
305 void
306 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
307 struct radv_device *device);
308 void
309 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
310 void
311 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
312 const void *data, size_t size);
313
314 struct radv_shader_variant *
315 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
316 struct radv_pipeline_cache *cache,
317 const unsigned char *sha1);
318
319 struct radv_shader_variant *
320 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
321 const unsigned char *sha1,
322 struct radv_shader_variant *variant,
323 const void *code, unsigned code_size);
324
325 void radv_shader_variant_destroy(struct radv_device *device,
326 struct radv_shader_variant *variant);
327
328 struct radv_meta_state {
329 VkAllocationCallbacks alloc;
330
331 struct radv_pipeline_cache cache;
332
333 /**
334 * Use array element `i` for images with `2^i` samples.
335 */
336 struct {
337 VkRenderPass render_pass[NUM_META_FS_KEYS];
338 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
339
340 VkRenderPass depthstencil_rp;
341 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
342 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
343 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
344 } clear[1 + MAX_SAMPLES_LOG2];
345
346 VkPipelineLayout clear_color_p_layout;
347 VkPipelineLayout clear_depth_p_layout;
348 struct {
349 VkRenderPass render_pass[NUM_META_FS_KEYS];
350
351 /** Pipeline that blits from a 1D image. */
352 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
353
354 /** Pipeline that blits from a 2D image. */
355 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
356
357 /** Pipeline that blits from a 3D image. */
358 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
359
360 VkRenderPass depth_only_rp;
361 VkPipeline depth_only_1d_pipeline;
362 VkPipeline depth_only_2d_pipeline;
363 VkPipeline depth_only_3d_pipeline;
364
365 VkRenderPass stencil_only_rp;
366 VkPipeline stencil_only_1d_pipeline;
367 VkPipeline stencil_only_2d_pipeline;
368 VkPipeline stencil_only_3d_pipeline;
369 VkPipelineLayout pipeline_layout;
370 VkDescriptorSetLayout ds_layout;
371 } blit;
372
373 struct {
374 VkRenderPass render_passes[NUM_META_FS_KEYS];
375
376 VkPipelineLayout p_layouts[2];
377 VkDescriptorSetLayout ds_layouts[2];
378 VkPipeline pipelines[2][NUM_META_FS_KEYS];
379
380 VkRenderPass depth_only_rp;
381 VkPipeline depth_only_pipeline[2];
382
383 VkRenderPass stencil_only_rp;
384 VkPipeline stencil_only_pipeline[2];
385 } blit2d;
386
387 struct {
388 VkPipelineLayout img_p_layout;
389 VkDescriptorSetLayout img_ds_layout;
390 VkPipeline pipeline;
391 } itob;
392 struct {
393 VkRenderPass render_pass;
394 VkPipelineLayout img_p_layout;
395 VkDescriptorSetLayout img_ds_layout;
396 VkPipeline pipeline;
397 } btoi;
398 struct {
399 VkPipelineLayout img_p_layout;
400 VkDescriptorSetLayout img_ds_layout;
401 VkPipeline pipeline;
402 } itoi;
403 struct {
404 VkPipelineLayout img_p_layout;
405 VkDescriptorSetLayout img_ds_layout;
406 VkPipeline pipeline;
407 } cleari;
408
409 struct {
410 VkPipeline pipeline;
411 VkRenderPass pass;
412 } resolve;
413
414 struct {
415 VkDescriptorSetLayout ds_layout;
416 VkPipelineLayout p_layout;
417 struct {
418 VkPipeline pipeline;
419 VkPipeline i_pipeline;
420 VkPipeline srgb_pipeline;
421 } rc[MAX_SAMPLES_LOG2];
422 } resolve_compute;
423
424 struct {
425 VkDescriptorSetLayout ds_layout;
426 VkPipelineLayout p_layout;
427
428 struct {
429 VkRenderPass srgb_render_pass;
430 VkPipeline srgb_pipeline;
431 VkRenderPass render_pass[NUM_META_FS_KEYS];
432 VkPipeline pipeline[NUM_META_FS_KEYS];
433 } rc[MAX_SAMPLES_LOG2];
434 } resolve_fragment;
435
436 struct {
437 VkPipeline decompress_pipeline;
438 VkPipeline resummarize_pipeline;
439 VkRenderPass pass;
440 } depth_decomp;
441
442 struct {
443 VkPipeline cmask_eliminate_pipeline;
444 VkPipeline fmask_decompress_pipeline;
445 VkRenderPass pass;
446 } fast_clear_flush;
447
448 struct {
449 VkPipelineLayout fill_p_layout;
450 VkPipelineLayout copy_p_layout;
451 VkDescriptorSetLayout fill_ds_layout;
452 VkDescriptorSetLayout copy_ds_layout;
453 VkPipeline fill_pipeline;
454 VkPipeline copy_pipeline;
455 } buffer;
456
457 struct {
458 VkDescriptorSetLayout ds_layout;
459 VkPipelineLayout p_layout;
460 VkPipeline occlusion_query_pipeline;
461 VkPipeline pipeline_statistics_query_pipeline;
462 } query;
463 };
464
465 /* queue types */
466 #define RADV_QUEUE_GENERAL 0
467 #define RADV_QUEUE_COMPUTE 1
468 #define RADV_QUEUE_TRANSFER 2
469
470 #define RADV_MAX_QUEUE_FAMILIES 3
471
472 enum ring_type radv_queue_family_to_ring(int f);
473
474 struct radv_queue {
475 VK_LOADER_DATA _loader_data;
476 struct radv_device * device;
477 struct radeon_winsys_ctx *hw_ctx;
478 int queue_family_index;
479 int queue_idx;
480
481 uint32_t scratch_size;
482 uint32_t compute_scratch_size;
483 uint32_t esgs_ring_size;
484 uint32_t gsvs_ring_size;
485 bool has_tess_rings;
486 bool has_sample_positions;
487
488 struct radeon_winsys_bo *scratch_bo;
489 struct radeon_winsys_bo *descriptor_bo;
490 struct radeon_winsys_bo *compute_scratch_bo;
491 struct radeon_winsys_bo *esgs_ring_bo;
492 struct radeon_winsys_bo *gsvs_ring_bo;
493 struct radeon_winsys_bo *tess_factor_ring_bo;
494 struct radeon_winsys_bo *tess_offchip_ring_bo;
495 struct radeon_winsys_cs *initial_preamble_cs;
496 struct radeon_winsys_cs *continue_preamble_cs;
497 };
498
499 struct radv_device {
500 VK_LOADER_DATA _loader_data;
501
502 VkAllocationCallbacks alloc;
503
504 struct radv_instance * instance;
505 struct radeon_winsys *ws;
506
507 struct radv_meta_state meta_state;
508
509 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
510 int queue_count[RADV_MAX_QUEUE_FAMILIES];
511 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
512 struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
513 struct radeon_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
514 uint64_t debug_flags;
515
516 bool llvm_supports_spill;
517 bool has_distributed_tess;
518 uint32_t tess_offchip_block_dw_size;
519 uint32_t scratch_waves;
520
521 uint32_t gs_table_depth;
522
523 /* MSAA sample locations.
524 * The first index is the sample index.
525 * The second index is the coordinate: X, Y. */
526 float sample_locations_1x[1][2];
527 float sample_locations_2x[2][2];
528 float sample_locations_4x[4][2];
529 float sample_locations_8x[8][2];
530 float sample_locations_16x[16][2];
531
532 /* CIK and later */
533 uint32_t gfx_init_size_dw;
534 struct radeon_winsys_bo *gfx_init;
535
536 struct radeon_winsys_bo *trace_bo;
537 uint32_t *trace_id_ptr;
538
539 struct radv_physical_device *physical_device;
540
541 /* Backup in-memory cache to be used if the app doesn't provide one */
542 struct radv_pipeline_cache * mem_cache;
543 };
544
545 struct radv_device_memory {
546 struct radeon_winsys_bo *bo;
547 /* for dedicated allocations */
548 struct radv_image *image;
549 struct radv_buffer *buffer;
550 uint32_t type_index;
551 VkDeviceSize map_size;
552 void * map;
553 };
554
555
556 struct radv_descriptor_range {
557 uint64_t va;
558 uint32_t size;
559 };
560
561 struct radv_descriptor_set {
562 const struct radv_descriptor_set_layout *layout;
563 uint32_t size;
564
565 struct radeon_winsys_bo *bo;
566 uint64_t va;
567 uint32_t *mapped_ptr;
568 struct radv_descriptor_range *dynamic_descriptors;
569
570 struct list_head vram_list;
571
572 struct radeon_winsys_bo *descriptors[0];
573 };
574
575 struct radv_push_descriptor_set
576 {
577 struct radv_descriptor_set set;
578 uint32_t capacity;
579 };
580
581 struct radv_descriptor_pool {
582 struct radeon_winsys_bo *bo;
583 uint8_t *mapped_ptr;
584 uint64_t current_offset;
585 uint64_t size;
586
587 struct list_head vram_list;
588
589 uint8_t *host_memory_base;
590 uint8_t *host_memory_ptr;
591 uint8_t *host_memory_end;
592 };
593
594 struct radv_descriptor_update_template_entry {
595 VkDescriptorType descriptor_type;
596
597 /* The number of descriptors to update */
598 uint32_t descriptor_count;
599
600 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
601 uint32_t dst_offset;
602
603 /* In dwords. Not valid/used for dynamic descriptors */
604 uint32_t dst_stride;
605
606 uint32_t buffer_offset;
607
608 /* Only valid for combined image samplers and samplers */
609 uint16_t has_sampler;
610
611 /* In bytes */
612 size_t src_offset;
613 size_t src_stride;
614
615 /* For push descriptors */
616 const uint32_t *immutable_samplers;
617 };
618
619 struct radv_descriptor_update_template {
620 uint32_t entry_count;
621 struct radv_descriptor_update_template_entry entry[0];
622 };
623
624 struct radv_buffer {
625 struct radv_device * device;
626 VkDeviceSize size;
627
628 VkBufferUsageFlags usage;
629 VkBufferCreateFlags flags;
630
631 /* Set when bound */
632 struct radeon_winsys_bo * bo;
633 VkDeviceSize offset;
634 };
635
636
637 enum radv_cmd_dirty_bits {
638 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
639 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
640 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
641 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
642 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
643 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
644 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
645 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
646 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
647 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
648 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
649 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
650 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
651 };
652 typedef uint32_t radv_cmd_dirty_mask_t;
653
654 enum radv_cmd_flush_bits {
655 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
656 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
657 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
658 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
659 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
660 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
661 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
662 /* Same as above, but only writes back and doesn't invalidate */
663 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
664 /* Framebuffer caches */
665 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
666 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
667 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
668 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
669 /* Engine synchronization. */
670 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
671 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
672 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
673 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
674
675 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
676 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
677 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
678 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
679 };
680
681 struct radv_vertex_binding {
682 struct radv_buffer * buffer;
683 VkDeviceSize offset;
684 };
685
686 struct radv_dynamic_state {
687 struct {
688 uint32_t count;
689 VkViewport viewports[MAX_VIEWPORTS];
690 } viewport;
691
692 struct {
693 uint32_t count;
694 VkRect2D scissors[MAX_SCISSORS];
695 } scissor;
696
697 float line_width;
698
699 struct {
700 float bias;
701 float clamp;
702 float slope;
703 } depth_bias;
704
705 float blend_constants[4];
706
707 struct {
708 float min;
709 float max;
710 } depth_bounds;
711
712 struct {
713 uint32_t front;
714 uint32_t back;
715 } stencil_compare_mask;
716
717 struct {
718 uint32_t front;
719 uint32_t back;
720 } stencil_write_mask;
721
722 struct {
723 uint32_t front;
724 uint32_t back;
725 } stencil_reference;
726 };
727
728 extern const struct radv_dynamic_state default_dynamic_state;
729
730 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
731 const struct radv_dynamic_state *src,
732 uint32_t copy_mask);
733 /**
734 * Attachment state when recording a renderpass instance.
735 *
736 * The clear value is valid only if there exists a pending clear.
737 */
738 struct radv_attachment_state {
739 VkImageAspectFlags pending_clear_aspects;
740 VkClearValue clear_value;
741 VkImageLayout current_layout;
742 };
743
744 struct radv_cmd_state {
745 uint32_t vb_dirty;
746 radv_cmd_dirty_mask_t dirty;
747 bool vertex_descriptors_dirty;
748 bool push_descriptors_dirty;
749
750 struct radv_pipeline * pipeline;
751 struct radv_pipeline * emitted_pipeline;
752 struct radv_pipeline * compute_pipeline;
753 struct radv_pipeline * emitted_compute_pipeline;
754 struct radv_framebuffer * framebuffer;
755 struct radv_render_pass * pass;
756 const struct radv_subpass * subpass;
757 struct radv_dynamic_state dynamic;
758 struct radv_vertex_binding vertex_bindings[MAX_VBS];
759 struct radv_descriptor_set * descriptors[MAX_SETS];
760 struct radv_attachment_state * attachments;
761 VkRect2D render_area;
762 struct radv_buffer * index_buffer;
763 uint32_t index_type;
764 uint32_t index_offset;
765 int32_t last_primitive_reset_en;
766 uint32_t last_primitive_reset_index;
767 enum radv_cmd_flush_bits flush_bits;
768 unsigned active_occlusion_queries;
769 float offset_scale;
770 uint32_t descriptors_dirty;
771 uint32_t trace_id;
772 uint32_t last_ia_multi_vgt_param;
773 };
774
775 struct radv_cmd_pool {
776 VkAllocationCallbacks alloc;
777 struct list_head cmd_buffers;
778 struct list_head free_cmd_buffers;
779 uint32_t queue_family_index;
780 };
781
782 struct radv_cmd_buffer_upload {
783 uint8_t *map;
784 unsigned offset;
785 uint64_t size;
786 struct radeon_winsys_bo *upload_bo;
787 struct list_head list;
788 };
789
790 struct radv_cmd_buffer {
791 VK_LOADER_DATA _loader_data;
792
793 struct radv_device * device;
794
795 struct radv_cmd_pool * pool;
796 struct list_head pool_link;
797
798 VkCommandBufferUsageFlags usage_flags;
799 VkCommandBufferLevel level;
800 struct radeon_winsys_cs *cs;
801 struct radv_cmd_state state;
802 uint32_t queue_family_index;
803
804 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
805 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
806 VkShaderStageFlags push_constant_stages;
807 struct radv_push_descriptor_set push_descriptors;
808 struct radv_descriptor_set meta_push_descriptors;
809
810 struct radv_cmd_buffer_upload upload;
811
812 uint32_t scratch_size_needed;
813 uint32_t compute_scratch_size_needed;
814 uint32_t esgs_ring_size_needed;
815 uint32_t gsvs_ring_size_needed;
816 bool tess_rings_needed;
817 bool sample_positions_needed;
818
819 bool record_fail;
820
821 int ring_offsets_idx; /* just used for verification */
822 };
823
824 struct radv_image;
825
826 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
827
828 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
829 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
830
831 void cik_create_gfx_config(struct radv_device *device);
832
833 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
834 int count, const VkViewport *viewports);
835 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
836 int count, const VkRect2D *scissors,
837 const VkViewport *viewports, bool can_use_guardband);
838 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
839 bool instanced_draw, bool indirect_draw,
840 uint32_t draw_vertex_count);
841 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
842 enum chip_class chip_class,
843 bool is_mec,
844 unsigned event, unsigned event_flags,
845 unsigned data_sel,
846 uint64_t va,
847 uint32_t old_fence,
848 uint32_t new_fence);
849
850 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
851 uint64_t va, uint32_t ref,
852 uint32_t mask);
853 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
854 enum chip_class chip_class,
855 bool is_mec,
856 enum radv_cmd_flush_bits flush_bits);
857 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
858 enum chip_class chip_class,
859 bool is_mec,
860 enum radv_cmd_flush_bits flush_bits);
861 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
862 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
863 uint64_t src_va, uint64_t dest_va,
864 uint64_t size);
865 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
866 unsigned size);
867 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
868 uint64_t size, unsigned value);
869 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
870 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
871 struct radv_descriptor_set *set,
872 unsigned idx);
873 bool
874 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
875 unsigned size,
876 unsigned alignment,
877 unsigned *out_offset,
878 void **ptr);
879 void
880 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
881 const struct radv_subpass *subpass,
882 bool transitions);
883 bool
884 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
885 unsigned size, unsigned alignmnet,
886 const void *data, unsigned *out_offset);
887 void
888 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
889 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
890 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
891 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
892 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
893 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
894 unsigned radv_cayman_get_maxdist(int log_samples);
895 void radv_device_init_msaa(struct radv_device *device);
896 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
897 struct radv_image *image,
898 VkClearDepthStencilValue ds_clear_value,
899 VkImageAspectFlags aspects);
900 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_image *image,
902 int idx,
903 uint32_t color_values[2]);
904 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
905 struct radeon_winsys_bo *bo,
906 uint64_t offset, uint64_t size, uint32_t value);
907 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
908 bool radv_get_memory_fd(struct radv_device *device,
909 struct radv_device_memory *memory,
910 int *pFD);
911 /*
912 * Takes x,y,z as exact numbers of invocations, instead of blocks.
913 *
914 * Limitations: Can't call normal dispatch functions without binding or rebinding
915 * the compute pipeline.
916 */
917 void radv_unaligned_dispatch(
918 struct radv_cmd_buffer *cmd_buffer,
919 uint32_t x,
920 uint32_t y,
921 uint32_t z);
922
923 struct radv_event {
924 struct radeon_winsys_bo *bo;
925 uint64_t *map;
926 };
927
928 struct nir_shader;
929
930 struct radv_shader_module {
931 struct nir_shader * nir;
932 unsigned char sha1[20];
933 uint32_t size;
934 char data[0];
935 };
936
937 union ac_shader_variant_key;
938
939 void
940 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
941 const char *entrypoint,
942 const VkSpecializationInfo *spec_info,
943 const struct radv_pipeline_layout *layout,
944 const union ac_shader_variant_key *key,
945 uint32_t is_geom_copy_shader);
946
947 static inline gl_shader_stage
948 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
949 {
950 assert(__builtin_popcount(vk_stage) == 1);
951 return ffs(vk_stage) - 1;
952 }
953
954 static inline VkShaderStageFlagBits
955 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
956 {
957 return (1 << mesa_stage);
958 }
959
960 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
961
962 #define radv_foreach_stage(stage, stage_bits) \
963 for (gl_shader_stage stage, \
964 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
965 stage = __builtin_ffs(__tmp) - 1, __tmp; \
966 __tmp &= ~(1 << (stage)))
967
968 struct radv_shader_variant {
969 uint32_t ref_count;
970
971 struct radeon_winsys_bo *bo;
972 struct ac_shader_config config;
973 struct ac_shader_variant_info info;
974 unsigned rsrc1;
975 unsigned rsrc2;
976 uint32_t code_size;
977 };
978
979 struct radv_depth_stencil_state {
980 uint32_t db_depth_control;
981 uint32_t db_stencil_control;
982 uint32_t db_render_control;
983 uint32_t db_render_override2;
984 };
985
986 struct radv_blend_state {
987 uint32_t cb_color_control;
988 uint32_t cb_target_mask;
989 uint32_t sx_mrt0_blend_opt[8];
990 uint32_t cb_blend_control[8];
991
992 uint32_t spi_shader_col_format;
993 uint32_t cb_shader_mask;
994 uint32_t db_alpha_to_mask;
995 };
996
997 unsigned radv_format_meta_fs_key(VkFormat format);
998
999 struct radv_raster_state {
1000 uint32_t pa_cl_clip_cntl;
1001 uint32_t spi_interp_control;
1002 uint32_t pa_su_point_size;
1003 uint32_t pa_su_point_minmax;
1004 uint32_t pa_su_line_cntl;
1005 uint32_t pa_su_vtx_cntl;
1006 uint32_t pa_su_sc_mode_cntl;
1007 };
1008
1009 struct radv_multisample_state {
1010 uint32_t db_eqaa;
1011 uint32_t pa_sc_line_cntl;
1012 uint32_t pa_sc_mode_cntl_0;
1013 uint32_t pa_sc_mode_cntl_1;
1014 uint32_t pa_sc_aa_config;
1015 uint32_t pa_sc_aa_mask[2];
1016 unsigned num_samples;
1017 };
1018
1019 struct radv_prim_vertex_count {
1020 uint8_t min;
1021 uint8_t incr;
1022 };
1023
1024 struct radv_tessellation_state {
1025 uint32_t ls_hs_config;
1026 uint32_t tcs_in_layout;
1027 uint32_t tcs_out_layout;
1028 uint32_t tcs_out_offsets;
1029 uint32_t offchip_layout;
1030 unsigned num_patches;
1031 unsigned lds_size;
1032 unsigned num_tcs_input_cp;
1033 uint32_t tf_param;
1034 };
1035
1036 struct radv_pipeline {
1037 struct radv_device * device;
1038 uint32_t dynamic_state_mask;
1039 struct radv_dynamic_state dynamic_state;
1040
1041 struct radv_pipeline_layout * layout;
1042
1043 bool needs_data_cache;
1044 bool need_indirect_descriptor_sets;
1045 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1046 struct radv_shader_variant *gs_copy_shader;
1047 VkShaderStageFlags active_stages;
1048
1049 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
1050 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
1051 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
1052 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
1053 uint32_t num_vertex_attribs;
1054 uint32_t binding_stride[MAX_VBS];
1055
1056 union {
1057 struct {
1058 struct radv_blend_state blend;
1059 struct radv_depth_stencil_state ds;
1060 struct radv_raster_state raster;
1061 struct radv_multisample_state ms;
1062 struct radv_tessellation_state tess;
1063 uint32_t db_shader_control;
1064 uint32_t shader_z_format;
1065 unsigned prim;
1066 unsigned gs_out;
1067 uint32_t vgt_gs_mode;
1068 bool prim_restart_enable;
1069 unsigned esgs_ring_size;
1070 unsigned gsvs_ring_size;
1071 uint32_t ps_input_cntl[32];
1072 uint32_t ps_input_cntl_num;
1073 uint32_t pa_cl_vs_out_cntl;
1074 uint32_t vgt_shader_stages_en;
1075 struct radv_prim_vertex_count prim_vertex_count;
1076 bool can_use_guardband;
1077 } graphics;
1078 };
1079
1080 unsigned max_waves;
1081 unsigned scratch_bytes_per_wave;
1082 };
1083
1084 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1085 {
1086 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1087 }
1088
1089 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1090 {
1091 return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
1092 }
1093
1094 struct radv_graphics_pipeline_create_info {
1095 bool use_rectlist;
1096 bool db_depth_clear;
1097 bool db_stencil_clear;
1098 bool db_depth_disable_expclear;
1099 bool db_stencil_disable_expclear;
1100 bool db_flush_depth_inplace;
1101 bool db_flush_stencil_inplace;
1102 bool db_resummarize;
1103 uint32_t custom_blend_mode;
1104 };
1105
1106 VkResult
1107 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
1108 struct radv_pipeline_cache *cache,
1109 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1110 const struct radv_graphics_pipeline_create_info *extra,
1111 const VkAllocationCallbacks *alloc);
1112
1113 VkResult
1114 radv_graphics_pipeline_create(VkDevice device,
1115 VkPipelineCache cache,
1116 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1117 const struct radv_graphics_pipeline_create_info *extra,
1118 const VkAllocationCallbacks *alloc,
1119 VkPipeline *pPipeline);
1120
1121 struct vk_format_description;
1122 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1123 int first_non_void);
1124 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1125 int first_non_void);
1126 uint32_t radv_translate_colorformat(VkFormat format);
1127 uint32_t radv_translate_color_numformat(VkFormat format,
1128 const struct vk_format_description *desc,
1129 int first_non_void);
1130 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1131 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1132 uint32_t radv_translate_dbformat(VkFormat format);
1133 uint32_t radv_translate_tex_dataformat(VkFormat format,
1134 const struct vk_format_description *desc,
1135 int first_non_void);
1136 uint32_t radv_translate_tex_numformat(VkFormat format,
1137 const struct vk_format_description *desc,
1138 int first_non_void);
1139 bool radv_format_pack_clear_color(VkFormat format,
1140 uint32_t clear_vals[2],
1141 VkClearColorValue *value);
1142 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1143
1144 struct radv_fmask_info {
1145 uint64_t offset;
1146 uint64_t size;
1147 unsigned alignment;
1148 unsigned pitch_in_pixels;
1149 unsigned bank_height;
1150 unsigned slice_tile_max;
1151 unsigned tile_mode_index;
1152 };
1153
1154 struct radv_cmask_info {
1155 uint64_t offset;
1156 uint64_t size;
1157 unsigned alignment;
1158 unsigned slice_tile_max;
1159 unsigned base_address_reg;
1160 };
1161
1162 struct r600_htile_info {
1163 uint64_t offset;
1164 uint64_t size;
1165 unsigned pitch;
1166 unsigned height;
1167 unsigned xalign;
1168 unsigned yalign;
1169 };
1170
1171 struct radv_image {
1172 VkImageType type;
1173 /* The original VkFormat provided by the client. This may not match any
1174 * of the actual surface formats.
1175 */
1176 VkFormat vk_format;
1177 VkImageAspectFlags aspects;
1178 struct radeon_surf_info info;
1179 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1180 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1181 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1182
1183 VkDeviceSize size;
1184 uint32_t alignment;
1185
1186 bool exclusive;
1187 unsigned queue_family_mask;
1188
1189 /* Set when bound */
1190 struct radeon_winsys_bo *bo;
1191 VkDeviceSize offset;
1192 uint32_t dcc_offset;
1193 uint32_t htile_offset;
1194 struct radeon_surf surface;
1195
1196 struct radv_fmask_info fmask;
1197 struct radv_cmask_info cmask;
1198 uint32_t clear_value_offset;
1199 };
1200
1201 /* Whether the image has a htile that is known consistent with the contents of
1202 * the image. */
1203 bool radv_layout_has_htile(const struct radv_image *image,
1204 VkImageLayout layout,
1205 unsigned queue_mask);
1206
1207 /* Whether the image has a htile that is known consistent with the contents of
1208 * the image and is allowed to be in compressed form.
1209 *
1210 * If this is false reads that don't use the htile should be able to return
1211 * correct results.
1212 */
1213 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1214 VkImageLayout layout,
1215 unsigned queue_mask);
1216
1217 bool radv_layout_can_fast_clear(const struct radv_image *image,
1218 VkImageLayout layout,
1219 unsigned queue_mask);
1220
1221
1222 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1223
1224 static inline uint32_t
1225 radv_get_layerCount(const struct radv_image *image,
1226 const VkImageSubresourceRange *range)
1227 {
1228 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1229 image->info.array_size - range->baseArrayLayer : range->layerCount;
1230 }
1231
1232 static inline uint32_t
1233 radv_get_levelCount(const struct radv_image *image,
1234 const VkImageSubresourceRange *range)
1235 {
1236 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1237 image->info.levels - range->baseMipLevel : range->levelCount;
1238 }
1239
1240 struct radeon_bo_metadata;
1241 void
1242 radv_init_metadata(struct radv_device *device,
1243 struct radv_image *image,
1244 struct radeon_bo_metadata *metadata);
1245
1246 struct radv_image_view {
1247 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1248 struct radeon_winsys_bo *bo;
1249
1250 VkImageViewType type;
1251 VkImageAspectFlags aspect_mask;
1252 VkFormat vk_format;
1253 uint32_t base_layer;
1254 uint32_t layer_count;
1255 uint32_t base_mip;
1256 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1257
1258 uint32_t descriptor[8];
1259 uint32_t fmask_descriptor[8];
1260 };
1261
1262 struct radv_image_create_info {
1263 const VkImageCreateInfo *vk_info;
1264 uint32_t stride;
1265 bool scanout;
1266 };
1267
1268 VkResult radv_image_create(VkDevice _device,
1269 const struct radv_image_create_info *info,
1270 const VkAllocationCallbacks* alloc,
1271 VkImage *pImage);
1272
1273 void radv_image_view_init(struct radv_image_view *view,
1274 struct radv_device *device,
1275 const VkImageViewCreateInfo* pCreateInfo,
1276 struct radv_cmd_buffer *cmd_buffer,
1277 VkImageUsageFlags usage_mask);
1278
1279 struct radv_buffer_view {
1280 struct radeon_winsys_bo *bo;
1281 VkFormat vk_format;
1282 uint64_t range; /**< VkBufferViewCreateInfo::range */
1283 uint32_t state[4];
1284 };
1285 void radv_buffer_view_init(struct radv_buffer_view *view,
1286 struct radv_device *device,
1287 const VkBufferViewCreateInfo* pCreateInfo,
1288 struct radv_cmd_buffer *cmd_buffer);
1289
1290 static inline struct VkExtent3D
1291 radv_sanitize_image_extent(const VkImageType imageType,
1292 const struct VkExtent3D imageExtent)
1293 {
1294 switch (imageType) {
1295 case VK_IMAGE_TYPE_1D:
1296 return (VkExtent3D) { imageExtent.width, 1, 1 };
1297 case VK_IMAGE_TYPE_2D:
1298 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1299 case VK_IMAGE_TYPE_3D:
1300 return imageExtent;
1301 default:
1302 unreachable("invalid image type");
1303 }
1304 }
1305
1306 static inline struct VkOffset3D
1307 radv_sanitize_image_offset(const VkImageType imageType,
1308 const struct VkOffset3D imageOffset)
1309 {
1310 switch (imageType) {
1311 case VK_IMAGE_TYPE_1D:
1312 return (VkOffset3D) { imageOffset.x, 0, 0 };
1313 case VK_IMAGE_TYPE_2D:
1314 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1315 case VK_IMAGE_TYPE_3D:
1316 return imageOffset;
1317 default:
1318 unreachable("invalid image type");
1319 }
1320 }
1321
1322 static inline bool
1323 radv_image_extent_compare(const struct radv_image *image,
1324 const VkExtent3D *extent)
1325 {
1326 if (extent->width != image->info.width ||
1327 extent->height != image->info.height ||
1328 extent->depth != image->info.depth)
1329 return false;
1330 return true;
1331 }
1332
1333 struct radv_sampler {
1334 uint32_t state[4];
1335 };
1336
1337 struct radv_color_buffer_info {
1338 uint64_t cb_color_base;
1339 uint64_t cb_color_cmask;
1340 uint64_t cb_color_fmask;
1341 uint64_t cb_dcc_base;
1342 uint32_t cb_color_pitch;
1343 uint32_t cb_color_slice;
1344 uint32_t cb_color_view;
1345 uint32_t cb_color_info;
1346 uint32_t cb_color_attrib;
1347 uint32_t cb_dcc_control;
1348 uint32_t cb_color_cmask_slice;
1349 uint32_t cb_color_fmask_slice;
1350 uint32_t cb_clear_value0;
1351 uint32_t cb_clear_value1;
1352 uint32_t micro_tile_mode;
1353 };
1354
1355 struct radv_ds_buffer_info {
1356 uint64_t db_z_read_base;
1357 uint64_t db_stencil_read_base;
1358 uint64_t db_z_write_base;
1359 uint64_t db_stencil_write_base;
1360 uint64_t db_htile_data_base;
1361 uint32_t db_depth_info;
1362 uint32_t db_z_info;
1363 uint32_t db_stencil_info;
1364 uint32_t db_depth_view;
1365 uint32_t db_depth_size;
1366 uint32_t db_depth_slice;
1367 uint32_t db_htile_surface;
1368 uint32_t pa_su_poly_offset_db_fmt_cntl;
1369 float offset_scale;
1370 };
1371
1372 struct radv_attachment_info {
1373 union {
1374 struct radv_color_buffer_info cb;
1375 struct radv_ds_buffer_info ds;
1376 };
1377 struct radv_image_view *attachment;
1378 };
1379
1380 struct radv_framebuffer {
1381 uint32_t width;
1382 uint32_t height;
1383 uint32_t layers;
1384
1385 uint32_t attachment_count;
1386 struct radv_attachment_info attachments[0];
1387 };
1388
1389 struct radv_subpass_barrier {
1390 VkPipelineStageFlags src_stage_mask;
1391 VkAccessFlags src_access_mask;
1392 VkAccessFlags dst_access_mask;
1393 };
1394
1395 struct radv_subpass {
1396 uint32_t input_count;
1397 uint32_t color_count;
1398 VkAttachmentReference * input_attachments;
1399 VkAttachmentReference * color_attachments;
1400 VkAttachmentReference * resolve_attachments;
1401 VkAttachmentReference depth_stencil_attachment;
1402
1403 /** Subpass has at least one resolve attachment */
1404 bool has_resolve;
1405
1406 struct radv_subpass_barrier start_barrier;
1407 };
1408
1409 struct radv_render_pass_attachment {
1410 VkFormat format;
1411 uint32_t samples;
1412 VkAttachmentLoadOp load_op;
1413 VkAttachmentLoadOp stencil_load_op;
1414 VkImageLayout initial_layout;
1415 VkImageLayout final_layout;
1416 };
1417
1418 struct radv_render_pass {
1419 uint32_t attachment_count;
1420 uint32_t subpass_count;
1421 VkAttachmentReference * subpass_attachments;
1422 struct radv_render_pass_attachment * attachments;
1423 struct radv_subpass_barrier end_barrier;
1424 struct radv_subpass subpasses[0];
1425 };
1426
1427 VkResult radv_device_init_meta(struct radv_device *device);
1428 void radv_device_finish_meta(struct radv_device *device);
1429
1430 struct radv_query_pool {
1431 struct radeon_winsys_bo *bo;
1432 uint32_t stride;
1433 uint32_t availability_offset;
1434 char *ptr;
1435 VkQueryType type;
1436 uint32_t pipeline_stats_mask;
1437 };
1438
1439 void
1440 radv_update_descriptor_sets(struct radv_device *device,
1441 struct radv_cmd_buffer *cmd_buffer,
1442 VkDescriptorSet overrideSet,
1443 uint32_t descriptorWriteCount,
1444 const VkWriteDescriptorSet *pDescriptorWrites,
1445 uint32_t descriptorCopyCount,
1446 const VkCopyDescriptorSet *pDescriptorCopies);
1447
1448 void
1449 radv_update_descriptor_set_with_template(struct radv_device *device,
1450 struct radv_cmd_buffer *cmd_buffer,
1451 struct radv_descriptor_set *set,
1452 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1453 const void *pData);
1454
1455 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1456 VkPipelineBindPoint pipelineBindPoint,
1457 VkPipelineLayout _layout,
1458 uint32_t set,
1459 uint32_t descriptorWriteCount,
1460 const VkWriteDescriptorSet *pDescriptorWrites);
1461
1462 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1463 struct radv_image *image, uint32_t value);
1464 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1465 struct radv_image *image, uint32_t value);
1466
1467 struct radv_fence {
1468 struct radeon_winsys_fence *fence;
1469 bool submitted;
1470 bool signalled;
1471 };
1472
1473 struct radeon_winsys_sem;
1474
1475 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1476 \
1477 static inline struct __radv_type * \
1478 __radv_type ## _from_handle(__VkType _handle) \
1479 { \
1480 return (struct __radv_type *) _handle; \
1481 } \
1482 \
1483 static inline __VkType \
1484 __radv_type ## _to_handle(struct __radv_type *_obj) \
1485 { \
1486 return (__VkType) _obj; \
1487 }
1488
1489 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1490 \
1491 static inline struct __radv_type * \
1492 __radv_type ## _from_handle(__VkType _handle) \
1493 { \
1494 return (struct __radv_type *)(uintptr_t) _handle; \
1495 } \
1496 \
1497 static inline __VkType \
1498 __radv_type ## _to_handle(struct __radv_type *_obj) \
1499 { \
1500 return (__VkType)(uintptr_t) _obj; \
1501 }
1502
1503 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1504 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1505
1506 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1507 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1508 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1509 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1510 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1511
1512 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1513 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1514 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1515 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1516 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1517 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1518 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1519 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1520 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1521 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1522 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1523 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1524 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1525 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1526 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1527 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1528 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1529 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1530 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1531 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1532 RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
1533
1534 #endif /* RADV_PRIVATE_H */