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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275 bool cpdma_prefetch_writes_memory;
276
277 /* This is the drivers on-disk cache used as a fallback as opposed to
278 * the pipeline cache defined by apps.
279 */
280 struct disk_cache * disk_cache;
281
282 VkPhysicalDeviceMemoryProperties memory_properties;
283 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
284 };
285
286 struct radv_instance {
287 VK_LOADER_DATA _loader_data;
288
289 VkAllocationCallbacks alloc;
290
291 uint32_t apiVersion;
292 int physicalDeviceCount;
293 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
294
295 uint64_t debug_flags;
296 uint64_t perftest_flags;
297 };
298
299 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
300 void radv_finish_wsi(struct radv_physical_device *physical_device);
301
302 bool radv_instance_extension_supported(const char *name);
303 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
304 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
305 const char *name);
306
307 struct cache_entry;
308
309 struct radv_pipeline_cache {
310 struct radv_device * device;
311 pthread_mutex_t mutex;
312
313 uint32_t total_size;
314 uint32_t table_size;
315 uint32_t kernel_count;
316 struct cache_entry ** hash_table;
317 bool modified;
318
319 VkAllocationCallbacks alloc;
320 };
321
322 struct radv_pipeline_key {
323 uint32_t instance_rate_inputs;
324 unsigned tess_input_vertices;
325 uint32_t col_format;
326 uint32_t is_int8;
327 uint32_t is_int10;
328 uint32_t multisample : 1;
329 uint32_t has_multiview_view_index : 1;
330 };
331
332 void
333 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
334 struct radv_device *device);
335 void
336 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
337 void
338 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
339 const void *data, size_t size);
340
341 struct radv_shader_variant;
342
343 bool
344 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
345 struct radv_pipeline_cache *cache,
346 const unsigned char *sha1,
347 struct radv_shader_variant **variants);
348
349 void
350 radv_pipeline_cache_insert_shaders(struct radv_device *device,
351 struct radv_pipeline_cache *cache,
352 const unsigned char *sha1,
353 struct radv_shader_variant **variants,
354 const void *const *codes,
355 const unsigned *code_sizes);
356
357 enum radv_blit_ds_layout {
358 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
359 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
360 RADV_BLIT_DS_LAYOUT_COUNT,
361 };
362
363 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
364 {
365 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
366 }
367
368 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
369 {
370 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
371 }
372
373 enum radv_meta_dst_layout {
374 RADV_META_DST_LAYOUT_GENERAL,
375 RADV_META_DST_LAYOUT_OPTIMAL,
376 RADV_META_DST_LAYOUT_COUNT,
377 };
378
379 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
380 {
381 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
382 }
383
384 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
385 {
386 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
387 }
388
389 struct radv_meta_state {
390 VkAllocationCallbacks alloc;
391
392 struct radv_pipeline_cache cache;
393
394 /**
395 * Use array element `i` for images with `2^i` samples.
396 */
397 struct {
398 VkRenderPass render_pass[NUM_META_FS_KEYS];
399 VkPipeline color_pipelines[NUM_META_FS_KEYS];
400
401 VkRenderPass depthstencil_rp;
402 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
403 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
404 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
405 } clear[1 + MAX_SAMPLES_LOG2];
406
407 VkPipelineLayout clear_color_p_layout;
408 VkPipelineLayout clear_depth_p_layout;
409 struct {
410 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
411
412 /** Pipeline that blits from a 1D image. */
413 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
414
415 /** Pipeline that blits from a 2D image. */
416 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
417
418 /** Pipeline that blits from a 3D image. */
419 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
420
421 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
422 VkPipeline depth_only_1d_pipeline;
423 VkPipeline depth_only_2d_pipeline;
424 VkPipeline depth_only_3d_pipeline;
425
426 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
427 VkPipeline stencil_only_1d_pipeline;
428 VkPipeline stencil_only_2d_pipeline;
429 VkPipeline stencil_only_3d_pipeline;
430 VkPipelineLayout pipeline_layout;
431 VkDescriptorSetLayout ds_layout;
432 } blit;
433
434 struct {
435 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
436
437 VkPipelineLayout p_layouts[3];
438 VkDescriptorSetLayout ds_layouts[3];
439 VkPipeline pipelines[3][NUM_META_FS_KEYS];
440
441 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
442 VkPipeline depth_only_pipeline[3];
443
444 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
445 VkPipeline stencil_only_pipeline[3];
446 } blit2d;
447
448 struct {
449 VkPipelineLayout img_p_layout;
450 VkDescriptorSetLayout img_ds_layout;
451 VkPipeline pipeline;
452 VkPipeline pipeline_3d;
453 } itob;
454 struct {
455 VkPipelineLayout img_p_layout;
456 VkDescriptorSetLayout img_ds_layout;
457 VkPipeline pipeline;
458 VkPipeline pipeline_3d;
459 } btoi;
460 struct {
461 VkPipelineLayout img_p_layout;
462 VkDescriptorSetLayout img_ds_layout;
463 VkPipeline pipeline;
464 VkPipeline pipeline_3d;
465 } itoi;
466 struct {
467 VkPipelineLayout img_p_layout;
468 VkDescriptorSetLayout img_ds_layout;
469 VkPipeline pipeline;
470 VkPipeline pipeline_3d;
471 } cleari;
472
473 struct {
474 VkPipelineLayout p_layout;
475 VkPipeline pipeline;
476 VkRenderPass pass;
477 } resolve;
478
479 struct {
480 VkDescriptorSetLayout ds_layout;
481 VkPipelineLayout p_layout;
482 struct {
483 VkPipeline pipeline;
484 VkPipeline i_pipeline;
485 VkPipeline srgb_pipeline;
486 } rc[MAX_SAMPLES_LOG2];
487 } resolve_compute;
488
489 struct {
490 VkDescriptorSetLayout ds_layout;
491 VkPipelineLayout p_layout;
492
493 struct {
494 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
495 VkPipeline pipeline[NUM_META_FS_KEYS];
496 } rc[MAX_SAMPLES_LOG2];
497 } resolve_fragment;
498
499 struct {
500 VkPipelineLayout p_layout;
501 VkPipeline decompress_pipeline;
502 VkPipeline resummarize_pipeline;
503 VkRenderPass pass;
504 } depth_decomp[1 + MAX_SAMPLES_LOG2];
505
506 struct {
507 VkPipelineLayout p_layout;
508 VkPipeline cmask_eliminate_pipeline;
509 VkPipeline fmask_decompress_pipeline;
510 VkPipeline dcc_decompress_pipeline;
511 VkRenderPass pass;
512
513 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
514 VkPipelineLayout dcc_decompress_compute_p_layout;
515 VkPipeline dcc_decompress_compute_pipeline;
516 } fast_clear_flush;
517
518 struct {
519 VkPipelineLayout fill_p_layout;
520 VkPipelineLayout copy_p_layout;
521 VkDescriptorSetLayout fill_ds_layout;
522 VkDescriptorSetLayout copy_ds_layout;
523 VkPipeline fill_pipeline;
524 VkPipeline copy_pipeline;
525 } buffer;
526
527 struct {
528 VkDescriptorSetLayout ds_layout;
529 VkPipelineLayout p_layout;
530 VkPipeline occlusion_query_pipeline;
531 VkPipeline pipeline_statistics_query_pipeline;
532 } query;
533 };
534
535 /* queue types */
536 #define RADV_QUEUE_GENERAL 0
537 #define RADV_QUEUE_COMPUTE 1
538 #define RADV_QUEUE_TRANSFER 2
539
540 #define RADV_MAX_QUEUE_FAMILIES 3
541
542 enum ring_type radv_queue_family_to_ring(int f);
543
544 struct radv_queue {
545 VK_LOADER_DATA _loader_data;
546 struct radv_device * device;
547 struct radeon_winsys_ctx *hw_ctx;
548 enum radeon_ctx_priority priority;
549 uint32_t queue_family_index;
550 int queue_idx;
551
552 uint32_t scratch_size;
553 uint32_t compute_scratch_size;
554 uint32_t esgs_ring_size;
555 uint32_t gsvs_ring_size;
556 bool has_tess_rings;
557 bool has_sample_positions;
558
559 struct radeon_winsys_bo *scratch_bo;
560 struct radeon_winsys_bo *descriptor_bo;
561 struct radeon_winsys_bo *compute_scratch_bo;
562 struct radeon_winsys_bo *esgs_ring_bo;
563 struct radeon_winsys_bo *gsvs_ring_bo;
564 struct radeon_winsys_bo *tess_factor_ring_bo;
565 struct radeon_winsys_bo *tess_offchip_ring_bo;
566 struct radeon_winsys_cs *initial_preamble_cs;
567 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
568 struct radeon_winsys_cs *continue_preamble_cs;
569 };
570
571 struct radv_device {
572 VK_LOADER_DATA _loader_data;
573
574 VkAllocationCallbacks alloc;
575
576 struct radv_instance * instance;
577 struct radeon_winsys *ws;
578
579 struct radv_meta_state meta_state;
580
581 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
582 int queue_count[RADV_MAX_QUEUE_FAMILIES];
583 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
584
585 bool llvm_supports_spill;
586 bool has_distributed_tess;
587 bool pbb_allowed;
588 bool dfsm_allowed;
589 uint32_t tess_offchip_block_dw_size;
590 uint32_t scratch_waves;
591 uint32_t dispatch_initiator;
592
593 uint32_t gs_table_depth;
594
595 /* MSAA sample locations.
596 * The first index is the sample index.
597 * The second index is the coordinate: X, Y. */
598 float sample_locations_1x[1][2];
599 float sample_locations_2x[2][2];
600 float sample_locations_4x[4][2];
601 float sample_locations_8x[8][2];
602 float sample_locations_16x[16][2];
603
604 /* CIK and later */
605 uint32_t gfx_init_size_dw;
606 struct radeon_winsys_bo *gfx_init;
607
608 struct radeon_winsys_bo *trace_bo;
609 uint32_t *trace_id_ptr;
610
611 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
612 bool keep_shader_info;
613
614 struct radv_physical_device *physical_device;
615
616 /* Backup in-memory cache to be used if the app doesn't provide one */
617 struct radv_pipeline_cache * mem_cache;
618
619 /*
620 * use different counters so MSAA MRTs get consecutive surface indices,
621 * even if MASK is allocated in between.
622 */
623 uint32_t image_mrt_offset_counter;
624 uint32_t fmask_mrt_offset_counter;
625 struct list_head shader_slabs;
626 mtx_t shader_slab_mutex;
627
628 /* For detecting VM faults reported by dmesg. */
629 uint64_t dmesg_timestamp;
630 };
631
632 struct radv_device_memory {
633 struct radeon_winsys_bo *bo;
634 /* for dedicated allocations */
635 struct radv_image *image;
636 struct radv_buffer *buffer;
637 uint32_t type_index;
638 VkDeviceSize map_size;
639 void * map;
640 };
641
642
643 struct radv_descriptor_range {
644 uint64_t va;
645 uint32_t size;
646 };
647
648 struct radv_descriptor_set {
649 const struct radv_descriptor_set_layout *layout;
650 uint32_t size;
651
652 struct radeon_winsys_bo *bo;
653 uint64_t va;
654 uint32_t *mapped_ptr;
655 struct radv_descriptor_range *dynamic_descriptors;
656
657 struct radeon_winsys_bo *descriptors[0];
658 };
659
660 struct radv_push_descriptor_set
661 {
662 struct radv_descriptor_set set;
663 uint32_t capacity;
664 };
665
666 struct radv_descriptor_pool_entry {
667 uint32_t offset;
668 uint32_t size;
669 struct radv_descriptor_set *set;
670 };
671
672 struct radv_descriptor_pool {
673 struct radeon_winsys_bo *bo;
674 uint8_t *mapped_ptr;
675 uint64_t current_offset;
676 uint64_t size;
677
678 uint8_t *host_memory_base;
679 uint8_t *host_memory_ptr;
680 uint8_t *host_memory_end;
681
682 uint32_t entry_count;
683 uint32_t max_entry_count;
684 struct radv_descriptor_pool_entry entries[0];
685 };
686
687 struct radv_descriptor_update_template_entry {
688 VkDescriptorType descriptor_type;
689
690 /* The number of descriptors to update */
691 uint32_t descriptor_count;
692
693 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
694 uint32_t dst_offset;
695
696 /* In dwords. Not valid/used for dynamic descriptors */
697 uint32_t dst_stride;
698
699 uint32_t buffer_offset;
700
701 /* Only valid for combined image samplers and samplers */
702 uint16_t has_sampler;
703
704 /* In bytes */
705 size_t src_offset;
706 size_t src_stride;
707
708 /* For push descriptors */
709 const uint32_t *immutable_samplers;
710 };
711
712 struct radv_descriptor_update_template {
713 uint32_t entry_count;
714 struct radv_descriptor_update_template_entry entry[0];
715 };
716
717 struct radv_buffer {
718 struct radv_device * device;
719 VkDeviceSize size;
720
721 VkBufferUsageFlags usage;
722 VkBufferCreateFlags flags;
723
724 /* Set when bound */
725 struct radeon_winsys_bo * bo;
726 VkDeviceSize offset;
727
728 bool shareable;
729 };
730
731
732 enum radv_cmd_dirty_bits {
733 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
734 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
735 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
736 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
737 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
738 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
739 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
740 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
741 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
742 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
743 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
744 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
745 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
746 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
747 };
748
749 enum radv_cmd_flush_bits {
750 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
751 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
752 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
753 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
754 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
755 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
756 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
757 /* Same as above, but only writes back and doesn't invalidate */
758 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
759 /* Framebuffer caches */
760 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
761 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
762 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
763 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
764 /* Engine synchronization. */
765 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
766 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
767 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
768 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
769
770 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
771 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
772 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
773 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
774 };
775
776 struct radv_vertex_binding {
777 struct radv_buffer * buffer;
778 VkDeviceSize offset;
779 };
780
781 struct radv_viewport_state {
782 uint32_t count;
783 VkViewport viewports[MAX_VIEWPORTS];
784 };
785
786 struct radv_scissor_state {
787 uint32_t count;
788 VkRect2D scissors[MAX_SCISSORS];
789 };
790
791 struct radv_dynamic_state {
792 /**
793 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
794 * Defines the set of saved dynamic state.
795 */
796 uint32_t mask;
797
798 struct radv_viewport_state viewport;
799
800 struct radv_scissor_state scissor;
801
802 float line_width;
803
804 struct {
805 float bias;
806 float clamp;
807 float slope;
808 } depth_bias;
809
810 float blend_constants[4];
811
812 struct {
813 float min;
814 float max;
815 } depth_bounds;
816
817 struct {
818 uint32_t front;
819 uint32_t back;
820 } stencil_compare_mask;
821
822 struct {
823 uint32_t front;
824 uint32_t back;
825 } stencil_write_mask;
826
827 struct {
828 uint32_t front;
829 uint32_t back;
830 } stencil_reference;
831 };
832
833 extern const struct radv_dynamic_state default_dynamic_state;
834
835 const char *
836 radv_get_debug_option_name(int id);
837
838 const char *
839 radv_get_perftest_option_name(int id);
840
841 /**
842 * Attachment state when recording a renderpass instance.
843 *
844 * The clear value is valid only if there exists a pending clear.
845 */
846 struct radv_attachment_state {
847 VkImageAspectFlags pending_clear_aspects;
848 uint32_t cleared_views;
849 VkClearValue clear_value;
850 VkImageLayout current_layout;
851 };
852
853 struct radv_cmd_state {
854 /* Vertex descriptors */
855 bool vb_prefetch_dirty;
856 uint64_t vb_va;
857 unsigned vb_size;
858
859 bool push_descriptors_dirty;
860 bool predicating;
861 uint32_t dirty;
862
863 struct radv_pipeline * pipeline;
864 struct radv_pipeline * emitted_pipeline;
865 struct radv_pipeline * compute_pipeline;
866 struct radv_pipeline * emitted_compute_pipeline;
867 struct radv_framebuffer * framebuffer;
868 struct radv_render_pass * pass;
869 const struct radv_subpass * subpass;
870 struct radv_dynamic_state dynamic;
871 struct radv_attachment_state * attachments;
872 VkRect2D render_area;
873
874 /* Index buffer */
875 struct radv_buffer *index_buffer;
876 uint64_t index_offset;
877 uint32_t index_type;
878 uint32_t max_index_count;
879 uint64_t index_va;
880 int32_t last_index_type;
881
882 int32_t last_primitive_reset_en;
883 uint32_t last_primitive_reset_index;
884 enum radv_cmd_flush_bits flush_bits;
885 unsigned active_occlusion_queries;
886 float offset_scale;
887 uint32_t descriptors_dirty;
888 uint32_t valid_descriptors;
889 uint32_t trace_id;
890 uint32_t last_ia_multi_vgt_param;
891 };
892
893 struct radv_cmd_pool {
894 VkAllocationCallbacks alloc;
895 struct list_head cmd_buffers;
896 struct list_head free_cmd_buffers;
897 uint32_t queue_family_index;
898 };
899
900 struct radv_cmd_buffer_upload {
901 uint8_t *map;
902 unsigned offset;
903 uint64_t size;
904 struct radeon_winsys_bo *upload_bo;
905 struct list_head list;
906 };
907
908 enum radv_cmd_buffer_status {
909 RADV_CMD_BUFFER_STATUS_INVALID,
910 RADV_CMD_BUFFER_STATUS_INITIAL,
911 RADV_CMD_BUFFER_STATUS_RECORDING,
912 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
913 RADV_CMD_BUFFER_STATUS_PENDING,
914 };
915
916 struct radv_cmd_buffer {
917 VK_LOADER_DATA _loader_data;
918
919 struct radv_device * device;
920
921 struct radv_cmd_pool * pool;
922 struct list_head pool_link;
923
924 VkCommandBufferUsageFlags usage_flags;
925 VkCommandBufferLevel level;
926 enum radv_cmd_buffer_status status;
927 struct radeon_winsys_cs *cs;
928 struct radv_cmd_state state;
929 struct radv_vertex_binding vertex_bindings[MAX_VBS];
930 uint32_t queue_family_index;
931
932 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
933 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
934 VkShaderStageFlags push_constant_stages;
935 struct radv_push_descriptor_set push_descriptors;
936 struct radv_descriptor_set meta_push_descriptors;
937 struct radv_descriptor_set *descriptors[MAX_SETS];
938
939 struct radv_cmd_buffer_upload upload;
940
941 uint32_t scratch_size_needed;
942 uint32_t compute_scratch_size_needed;
943 uint32_t esgs_ring_size_needed;
944 uint32_t gsvs_ring_size_needed;
945 bool tess_rings_needed;
946 bool sample_positions_needed;
947
948 VkResult record_result;
949
950 int ring_offsets_idx; /* just used for verification */
951 uint32_t gfx9_fence_offset;
952 struct radeon_winsys_bo *gfx9_fence_bo;
953 uint32_t gfx9_fence_idx;
954 };
955
956 struct radv_image;
957
958 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
959
960 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
961 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
962
963 void cik_create_gfx_config(struct radv_device *device);
964
965 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
966 int count, const VkViewport *viewports);
967 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
968 int count, const VkRect2D *scissors,
969 const VkViewport *viewports, bool can_use_guardband);
970 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
971 bool instanced_draw, bool indirect_draw,
972 uint32_t draw_vertex_count);
973 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
974 bool predicated,
975 enum chip_class chip_class,
976 bool is_mec,
977 unsigned event, unsigned event_flags,
978 unsigned data_sel,
979 uint64_t va,
980 uint32_t old_fence,
981 uint32_t new_fence);
982
983 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
984 bool predicated,
985 uint64_t va, uint32_t ref,
986 uint32_t mask);
987 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
988 bool predicated,
989 enum chip_class chip_class,
990 uint32_t *fence_ptr, uint64_t va,
991 bool is_mec,
992 enum radv_cmd_flush_bits flush_bits);
993 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
994 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
995 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
996 uint64_t src_va, uint64_t dest_va,
997 uint64_t size);
998 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
999 unsigned size);
1000 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1001 uint64_t size, unsigned value);
1002 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1003 bool
1004 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1005 unsigned size,
1006 unsigned alignment,
1007 unsigned *out_offset,
1008 void **ptr);
1009 void
1010 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1011 const struct radv_subpass *subpass,
1012 bool transitions);
1013 bool
1014 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1015 unsigned size, unsigned alignmnet,
1016 const void *data, unsigned *out_offset);
1017
1018 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1019 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1020 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1021 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1022 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1023 unsigned radv_cayman_get_maxdist(int log_samples);
1024 void radv_device_init_msaa(struct radv_device *device);
1025 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1026 struct radv_image *image,
1027 VkClearDepthStencilValue ds_clear_value,
1028 VkImageAspectFlags aspects);
1029 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1030 struct radv_image *image,
1031 int idx,
1032 uint32_t color_values[2]);
1033 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1034 struct radv_image *image,
1035 bool value);
1036 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1037 struct radeon_winsys_bo *bo,
1038 uint64_t offset, uint64_t size, uint32_t value);
1039 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1040 bool radv_get_memory_fd(struct radv_device *device,
1041 struct radv_device_memory *memory,
1042 int *pFD);
1043
1044 /*
1045 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1046 *
1047 * Limitations: Can't call normal dispatch functions without binding or rebinding
1048 * the compute pipeline.
1049 */
1050 void radv_unaligned_dispatch(
1051 struct radv_cmd_buffer *cmd_buffer,
1052 uint32_t x,
1053 uint32_t y,
1054 uint32_t z);
1055
1056 struct radv_event {
1057 struct radeon_winsys_bo *bo;
1058 uint64_t *map;
1059 };
1060
1061 struct radv_shader_module;
1062
1063 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1064 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1065 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1066 void
1067 radv_hash_shaders(unsigned char *hash,
1068 const VkPipelineShaderStageCreateInfo **stages,
1069 const struct radv_pipeline_layout *layout,
1070 const struct radv_pipeline_key *key,
1071 uint32_t flags);
1072
1073 static inline gl_shader_stage
1074 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1075 {
1076 assert(__builtin_popcount(vk_stage) == 1);
1077 return ffs(vk_stage) - 1;
1078 }
1079
1080 static inline VkShaderStageFlagBits
1081 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1082 {
1083 return (1 << mesa_stage);
1084 }
1085
1086 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1087
1088 #define radv_foreach_stage(stage, stage_bits) \
1089 for (gl_shader_stage stage, \
1090 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1091 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1092 __tmp &= ~(1 << (stage)))
1093
1094 struct radv_depth_stencil_state {
1095 uint32_t db_depth_control;
1096 uint32_t db_stencil_control;
1097 uint32_t db_render_control;
1098 uint32_t db_render_override2;
1099 };
1100
1101 struct radv_blend_state {
1102 uint32_t cb_color_control;
1103 uint32_t cb_target_mask;
1104 uint32_t sx_mrt_blend_opt[8];
1105 uint32_t cb_blend_control[8];
1106
1107 uint32_t spi_shader_col_format;
1108 uint32_t cb_shader_mask;
1109 uint32_t db_alpha_to_mask;
1110 };
1111
1112 unsigned radv_format_meta_fs_key(VkFormat format);
1113
1114 struct radv_raster_state {
1115 uint32_t pa_cl_clip_cntl;
1116 uint32_t spi_interp_control;
1117 uint32_t pa_su_vtx_cntl;
1118 uint32_t pa_su_sc_mode_cntl;
1119 };
1120
1121 struct radv_multisample_state {
1122 uint32_t db_eqaa;
1123 uint32_t pa_sc_line_cntl;
1124 uint32_t pa_sc_mode_cntl_0;
1125 uint32_t pa_sc_mode_cntl_1;
1126 uint32_t pa_sc_aa_config;
1127 uint32_t pa_sc_aa_mask[2];
1128 unsigned num_samples;
1129 };
1130
1131 struct radv_prim_vertex_count {
1132 uint8_t min;
1133 uint8_t incr;
1134 };
1135
1136 struct radv_tessellation_state {
1137 uint32_t ls_hs_config;
1138 uint32_t tcs_in_layout;
1139 uint32_t tcs_out_layout;
1140 uint32_t tcs_out_offsets;
1141 uint32_t offchip_layout;
1142 unsigned num_patches;
1143 unsigned lds_size;
1144 unsigned num_tcs_input_cp;
1145 uint32_t tf_param;
1146 };
1147
1148 struct radv_gs_state {
1149 uint32_t vgt_gs_onchip_cntl;
1150 uint32_t vgt_gs_max_prims_per_subgroup;
1151 uint32_t vgt_esgs_ring_itemsize;
1152 uint32_t lds_size;
1153 };
1154
1155 struct radv_vertex_elements_info {
1156 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1157 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1158 uint32_t binding[MAX_VERTEX_ATTRIBS];
1159 uint32_t offset[MAX_VERTEX_ATTRIBS];
1160 uint32_t count;
1161 };
1162
1163 struct radv_vs_state {
1164 uint32_t pa_cl_vs_out_cntl;
1165 uint32_t spi_shader_pos_format;
1166 uint32_t spi_vs_out_config;
1167 uint32_t vgt_reuse_off;
1168 };
1169
1170 struct radv_binning_state {
1171 uint32_t pa_sc_binner_cntl_0;
1172 uint32_t db_dfsm_control;
1173 };
1174
1175 #define SI_GS_PER_ES 128
1176
1177 struct radv_pipeline {
1178 struct radv_device * device;
1179 struct radv_dynamic_state dynamic_state;
1180
1181 struct radv_pipeline_layout * layout;
1182
1183 bool needs_data_cache;
1184 bool need_indirect_descriptor_sets;
1185 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1186 struct radv_shader_variant *gs_copy_shader;
1187 VkShaderStageFlags active_stages;
1188
1189 struct radv_vertex_elements_info vertex_elements;
1190
1191 uint32_t binding_stride[MAX_VBS];
1192
1193 uint32_t user_data_0[MESA_SHADER_STAGES];
1194 union {
1195 struct {
1196 struct radv_blend_state blend;
1197 struct radv_depth_stencil_state ds;
1198 struct radv_raster_state raster;
1199 struct radv_multisample_state ms;
1200 struct radv_tessellation_state tess;
1201 struct radv_gs_state gs;
1202 struct radv_vs_state vs;
1203 struct radv_binning_state bin;
1204 uint32_t db_shader_control;
1205 uint32_t shader_z_format;
1206 unsigned prim;
1207 unsigned gs_out;
1208 uint32_t vgt_gs_mode;
1209 bool vgt_primitiveid_en;
1210 bool prim_restart_enable;
1211 bool partial_es_wave;
1212 uint8_t primgroup_size;
1213 unsigned esgs_ring_size;
1214 unsigned gsvs_ring_size;
1215 uint32_t ps_input_cntl[32];
1216 uint32_t ps_input_cntl_num;
1217 uint32_t vgt_shader_stages_en;
1218 uint32_t vtx_base_sgpr;
1219 uint32_t base_ia_multi_vgt_param;
1220 bool wd_switch_on_eop;
1221 bool ia_switch_on_eoi;
1222 bool partial_vs_wave;
1223 uint8_t vtx_emit_num;
1224 uint32_t vtx_reuse_depth;
1225 struct radv_prim_vertex_count prim_vertex_count;
1226 bool can_use_guardband;
1227 } graphics;
1228 };
1229
1230 unsigned max_waves;
1231 unsigned scratch_bytes_per_wave;
1232 };
1233
1234 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1235 {
1236 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1237 }
1238
1239 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1240 {
1241 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1242 }
1243
1244 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1245 gl_shader_stage stage,
1246 int idx);
1247
1248 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1249
1250 struct radv_graphics_pipeline_create_info {
1251 bool use_rectlist;
1252 bool db_depth_clear;
1253 bool db_stencil_clear;
1254 bool db_depth_disable_expclear;
1255 bool db_stencil_disable_expclear;
1256 bool db_flush_depth_inplace;
1257 bool db_flush_stencil_inplace;
1258 bool db_resummarize;
1259 uint32_t custom_blend_mode;
1260 };
1261
1262 VkResult
1263 radv_graphics_pipeline_create(VkDevice device,
1264 VkPipelineCache cache,
1265 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1266 const struct radv_graphics_pipeline_create_info *extra,
1267 const VkAllocationCallbacks *alloc,
1268 VkPipeline *pPipeline);
1269
1270 struct vk_format_description;
1271 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1272 int first_non_void);
1273 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1274 int first_non_void);
1275 uint32_t radv_translate_colorformat(VkFormat format);
1276 uint32_t radv_translate_color_numformat(VkFormat format,
1277 const struct vk_format_description *desc,
1278 int first_non_void);
1279 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1280 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1281 uint32_t radv_translate_dbformat(VkFormat format);
1282 uint32_t radv_translate_tex_dataformat(VkFormat format,
1283 const struct vk_format_description *desc,
1284 int first_non_void);
1285 uint32_t radv_translate_tex_numformat(VkFormat format,
1286 const struct vk_format_description *desc,
1287 int first_non_void);
1288 bool radv_format_pack_clear_color(VkFormat format,
1289 uint32_t clear_vals[2],
1290 VkClearColorValue *value);
1291 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1292 bool radv_dcc_formats_compatible(VkFormat format1,
1293 VkFormat format2);
1294
1295 struct radv_fmask_info {
1296 uint64_t offset;
1297 uint64_t size;
1298 unsigned alignment;
1299 unsigned pitch_in_pixels;
1300 unsigned bank_height;
1301 unsigned slice_tile_max;
1302 unsigned tile_mode_index;
1303 unsigned tile_swizzle;
1304 };
1305
1306 struct radv_cmask_info {
1307 uint64_t offset;
1308 uint64_t size;
1309 unsigned alignment;
1310 unsigned slice_tile_max;
1311 };
1312
1313 struct radv_image {
1314 VkImageType type;
1315 /* The original VkFormat provided by the client. This may not match any
1316 * of the actual surface formats.
1317 */
1318 VkFormat vk_format;
1319 VkImageAspectFlags aspects;
1320 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1321 struct ac_surf_info info;
1322 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1323 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1324
1325 VkDeviceSize size;
1326 uint32_t alignment;
1327
1328 unsigned queue_family_mask;
1329 bool exclusive;
1330 bool shareable;
1331
1332 /* Set when bound */
1333 struct radeon_winsys_bo *bo;
1334 VkDeviceSize offset;
1335 uint64_t dcc_offset;
1336 uint64_t htile_offset;
1337 bool tc_compatible_htile;
1338 struct radeon_surf surface;
1339
1340 struct radv_fmask_info fmask;
1341 struct radv_cmask_info cmask;
1342 uint64_t clear_value_offset;
1343 uint64_t dcc_pred_offset;
1344 };
1345
1346 /* Whether the image has a htile that is known consistent with the contents of
1347 * the image. */
1348 bool radv_layout_has_htile(const struct radv_image *image,
1349 VkImageLayout layout,
1350 unsigned queue_mask);
1351
1352 /* Whether the image has a htile that is known consistent with the contents of
1353 * the image and is allowed to be in compressed form.
1354 *
1355 * If this is false reads that don't use the htile should be able to return
1356 * correct results.
1357 */
1358 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1359 VkImageLayout layout,
1360 unsigned queue_mask);
1361
1362 bool radv_layout_can_fast_clear(const struct radv_image *image,
1363 VkImageLayout layout,
1364 unsigned queue_mask);
1365
1366 bool radv_layout_dcc_compressed(const struct radv_image *image,
1367 VkImageLayout layout,
1368 unsigned queue_mask);
1369
1370 static inline bool
1371 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1372 {
1373 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1374 }
1375
1376 static inline bool
1377 radv_htile_enabled(const struct radv_image *image, unsigned level)
1378 {
1379 return image->surface.htile_size && level == 0;
1380 }
1381
1382 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1383
1384 static inline uint32_t
1385 radv_get_layerCount(const struct radv_image *image,
1386 const VkImageSubresourceRange *range)
1387 {
1388 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1389 image->info.array_size - range->baseArrayLayer : range->layerCount;
1390 }
1391
1392 static inline uint32_t
1393 radv_get_levelCount(const struct radv_image *image,
1394 const VkImageSubresourceRange *range)
1395 {
1396 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1397 image->info.levels - range->baseMipLevel : range->levelCount;
1398 }
1399
1400 struct radeon_bo_metadata;
1401 void
1402 radv_init_metadata(struct radv_device *device,
1403 struct radv_image *image,
1404 struct radeon_bo_metadata *metadata);
1405
1406 struct radv_image_view {
1407 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1408 struct radeon_winsys_bo *bo;
1409
1410 VkImageViewType type;
1411 VkImageAspectFlags aspect_mask;
1412 VkFormat vk_format;
1413 uint32_t base_layer;
1414 uint32_t layer_count;
1415 uint32_t base_mip;
1416 uint32_t level_count;
1417 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1418
1419 uint32_t descriptor[16];
1420
1421 /* Descriptor for use as a storage image as opposed to a sampled image.
1422 * This has a few differences for cube maps (e.g. type).
1423 */
1424 uint32_t storage_descriptor[16];
1425 };
1426
1427 struct radv_image_create_info {
1428 const VkImageCreateInfo *vk_info;
1429 bool scanout;
1430 };
1431
1432 VkResult radv_image_create(VkDevice _device,
1433 const struct radv_image_create_info *info,
1434 const VkAllocationCallbacks* alloc,
1435 VkImage *pImage);
1436
1437 void radv_image_view_init(struct radv_image_view *view,
1438 struct radv_device *device,
1439 const VkImageViewCreateInfo* pCreateInfo);
1440
1441 struct radv_buffer_view {
1442 struct radeon_winsys_bo *bo;
1443 VkFormat vk_format;
1444 uint64_t range; /**< VkBufferViewCreateInfo::range */
1445 uint32_t state[4];
1446 };
1447 void radv_buffer_view_init(struct radv_buffer_view *view,
1448 struct radv_device *device,
1449 const VkBufferViewCreateInfo* pCreateInfo);
1450
1451 static inline struct VkExtent3D
1452 radv_sanitize_image_extent(const VkImageType imageType,
1453 const struct VkExtent3D imageExtent)
1454 {
1455 switch (imageType) {
1456 case VK_IMAGE_TYPE_1D:
1457 return (VkExtent3D) { imageExtent.width, 1, 1 };
1458 case VK_IMAGE_TYPE_2D:
1459 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1460 case VK_IMAGE_TYPE_3D:
1461 return imageExtent;
1462 default:
1463 unreachable("invalid image type");
1464 }
1465 }
1466
1467 static inline struct VkOffset3D
1468 radv_sanitize_image_offset(const VkImageType imageType,
1469 const struct VkOffset3D imageOffset)
1470 {
1471 switch (imageType) {
1472 case VK_IMAGE_TYPE_1D:
1473 return (VkOffset3D) { imageOffset.x, 0, 0 };
1474 case VK_IMAGE_TYPE_2D:
1475 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1476 case VK_IMAGE_TYPE_3D:
1477 return imageOffset;
1478 default:
1479 unreachable("invalid image type");
1480 }
1481 }
1482
1483 static inline bool
1484 radv_image_extent_compare(const struct radv_image *image,
1485 const VkExtent3D *extent)
1486 {
1487 if (extent->width != image->info.width ||
1488 extent->height != image->info.height ||
1489 extent->depth != image->info.depth)
1490 return false;
1491 return true;
1492 }
1493
1494 struct radv_sampler {
1495 uint32_t state[4];
1496 };
1497
1498 struct radv_color_buffer_info {
1499 uint64_t cb_color_base;
1500 uint64_t cb_color_cmask;
1501 uint64_t cb_color_fmask;
1502 uint64_t cb_dcc_base;
1503 uint32_t cb_color_pitch;
1504 uint32_t cb_color_slice;
1505 uint32_t cb_color_view;
1506 uint32_t cb_color_info;
1507 uint32_t cb_color_attrib;
1508 uint32_t cb_color_attrib2;
1509 uint32_t cb_dcc_control;
1510 uint32_t cb_color_cmask_slice;
1511 uint32_t cb_color_fmask_slice;
1512 };
1513
1514 struct radv_ds_buffer_info {
1515 uint64_t db_z_read_base;
1516 uint64_t db_stencil_read_base;
1517 uint64_t db_z_write_base;
1518 uint64_t db_stencil_write_base;
1519 uint64_t db_htile_data_base;
1520 uint32_t db_depth_info;
1521 uint32_t db_z_info;
1522 uint32_t db_stencil_info;
1523 uint32_t db_depth_view;
1524 uint32_t db_depth_size;
1525 uint32_t db_depth_slice;
1526 uint32_t db_htile_surface;
1527 uint32_t pa_su_poly_offset_db_fmt_cntl;
1528 uint32_t db_z_info2;
1529 uint32_t db_stencil_info2;
1530 float offset_scale;
1531 };
1532
1533 struct radv_attachment_info {
1534 union {
1535 struct radv_color_buffer_info cb;
1536 struct radv_ds_buffer_info ds;
1537 };
1538 struct radv_image_view *attachment;
1539 };
1540
1541 struct radv_framebuffer {
1542 uint32_t width;
1543 uint32_t height;
1544 uint32_t layers;
1545
1546 uint32_t attachment_count;
1547 struct radv_attachment_info attachments[0];
1548 };
1549
1550 struct radv_subpass_barrier {
1551 VkPipelineStageFlags src_stage_mask;
1552 VkAccessFlags src_access_mask;
1553 VkAccessFlags dst_access_mask;
1554 };
1555
1556 struct radv_subpass {
1557 uint32_t input_count;
1558 uint32_t color_count;
1559 VkAttachmentReference * input_attachments;
1560 VkAttachmentReference * color_attachments;
1561 VkAttachmentReference * resolve_attachments;
1562 VkAttachmentReference depth_stencil_attachment;
1563
1564 /** Subpass has at least one resolve attachment */
1565 bool has_resolve;
1566
1567 struct radv_subpass_barrier start_barrier;
1568
1569 uint32_t view_mask;
1570 };
1571
1572 struct radv_render_pass_attachment {
1573 VkFormat format;
1574 uint32_t samples;
1575 VkAttachmentLoadOp load_op;
1576 VkAttachmentLoadOp stencil_load_op;
1577 VkImageLayout initial_layout;
1578 VkImageLayout final_layout;
1579 uint32_t view_mask;
1580 };
1581
1582 struct radv_render_pass {
1583 uint32_t attachment_count;
1584 uint32_t subpass_count;
1585 VkAttachmentReference * subpass_attachments;
1586 struct radv_render_pass_attachment * attachments;
1587 struct radv_subpass_barrier end_barrier;
1588 struct radv_subpass subpasses[0];
1589 };
1590
1591 VkResult radv_device_init_meta(struct radv_device *device);
1592 void radv_device_finish_meta(struct radv_device *device);
1593
1594 struct radv_query_pool {
1595 struct radeon_winsys_bo *bo;
1596 uint32_t stride;
1597 uint32_t availability_offset;
1598 char *ptr;
1599 VkQueryType type;
1600 uint32_t pipeline_stats_mask;
1601 };
1602
1603 struct radv_semaphore {
1604 /* use a winsys sem for non-exportable */
1605 struct radeon_winsys_sem *sem;
1606 uint32_t syncobj;
1607 uint32_t temp_syncobj;
1608 };
1609
1610 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1611 int num_wait_sems,
1612 const VkSemaphore *wait_sems,
1613 int num_signal_sems,
1614 const VkSemaphore *signal_sems,
1615 VkFence fence);
1616 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1617
1618 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1619 struct radv_descriptor_set *set,
1620 unsigned idx);
1621
1622 void
1623 radv_update_descriptor_sets(struct radv_device *device,
1624 struct radv_cmd_buffer *cmd_buffer,
1625 VkDescriptorSet overrideSet,
1626 uint32_t descriptorWriteCount,
1627 const VkWriteDescriptorSet *pDescriptorWrites,
1628 uint32_t descriptorCopyCount,
1629 const VkCopyDescriptorSet *pDescriptorCopies);
1630
1631 void
1632 radv_update_descriptor_set_with_template(struct radv_device *device,
1633 struct radv_cmd_buffer *cmd_buffer,
1634 struct radv_descriptor_set *set,
1635 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1636 const void *pData);
1637
1638 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1639 VkPipelineBindPoint pipelineBindPoint,
1640 VkPipelineLayout _layout,
1641 uint32_t set,
1642 uint32_t descriptorWriteCount,
1643 const VkWriteDescriptorSet *pDescriptorWrites);
1644
1645 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1646 struct radv_image *image, uint32_t value);
1647 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1648 struct radv_image *image, uint32_t value);
1649
1650 struct radv_fence {
1651 struct radeon_winsys_fence *fence;
1652 bool submitted;
1653 bool signalled;
1654
1655 uint32_t syncobj;
1656 uint32_t temp_syncobj;
1657 };
1658
1659 struct radeon_winsys_sem;
1660
1661 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1662 \
1663 static inline struct __radv_type * \
1664 __radv_type ## _from_handle(__VkType _handle) \
1665 { \
1666 return (struct __radv_type *) _handle; \
1667 } \
1668 \
1669 static inline __VkType \
1670 __radv_type ## _to_handle(struct __radv_type *_obj) \
1671 { \
1672 return (__VkType) _obj; \
1673 }
1674
1675 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1676 \
1677 static inline struct __radv_type * \
1678 __radv_type ## _from_handle(__VkType _handle) \
1679 { \
1680 return (struct __radv_type *)(uintptr_t) _handle; \
1681 } \
1682 \
1683 static inline __VkType \
1684 __radv_type ## _to_handle(struct __radv_type *_obj) \
1685 { \
1686 return (__VkType)(uintptr_t) _obj; \
1687 }
1688
1689 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1690 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1691
1692 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1693 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1694 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1695 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1696 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1697
1698 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1699 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1700 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1701 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1702 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1703 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1704 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1705 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1706 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1709 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1710 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1711 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1712 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1715 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1716 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1719
1720 #endif /* RADV_PRIVATE_H */