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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52 #include "vk_debug_report.h"
53
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60
61 #include <llvm-c/TargetMachine.h>
62
63 /* Pre-declarations needed for WSI entrypoints */
64 struct wl_surface;
65 struct wl_display;
66 typedef struct xcb_connection_t xcb_connection_t;
67 typedef uint32_t xcb_visualid_t;
68 typedef uint32_t xcb_window_t;
69
70 #include <vulkan/vulkan.h>
71 #include <vulkan/vulkan_intel.h>
72 #include <vulkan/vk_icd.h>
73 #include <vulkan/vk_android_native_buffer.h>
74
75 #include "radv_entrypoints.h"
76
77 #include "wsi_common.h"
78
79 #define ATI_VENDOR_ID 0x1002
80
81 #define MAX_VBS 32
82 #define MAX_VERTEX_ATTRIBS 32
83 #define MAX_RTS 8
84 #define MAX_VIEWPORTS 16
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_BUFFERS 16
90 #define MAX_SAMPLES_LOG2 4
91 #define NUM_META_FS_KEYS 13
92 #define RADV_MAX_DRM_DEVICES 8
93 #define MAX_VIEWS 8
94
95 #define NUM_DEPTH_CLEAR_PIPELINES 3
96
97 enum radv_mem_heap {
98 RADV_MEM_HEAP_VRAM,
99 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
100 RADV_MEM_HEAP_GTT,
101 RADV_MEM_HEAP_COUNT
102 };
103
104 enum radv_mem_type {
105 RADV_MEM_TYPE_VRAM,
106 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
107 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
108 RADV_MEM_TYPE_GTT_CACHED,
109 RADV_MEM_TYPE_COUNT
110 };
111
112 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
113
114 static inline uint32_t
115 align_u32(uint32_t v, uint32_t a)
116 {
117 assert(a != 0 && a == (a & -a));
118 return (v + a - 1) & ~(a - 1);
119 }
120
121 static inline uint32_t
122 align_u32_npot(uint32_t v, uint32_t a)
123 {
124 return (v + a - 1) / a * a;
125 }
126
127 static inline uint64_t
128 align_u64(uint64_t v, uint64_t a)
129 {
130 assert(a != 0 && a == (a & -a));
131 return (v + a - 1) & ~(a - 1);
132 }
133
134 static inline int32_t
135 align_i32(int32_t v, int32_t a)
136 {
137 assert(a != 0 && a == (a & -a));
138 return (v + a - 1) & ~(a - 1);
139 }
140
141 /** Alignment must be a power of 2. */
142 static inline bool
143 radv_is_aligned(uintmax_t n, uintmax_t a)
144 {
145 assert(a == (a & -a));
146 return (n & (a - 1)) == 0;
147 }
148
149 static inline uint32_t
150 round_up_u32(uint32_t v, uint32_t a)
151 {
152 return (v + a - 1) / a;
153 }
154
155 static inline uint64_t
156 round_up_u64(uint64_t v, uint64_t a)
157 {
158 return (v + a - 1) / a;
159 }
160
161 static inline uint32_t
162 radv_minify(uint32_t n, uint32_t levels)
163 {
164 if (unlikely(n == 0))
165 return 0;
166 else
167 return MAX2(n >> levels, 1);
168 }
169 static inline float
170 radv_clamp_f(float f, float min, float max)
171 {
172 assert(min < max);
173
174 if (f > max)
175 return max;
176 else if (f < min)
177 return min;
178 else
179 return f;
180 }
181
182 static inline bool
183 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
184 {
185 if (*inout_mask & clear_mask) {
186 *inout_mask &= ~clear_mask;
187 return true;
188 } else {
189 return false;
190 }
191 }
192
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
197
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 })
202
203 /* Whenever we generate an error, pass it through this function. Useful for
204 * debugging, where we can break on it. Only call at error site, not when
205 * propagating errors. Might be useful to plug in a stack trace here.
206 */
207
208 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
209
210 #ifdef DEBUG
211 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
212 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
213 #else
214 #define vk_error(error) error
215 #define vk_errorf(error, format, ...) error
216 #endif
217
218 void __radv_finishme(const char *file, int line, const char *format, ...)
219 radv_printflike(3, 4);
220 void radv_loge(const char *format, ...) radv_printflike(1, 2);
221 void radv_loge_v(const char *format, va_list va);
222
223 /**
224 * Print a FINISHME message, including its source location.
225 */
226 #define radv_finishme(format, ...) \
227 do { \
228 static bool reported = false; \
229 if (!reported) { \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
231 reported = true; \
232 } \
233 } while (0)
234
235 /* A non-fatal assert. Useful for debugging. */
236 #ifdef DEBUG
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 })
241 #else
242 #define radv_assert(x)
243 #endif
244
245 #define stub_return(v) \
246 do { \
247 radv_finishme("stub %s", __func__); \
248 return (v); \
249 } while (0)
250
251 #define stub() \
252 do { \
253 radv_finishme("stub %s", __func__); \
254 return; \
255 } while (0)
256
257 void *radv_lookup_entrypoint(const char *name);
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 char path[20];
267 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
268 uint8_t driver_uuid[VK_UUID_SIZE];
269 uint8_t device_uuid[VK_UUID_SIZE];
270 uint8_t cache_uuid[VK_UUID_SIZE];
271
272 int local_fd;
273 struct wsi_device wsi_device;
274
275 bool has_rbplus; /* if RB+ register exist */
276 bool rbplus_allowed; /* if RB+ is allowed */
277 bool has_clear_state;
278 bool cpdma_prefetch_writes_memory;
279 bool has_scissor_bug;
280
281 /* This is the drivers on-disk cache used as a fallback as opposed to
282 * the pipeline cache defined by apps.
283 */
284 struct disk_cache * disk_cache;
285
286 VkPhysicalDeviceMemoryProperties memory_properties;
287 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
288 };
289
290 struct radv_instance {
291 VK_LOADER_DATA _loader_data;
292
293 VkAllocationCallbacks alloc;
294
295 uint32_t apiVersion;
296 int physicalDeviceCount;
297 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
298
299 uint64_t debug_flags;
300 uint64_t perftest_flags;
301
302 struct vk_debug_report_instance debug_report_callbacks;
303 };
304
305 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
306 void radv_finish_wsi(struct radv_physical_device *physical_device);
307
308 bool radv_instance_extension_supported(const char *name);
309 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
310 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
311 const char *name);
312
313 struct cache_entry;
314
315 struct radv_pipeline_cache {
316 struct radv_device * device;
317 pthread_mutex_t mutex;
318
319 uint32_t total_size;
320 uint32_t table_size;
321 uint32_t kernel_count;
322 struct cache_entry ** hash_table;
323 bool modified;
324
325 VkAllocationCallbacks alloc;
326 };
327
328 struct radv_pipeline_key {
329 uint32_t instance_rate_inputs;
330 unsigned tess_input_vertices;
331 uint32_t col_format;
332 uint32_t is_int8;
333 uint32_t is_int10;
334 uint32_t multisample : 1;
335 uint32_t has_multiview_view_index : 1;
336 };
337
338 void
339 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
340 struct radv_device *device);
341 void
342 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
343 void
344 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
345 const void *data, size_t size);
346
347 struct radv_shader_variant;
348
349 bool
350 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
351 struct radv_pipeline_cache *cache,
352 const unsigned char *sha1,
353 struct radv_shader_variant **variants);
354
355 void
356 radv_pipeline_cache_insert_shaders(struct radv_device *device,
357 struct radv_pipeline_cache *cache,
358 const unsigned char *sha1,
359 struct radv_shader_variant **variants,
360 const void *const *codes,
361 const unsigned *code_sizes);
362
363 enum radv_blit_ds_layout {
364 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
365 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
366 RADV_BLIT_DS_LAYOUT_COUNT,
367 };
368
369 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
370 {
371 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
372 }
373
374 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
375 {
376 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
377 }
378
379 enum radv_meta_dst_layout {
380 RADV_META_DST_LAYOUT_GENERAL,
381 RADV_META_DST_LAYOUT_OPTIMAL,
382 RADV_META_DST_LAYOUT_COUNT,
383 };
384
385 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
386 {
387 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
388 }
389
390 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
391 {
392 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
393 }
394
395 struct radv_meta_state {
396 VkAllocationCallbacks alloc;
397
398 struct radv_pipeline_cache cache;
399
400 /**
401 * Use array element `i` for images with `2^i` samples.
402 */
403 struct {
404 VkRenderPass render_pass[NUM_META_FS_KEYS];
405 VkPipeline color_pipelines[NUM_META_FS_KEYS];
406
407 VkRenderPass depthstencil_rp;
408 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
409 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
410 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
411 } clear[1 + MAX_SAMPLES_LOG2];
412
413 VkPipelineLayout clear_color_p_layout;
414 VkPipelineLayout clear_depth_p_layout;
415 struct {
416 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
417
418 /** Pipeline that blits from a 1D image. */
419 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
420
421 /** Pipeline that blits from a 2D image. */
422 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
423
424 /** Pipeline that blits from a 3D image. */
425 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
426
427 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
428 VkPipeline depth_only_1d_pipeline;
429 VkPipeline depth_only_2d_pipeline;
430 VkPipeline depth_only_3d_pipeline;
431
432 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
433 VkPipeline stencil_only_1d_pipeline;
434 VkPipeline stencil_only_2d_pipeline;
435 VkPipeline stencil_only_3d_pipeline;
436 VkPipelineLayout pipeline_layout;
437 VkDescriptorSetLayout ds_layout;
438 } blit;
439
440 struct {
441 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
442
443 VkPipelineLayout p_layouts[3];
444 VkDescriptorSetLayout ds_layouts[3];
445 VkPipeline pipelines[3][NUM_META_FS_KEYS];
446
447 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
448 VkPipeline depth_only_pipeline[3];
449
450 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
451 VkPipeline stencil_only_pipeline[3];
452 } blit2d;
453
454 struct {
455 VkPipelineLayout img_p_layout;
456 VkDescriptorSetLayout img_ds_layout;
457 VkPipeline pipeline;
458 VkPipeline pipeline_3d;
459 } itob;
460 struct {
461 VkPipelineLayout img_p_layout;
462 VkDescriptorSetLayout img_ds_layout;
463 VkPipeline pipeline;
464 VkPipeline pipeline_3d;
465 } btoi;
466 struct {
467 VkPipelineLayout img_p_layout;
468 VkDescriptorSetLayout img_ds_layout;
469 VkPipeline pipeline;
470 VkPipeline pipeline_3d;
471 } itoi;
472 struct {
473 VkPipelineLayout img_p_layout;
474 VkDescriptorSetLayout img_ds_layout;
475 VkPipeline pipeline;
476 VkPipeline pipeline_3d;
477 } cleari;
478
479 struct {
480 VkPipelineLayout p_layout;
481 VkPipeline pipeline;
482 VkRenderPass pass;
483 } resolve;
484
485 struct {
486 VkDescriptorSetLayout ds_layout;
487 VkPipelineLayout p_layout;
488 struct {
489 VkPipeline pipeline;
490 VkPipeline i_pipeline;
491 VkPipeline srgb_pipeline;
492 } rc[MAX_SAMPLES_LOG2];
493 } resolve_compute;
494
495 struct {
496 VkDescriptorSetLayout ds_layout;
497 VkPipelineLayout p_layout;
498
499 struct {
500 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
501 VkPipeline pipeline[NUM_META_FS_KEYS];
502 } rc[MAX_SAMPLES_LOG2];
503 } resolve_fragment;
504
505 struct {
506 VkPipelineLayout p_layout;
507 VkPipeline decompress_pipeline;
508 VkPipeline resummarize_pipeline;
509 VkRenderPass pass;
510 } depth_decomp[1 + MAX_SAMPLES_LOG2];
511
512 struct {
513 VkPipelineLayout p_layout;
514 VkPipeline cmask_eliminate_pipeline;
515 VkPipeline fmask_decompress_pipeline;
516 VkPipeline dcc_decompress_pipeline;
517 VkRenderPass pass;
518
519 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
520 VkPipelineLayout dcc_decompress_compute_p_layout;
521 VkPipeline dcc_decompress_compute_pipeline;
522 } fast_clear_flush;
523
524 struct {
525 VkPipelineLayout fill_p_layout;
526 VkPipelineLayout copy_p_layout;
527 VkDescriptorSetLayout fill_ds_layout;
528 VkDescriptorSetLayout copy_ds_layout;
529 VkPipeline fill_pipeline;
530 VkPipeline copy_pipeline;
531 } buffer;
532
533 struct {
534 VkDescriptorSetLayout ds_layout;
535 VkPipelineLayout p_layout;
536 VkPipeline occlusion_query_pipeline;
537 VkPipeline pipeline_statistics_query_pipeline;
538 } query;
539 };
540
541 /* queue types */
542 #define RADV_QUEUE_GENERAL 0
543 #define RADV_QUEUE_COMPUTE 1
544 #define RADV_QUEUE_TRANSFER 2
545
546 #define RADV_MAX_QUEUE_FAMILIES 3
547
548 enum ring_type radv_queue_family_to_ring(int f);
549
550 struct radv_queue {
551 VK_LOADER_DATA _loader_data;
552 struct radv_device * device;
553 struct radeon_winsys_ctx *hw_ctx;
554 enum radeon_ctx_priority priority;
555 uint32_t queue_family_index;
556 int queue_idx;
557
558 uint32_t scratch_size;
559 uint32_t compute_scratch_size;
560 uint32_t esgs_ring_size;
561 uint32_t gsvs_ring_size;
562 bool has_tess_rings;
563 bool has_sample_positions;
564
565 struct radeon_winsys_bo *scratch_bo;
566 struct radeon_winsys_bo *descriptor_bo;
567 struct radeon_winsys_bo *compute_scratch_bo;
568 struct radeon_winsys_bo *esgs_ring_bo;
569 struct radeon_winsys_bo *gsvs_ring_bo;
570 struct radeon_winsys_bo *tess_factor_ring_bo;
571 struct radeon_winsys_bo *tess_offchip_ring_bo;
572 struct radeon_winsys_cs *initial_preamble_cs;
573 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
574 struct radeon_winsys_cs *continue_preamble_cs;
575 };
576
577 struct radv_device {
578 VK_LOADER_DATA _loader_data;
579
580 VkAllocationCallbacks alloc;
581
582 struct radv_instance * instance;
583 struct radeon_winsys *ws;
584
585 struct radv_meta_state meta_state;
586
587 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
588 int queue_count[RADV_MAX_QUEUE_FAMILIES];
589 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
590
591 bool always_use_syncobj;
592 bool llvm_supports_spill;
593 bool has_distributed_tess;
594 bool pbb_allowed;
595 bool dfsm_allowed;
596 uint32_t tess_offchip_block_dw_size;
597 uint32_t scratch_waves;
598 uint32_t dispatch_initiator;
599
600 uint32_t gs_table_depth;
601
602 /* MSAA sample locations.
603 * The first index is the sample index.
604 * The second index is the coordinate: X, Y. */
605 float sample_locations_1x[1][2];
606 float sample_locations_2x[2][2];
607 float sample_locations_4x[4][2];
608 float sample_locations_8x[8][2];
609 float sample_locations_16x[16][2];
610
611 /* CIK and later */
612 uint32_t gfx_init_size_dw;
613 struct radeon_winsys_bo *gfx_init;
614
615 struct radeon_winsys_bo *trace_bo;
616 uint32_t *trace_id_ptr;
617
618 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
619 bool keep_shader_info;
620
621 struct radv_physical_device *physical_device;
622
623 /* Backup in-memory cache to be used if the app doesn't provide one */
624 struct radv_pipeline_cache * mem_cache;
625
626 /*
627 * use different counters so MSAA MRTs get consecutive surface indices,
628 * even if MASK is allocated in between.
629 */
630 uint32_t image_mrt_offset_counter;
631 uint32_t fmask_mrt_offset_counter;
632 struct list_head shader_slabs;
633 mtx_t shader_slab_mutex;
634
635 /* For detecting VM faults reported by dmesg. */
636 uint64_t dmesg_timestamp;
637 };
638
639 struct radv_device_memory {
640 struct radeon_winsys_bo *bo;
641 /* for dedicated allocations */
642 struct radv_image *image;
643 struct radv_buffer *buffer;
644 uint32_t type_index;
645 VkDeviceSize map_size;
646 void * map;
647 };
648
649
650 struct radv_descriptor_range {
651 uint64_t va;
652 uint32_t size;
653 };
654
655 struct radv_descriptor_set {
656 const struct radv_descriptor_set_layout *layout;
657 uint32_t size;
658
659 struct radeon_winsys_bo *bo;
660 uint64_t va;
661 uint32_t *mapped_ptr;
662 struct radv_descriptor_range *dynamic_descriptors;
663
664 struct radeon_winsys_bo *descriptors[0];
665 };
666
667 struct radv_push_descriptor_set
668 {
669 struct radv_descriptor_set set;
670 uint32_t capacity;
671 };
672
673 struct radv_descriptor_pool_entry {
674 uint32_t offset;
675 uint32_t size;
676 struct radv_descriptor_set *set;
677 };
678
679 struct radv_descriptor_pool {
680 struct radeon_winsys_bo *bo;
681 uint8_t *mapped_ptr;
682 uint64_t current_offset;
683 uint64_t size;
684
685 uint8_t *host_memory_base;
686 uint8_t *host_memory_ptr;
687 uint8_t *host_memory_end;
688
689 uint32_t entry_count;
690 uint32_t max_entry_count;
691 struct radv_descriptor_pool_entry entries[0];
692 };
693
694 struct radv_descriptor_update_template_entry {
695 VkDescriptorType descriptor_type;
696
697 /* The number of descriptors to update */
698 uint32_t descriptor_count;
699
700 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
701 uint32_t dst_offset;
702
703 /* In dwords. Not valid/used for dynamic descriptors */
704 uint32_t dst_stride;
705
706 uint32_t buffer_offset;
707
708 /* Only valid for combined image samplers and samplers */
709 uint16_t has_sampler;
710
711 /* In bytes */
712 size_t src_offset;
713 size_t src_stride;
714
715 /* For push descriptors */
716 const uint32_t *immutable_samplers;
717 };
718
719 struct radv_descriptor_update_template {
720 uint32_t entry_count;
721 struct radv_descriptor_update_template_entry entry[0];
722 };
723
724 struct radv_buffer {
725 struct radv_device * device;
726 VkDeviceSize size;
727
728 VkBufferUsageFlags usage;
729 VkBufferCreateFlags flags;
730
731 /* Set when bound */
732 struct radeon_winsys_bo * bo;
733 VkDeviceSize offset;
734
735 bool shareable;
736 };
737
738 enum radv_dynamic_state_bits {
739 RADV_DYNAMIC_VIEWPORT = 1 << 0,
740 RADV_DYNAMIC_SCISSOR = 1 << 1,
741 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
742 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
743 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
744 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
745 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
746 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
747 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
748 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
749 RADV_DYNAMIC_ALL = (1 << 10) - 1,
750 };
751
752 enum radv_cmd_dirty_bits {
753 /* Keep the dynamic state dirty bits in sync with
754 * enum radv_dynamic_state_bits */
755 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
756 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
757 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
758 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
759 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
760 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
761 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
762 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
763 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
764 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
765 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
766 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
767 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
768 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
769 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
770 };
771
772 enum radv_cmd_flush_bits {
773 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
774 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
775 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
776 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
777 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
778 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
779 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
780 /* Same as above, but only writes back and doesn't invalidate */
781 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
782 /* Framebuffer caches */
783 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
784 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
785 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
786 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
787 /* Engine synchronization. */
788 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
789 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
790 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
791 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
792
793 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
794 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
795 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
796 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
797 };
798
799 struct radv_vertex_binding {
800 struct radv_buffer * buffer;
801 VkDeviceSize offset;
802 };
803
804 struct radv_viewport_state {
805 uint32_t count;
806 VkViewport viewports[MAX_VIEWPORTS];
807 };
808
809 struct radv_scissor_state {
810 uint32_t count;
811 VkRect2D scissors[MAX_SCISSORS];
812 };
813
814 struct radv_discard_rectangle_state {
815 uint32_t count;
816 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
817 };
818
819 struct radv_dynamic_state {
820 /**
821 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
822 * Defines the set of saved dynamic state.
823 */
824 uint32_t mask;
825
826 struct radv_viewport_state viewport;
827
828 struct radv_scissor_state scissor;
829
830 float line_width;
831
832 struct {
833 float bias;
834 float clamp;
835 float slope;
836 } depth_bias;
837
838 float blend_constants[4];
839
840 struct {
841 float min;
842 float max;
843 } depth_bounds;
844
845 struct {
846 uint32_t front;
847 uint32_t back;
848 } stencil_compare_mask;
849
850 struct {
851 uint32_t front;
852 uint32_t back;
853 } stencil_write_mask;
854
855 struct {
856 uint32_t front;
857 uint32_t back;
858 } stencil_reference;
859
860 struct radv_discard_rectangle_state discard_rectangle;
861 };
862
863 extern const struct radv_dynamic_state default_dynamic_state;
864
865 const char *
866 radv_get_debug_option_name(int id);
867
868 const char *
869 radv_get_perftest_option_name(int id);
870
871 /**
872 * Attachment state when recording a renderpass instance.
873 *
874 * The clear value is valid only if there exists a pending clear.
875 */
876 struct radv_attachment_state {
877 VkImageAspectFlags pending_clear_aspects;
878 uint32_t cleared_views;
879 VkClearValue clear_value;
880 VkImageLayout current_layout;
881 };
882
883 struct radv_cmd_state {
884 /* Vertex descriptors */
885 bool vb_prefetch_dirty;
886 uint64_t vb_va;
887 unsigned vb_size;
888
889 bool push_descriptors_dirty;
890 bool predicating;
891 uint32_t dirty;
892
893 struct radv_pipeline * pipeline;
894 struct radv_pipeline * emitted_pipeline;
895 struct radv_pipeline * compute_pipeline;
896 struct radv_pipeline * emitted_compute_pipeline;
897 struct radv_framebuffer * framebuffer;
898 struct radv_render_pass * pass;
899 const struct radv_subpass * subpass;
900 struct radv_dynamic_state dynamic;
901 struct radv_attachment_state * attachments;
902 VkRect2D render_area;
903
904 /* Index buffer */
905 struct radv_buffer *index_buffer;
906 uint64_t index_offset;
907 uint32_t index_type;
908 uint32_t max_index_count;
909 uint64_t index_va;
910 int32_t last_index_type;
911
912 int32_t last_primitive_reset_en;
913 uint32_t last_primitive_reset_index;
914 enum radv_cmd_flush_bits flush_bits;
915 unsigned active_occlusion_queries;
916 float offset_scale;
917 uint32_t descriptors_dirty;
918 uint32_t valid_descriptors;
919 uint32_t trace_id;
920 uint32_t last_ia_multi_vgt_param;
921
922 uint32_t last_num_instances;
923 uint32_t last_first_instance;
924 uint32_t last_vertex_offset;
925 };
926
927 struct radv_cmd_pool {
928 VkAllocationCallbacks alloc;
929 struct list_head cmd_buffers;
930 struct list_head free_cmd_buffers;
931 uint32_t queue_family_index;
932 };
933
934 struct radv_cmd_buffer_upload {
935 uint8_t *map;
936 unsigned offset;
937 uint64_t size;
938 struct radeon_winsys_bo *upload_bo;
939 struct list_head list;
940 };
941
942 enum radv_cmd_buffer_status {
943 RADV_CMD_BUFFER_STATUS_INVALID,
944 RADV_CMD_BUFFER_STATUS_INITIAL,
945 RADV_CMD_BUFFER_STATUS_RECORDING,
946 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
947 RADV_CMD_BUFFER_STATUS_PENDING,
948 };
949
950 struct radv_cmd_buffer {
951 VK_LOADER_DATA _loader_data;
952
953 struct radv_device * device;
954
955 struct radv_cmd_pool * pool;
956 struct list_head pool_link;
957
958 VkCommandBufferUsageFlags usage_flags;
959 VkCommandBufferLevel level;
960 enum radv_cmd_buffer_status status;
961 struct radeon_winsys_cs *cs;
962 struct radv_cmd_state state;
963 struct radv_vertex_binding vertex_bindings[MAX_VBS];
964 uint32_t queue_family_index;
965
966 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
967 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
968 VkShaderStageFlags push_constant_stages;
969 struct radv_push_descriptor_set push_descriptors;
970 struct radv_descriptor_set meta_push_descriptors;
971 struct radv_descriptor_set *descriptors[MAX_SETS];
972
973 struct radv_cmd_buffer_upload upload;
974
975 uint32_t scratch_size_needed;
976 uint32_t compute_scratch_size_needed;
977 uint32_t esgs_ring_size_needed;
978 uint32_t gsvs_ring_size_needed;
979 bool tess_rings_needed;
980 bool sample_positions_needed;
981
982 VkResult record_result;
983
984 int ring_offsets_idx; /* just used for verification */
985 uint32_t gfx9_fence_offset;
986 struct radeon_winsys_bo *gfx9_fence_bo;
987 uint32_t gfx9_fence_idx;
988 };
989
990 struct radv_image;
991
992 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
993
994 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
995 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
996
997 void cik_create_gfx_config(struct radv_device *device);
998
999 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1000 int count, const VkViewport *viewports);
1001 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1002 int count, const VkRect2D *scissors,
1003 const VkViewport *viewports, bool can_use_guardband);
1004 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1005 bool instanced_draw, bool indirect_draw,
1006 uint32_t draw_vertex_count);
1007 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1008 bool predicated,
1009 enum chip_class chip_class,
1010 bool is_mec,
1011 unsigned event, unsigned event_flags,
1012 unsigned data_sel,
1013 uint64_t va,
1014 uint32_t old_fence,
1015 uint32_t new_fence);
1016
1017 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1018 bool predicated,
1019 uint64_t va, uint32_t ref,
1020 uint32_t mask);
1021 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1022 bool predicated,
1023 enum chip_class chip_class,
1024 uint32_t *fence_ptr, uint64_t va,
1025 bool is_mec,
1026 enum radv_cmd_flush_bits flush_bits);
1027 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1028 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1029 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1030 uint64_t src_va, uint64_t dest_va,
1031 uint64_t size);
1032 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1033 unsigned size);
1034 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1035 uint64_t size, unsigned value);
1036 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1037 bool
1038 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1039 unsigned size,
1040 unsigned alignment,
1041 unsigned *out_offset,
1042 void **ptr);
1043 void
1044 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1045 const struct radv_subpass *subpass,
1046 bool transitions);
1047 bool
1048 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1049 unsigned size, unsigned alignmnet,
1050 const void *data, unsigned *out_offset);
1051
1052 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1053 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1054 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1055 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1056 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1057 unsigned radv_cayman_get_maxdist(int log_samples);
1058 void radv_device_init_msaa(struct radv_device *device);
1059 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1060 struct radv_image *image,
1061 VkClearDepthStencilValue ds_clear_value,
1062 VkImageAspectFlags aspects);
1063 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1064 struct radv_image *image,
1065 int idx,
1066 uint32_t color_values[2]);
1067 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1068 struct radv_image *image,
1069 bool value);
1070 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1071 struct radeon_winsys_bo *bo,
1072 uint64_t offset, uint64_t size, uint32_t value);
1073 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1074 bool radv_get_memory_fd(struct radv_device *device,
1075 struct radv_device_memory *memory,
1076 int *pFD);
1077
1078 /*
1079 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1080 *
1081 * Limitations: Can't call normal dispatch functions without binding or rebinding
1082 * the compute pipeline.
1083 */
1084 void radv_unaligned_dispatch(
1085 struct radv_cmd_buffer *cmd_buffer,
1086 uint32_t x,
1087 uint32_t y,
1088 uint32_t z);
1089
1090 struct radv_event {
1091 struct radeon_winsys_bo *bo;
1092 uint64_t *map;
1093 };
1094
1095 struct radv_shader_module;
1096
1097 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1098 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1099 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1100 void
1101 radv_hash_shaders(unsigned char *hash,
1102 const VkPipelineShaderStageCreateInfo **stages,
1103 const struct radv_pipeline_layout *layout,
1104 const struct radv_pipeline_key *key,
1105 uint32_t flags);
1106
1107 static inline gl_shader_stage
1108 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1109 {
1110 assert(__builtin_popcount(vk_stage) == 1);
1111 return ffs(vk_stage) - 1;
1112 }
1113
1114 static inline VkShaderStageFlagBits
1115 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1116 {
1117 return (1 << mesa_stage);
1118 }
1119
1120 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1121
1122 #define radv_foreach_stage(stage, stage_bits) \
1123 for (gl_shader_stage stage, \
1124 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1125 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1126 __tmp &= ~(1 << (stage)))
1127
1128 struct radv_depth_stencil_state {
1129 uint32_t db_depth_control;
1130 uint32_t db_stencil_control;
1131 uint32_t db_render_control;
1132 uint32_t db_render_override2;
1133 };
1134
1135 struct radv_blend_state {
1136 uint32_t cb_color_control;
1137 uint32_t cb_target_mask;
1138 uint32_t sx_mrt_blend_opt[8];
1139 uint32_t cb_blend_control[8];
1140
1141 uint32_t spi_shader_col_format;
1142 uint32_t cb_shader_mask;
1143 uint32_t db_alpha_to_mask;
1144 };
1145
1146 unsigned radv_format_meta_fs_key(VkFormat format);
1147
1148 struct radv_raster_state {
1149 uint32_t pa_cl_clip_cntl;
1150 uint32_t spi_interp_control;
1151 uint32_t pa_su_vtx_cntl;
1152 uint32_t pa_su_sc_mode_cntl;
1153 };
1154
1155 struct radv_multisample_state {
1156 uint32_t db_eqaa;
1157 uint32_t pa_sc_line_cntl;
1158 uint32_t pa_sc_mode_cntl_0;
1159 uint32_t pa_sc_mode_cntl_1;
1160 uint32_t pa_sc_aa_config;
1161 uint32_t pa_sc_aa_mask[2];
1162 unsigned num_samples;
1163 };
1164
1165 struct radv_prim_vertex_count {
1166 uint8_t min;
1167 uint8_t incr;
1168 };
1169
1170 struct radv_tessellation_state {
1171 uint32_t ls_hs_config;
1172 uint32_t tcs_in_layout;
1173 uint32_t tcs_out_layout;
1174 uint32_t tcs_out_offsets;
1175 uint32_t offchip_layout;
1176 unsigned num_patches;
1177 unsigned lds_size;
1178 unsigned num_tcs_input_cp;
1179 uint32_t tf_param;
1180 };
1181
1182 struct radv_gs_state {
1183 uint32_t vgt_gs_onchip_cntl;
1184 uint32_t vgt_gs_max_prims_per_subgroup;
1185 uint32_t vgt_esgs_ring_itemsize;
1186 uint32_t lds_size;
1187 };
1188
1189 struct radv_vertex_elements_info {
1190 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1191 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1192 uint32_t binding[MAX_VERTEX_ATTRIBS];
1193 uint32_t offset[MAX_VERTEX_ATTRIBS];
1194 uint32_t count;
1195 };
1196
1197 struct radv_vs_state {
1198 uint32_t pa_cl_vs_out_cntl;
1199 uint32_t spi_shader_pos_format;
1200 uint32_t spi_vs_out_config;
1201 uint32_t vgt_reuse_off;
1202 };
1203
1204 struct radv_binning_state {
1205 uint32_t pa_sc_binner_cntl_0;
1206 uint32_t db_dfsm_control;
1207 };
1208
1209 #define SI_GS_PER_ES 128
1210
1211 struct radv_pipeline {
1212 struct radv_device * device;
1213 struct radv_dynamic_state dynamic_state;
1214
1215 struct radv_pipeline_layout * layout;
1216
1217 bool needs_data_cache;
1218 bool need_indirect_descriptor_sets;
1219 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1220 struct radv_shader_variant *gs_copy_shader;
1221 VkShaderStageFlags active_stages;
1222
1223 struct radv_vertex_elements_info vertex_elements;
1224
1225 uint32_t binding_stride[MAX_VBS];
1226
1227 uint32_t user_data_0[MESA_SHADER_STAGES];
1228 union {
1229 struct {
1230 struct radv_blend_state blend;
1231 struct radv_depth_stencil_state ds;
1232 struct radv_raster_state raster;
1233 struct radv_multisample_state ms;
1234 struct radv_tessellation_state tess;
1235 struct radv_gs_state gs;
1236 struct radv_vs_state vs;
1237 struct radv_binning_state bin;
1238 uint32_t db_shader_control;
1239 uint32_t shader_z_format;
1240 unsigned prim;
1241 unsigned gs_out;
1242 uint32_t vgt_gs_mode;
1243 bool vgt_primitiveid_en;
1244 bool prim_restart_enable;
1245 bool partial_es_wave;
1246 uint8_t primgroup_size;
1247 unsigned esgs_ring_size;
1248 unsigned gsvs_ring_size;
1249 uint32_t ps_input_cntl[32];
1250 uint32_t ps_input_cntl_num;
1251 uint32_t vgt_shader_stages_en;
1252 uint32_t vtx_base_sgpr;
1253 uint32_t base_ia_multi_vgt_param;
1254 bool wd_switch_on_eop;
1255 bool ia_switch_on_eoi;
1256 bool partial_vs_wave;
1257 uint8_t vtx_emit_num;
1258 uint32_t vtx_reuse_depth;
1259 struct radv_prim_vertex_count prim_vertex_count;
1260 bool can_use_guardband;
1261 uint32_t pa_sc_cliprect_rule;
1262 } graphics;
1263 };
1264
1265 unsigned max_waves;
1266 unsigned scratch_bytes_per_wave;
1267 };
1268
1269 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1270 {
1271 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1272 }
1273
1274 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1275 {
1276 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1277 }
1278
1279 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1280 gl_shader_stage stage,
1281 int idx);
1282
1283 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1284
1285 struct radv_graphics_pipeline_create_info {
1286 bool use_rectlist;
1287 bool db_depth_clear;
1288 bool db_stencil_clear;
1289 bool db_depth_disable_expclear;
1290 bool db_stencil_disable_expclear;
1291 bool db_flush_depth_inplace;
1292 bool db_flush_stencil_inplace;
1293 bool db_resummarize;
1294 uint32_t custom_blend_mode;
1295 };
1296
1297 VkResult
1298 radv_graphics_pipeline_create(VkDevice device,
1299 VkPipelineCache cache,
1300 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1301 const struct radv_graphics_pipeline_create_info *extra,
1302 const VkAllocationCallbacks *alloc,
1303 VkPipeline *pPipeline);
1304
1305 struct vk_format_description;
1306 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1307 int first_non_void);
1308 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1309 int first_non_void);
1310 uint32_t radv_translate_colorformat(VkFormat format);
1311 uint32_t radv_translate_color_numformat(VkFormat format,
1312 const struct vk_format_description *desc,
1313 int first_non_void);
1314 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1315 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1316 uint32_t radv_translate_dbformat(VkFormat format);
1317 uint32_t radv_translate_tex_dataformat(VkFormat format,
1318 const struct vk_format_description *desc,
1319 int first_non_void);
1320 uint32_t radv_translate_tex_numformat(VkFormat format,
1321 const struct vk_format_description *desc,
1322 int first_non_void);
1323 bool radv_format_pack_clear_color(VkFormat format,
1324 uint32_t clear_vals[2],
1325 VkClearColorValue *value);
1326 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1327 bool radv_dcc_formats_compatible(VkFormat format1,
1328 VkFormat format2);
1329
1330 struct radv_fmask_info {
1331 uint64_t offset;
1332 uint64_t size;
1333 unsigned alignment;
1334 unsigned pitch_in_pixels;
1335 unsigned bank_height;
1336 unsigned slice_tile_max;
1337 unsigned tile_mode_index;
1338 unsigned tile_swizzle;
1339 };
1340
1341 struct radv_cmask_info {
1342 uint64_t offset;
1343 uint64_t size;
1344 unsigned alignment;
1345 unsigned slice_tile_max;
1346 };
1347
1348 struct radv_image {
1349 VkImageType type;
1350 /* The original VkFormat provided by the client. This may not match any
1351 * of the actual surface formats.
1352 */
1353 VkFormat vk_format;
1354 VkImageAspectFlags aspects;
1355 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1356 struct ac_surf_info info;
1357 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1358 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1359
1360 VkDeviceSize size;
1361 uint32_t alignment;
1362
1363 unsigned queue_family_mask;
1364 bool exclusive;
1365 bool shareable;
1366
1367 /* Set when bound */
1368 struct radeon_winsys_bo *bo;
1369 VkDeviceSize offset;
1370 uint64_t dcc_offset;
1371 uint64_t htile_offset;
1372 bool tc_compatible_htile;
1373 struct radeon_surf surface;
1374
1375 struct radv_fmask_info fmask;
1376 struct radv_cmask_info cmask;
1377 uint64_t clear_value_offset;
1378 uint64_t dcc_pred_offset;
1379
1380 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1381 VkDeviceMemory owned_memory;
1382 };
1383
1384 /* Whether the image has a htile that is known consistent with the contents of
1385 * the image. */
1386 bool radv_layout_has_htile(const struct radv_image *image,
1387 VkImageLayout layout,
1388 unsigned queue_mask);
1389
1390 /* Whether the image has a htile that is known consistent with the contents of
1391 * the image and is allowed to be in compressed form.
1392 *
1393 * If this is false reads that don't use the htile should be able to return
1394 * correct results.
1395 */
1396 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1397 VkImageLayout layout,
1398 unsigned queue_mask);
1399
1400 bool radv_layout_can_fast_clear(const struct radv_image *image,
1401 VkImageLayout layout,
1402 unsigned queue_mask);
1403
1404 bool radv_layout_dcc_compressed(const struct radv_image *image,
1405 VkImageLayout layout,
1406 unsigned queue_mask);
1407
1408 static inline bool
1409 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1410 {
1411 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1412 }
1413
1414 static inline bool
1415 radv_htile_enabled(const struct radv_image *image, unsigned level)
1416 {
1417 return image->surface.htile_size && level == 0;
1418 }
1419
1420 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1421
1422 static inline uint32_t
1423 radv_get_layerCount(const struct radv_image *image,
1424 const VkImageSubresourceRange *range)
1425 {
1426 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1427 image->info.array_size - range->baseArrayLayer : range->layerCount;
1428 }
1429
1430 static inline uint32_t
1431 radv_get_levelCount(const struct radv_image *image,
1432 const VkImageSubresourceRange *range)
1433 {
1434 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1435 image->info.levels - range->baseMipLevel : range->levelCount;
1436 }
1437
1438 struct radeon_bo_metadata;
1439 void
1440 radv_init_metadata(struct radv_device *device,
1441 struct radv_image *image,
1442 struct radeon_bo_metadata *metadata);
1443
1444 struct radv_image_view {
1445 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1446 struct radeon_winsys_bo *bo;
1447
1448 VkImageViewType type;
1449 VkImageAspectFlags aspect_mask;
1450 VkFormat vk_format;
1451 uint32_t base_layer;
1452 uint32_t layer_count;
1453 uint32_t base_mip;
1454 uint32_t level_count;
1455 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1456
1457 uint32_t descriptor[16];
1458
1459 /* Descriptor for use as a storage image as opposed to a sampled image.
1460 * This has a few differences for cube maps (e.g. type).
1461 */
1462 uint32_t storage_descriptor[16];
1463 };
1464
1465 struct radv_image_create_info {
1466 const VkImageCreateInfo *vk_info;
1467 bool scanout;
1468 bool no_metadata_planes;
1469 };
1470
1471 VkResult radv_image_create(VkDevice _device,
1472 const struct radv_image_create_info *info,
1473 const VkAllocationCallbacks* alloc,
1474 VkImage *pImage);
1475
1476 VkResult
1477 radv_image_from_gralloc(VkDevice device_h,
1478 const VkImageCreateInfo *base_info,
1479 const VkNativeBufferANDROID *gralloc_info,
1480 const VkAllocationCallbacks *alloc,
1481 VkImage *out_image_h);
1482
1483 void radv_image_view_init(struct radv_image_view *view,
1484 struct radv_device *device,
1485 const VkImageViewCreateInfo* pCreateInfo);
1486
1487 struct radv_buffer_view {
1488 struct radeon_winsys_bo *bo;
1489 VkFormat vk_format;
1490 uint64_t range; /**< VkBufferViewCreateInfo::range */
1491 uint32_t state[4];
1492 };
1493 void radv_buffer_view_init(struct radv_buffer_view *view,
1494 struct radv_device *device,
1495 const VkBufferViewCreateInfo* pCreateInfo);
1496
1497 static inline struct VkExtent3D
1498 radv_sanitize_image_extent(const VkImageType imageType,
1499 const struct VkExtent3D imageExtent)
1500 {
1501 switch (imageType) {
1502 case VK_IMAGE_TYPE_1D:
1503 return (VkExtent3D) { imageExtent.width, 1, 1 };
1504 case VK_IMAGE_TYPE_2D:
1505 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1506 case VK_IMAGE_TYPE_3D:
1507 return imageExtent;
1508 default:
1509 unreachable("invalid image type");
1510 }
1511 }
1512
1513 static inline struct VkOffset3D
1514 radv_sanitize_image_offset(const VkImageType imageType,
1515 const struct VkOffset3D imageOffset)
1516 {
1517 switch (imageType) {
1518 case VK_IMAGE_TYPE_1D:
1519 return (VkOffset3D) { imageOffset.x, 0, 0 };
1520 case VK_IMAGE_TYPE_2D:
1521 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1522 case VK_IMAGE_TYPE_3D:
1523 return imageOffset;
1524 default:
1525 unreachable("invalid image type");
1526 }
1527 }
1528
1529 static inline bool
1530 radv_image_extent_compare(const struct radv_image *image,
1531 const VkExtent3D *extent)
1532 {
1533 if (extent->width != image->info.width ||
1534 extent->height != image->info.height ||
1535 extent->depth != image->info.depth)
1536 return false;
1537 return true;
1538 }
1539
1540 struct radv_sampler {
1541 uint32_t state[4];
1542 };
1543
1544 struct radv_color_buffer_info {
1545 uint64_t cb_color_base;
1546 uint64_t cb_color_cmask;
1547 uint64_t cb_color_fmask;
1548 uint64_t cb_dcc_base;
1549 uint32_t cb_color_pitch;
1550 uint32_t cb_color_slice;
1551 uint32_t cb_color_view;
1552 uint32_t cb_color_info;
1553 uint32_t cb_color_attrib;
1554 uint32_t cb_color_attrib2;
1555 uint32_t cb_dcc_control;
1556 uint32_t cb_color_cmask_slice;
1557 uint32_t cb_color_fmask_slice;
1558 };
1559
1560 struct radv_ds_buffer_info {
1561 uint64_t db_z_read_base;
1562 uint64_t db_stencil_read_base;
1563 uint64_t db_z_write_base;
1564 uint64_t db_stencil_write_base;
1565 uint64_t db_htile_data_base;
1566 uint32_t db_depth_info;
1567 uint32_t db_z_info;
1568 uint32_t db_stencil_info;
1569 uint32_t db_depth_view;
1570 uint32_t db_depth_size;
1571 uint32_t db_depth_slice;
1572 uint32_t db_htile_surface;
1573 uint32_t pa_su_poly_offset_db_fmt_cntl;
1574 uint32_t db_z_info2;
1575 uint32_t db_stencil_info2;
1576 float offset_scale;
1577 };
1578
1579 struct radv_attachment_info {
1580 union {
1581 struct radv_color_buffer_info cb;
1582 struct radv_ds_buffer_info ds;
1583 };
1584 struct radv_image_view *attachment;
1585 };
1586
1587 struct radv_framebuffer {
1588 uint32_t width;
1589 uint32_t height;
1590 uint32_t layers;
1591
1592 uint32_t attachment_count;
1593 struct radv_attachment_info attachments[0];
1594 };
1595
1596 struct radv_subpass_barrier {
1597 VkPipelineStageFlags src_stage_mask;
1598 VkAccessFlags src_access_mask;
1599 VkAccessFlags dst_access_mask;
1600 };
1601
1602 struct radv_subpass {
1603 uint32_t input_count;
1604 uint32_t color_count;
1605 VkAttachmentReference * input_attachments;
1606 VkAttachmentReference * color_attachments;
1607 VkAttachmentReference * resolve_attachments;
1608 VkAttachmentReference depth_stencil_attachment;
1609
1610 /** Subpass has at least one resolve attachment */
1611 bool has_resolve;
1612
1613 struct radv_subpass_barrier start_barrier;
1614
1615 uint32_t view_mask;
1616 };
1617
1618 struct radv_render_pass_attachment {
1619 VkFormat format;
1620 uint32_t samples;
1621 VkAttachmentLoadOp load_op;
1622 VkAttachmentLoadOp stencil_load_op;
1623 VkImageLayout initial_layout;
1624 VkImageLayout final_layout;
1625 uint32_t view_mask;
1626 };
1627
1628 struct radv_render_pass {
1629 uint32_t attachment_count;
1630 uint32_t subpass_count;
1631 VkAttachmentReference * subpass_attachments;
1632 struct radv_render_pass_attachment * attachments;
1633 struct radv_subpass_barrier end_barrier;
1634 struct radv_subpass subpasses[0];
1635 };
1636
1637 VkResult radv_device_init_meta(struct radv_device *device);
1638 void radv_device_finish_meta(struct radv_device *device);
1639
1640 struct radv_query_pool {
1641 struct radeon_winsys_bo *bo;
1642 uint32_t stride;
1643 uint32_t availability_offset;
1644 char *ptr;
1645 VkQueryType type;
1646 uint32_t pipeline_stats_mask;
1647 };
1648
1649 struct radv_semaphore {
1650 /* use a winsys sem for non-exportable */
1651 struct radeon_winsys_sem *sem;
1652 uint32_t syncobj;
1653 uint32_t temp_syncobj;
1654 };
1655
1656 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1657 int num_wait_sems,
1658 const VkSemaphore *wait_sems,
1659 int num_signal_sems,
1660 const VkSemaphore *signal_sems,
1661 VkFence fence);
1662 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1663
1664 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1665 struct radv_descriptor_set *set,
1666 unsigned idx);
1667
1668 void
1669 radv_update_descriptor_sets(struct radv_device *device,
1670 struct radv_cmd_buffer *cmd_buffer,
1671 VkDescriptorSet overrideSet,
1672 uint32_t descriptorWriteCount,
1673 const VkWriteDescriptorSet *pDescriptorWrites,
1674 uint32_t descriptorCopyCount,
1675 const VkCopyDescriptorSet *pDescriptorCopies);
1676
1677 void
1678 radv_update_descriptor_set_with_template(struct radv_device *device,
1679 struct radv_cmd_buffer *cmd_buffer,
1680 struct radv_descriptor_set *set,
1681 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1682 const void *pData);
1683
1684 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1685 VkPipelineBindPoint pipelineBindPoint,
1686 VkPipelineLayout _layout,
1687 uint32_t set,
1688 uint32_t descriptorWriteCount,
1689 const VkWriteDescriptorSet *pDescriptorWrites);
1690
1691 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1692 struct radv_image *image, uint32_t value);
1693 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1694 struct radv_image *image, uint32_t value);
1695
1696 struct radv_fence {
1697 struct radeon_winsys_fence *fence;
1698 bool submitted;
1699 bool signalled;
1700
1701 uint32_t syncobj;
1702 uint32_t temp_syncobj;
1703 };
1704
1705 struct radeon_winsys_sem;
1706
1707 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1708 \
1709 static inline struct __radv_type * \
1710 __radv_type ## _from_handle(__VkType _handle) \
1711 { \
1712 return (struct __radv_type *) _handle; \
1713 } \
1714 \
1715 static inline __VkType \
1716 __radv_type ## _to_handle(struct __radv_type *_obj) \
1717 { \
1718 return (__VkType) _obj; \
1719 }
1720
1721 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1722 \
1723 static inline struct __radv_type * \
1724 __radv_type ## _from_handle(__VkType _handle) \
1725 { \
1726 return (struct __radv_type *)(uintptr_t) _handle; \
1727 } \
1728 \
1729 static inline __VkType \
1730 __radv_type ## _to_handle(struct __radv_type *_obj) \
1731 { \
1732 return (__VkType)(uintptr_t) _obj; \
1733 }
1734
1735 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1736 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1737
1738 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1739 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1740 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1741 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1742 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1743
1744 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1745 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1746 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1747 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1748 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1749 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1750 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1751 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1752 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1753 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1754 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1755 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1756 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1757 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1758 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1759 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1760 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1761 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1762 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1763 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1764 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1765
1766 #endif /* RADV_PRIVATE_H */