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radv: Track enabled extensions.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52 #include "vk_debug_report.h"
53
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60 #include "radv_extensions.h"
61
62 #include <llvm-c/TargetMachine.h>
63
64 /* Pre-declarations needed for WSI entrypoints */
65 struct wl_surface;
66 struct wl_display;
67 typedef struct xcb_connection_t xcb_connection_t;
68 typedef uint32_t xcb_visualid_t;
69 typedef uint32_t xcb_window_t;
70
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
75
76 #include "radv_entrypoints.h"
77
78 #include "wsi_common.h"
79
80 #define ATI_VENDOR_ID 0x1002
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VIEWPORTS 16
86 #define MAX_SCISSORS 16
87 #define MAX_DISCARD_RECTANGLES 4
88 #define MAX_PUSH_CONSTANTS_SIZE 128
89 #define MAX_PUSH_DESCRIPTORS 32
90 #define MAX_DYNAMIC_BUFFERS 16
91 #define MAX_SAMPLES_LOG2 4
92 #define NUM_META_FS_KEYS 13
93 #define RADV_MAX_DRM_DEVICES 8
94 #define MAX_VIEWS 8
95
96 #define NUM_DEPTH_CLEAR_PIPELINES 3
97
98 enum radv_mem_heap {
99 RADV_MEM_HEAP_VRAM,
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
101 RADV_MEM_HEAP_GTT,
102 RADV_MEM_HEAP_COUNT
103 };
104
105 enum radv_mem_type {
106 RADV_MEM_TYPE_VRAM,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
109 RADV_MEM_TYPE_GTT_CACHED,
110 RADV_MEM_TYPE_COUNT
111 };
112
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
114
115 static inline uint32_t
116 align_u32(uint32_t v, uint32_t a)
117 {
118 assert(a != 0 && a == (a & -a));
119 return (v + a - 1) & ~(a - 1);
120 }
121
122 static inline uint32_t
123 align_u32_npot(uint32_t v, uint32_t a)
124 {
125 return (v + a - 1) / a * a;
126 }
127
128 static inline uint64_t
129 align_u64(uint64_t v, uint64_t a)
130 {
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
133 }
134
135 static inline int32_t
136 align_i32(int32_t v, int32_t a)
137 {
138 assert(a != 0 && a == (a & -a));
139 return (v + a - 1) & ~(a - 1);
140 }
141
142 /** Alignment must be a power of 2. */
143 static inline bool
144 radv_is_aligned(uintmax_t n, uintmax_t a)
145 {
146 assert(a == (a & -a));
147 return (n & (a - 1)) == 0;
148 }
149
150 static inline uint32_t
151 round_up_u32(uint32_t v, uint32_t a)
152 {
153 return (v + a - 1) / a;
154 }
155
156 static inline uint64_t
157 round_up_u64(uint64_t v, uint64_t a)
158 {
159 return (v + a - 1) / a;
160 }
161
162 static inline uint32_t
163 radv_minify(uint32_t n, uint32_t levels)
164 {
165 if (unlikely(n == 0))
166 return 0;
167 else
168 return MAX2(n >> levels, 1);
169 }
170 static inline float
171 radv_clamp_f(float f, float min, float max)
172 {
173 assert(min < max);
174
175 if (f > max)
176 return max;
177 else if (f < min)
178 return min;
179 else
180 return f;
181 }
182
183 static inline bool
184 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
185 {
186 if (*inout_mask & clear_mask) {
187 *inout_mask &= ~clear_mask;
188 return true;
189 } else {
190 return false;
191 }
192 }
193
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
198
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
202 })
203
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
207 */
208
209 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
210
211 #ifdef DEBUG
212 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
213 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
214 #else
215 #define vk_error(error) error
216 #define vk_errorf(error, format, ...) error
217 #endif
218
219 void __radv_finishme(const char *file, int line, const char *format, ...)
220 radv_printflike(3, 4);
221 void radv_loge(const char *format, ...) radv_printflike(1, 2);
222 void radv_loge_v(const char *format, va_list va);
223
224 /**
225 * Print a FINISHME message, including its source location.
226 */
227 #define radv_finishme(format, ...) \
228 do { \
229 static bool reported = false; \
230 if (!reported) { \
231 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
232 reported = true; \
233 } \
234 } while (0)
235
236 /* A non-fatal assert. Useful for debugging. */
237 #ifdef DEBUG
238 #define radv_assert(x) ({ \
239 if (unlikely(!(x))) \
240 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
241 })
242 #else
243 #define radv_assert(x)
244 #endif
245
246 #define stub_return(v) \
247 do { \
248 radv_finishme("stub %s", __func__); \
249 return (v); \
250 } while (0)
251
252 #define stub() \
253 do { \
254 radv_finishme("stub %s", __func__); \
255 return; \
256 } while (0)
257
258 void *radv_lookup_entrypoint(const char *name);
259
260 struct radv_physical_device {
261 VK_LOADER_DATA _loader_data;
262
263 struct radv_instance * instance;
264
265 struct radeon_winsys *ws;
266 struct radeon_info rad_info;
267 char path[20];
268 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
269 uint8_t driver_uuid[VK_UUID_SIZE];
270 uint8_t device_uuid[VK_UUID_SIZE];
271 uint8_t cache_uuid[VK_UUID_SIZE];
272
273 int local_fd;
274 struct wsi_device wsi_device;
275
276 bool has_rbplus; /* if RB+ register exist */
277 bool rbplus_allowed; /* if RB+ is allowed */
278 bool has_clear_state;
279 bool cpdma_prefetch_writes_memory;
280 bool has_scissor_bug;
281
282 /* This is the drivers on-disk cache used as a fallback as opposed to
283 * the pipeline cache defined by apps.
284 */
285 struct disk_cache * disk_cache;
286
287 VkPhysicalDeviceMemoryProperties memory_properties;
288 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
289
290 struct radv_device_extension_table supported_extensions;
291 };
292
293 struct radv_instance {
294 VK_LOADER_DATA _loader_data;
295
296 VkAllocationCallbacks alloc;
297
298 uint32_t apiVersion;
299 int physicalDeviceCount;
300 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
301
302 uint64_t debug_flags;
303 uint64_t perftest_flags;
304
305 struct vk_debug_report_instance debug_report_callbacks;
306
307 struct radv_instance_extension_table enabled_extensions;
308 };
309
310 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
311 void radv_finish_wsi(struct radv_physical_device *physical_device);
312
313 bool radv_instance_extension_supported(const char *name);
314 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
315 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
316 const char *name);
317
318 struct cache_entry;
319
320 struct radv_pipeline_cache {
321 struct radv_device * device;
322 pthread_mutex_t mutex;
323
324 uint32_t total_size;
325 uint32_t table_size;
326 uint32_t kernel_count;
327 struct cache_entry ** hash_table;
328 bool modified;
329
330 VkAllocationCallbacks alloc;
331 };
332
333 struct radv_pipeline_key {
334 uint32_t instance_rate_inputs;
335 unsigned tess_input_vertices;
336 uint32_t col_format;
337 uint32_t is_int8;
338 uint32_t is_int10;
339 uint8_t log2_ps_iter_samples;
340 uint8_t log2_num_samples;
341 uint32_t multisample : 1;
342 uint32_t has_multiview_view_index : 1;
343 };
344
345 void
346 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
347 struct radv_device *device);
348 void
349 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
350 void
351 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
352 const void *data, size_t size);
353
354 struct radv_shader_variant;
355
356 bool
357 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
358 struct radv_pipeline_cache *cache,
359 const unsigned char *sha1,
360 struct radv_shader_variant **variants);
361
362 void
363 radv_pipeline_cache_insert_shaders(struct radv_device *device,
364 struct radv_pipeline_cache *cache,
365 const unsigned char *sha1,
366 struct radv_shader_variant **variants,
367 const void *const *codes,
368 const unsigned *code_sizes);
369
370 enum radv_blit_ds_layout {
371 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
372 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
373 RADV_BLIT_DS_LAYOUT_COUNT,
374 };
375
376 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
377 {
378 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
379 }
380
381 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
382 {
383 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
384 }
385
386 enum radv_meta_dst_layout {
387 RADV_META_DST_LAYOUT_GENERAL,
388 RADV_META_DST_LAYOUT_OPTIMAL,
389 RADV_META_DST_LAYOUT_COUNT,
390 };
391
392 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
393 {
394 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
395 }
396
397 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
398 {
399 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
400 }
401
402 struct radv_meta_state {
403 VkAllocationCallbacks alloc;
404
405 struct radv_pipeline_cache cache;
406
407 /**
408 * Use array element `i` for images with `2^i` samples.
409 */
410 struct {
411 VkRenderPass render_pass[NUM_META_FS_KEYS];
412 VkPipeline color_pipelines[NUM_META_FS_KEYS];
413
414 VkRenderPass depthstencil_rp;
415 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
416 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
417 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
418 } clear[1 + MAX_SAMPLES_LOG2];
419
420 VkPipelineLayout clear_color_p_layout;
421 VkPipelineLayout clear_depth_p_layout;
422 struct {
423 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
424
425 /** Pipeline that blits from a 1D image. */
426 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
427
428 /** Pipeline that blits from a 2D image. */
429 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
430
431 /** Pipeline that blits from a 3D image. */
432 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
433
434 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
435 VkPipeline depth_only_1d_pipeline;
436 VkPipeline depth_only_2d_pipeline;
437 VkPipeline depth_only_3d_pipeline;
438
439 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
440 VkPipeline stencil_only_1d_pipeline;
441 VkPipeline stencil_only_2d_pipeline;
442 VkPipeline stencil_only_3d_pipeline;
443 VkPipelineLayout pipeline_layout;
444 VkDescriptorSetLayout ds_layout;
445 } blit;
446
447 struct {
448 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
449
450 VkPipelineLayout p_layouts[3];
451 VkDescriptorSetLayout ds_layouts[3];
452 VkPipeline pipelines[3][NUM_META_FS_KEYS];
453
454 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
455 VkPipeline depth_only_pipeline[3];
456
457 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
458 VkPipeline stencil_only_pipeline[3];
459 } blit2d;
460
461 struct {
462 VkPipelineLayout img_p_layout;
463 VkDescriptorSetLayout img_ds_layout;
464 VkPipeline pipeline;
465 VkPipeline pipeline_3d;
466 } itob;
467 struct {
468 VkPipelineLayout img_p_layout;
469 VkDescriptorSetLayout img_ds_layout;
470 VkPipeline pipeline;
471 VkPipeline pipeline_3d;
472 } btoi;
473 struct {
474 VkPipelineLayout img_p_layout;
475 VkDescriptorSetLayout img_ds_layout;
476 VkPipeline pipeline;
477 VkPipeline pipeline_3d;
478 } itoi;
479 struct {
480 VkPipelineLayout img_p_layout;
481 VkDescriptorSetLayout img_ds_layout;
482 VkPipeline pipeline;
483 VkPipeline pipeline_3d;
484 } cleari;
485
486 struct {
487 VkPipelineLayout p_layout;
488 VkPipeline pipeline[NUM_META_FS_KEYS];
489 VkRenderPass pass[NUM_META_FS_KEYS];
490 } resolve;
491
492 struct {
493 VkDescriptorSetLayout ds_layout;
494 VkPipelineLayout p_layout;
495 struct {
496 VkPipeline pipeline;
497 VkPipeline i_pipeline;
498 VkPipeline srgb_pipeline;
499 } rc[MAX_SAMPLES_LOG2];
500 } resolve_compute;
501
502 struct {
503 VkDescriptorSetLayout ds_layout;
504 VkPipelineLayout p_layout;
505
506 struct {
507 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
508 VkPipeline pipeline[NUM_META_FS_KEYS];
509 } rc[MAX_SAMPLES_LOG2];
510 } resolve_fragment;
511
512 struct {
513 VkPipelineLayout p_layout;
514 VkPipeline decompress_pipeline;
515 VkPipeline resummarize_pipeline;
516 VkRenderPass pass;
517 } depth_decomp[1 + MAX_SAMPLES_LOG2];
518
519 struct {
520 VkPipelineLayout p_layout;
521 VkPipeline cmask_eliminate_pipeline;
522 VkPipeline fmask_decompress_pipeline;
523 VkPipeline dcc_decompress_pipeline;
524 VkRenderPass pass;
525
526 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
527 VkPipelineLayout dcc_decompress_compute_p_layout;
528 VkPipeline dcc_decompress_compute_pipeline;
529 } fast_clear_flush;
530
531 struct {
532 VkPipelineLayout fill_p_layout;
533 VkPipelineLayout copy_p_layout;
534 VkDescriptorSetLayout fill_ds_layout;
535 VkDescriptorSetLayout copy_ds_layout;
536 VkPipeline fill_pipeline;
537 VkPipeline copy_pipeline;
538 } buffer;
539
540 struct {
541 VkDescriptorSetLayout ds_layout;
542 VkPipelineLayout p_layout;
543 VkPipeline occlusion_query_pipeline;
544 VkPipeline pipeline_statistics_query_pipeline;
545 } query;
546 };
547
548 /* queue types */
549 #define RADV_QUEUE_GENERAL 0
550 #define RADV_QUEUE_COMPUTE 1
551 #define RADV_QUEUE_TRANSFER 2
552
553 #define RADV_MAX_QUEUE_FAMILIES 3
554
555 enum ring_type radv_queue_family_to_ring(int f);
556
557 struct radv_queue {
558 VK_LOADER_DATA _loader_data;
559 struct radv_device * device;
560 struct radeon_winsys_ctx *hw_ctx;
561 enum radeon_ctx_priority priority;
562 uint32_t queue_family_index;
563 int queue_idx;
564
565 uint32_t scratch_size;
566 uint32_t compute_scratch_size;
567 uint32_t esgs_ring_size;
568 uint32_t gsvs_ring_size;
569 bool has_tess_rings;
570 bool has_sample_positions;
571
572 struct radeon_winsys_bo *scratch_bo;
573 struct radeon_winsys_bo *descriptor_bo;
574 struct radeon_winsys_bo *compute_scratch_bo;
575 struct radeon_winsys_bo *esgs_ring_bo;
576 struct radeon_winsys_bo *gsvs_ring_bo;
577 struct radeon_winsys_bo *tess_factor_ring_bo;
578 struct radeon_winsys_bo *tess_offchip_ring_bo;
579 struct radeon_winsys_cs *initial_preamble_cs;
580 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
581 struct radeon_winsys_cs *continue_preamble_cs;
582 };
583
584 struct radv_device {
585 VK_LOADER_DATA _loader_data;
586
587 VkAllocationCallbacks alloc;
588
589 struct radv_instance * instance;
590 struct radeon_winsys *ws;
591
592 struct radv_meta_state meta_state;
593
594 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
595 int queue_count[RADV_MAX_QUEUE_FAMILIES];
596 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
597
598 bool always_use_syncobj;
599 bool llvm_supports_spill;
600 bool has_distributed_tess;
601 bool pbb_allowed;
602 bool dfsm_allowed;
603 uint32_t tess_offchip_block_dw_size;
604 uint32_t scratch_waves;
605 uint32_t dispatch_initiator;
606
607 uint32_t gs_table_depth;
608
609 /* MSAA sample locations.
610 * The first index is the sample index.
611 * The second index is the coordinate: X, Y. */
612 float sample_locations_1x[1][2];
613 float sample_locations_2x[2][2];
614 float sample_locations_4x[4][2];
615 float sample_locations_8x[8][2];
616 float sample_locations_16x[16][2];
617
618 /* CIK and later */
619 uint32_t gfx_init_size_dw;
620 struct radeon_winsys_bo *gfx_init;
621
622 struct radeon_winsys_bo *trace_bo;
623 uint32_t *trace_id_ptr;
624
625 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
626 bool keep_shader_info;
627
628 struct radv_physical_device *physical_device;
629
630 /* Backup in-memory cache to be used if the app doesn't provide one */
631 struct radv_pipeline_cache * mem_cache;
632
633 /*
634 * use different counters so MSAA MRTs get consecutive surface indices,
635 * even if MASK is allocated in between.
636 */
637 uint32_t image_mrt_offset_counter;
638 uint32_t fmask_mrt_offset_counter;
639 struct list_head shader_slabs;
640 mtx_t shader_slab_mutex;
641
642 /* For detecting VM faults reported by dmesg. */
643 uint64_t dmesg_timestamp;
644
645 struct radv_device_extension_table enabled_extensions;
646 };
647
648 struct radv_device_memory {
649 struct radeon_winsys_bo *bo;
650 /* for dedicated allocations */
651 struct radv_image *image;
652 struct radv_buffer *buffer;
653 uint32_t type_index;
654 VkDeviceSize map_size;
655 void * map;
656 void * user_ptr;
657 };
658
659
660 struct radv_descriptor_range {
661 uint64_t va;
662 uint32_t size;
663 };
664
665 struct radv_descriptor_set {
666 const struct radv_descriptor_set_layout *layout;
667 uint32_t size;
668
669 struct radeon_winsys_bo *bo;
670 uint64_t va;
671 uint32_t *mapped_ptr;
672 struct radv_descriptor_range *dynamic_descriptors;
673
674 struct radeon_winsys_bo *descriptors[0];
675 };
676
677 struct radv_push_descriptor_set
678 {
679 struct radv_descriptor_set set;
680 uint32_t capacity;
681 };
682
683 struct radv_descriptor_pool_entry {
684 uint32_t offset;
685 uint32_t size;
686 struct radv_descriptor_set *set;
687 };
688
689 struct radv_descriptor_pool {
690 struct radeon_winsys_bo *bo;
691 uint8_t *mapped_ptr;
692 uint64_t current_offset;
693 uint64_t size;
694
695 uint8_t *host_memory_base;
696 uint8_t *host_memory_ptr;
697 uint8_t *host_memory_end;
698
699 uint32_t entry_count;
700 uint32_t max_entry_count;
701 struct radv_descriptor_pool_entry entries[0];
702 };
703
704 struct radv_descriptor_update_template_entry {
705 VkDescriptorType descriptor_type;
706
707 /* The number of descriptors to update */
708 uint32_t descriptor_count;
709
710 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
711 uint32_t dst_offset;
712
713 /* In dwords. Not valid/used for dynamic descriptors */
714 uint32_t dst_stride;
715
716 uint32_t buffer_offset;
717
718 /* Only valid for combined image samplers and samplers */
719 uint16_t has_sampler;
720
721 /* In bytes */
722 size_t src_offset;
723 size_t src_stride;
724
725 /* For push descriptors */
726 const uint32_t *immutable_samplers;
727 };
728
729 struct radv_descriptor_update_template {
730 uint32_t entry_count;
731 VkPipelineBindPoint bind_point;
732 struct radv_descriptor_update_template_entry entry[0];
733 };
734
735 struct radv_buffer {
736 struct radv_device * device;
737 VkDeviceSize size;
738
739 VkBufferUsageFlags usage;
740 VkBufferCreateFlags flags;
741
742 /* Set when bound */
743 struct radeon_winsys_bo * bo;
744 VkDeviceSize offset;
745
746 bool shareable;
747 };
748
749 enum radv_dynamic_state_bits {
750 RADV_DYNAMIC_VIEWPORT = 1 << 0,
751 RADV_DYNAMIC_SCISSOR = 1 << 1,
752 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
753 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
754 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
755 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
756 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
757 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
758 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
759 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
760 RADV_DYNAMIC_ALL = (1 << 10) - 1,
761 };
762
763 enum radv_cmd_dirty_bits {
764 /* Keep the dynamic state dirty bits in sync with
765 * enum radv_dynamic_state_bits */
766 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
767 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
768 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
769 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
770 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
771 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
772 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
773 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
774 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
775 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
776 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
777 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
778 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
779 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
780 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
781 };
782
783 enum radv_cmd_flush_bits {
784 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
785 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
786 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
787 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
788 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
789 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
790 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
791 /* Same as above, but only writes back and doesn't invalidate */
792 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
793 /* Framebuffer caches */
794 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
795 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
796 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
797 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
798 /* Engine synchronization. */
799 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
800 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
801 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
802 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
803
804 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
805 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
806 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
807 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
808 };
809
810 struct radv_vertex_binding {
811 struct radv_buffer * buffer;
812 VkDeviceSize offset;
813 };
814
815 struct radv_viewport_state {
816 uint32_t count;
817 VkViewport viewports[MAX_VIEWPORTS];
818 };
819
820 struct radv_scissor_state {
821 uint32_t count;
822 VkRect2D scissors[MAX_SCISSORS];
823 };
824
825 struct radv_discard_rectangle_state {
826 uint32_t count;
827 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
828 };
829
830 struct radv_dynamic_state {
831 /**
832 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
833 * Defines the set of saved dynamic state.
834 */
835 uint32_t mask;
836
837 struct radv_viewport_state viewport;
838
839 struct radv_scissor_state scissor;
840
841 float line_width;
842
843 struct {
844 float bias;
845 float clamp;
846 float slope;
847 } depth_bias;
848
849 float blend_constants[4];
850
851 struct {
852 float min;
853 float max;
854 } depth_bounds;
855
856 struct {
857 uint32_t front;
858 uint32_t back;
859 } stencil_compare_mask;
860
861 struct {
862 uint32_t front;
863 uint32_t back;
864 } stencil_write_mask;
865
866 struct {
867 uint32_t front;
868 uint32_t back;
869 } stencil_reference;
870
871 struct radv_discard_rectangle_state discard_rectangle;
872 };
873
874 extern const struct radv_dynamic_state default_dynamic_state;
875
876 const char *
877 radv_get_debug_option_name(int id);
878
879 const char *
880 radv_get_perftest_option_name(int id);
881
882 /**
883 * Attachment state when recording a renderpass instance.
884 *
885 * The clear value is valid only if there exists a pending clear.
886 */
887 struct radv_attachment_state {
888 VkImageAspectFlags pending_clear_aspects;
889 uint32_t cleared_views;
890 VkClearValue clear_value;
891 VkImageLayout current_layout;
892 };
893
894 struct radv_descriptor_state {
895 struct radv_descriptor_set *sets[MAX_SETS];
896 uint32_t dirty;
897 uint32_t valid;
898 struct radv_push_descriptor_set push_set;
899 bool push_dirty;
900 };
901
902 struct radv_cmd_state {
903 /* Vertex descriptors */
904 bool vb_prefetch_dirty;
905 uint64_t vb_va;
906 unsigned vb_size;
907
908 bool predicating;
909 uint32_t dirty;
910
911 struct radv_pipeline * pipeline;
912 struct radv_pipeline * emitted_pipeline;
913 struct radv_pipeline * compute_pipeline;
914 struct radv_pipeline * emitted_compute_pipeline;
915 struct radv_framebuffer * framebuffer;
916 struct radv_render_pass * pass;
917 const struct radv_subpass * subpass;
918 struct radv_dynamic_state dynamic;
919 struct radv_attachment_state * attachments;
920 VkRect2D render_area;
921
922 /* Index buffer */
923 struct radv_buffer *index_buffer;
924 uint64_t index_offset;
925 uint32_t index_type;
926 uint32_t max_index_count;
927 uint64_t index_va;
928 int32_t last_index_type;
929
930 int32_t last_primitive_reset_en;
931 uint32_t last_primitive_reset_index;
932 enum radv_cmd_flush_bits flush_bits;
933 unsigned active_occlusion_queries;
934 float offset_scale;
935 uint32_t trace_id;
936 uint32_t last_ia_multi_vgt_param;
937
938 uint32_t last_num_instances;
939 uint32_t last_first_instance;
940 uint32_t last_vertex_offset;
941 };
942
943 struct radv_cmd_pool {
944 VkAllocationCallbacks alloc;
945 struct list_head cmd_buffers;
946 struct list_head free_cmd_buffers;
947 uint32_t queue_family_index;
948 };
949
950 struct radv_cmd_buffer_upload {
951 uint8_t *map;
952 unsigned offset;
953 uint64_t size;
954 struct radeon_winsys_bo *upload_bo;
955 struct list_head list;
956 };
957
958 enum radv_cmd_buffer_status {
959 RADV_CMD_BUFFER_STATUS_INVALID,
960 RADV_CMD_BUFFER_STATUS_INITIAL,
961 RADV_CMD_BUFFER_STATUS_RECORDING,
962 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
963 RADV_CMD_BUFFER_STATUS_PENDING,
964 };
965
966 struct radv_cmd_buffer {
967 VK_LOADER_DATA _loader_data;
968
969 struct radv_device * device;
970
971 struct radv_cmd_pool * pool;
972 struct list_head pool_link;
973
974 VkCommandBufferUsageFlags usage_flags;
975 VkCommandBufferLevel level;
976 enum radv_cmd_buffer_status status;
977 struct radeon_winsys_cs *cs;
978 struct radv_cmd_state state;
979 struct radv_vertex_binding vertex_bindings[MAX_VBS];
980 uint32_t queue_family_index;
981
982 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
983 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
984 VkShaderStageFlags push_constant_stages;
985 struct radv_descriptor_set meta_push_descriptors;
986
987 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
988
989 struct radv_cmd_buffer_upload upload;
990
991 uint32_t scratch_size_needed;
992 uint32_t compute_scratch_size_needed;
993 uint32_t esgs_ring_size_needed;
994 uint32_t gsvs_ring_size_needed;
995 bool tess_rings_needed;
996 bool sample_positions_needed;
997
998 VkResult record_result;
999
1000 int ring_offsets_idx; /* just used for verification */
1001 uint32_t gfx9_fence_offset;
1002 struct radeon_winsys_bo *gfx9_fence_bo;
1003 uint32_t gfx9_fence_idx;
1004 };
1005
1006 struct radv_image;
1007
1008 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1009
1010 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1011 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1012
1013 void cik_create_gfx_config(struct radv_device *device);
1014
1015 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1016 int count, const VkViewport *viewports);
1017 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1018 int count, const VkRect2D *scissors,
1019 const VkViewport *viewports, bool can_use_guardband);
1020 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1021 bool instanced_draw, bool indirect_draw,
1022 uint32_t draw_vertex_count);
1023 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1024 bool predicated,
1025 enum chip_class chip_class,
1026 bool is_mec,
1027 unsigned event, unsigned event_flags,
1028 unsigned data_sel,
1029 uint64_t va,
1030 uint32_t old_fence,
1031 uint32_t new_fence);
1032
1033 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1034 bool predicated,
1035 uint64_t va, uint32_t ref,
1036 uint32_t mask);
1037 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1038 enum chip_class chip_class,
1039 uint32_t *fence_ptr, uint64_t va,
1040 bool is_mec,
1041 enum radv_cmd_flush_bits flush_bits);
1042 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1043 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1044 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1045 uint64_t src_va, uint64_t dest_va,
1046 uint64_t size);
1047 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1048 unsigned size);
1049 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1050 uint64_t size, unsigned value);
1051 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1052 bool
1053 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1054 unsigned size,
1055 unsigned alignment,
1056 unsigned *out_offset,
1057 void **ptr);
1058 void
1059 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1060 const struct radv_subpass *subpass,
1061 bool transitions);
1062 bool
1063 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1064 unsigned size, unsigned alignmnet,
1065 const void *data, unsigned *out_offset);
1066
1067 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1068 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1069 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1070 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1071 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1072 unsigned radv_cayman_get_maxdist(int log_samples);
1073 void radv_device_init_msaa(struct radv_device *device);
1074 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1075 struct radv_image *image,
1076 VkClearDepthStencilValue ds_clear_value,
1077 VkImageAspectFlags aspects);
1078 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1079 struct radv_image *image,
1080 int idx,
1081 uint32_t color_values[2]);
1082 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1083 struct radv_image *image,
1084 bool value);
1085 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1086 struct radeon_winsys_bo *bo,
1087 uint64_t offset, uint64_t size, uint32_t value);
1088 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1089 bool radv_get_memory_fd(struct radv_device *device,
1090 struct radv_device_memory *memory,
1091 int *pFD);
1092
1093 static inline struct radv_descriptor_state *
1094 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1095 VkPipelineBindPoint bind_point)
1096 {
1097 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1098 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1099 return &cmd_buffer->descriptors[bind_point];
1100 }
1101
1102 /*
1103 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1104 *
1105 * Limitations: Can't call normal dispatch functions without binding or rebinding
1106 * the compute pipeline.
1107 */
1108 void radv_unaligned_dispatch(
1109 struct radv_cmd_buffer *cmd_buffer,
1110 uint32_t x,
1111 uint32_t y,
1112 uint32_t z);
1113
1114 struct radv_event {
1115 struct radeon_winsys_bo *bo;
1116 uint64_t *map;
1117 };
1118
1119 struct radv_shader_module;
1120
1121 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1122 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1123 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1124 void
1125 radv_hash_shaders(unsigned char *hash,
1126 const VkPipelineShaderStageCreateInfo **stages,
1127 const struct radv_pipeline_layout *layout,
1128 const struct radv_pipeline_key *key,
1129 uint32_t flags);
1130
1131 static inline gl_shader_stage
1132 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1133 {
1134 assert(__builtin_popcount(vk_stage) == 1);
1135 return ffs(vk_stage) - 1;
1136 }
1137
1138 static inline VkShaderStageFlagBits
1139 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1140 {
1141 return (1 << mesa_stage);
1142 }
1143
1144 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1145
1146 #define radv_foreach_stage(stage, stage_bits) \
1147 for (gl_shader_stage stage, \
1148 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1149 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1150 __tmp &= ~(1 << (stage)))
1151
1152 unsigned radv_format_meta_fs_key(VkFormat format);
1153
1154 struct radv_multisample_state {
1155 uint32_t db_eqaa;
1156 uint32_t pa_sc_line_cntl;
1157 uint32_t pa_sc_mode_cntl_0;
1158 uint32_t pa_sc_mode_cntl_1;
1159 uint32_t pa_sc_aa_config;
1160 uint32_t pa_sc_aa_mask[2];
1161 unsigned num_samples;
1162 };
1163
1164 struct radv_prim_vertex_count {
1165 uint8_t min;
1166 uint8_t incr;
1167 };
1168
1169 struct radv_vertex_elements_info {
1170 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1171 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1172 uint32_t binding[MAX_VERTEX_ATTRIBS];
1173 uint32_t offset[MAX_VERTEX_ATTRIBS];
1174 uint32_t count;
1175 };
1176
1177 struct radv_ia_multi_vgt_param_helpers {
1178 uint32_t base;
1179 bool partial_es_wave;
1180 uint8_t primgroup_size;
1181 bool wd_switch_on_eop;
1182 bool ia_switch_on_eoi;
1183 bool partial_vs_wave;
1184 };
1185
1186 #define SI_GS_PER_ES 128
1187
1188 struct radv_pipeline {
1189 struct radv_device * device;
1190 struct radv_dynamic_state dynamic_state;
1191
1192 struct radv_pipeline_layout * layout;
1193
1194 bool needs_data_cache;
1195 bool need_indirect_descriptor_sets;
1196 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1197 struct radv_shader_variant *gs_copy_shader;
1198 VkShaderStageFlags active_stages;
1199
1200 struct radeon_winsys_cs cs;
1201
1202 struct radv_vertex_elements_info vertex_elements;
1203
1204 uint32_t binding_stride[MAX_VBS];
1205
1206 uint32_t user_data_0[MESA_SHADER_STAGES];
1207 union {
1208 struct {
1209 struct radv_multisample_state ms;
1210 uint32_t spi_baryc_cntl;
1211 bool prim_restart_enable;
1212 unsigned esgs_ring_size;
1213 unsigned gsvs_ring_size;
1214 uint32_t vtx_base_sgpr;
1215 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1216 uint8_t vtx_emit_num;
1217 struct radv_prim_vertex_count prim_vertex_count;
1218 bool can_use_guardband;
1219 uint32_t needed_dynamic_state;
1220 } graphics;
1221 };
1222
1223 unsigned max_waves;
1224 unsigned scratch_bytes_per_wave;
1225 };
1226
1227 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1228 {
1229 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1230 }
1231
1232 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1233 {
1234 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1235 }
1236
1237 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1238 gl_shader_stage stage,
1239 int idx);
1240
1241 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1242
1243 struct radv_graphics_pipeline_create_info {
1244 bool use_rectlist;
1245 bool db_depth_clear;
1246 bool db_stencil_clear;
1247 bool db_depth_disable_expclear;
1248 bool db_stencil_disable_expclear;
1249 bool db_flush_depth_inplace;
1250 bool db_flush_stencil_inplace;
1251 bool db_resummarize;
1252 uint32_t custom_blend_mode;
1253 };
1254
1255 VkResult
1256 radv_graphics_pipeline_create(VkDevice device,
1257 VkPipelineCache cache,
1258 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1259 const struct radv_graphics_pipeline_create_info *extra,
1260 const VkAllocationCallbacks *alloc,
1261 VkPipeline *pPipeline);
1262
1263 struct vk_format_description;
1264 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1265 int first_non_void);
1266 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1267 int first_non_void);
1268 uint32_t radv_translate_colorformat(VkFormat format);
1269 uint32_t radv_translate_color_numformat(VkFormat format,
1270 const struct vk_format_description *desc,
1271 int first_non_void);
1272 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1273 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1274 uint32_t radv_translate_dbformat(VkFormat format);
1275 uint32_t radv_translate_tex_dataformat(VkFormat format,
1276 const struct vk_format_description *desc,
1277 int first_non_void);
1278 uint32_t radv_translate_tex_numformat(VkFormat format,
1279 const struct vk_format_description *desc,
1280 int first_non_void);
1281 bool radv_format_pack_clear_color(VkFormat format,
1282 uint32_t clear_vals[2],
1283 VkClearColorValue *value);
1284 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1285 bool radv_dcc_formats_compatible(VkFormat format1,
1286 VkFormat format2);
1287
1288 struct radv_fmask_info {
1289 uint64_t offset;
1290 uint64_t size;
1291 unsigned alignment;
1292 unsigned pitch_in_pixels;
1293 unsigned bank_height;
1294 unsigned slice_tile_max;
1295 unsigned tile_mode_index;
1296 unsigned tile_swizzle;
1297 };
1298
1299 struct radv_cmask_info {
1300 uint64_t offset;
1301 uint64_t size;
1302 unsigned alignment;
1303 unsigned slice_tile_max;
1304 };
1305
1306 struct radv_image {
1307 VkImageType type;
1308 /* The original VkFormat provided by the client. This may not match any
1309 * of the actual surface formats.
1310 */
1311 VkFormat vk_format;
1312 VkImageAspectFlags aspects;
1313 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1314 struct ac_surf_info info;
1315 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1316 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1317
1318 VkDeviceSize size;
1319 uint32_t alignment;
1320
1321 unsigned queue_family_mask;
1322 bool exclusive;
1323 bool shareable;
1324
1325 /* Set when bound */
1326 struct radeon_winsys_bo *bo;
1327 VkDeviceSize offset;
1328 uint64_t dcc_offset;
1329 uint64_t htile_offset;
1330 bool tc_compatible_htile;
1331 struct radeon_surf surface;
1332
1333 struct radv_fmask_info fmask;
1334 struct radv_cmask_info cmask;
1335 uint64_t clear_value_offset;
1336 uint64_t dcc_pred_offset;
1337
1338 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1339 VkDeviceMemory owned_memory;
1340 };
1341
1342 /* Whether the image has a htile that is known consistent with the contents of
1343 * the image. */
1344 bool radv_layout_has_htile(const struct radv_image *image,
1345 VkImageLayout layout,
1346 unsigned queue_mask);
1347
1348 /* Whether the image has a htile that is known consistent with the contents of
1349 * the image and is allowed to be in compressed form.
1350 *
1351 * If this is false reads that don't use the htile should be able to return
1352 * correct results.
1353 */
1354 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1355 VkImageLayout layout,
1356 unsigned queue_mask);
1357
1358 bool radv_layout_can_fast_clear(const struct radv_image *image,
1359 VkImageLayout layout,
1360 unsigned queue_mask);
1361
1362 bool radv_layout_dcc_compressed(const struct radv_image *image,
1363 VkImageLayout layout,
1364 unsigned queue_mask);
1365
1366 static inline bool
1367 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1368 {
1369 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1370 }
1371
1372 static inline bool
1373 radv_htile_enabled(const struct radv_image *image, unsigned level)
1374 {
1375 return image->surface.htile_size && level == 0;
1376 }
1377
1378 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1379
1380 static inline uint32_t
1381 radv_get_layerCount(const struct radv_image *image,
1382 const VkImageSubresourceRange *range)
1383 {
1384 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1385 image->info.array_size - range->baseArrayLayer : range->layerCount;
1386 }
1387
1388 static inline uint32_t
1389 radv_get_levelCount(const struct radv_image *image,
1390 const VkImageSubresourceRange *range)
1391 {
1392 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1393 image->info.levels - range->baseMipLevel : range->levelCount;
1394 }
1395
1396 struct radeon_bo_metadata;
1397 void
1398 radv_init_metadata(struct radv_device *device,
1399 struct radv_image *image,
1400 struct radeon_bo_metadata *metadata);
1401
1402 struct radv_image_view {
1403 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1404 struct radeon_winsys_bo *bo;
1405
1406 VkImageViewType type;
1407 VkImageAspectFlags aspect_mask;
1408 VkFormat vk_format;
1409 uint32_t base_layer;
1410 uint32_t layer_count;
1411 uint32_t base_mip;
1412 uint32_t level_count;
1413 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1414
1415 uint32_t descriptor[16];
1416
1417 /* Descriptor for use as a storage image as opposed to a sampled image.
1418 * This has a few differences for cube maps (e.g. type).
1419 */
1420 uint32_t storage_descriptor[16];
1421 };
1422
1423 struct radv_image_create_info {
1424 const VkImageCreateInfo *vk_info;
1425 bool scanout;
1426 bool no_metadata_planes;
1427 };
1428
1429 VkResult radv_image_create(VkDevice _device,
1430 const struct radv_image_create_info *info,
1431 const VkAllocationCallbacks* alloc,
1432 VkImage *pImage);
1433
1434 VkResult
1435 radv_image_from_gralloc(VkDevice device_h,
1436 const VkImageCreateInfo *base_info,
1437 const VkNativeBufferANDROID *gralloc_info,
1438 const VkAllocationCallbacks *alloc,
1439 VkImage *out_image_h);
1440
1441 void radv_image_view_init(struct radv_image_view *view,
1442 struct radv_device *device,
1443 const VkImageViewCreateInfo* pCreateInfo);
1444
1445 struct radv_buffer_view {
1446 struct radeon_winsys_bo *bo;
1447 VkFormat vk_format;
1448 uint64_t range; /**< VkBufferViewCreateInfo::range */
1449 uint32_t state[4];
1450 };
1451 void radv_buffer_view_init(struct radv_buffer_view *view,
1452 struct radv_device *device,
1453 const VkBufferViewCreateInfo* pCreateInfo);
1454
1455 static inline struct VkExtent3D
1456 radv_sanitize_image_extent(const VkImageType imageType,
1457 const struct VkExtent3D imageExtent)
1458 {
1459 switch (imageType) {
1460 case VK_IMAGE_TYPE_1D:
1461 return (VkExtent3D) { imageExtent.width, 1, 1 };
1462 case VK_IMAGE_TYPE_2D:
1463 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1464 case VK_IMAGE_TYPE_3D:
1465 return imageExtent;
1466 default:
1467 unreachable("invalid image type");
1468 }
1469 }
1470
1471 static inline struct VkOffset3D
1472 radv_sanitize_image_offset(const VkImageType imageType,
1473 const struct VkOffset3D imageOffset)
1474 {
1475 switch (imageType) {
1476 case VK_IMAGE_TYPE_1D:
1477 return (VkOffset3D) { imageOffset.x, 0, 0 };
1478 case VK_IMAGE_TYPE_2D:
1479 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1480 case VK_IMAGE_TYPE_3D:
1481 return imageOffset;
1482 default:
1483 unreachable("invalid image type");
1484 }
1485 }
1486
1487 static inline bool
1488 radv_image_extent_compare(const struct radv_image *image,
1489 const VkExtent3D *extent)
1490 {
1491 if (extent->width != image->info.width ||
1492 extent->height != image->info.height ||
1493 extent->depth != image->info.depth)
1494 return false;
1495 return true;
1496 }
1497
1498 struct radv_sampler {
1499 uint32_t state[4];
1500 };
1501
1502 struct radv_color_buffer_info {
1503 uint64_t cb_color_base;
1504 uint64_t cb_color_cmask;
1505 uint64_t cb_color_fmask;
1506 uint64_t cb_dcc_base;
1507 uint32_t cb_color_pitch;
1508 uint32_t cb_color_slice;
1509 uint32_t cb_color_view;
1510 uint32_t cb_color_info;
1511 uint32_t cb_color_attrib;
1512 uint32_t cb_color_attrib2;
1513 uint32_t cb_dcc_control;
1514 uint32_t cb_color_cmask_slice;
1515 uint32_t cb_color_fmask_slice;
1516 };
1517
1518 struct radv_ds_buffer_info {
1519 uint64_t db_z_read_base;
1520 uint64_t db_stencil_read_base;
1521 uint64_t db_z_write_base;
1522 uint64_t db_stencil_write_base;
1523 uint64_t db_htile_data_base;
1524 uint32_t db_depth_info;
1525 uint32_t db_z_info;
1526 uint32_t db_stencil_info;
1527 uint32_t db_depth_view;
1528 uint32_t db_depth_size;
1529 uint32_t db_depth_slice;
1530 uint32_t db_htile_surface;
1531 uint32_t pa_su_poly_offset_db_fmt_cntl;
1532 uint32_t db_z_info2;
1533 uint32_t db_stencil_info2;
1534 float offset_scale;
1535 };
1536
1537 struct radv_attachment_info {
1538 union {
1539 struct radv_color_buffer_info cb;
1540 struct radv_ds_buffer_info ds;
1541 };
1542 struct radv_image_view *attachment;
1543 };
1544
1545 struct radv_framebuffer {
1546 uint32_t width;
1547 uint32_t height;
1548 uint32_t layers;
1549
1550 uint32_t attachment_count;
1551 struct radv_attachment_info attachments[0];
1552 };
1553
1554 struct radv_subpass_barrier {
1555 VkPipelineStageFlags src_stage_mask;
1556 VkAccessFlags src_access_mask;
1557 VkAccessFlags dst_access_mask;
1558 };
1559
1560 struct radv_subpass {
1561 uint32_t input_count;
1562 uint32_t color_count;
1563 VkAttachmentReference * input_attachments;
1564 VkAttachmentReference * color_attachments;
1565 VkAttachmentReference * resolve_attachments;
1566 VkAttachmentReference depth_stencil_attachment;
1567
1568 /** Subpass has at least one resolve attachment */
1569 bool has_resolve;
1570
1571 struct radv_subpass_barrier start_barrier;
1572
1573 uint32_t view_mask;
1574 };
1575
1576 struct radv_render_pass_attachment {
1577 VkFormat format;
1578 uint32_t samples;
1579 VkAttachmentLoadOp load_op;
1580 VkAttachmentLoadOp stencil_load_op;
1581 VkImageLayout initial_layout;
1582 VkImageLayout final_layout;
1583 uint32_t view_mask;
1584 };
1585
1586 struct radv_render_pass {
1587 uint32_t attachment_count;
1588 uint32_t subpass_count;
1589 VkAttachmentReference * subpass_attachments;
1590 struct radv_render_pass_attachment * attachments;
1591 struct radv_subpass_barrier end_barrier;
1592 struct radv_subpass subpasses[0];
1593 };
1594
1595 VkResult radv_device_init_meta(struct radv_device *device);
1596 void radv_device_finish_meta(struct radv_device *device);
1597
1598 struct radv_query_pool {
1599 struct radeon_winsys_bo *bo;
1600 uint32_t stride;
1601 uint32_t availability_offset;
1602 char *ptr;
1603 VkQueryType type;
1604 uint32_t pipeline_stats_mask;
1605 };
1606
1607 struct radv_semaphore {
1608 /* use a winsys sem for non-exportable */
1609 struct radeon_winsys_sem *sem;
1610 uint32_t syncobj;
1611 uint32_t temp_syncobj;
1612 };
1613
1614 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1615 int num_wait_sems,
1616 const VkSemaphore *wait_sems,
1617 int num_signal_sems,
1618 const VkSemaphore *signal_sems,
1619 VkFence fence);
1620 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1621
1622 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1623 VkPipelineBindPoint bind_point,
1624 struct radv_descriptor_set *set,
1625 unsigned idx);
1626
1627 void
1628 radv_update_descriptor_sets(struct radv_device *device,
1629 struct radv_cmd_buffer *cmd_buffer,
1630 VkDescriptorSet overrideSet,
1631 uint32_t descriptorWriteCount,
1632 const VkWriteDescriptorSet *pDescriptorWrites,
1633 uint32_t descriptorCopyCount,
1634 const VkCopyDescriptorSet *pDescriptorCopies);
1635
1636 void
1637 radv_update_descriptor_set_with_template(struct radv_device *device,
1638 struct radv_cmd_buffer *cmd_buffer,
1639 struct radv_descriptor_set *set,
1640 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1641 const void *pData);
1642
1643 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1644 VkPipelineBindPoint pipelineBindPoint,
1645 VkPipelineLayout _layout,
1646 uint32_t set,
1647 uint32_t descriptorWriteCount,
1648 const VkWriteDescriptorSet *pDescriptorWrites);
1649
1650 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1651 struct radv_image *image, uint32_t value);
1652 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1653 struct radv_image *image, uint32_t value);
1654
1655 struct radv_fence {
1656 struct radeon_winsys_fence *fence;
1657 bool submitted;
1658 bool signalled;
1659
1660 uint32_t syncobj;
1661 uint32_t temp_syncobj;
1662 };
1663
1664 struct radeon_winsys_sem;
1665
1666 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1667 \
1668 static inline struct __radv_type * \
1669 __radv_type ## _from_handle(__VkType _handle) \
1670 { \
1671 return (struct __radv_type *) _handle; \
1672 } \
1673 \
1674 static inline __VkType \
1675 __radv_type ## _to_handle(struct __radv_type *_obj) \
1676 { \
1677 return (__VkType) _obj; \
1678 }
1679
1680 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1681 \
1682 static inline struct __radv_type * \
1683 __radv_type ## _from_handle(__VkType _handle) \
1684 { \
1685 return (struct __radv_type *)(uintptr_t) _handle; \
1686 } \
1687 \
1688 static inline __VkType \
1689 __radv_type ## _to_handle(struct __radv_type *_obj) \
1690 { \
1691 return (__VkType)(uintptr_t) _obj; \
1692 }
1693
1694 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1695 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1696
1697 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1698 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1699 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1700 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1701 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1702
1703 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1704 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1705 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1706 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1709 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1710 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1711 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1712 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1715 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1716 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1719 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1720 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1721 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1722 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1723 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1724
1725 #endif /* RADV_PRIVATE_H */