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radv/gfx9: fix 3d image clears on compute queues
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280
281 VkPhysicalDeviceMemoryProperties memory_properties;
282 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 uint64_t perftest_flags;
296 };
297
298 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
299 void radv_finish_wsi(struct radv_physical_device *physical_device);
300
301 bool radv_instance_extension_supported(const char *name);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
303 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
304 const char *name);
305
306 struct cache_entry;
307
308 struct radv_pipeline_cache {
309 struct radv_device * device;
310 pthread_mutex_t mutex;
311
312 uint32_t total_size;
313 uint32_t table_size;
314 uint32_t kernel_count;
315 struct cache_entry ** hash_table;
316 bool modified;
317
318 VkAllocationCallbacks alloc;
319 };
320
321 struct radv_pipeline_key {
322 uint32_t instance_rate_inputs;
323 unsigned tess_input_vertices;
324 uint32_t col_format;
325 uint32_t is_int8;
326 uint32_t is_int10;
327 uint32_t multisample : 1;
328 uint32_t has_multiview_view_index : 1;
329 };
330
331 void
332 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
333 struct radv_device *device);
334 void
335 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
336 void
337 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
338 const void *data, size_t size);
339
340 struct radv_shader_variant;
341
342 bool
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
344 struct radv_pipeline_cache *cache,
345 const unsigned char *sha1,
346 struct radv_shader_variant **variants);
347
348 void
349 radv_pipeline_cache_insert_shaders(struct radv_device *device,
350 struct radv_pipeline_cache *cache,
351 const unsigned char *sha1,
352 struct radv_shader_variant **variants,
353 const void *const *codes,
354 const unsigned *code_sizes);
355
356 enum radv_blit_ds_layout {
357 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
358 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
359 RADV_BLIT_DS_LAYOUT_COUNT,
360 };
361
362 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
363 {
364 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
365 }
366
367 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
368 {
369 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
370 }
371
372 struct radv_meta_state {
373 VkAllocationCallbacks alloc;
374
375 struct radv_pipeline_cache cache;
376
377 /**
378 * Use array element `i` for images with `2^i` samples.
379 */
380 struct {
381 VkRenderPass render_pass[NUM_META_FS_KEYS];
382 VkPipeline color_pipelines[NUM_META_FS_KEYS];
383
384 VkRenderPass depthstencil_rp;
385 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
386 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
387 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
388 } clear[1 + MAX_SAMPLES_LOG2];
389
390 VkPipelineLayout clear_color_p_layout;
391 VkPipelineLayout clear_depth_p_layout;
392 struct {
393 VkRenderPass render_pass[NUM_META_FS_KEYS];
394
395 /** Pipeline that blits from a 1D image. */
396 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
397
398 /** Pipeline that blits from a 2D image. */
399 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
400
401 /** Pipeline that blits from a 3D image. */
402 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
403
404 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
405 VkPipeline depth_only_1d_pipeline;
406 VkPipeline depth_only_2d_pipeline;
407 VkPipeline depth_only_3d_pipeline;
408
409 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
410 VkPipeline stencil_only_1d_pipeline;
411 VkPipeline stencil_only_2d_pipeline;
412 VkPipeline stencil_only_3d_pipeline;
413 VkPipelineLayout pipeline_layout;
414 VkDescriptorSetLayout ds_layout;
415 } blit;
416
417 struct {
418 VkRenderPass render_passes[NUM_META_FS_KEYS];
419
420 VkPipelineLayout p_layouts[3];
421 VkDescriptorSetLayout ds_layouts[3];
422 VkPipeline pipelines[3][NUM_META_FS_KEYS];
423
424 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
425 VkPipeline depth_only_pipeline[3];
426
427 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
428 VkPipeline stencil_only_pipeline[3];
429 } blit2d;
430
431 struct {
432 VkPipelineLayout img_p_layout;
433 VkDescriptorSetLayout img_ds_layout;
434 VkPipeline pipeline;
435 VkPipeline pipeline_3d;
436 } itob;
437 struct {
438 VkPipelineLayout img_p_layout;
439 VkDescriptorSetLayout img_ds_layout;
440 VkPipeline pipeline;
441 } btoi;
442 struct {
443 VkPipelineLayout img_p_layout;
444 VkDescriptorSetLayout img_ds_layout;
445 VkPipeline pipeline;
446 VkPipeline pipeline_3d;
447 } itoi;
448 struct {
449 VkPipelineLayout img_p_layout;
450 VkDescriptorSetLayout img_ds_layout;
451 VkPipeline pipeline;
452 VkPipeline pipeline_3d;
453 } cleari;
454
455 struct {
456 VkPipelineLayout p_layout;
457 VkPipeline pipeline;
458 VkRenderPass pass;
459 } resolve;
460
461 struct {
462 VkDescriptorSetLayout ds_layout;
463 VkPipelineLayout p_layout;
464 struct {
465 VkPipeline pipeline;
466 VkPipeline i_pipeline;
467 VkPipeline srgb_pipeline;
468 } rc[MAX_SAMPLES_LOG2];
469 } resolve_compute;
470
471 struct {
472 VkDescriptorSetLayout ds_layout;
473 VkPipelineLayout p_layout;
474
475 struct {
476 VkRenderPass render_pass[NUM_META_FS_KEYS];
477 VkPipeline pipeline[NUM_META_FS_KEYS];
478 } rc[MAX_SAMPLES_LOG2];
479 } resolve_fragment;
480
481 struct {
482 VkPipelineLayout p_layout;
483 VkPipeline decompress_pipeline;
484 VkPipeline resummarize_pipeline;
485 VkRenderPass pass;
486 } depth_decomp[1 + MAX_SAMPLES_LOG2];
487
488 struct {
489 VkPipelineLayout p_layout;
490 VkPipeline cmask_eliminate_pipeline;
491 VkPipeline fmask_decompress_pipeline;
492 VkRenderPass pass;
493 } fast_clear_flush;
494
495 struct {
496 VkPipelineLayout fill_p_layout;
497 VkPipelineLayout copy_p_layout;
498 VkDescriptorSetLayout fill_ds_layout;
499 VkDescriptorSetLayout copy_ds_layout;
500 VkPipeline fill_pipeline;
501 VkPipeline copy_pipeline;
502 } buffer;
503
504 struct {
505 VkDescriptorSetLayout ds_layout;
506 VkPipelineLayout p_layout;
507 VkPipeline occlusion_query_pipeline;
508 VkPipeline pipeline_statistics_query_pipeline;
509 } query;
510 };
511
512 /* queue types */
513 #define RADV_QUEUE_GENERAL 0
514 #define RADV_QUEUE_COMPUTE 1
515 #define RADV_QUEUE_TRANSFER 2
516
517 #define RADV_MAX_QUEUE_FAMILIES 3
518
519 enum ring_type radv_queue_family_to_ring(int f);
520
521 struct radv_queue {
522 VK_LOADER_DATA _loader_data;
523 struct radv_device * device;
524 struct radeon_winsys_ctx *hw_ctx;
525 enum radeon_ctx_priority priority;
526 uint32_t queue_family_index;
527 int queue_idx;
528
529 uint32_t scratch_size;
530 uint32_t compute_scratch_size;
531 uint32_t esgs_ring_size;
532 uint32_t gsvs_ring_size;
533 bool has_tess_rings;
534 bool has_sample_positions;
535
536 struct radeon_winsys_bo *scratch_bo;
537 struct radeon_winsys_bo *descriptor_bo;
538 struct radeon_winsys_bo *compute_scratch_bo;
539 struct radeon_winsys_bo *esgs_ring_bo;
540 struct radeon_winsys_bo *gsvs_ring_bo;
541 struct radeon_winsys_bo *tess_factor_ring_bo;
542 struct radeon_winsys_bo *tess_offchip_ring_bo;
543 struct radeon_winsys_cs *initial_preamble_cs;
544 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
545 struct radeon_winsys_cs *continue_preamble_cs;
546 };
547
548 struct radv_device {
549 VK_LOADER_DATA _loader_data;
550
551 VkAllocationCallbacks alloc;
552
553 struct radv_instance * instance;
554 struct radeon_winsys *ws;
555
556 struct radv_meta_state meta_state;
557
558 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
559 int queue_count[RADV_MAX_QUEUE_FAMILIES];
560 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
561
562 bool llvm_supports_spill;
563 bool has_distributed_tess;
564 bool dfsm_allowed;
565 uint32_t tess_offchip_block_dw_size;
566 uint32_t scratch_waves;
567 uint32_t dispatch_initiator;
568
569 uint32_t gs_table_depth;
570
571 /* MSAA sample locations.
572 * The first index is the sample index.
573 * The second index is the coordinate: X, Y. */
574 float sample_locations_1x[1][2];
575 float sample_locations_2x[2][2];
576 float sample_locations_4x[4][2];
577 float sample_locations_8x[8][2];
578 float sample_locations_16x[16][2];
579
580 /* CIK and later */
581 uint32_t gfx_init_size_dw;
582 struct radeon_winsys_bo *gfx_init;
583
584 struct radeon_winsys_bo *trace_bo;
585 uint32_t *trace_id_ptr;
586
587 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
588 bool keep_shader_info;
589
590 struct radv_physical_device *physical_device;
591
592 /* Backup in-memory cache to be used if the app doesn't provide one */
593 struct radv_pipeline_cache * mem_cache;
594
595 /*
596 * use different counters so MSAA MRTs get consecutive surface indices,
597 * even if MASK is allocated in between.
598 */
599 uint32_t image_mrt_offset_counter;
600 uint32_t fmask_mrt_offset_counter;
601 struct list_head shader_slabs;
602 mtx_t shader_slab_mutex;
603
604 /* For detecting VM faults reported by dmesg. */
605 uint64_t dmesg_timestamp;
606 };
607
608 struct radv_device_memory {
609 struct radeon_winsys_bo *bo;
610 /* for dedicated allocations */
611 struct radv_image *image;
612 struct radv_buffer *buffer;
613 uint32_t type_index;
614 VkDeviceSize map_size;
615 void * map;
616 };
617
618
619 struct radv_descriptor_range {
620 uint64_t va;
621 uint32_t size;
622 };
623
624 struct radv_descriptor_set {
625 const struct radv_descriptor_set_layout *layout;
626 uint32_t size;
627
628 struct radeon_winsys_bo *bo;
629 uint64_t va;
630 uint32_t *mapped_ptr;
631 struct radv_descriptor_range *dynamic_descriptors;
632
633 struct radeon_winsys_bo *descriptors[0];
634 };
635
636 struct radv_push_descriptor_set
637 {
638 struct radv_descriptor_set set;
639 uint32_t capacity;
640 };
641
642 struct radv_descriptor_pool_entry {
643 uint32_t offset;
644 uint32_t size;
645 struct radv_descriptor_set *set;
646 };
647
648 struct radv_descriptor_pool {
649 struct radeon_winsys_bo *bo;
650 uint8_t *mapped_ptr;
651 uint64_t current_offset;
652 uint64_t size;
653
654 uint8_t *host_memory_base;
655 uint8_t *host_memory_ptr;
656 uint8_t *host_memory_end;
657
658 uint32_t entry_count;
659 uint32_t max_entry_count;
660 struct radv_descriptor_pool_entry entries[0];
661 };
662
663 struct radv_descriptor_update_template_entry {
664 VkDescriptorType descriptor_type;
665
666 /* The number of descriptors to update */
667 uint32_t descriptor_count;
668
669 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
670 uint32_t dst_offset;
671
672 /* In dwords. Not valid/used for dynamic descriptors */
673 uint32_t dst_stride;
674
675 uint32_t buffer_offset;
676
677 /* Only valid for combined image samplers and samplers */
678 uint16_t has_sampler;
679
680 /* In bytes */
681 size_t src_offset;
682 size_t src_stride;
683
684 /* For push descriptors */
685 const uint32_t *immutable_samplers;
686 };
687
688 struct radv_descriptor_update_template {
689 uint32_t entry_count;
690 struct radv_descriptor_update_template_entry entry[0];
691 };
692
693 struct radv_buffer {
694 struct radv_device * device;
695 VkDeviceSize size;
696
697 VkBufferUsageFlags usage;
698 VkBufferCreateFlags flags;
699
700 /* Set when bound */
701 struct radeon_winsys_bo * bo;
702 VkDeviceSize offset;
703
704 bool shareable;
705 };
706
707
708 enum radv_cmd_dirty_bits {
709 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
710 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
711 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
712 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
713 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
714 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
715 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
716 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
717 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
718 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
719 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
720 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
721 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
722 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
723 };
724
725 enum radv_cmd_flush_bits {
726 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
727 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
728 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
729 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
730 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
731 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
732 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
733 /* Same as above, but only writes back and doesn't invalidate */
734 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
735 /* Framebuffer caches */
736 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
737 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
738 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
739 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
740 /* Engine synchronization. */
741 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
742 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
743 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
744 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
745
746 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
747 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
748 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
749 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
750 };
751
752 struct radv_vertex_binding {
753 struct radv_buffer * buffer;
754 VkDeviceSize offset;
755 };
756
757 struct radv_viewport_state {
758 uint32_t count;
759 VkViewport viewports[MAX_VIEWPORTS];
760 };
761
762 struct radv_scissor_state {
763 uint32_t count;
764 VkRect2D scissors[MAX_SCISSORS];
765 };
766
767 struct radv_dynamic_state {
768 /**
769 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
770 * Defines the set of saved dynamic state.
771 */
772 uint32_t mask;
773
774 struct radv_viewport_state viewport;
775
776 struct radv_scissor_state scissor;
777
778 float line_width;
779
780 struct {
781 float bias;
782 float clamp;
783 float slope;
784 } depth_bias;
785
786 float blend_constants[4];
787
788 struct {
789 float min;
790 float max;
791 } depth_bounds;
792
793 struct {
794 uint32_t front;
795 uint32_t back;
796 } stencil_compare_mask;
797
798 struct {
799 uint32_t front;
800 uint32_t back;
801 } stencil_write_mask;
802
803 struct {
804 uint32_t front;
805 uint32_t back;
806 } stencil_reference;
807 };
808
809 extern const struct radv_dynamic_state default_dynamic_state;
810
811 const char *
812 radv_get_debug_option_name(int id);
813
814 const char *
815 radv_get_perftest_option_name(int id);
816
817 /**
818 * Attachment state when recording a renderpass instance.
819 *
820 * The clear value is valid only if there exists a pending clear.
821 */
822 struct radv_attachment_state {
823 VkImageAspectFlags pending_clear_aspects;
824 uint32_t cleared_views;
825 VkClearValue clear_value;
826 VkImageLayout current_layout;
827 };
828
829 struct radv_cmd_state {
830 /* Vertex descriptors */
831 bool vb_prefetch_dirty;
832 uint64_t vb_va;
833 unsigned vb_size;
834
835 bool push_descriptors_dirty;
836 bool predicating;
837 uint32_t dirty;
838
839 struct radv_pipeline * pipeline;
840 struct radv_pipeline * emitted_pipeline;
841 struct radv_pipeline * compute_pipeline;
842 struct radv_pipeline * emitted_compute_pipeline;
843 struct radv_framebuffer * framebuffer;
844 struct radv_render_pass * pass;
845 const struct radv_subpass * subpass;
846 struct radv_dynamic_state dynamic;
847 struct radv_attachment_state * attachments;
848 VkRect2D render_area;
849
850 /* Index buffer */
851 struct radv_buffer *index_buffer;
852 uint64_t index_offset;
853 uint32_t index_type;
854 uint32_t max_index_count;
855 uint64_t index_va;
856 int32_t last_index_type;
857
858 int32_t last_primitive_reset_en;
859 uint32_t last_primitive_reset_index;
860 enum radv_cmd_flush_bits flush_bits;
861 unsigned active_occlusion_queries;
862 float offset_scale;
863 uint32_t descriptors_dirty;
864 uint32_t valid_descriptors;
865 uint32_t trace_id;
866 uint32_t last_ia_multi_vgt_param;
867 };
868
869 struct radv_cmd_pool {
870 VkAllocationCallbacks alloc;
871 struct list_head cmd_buffers;
872 struct list_head free_cmd_buffers;
873 uint32_t queue_family_index;
874 };
875
876 struct radv_cmd_buffer_upload {
877 uint8_t *map;
878 unsigned offset;
879 uint64_t size;
880 struct radeon_winsys_bo *upload_bo;
881 struct list_head list;
882 };
883
884 enum radv_cmd_buffer_status {
885 RADV_CMD_BUFFER_STATUS_INVALID,
886 RADV_CMD_BUFFER_STATUS_INITIAL,
887 RADV_CMD_BUFFER_STATUS_RECORDING,
888 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
889 RADV_CMD_BUFFER_STATUS_PENDING,
890 };
891
892 struct radv_cmd_buffer {
893 VK_LOADER_DATA _loader_data;
894
895 struct radv_device * device;
896
897 struct radv_cmd_pool * pool;
898 struct list_head pool_link;
899
900 VkCommandBufferUsageFlags usage_flags;
901 VkCommandBufferLevel level;
902 enum radv_cmd_buffer_status status;
903 struct radeon_winsys_cs *cs;
904 struct radv_cmd_state state;
905 struct radv_vertex_binding vertex_bindings[MAX_VBS];
906 uint32_t queue_family_index;
907
908 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
909 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
910 VkShaderStageFlags push_constant_stages;
911 struct radv_push_descriptor_set push_descriptors;
912 struct radv_descriptor_set meta_push_descriptors;
913 struct radv_descriptor_set *descriptors[MAX_SETS];
914
915 struct radv_cmd_buffer_upload upload;
916
917 uint32_t scratch_size_needed;
918 uint32_t compute_scratch_size_needed;
919 uint32_t esgs_ring_size_needed;
920 uint32_t gsvs_ring_size_needed;
921 bool tess_rings_needed;
922 bool sample_positions_needed;
923
924 VkResult record_result;
925
926 int ring_offsets_idx; /* just used for verification */
927 uint32_t gfx9_fence_offset;
928 struct radeon_winsys_bo *gfx9_fence_bo;
929 uint32_t gfx9_fence_idx;
930 };
931
932 struct radv_image;
933
934 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
935
936 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
937 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
938
939 void cik_create_gfx_config(struct radv_device *device);
940
941 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
942 int count, const VkViewport *viewports);
943 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
944 int count, const VkRect2D *scissors,
945 const VkViewport *viewports, bool can_use_guardband);
946 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
947 bool instanced_draw, bool indirect_draw,
948 uint32_t draw_vertex_count);
949 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
950 bool predicated,
951 enum chip_class chip_class,
952 bool is_mec,
953 unsigned event, unsigned event_flags,
954 unsigned data_sel,
955 uint64_t va,
956 uint32_t old_fence,
957 uint32_t new_fence);
958
959 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
960 bool predicated,
961 uint64_t va, uint32_t ref,
962 uint32_t mask);
963 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
964 bool predicated,
965 enum chip_class chip_class,
966 uint32_t *fence_ptr, uint64_t va,
967 bool is_mec,
968 enum radv_cmd_flush_bits flush_bits);
969 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
970 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
971 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
972 uint64_t src_va, uint64_t dest_va,
973 uint64_t size);
974 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
975 unsigned size);
976 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
977 uint64_t size, unsigned value);
978 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
979 bool
980 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
981 unsigned size,
982 unsigned alignment,
983 unsigned *out_offset,
984 void **ptr);
985 void
986 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
987 const struct radv_subpass *subpass,
988 bool transitions);
989 bool
990 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
991 unsigned size, unsigned alignmnet,
992 const void *data, unsigned *out_offset);
993
994 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
995 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
996 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
997 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
998 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
999 unsigned radv_cayman_get_maxdist(int log_samples);
1000 void radv_device_init_msaa(struct radv_device *device);
1001 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1002 struct radv_image *image,
1003 VkClearDepthStencilValue ds_clear_value,
1004 VkImageAspectFlags aspects);
1005 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1006 struct radv_image *image,
1007 int idx,
1008 uint32_t color_values[2]);
1009 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1010 struct radv_image *image,
1011 bool value);
1012 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1013 struct radeon_winsys_bo *bo,
1014 uint64_t offset, uint64_t size, uint32_t value);
1015 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1016 bool radv_get_memory_fd(struct radv_device *device,
1017 struct radv_device_memory *memory,
1018 int *pFD);
1019
1020 /*
1021 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1022 *
1023 * Limitations: Can't call normal dispatch functions without binding or rebinding
1024 * the compute pipeline.
1025 */
1026 void radv_unaligned_dispatch(
1027 struct radv_cmd_buffer *cmd_buffer,
1028 uint32_t x,
1029 uint32_t y,
1030 uint32_t z);
1031
1032 struct radv_event {
1033 struct radeon_winsys_bo *bo;
1034 uint64_t *map;
1035 };
1036
1037 struct radv_shader_module;
1038
1039 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1040 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1041 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1042 void
1043 radv_hash_shaders(unsigned char *hash,
1044 const VkPipelineShaderStageCreateInfo **stages,
1045 const struct radv_pipeline_layout *layout,
1046 const struct radv_pipeline_key *key,
1047 uint32_t flags);
1048
1049 static inline gl_shader_stage
1050 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1051 {
1052 assert(__builtin_popcount(vk_stage) == 1);
1053 return ffs(vk_stage) - 1;
1054 }
1055
1056 static inline VkShaderStageFlagBits
1057 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1058 {
1059 return (1 << mesa_stage);
1060 }
1061
1062 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1063
1064 #define radv_foreach_stage(stage, stage_bits) \
1065 for (gl_shader_stage stage, \
1066 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1067 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1068 __tmp &= ~(1 << (stage)))
1069
1070 struct radv_depth_stencil_state {
1071 uint32_t db_depth_control;
1072 uint32_t db_stencil_control;
1073 uint32_t db_render_control;
1074 uint32_t db_render_override2;
1075 };
1076
1077 struct radv_blend_state {
1078 uint32_t cb_color_control;
1079 uint32_t cb_target_mask;
1080 uint32_t sx_mrt_blend_opt[8];
1081 uint32_t cb_blend_control[8];
1082
1083 uint32_t spi_shader_col_format;
1084 uint32_t cb_shader_mask;
1085 uint32_t db_alpha_to_mask;
1086 };
1087
1088 unsigned radv_format_meta_fs_key(VkFormat format);
1089
1090 struct radv_raster_state {
1091 uint32_t pa_cl_clip_cntl;
1092 uint32_t spi_interp_control;
1093 uint32_t pa_su_vtx_cntl;
1094 uint32_t pa_su_sc_mode_cntl;
1095 };
1096
1097 struct radv_multisample_state {
1098 uint32_t db_eqaa;
1099 uint32_t pa_sc_line_cntl;
1100 uint32_t pa_sc_mode_cntl_0;
1101 uint32_t pa_sc_mode_cntl_1;
1102 uint32_t pa_sc_aa_config;
1103 uint32_t pa_sc_aa_mask[2];
1104 unsigned num_samples;
1105 };
1106
1107 struct radv_prim_vertex_count {
1108 uint8_t min;
1109 uint8_t incr;
1110 };
1111
1112 struct radv_tessellation_state {
1113 uint32_t ls_hs_config;
1114 uint32_t tcs_in_layout;
1115 uint32_t tcs_out_layout;
1116 uint32_t tcs_out_offsets;
1117 uint32_t offchip_layout;
1118 unsigned num_patches;
1119 unsigned lds_size;
1120 unsigned num_tcs_input_cp;
1121 uint32_t tf_param;
1122 };
1123
1124 struct radv_gs_state {
1125 uint32_t vgt_gs_onchip_cntl;
1126 uint32_t vgt_gs_max_prims_per_subgroup;
1127 uint32_t vgt_esgs_ring_itemsize;
1128 uint32_t lds_size;
1129 };
1130
1131 struct radv_vertex_elements_info {
1132 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1133 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1134 uint32_t binding[MAX_VERTEX_ATTRIBS];
1135 uint32_t offset[MAX_VERTEX_ATTRIBS];
1136 uint32_t count;
1137 };
1138
1139 struct radv_vs_state {
1140 uint32_t pa_cl_vs_out_cntl;
1141 uint32_t spi_shader_pos_format;
1142 uint32_t spi_vs_out_config;
1143 uint32_t vgt_reuse_off;
1144 };
1145
1146 #define SI_GS_PER_ES 128
1147
1148 struct radv_pipeline {
1149 struct radv_device * device;
1150 struct radv_dynamic_state dynamic_state;
1151
1152 struct radv_pipeline_layout * layout;
1153
1154 bool needs_data_cache;
1155 bool need_indirect_descriptor_sets;
1156 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1157 struct radv_shader_variant *gs_copy_shader;
1158 VkShaderStageFlags active_stages;
1159
1160 struct radv_vertex_elements_info vertex_elements;
1161
1162 uint32_t binding_stride[MAX_VBS];
1163
1164 uint32_t user_data_0[MESA_SHADER_STAGES];
1165 union {
1166 struct {
1167 struct radv_blend_state blend;
1168 struct radv_depth_stencil_state ds;
1169 struct radv_raster_state raster;
1170 struct radv_multisample_state ms;
1171 struct radv_tessellation_state tess;
1172 struct radv_gs_state gs;
1173 struct radv_vs_state vs;
1174 uint32_t db_shader_control;
1175 uint32_t shader_z_format;
1176 unsigned prim;
1177 unsigned gs_out;
1178 uint32_t vgt_gs_mode;
1179 bool vgt_primitiveid_en;
1180 bool prim_restart_enable;
1181 bool partial_es_wave;
1182 uint8_t primgroup_size;
1183 unsigned esgs_ring_size;
1184 unsigned gsvs_ring_size;
1185 uint32_t ps_input_cntl[32];
1186 uint32_t ps_input_cntl_num;
1187 uint32_t vgt_shader_stages_en;
1188 uint32_t vtx_base_sgpr;
1189 uint32_t base_ia_multi_vgt_param;
1190 bool wd_switch_on_eop;
1191 bool ia_switch_on_eoi;
1192 bool partial_vs_wave;
1193 uint8_t vtx_emit_num;
1194 uint32_t vtx_reuse_depth;
1195 struct radv_prim_vertex_count prim_vertex_count;
1196 bool can_use_guardband;
1197 } graphics;
1198 };
1199
1200 unsigned max_waves;
1201 unsigned scratch_bytes_per_wave;
1202 };
1203
1204 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1205 {
1206 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1207 }
1208
1209 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1210 {
1211 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1212 }
1213
1214 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1215 gl_shader_stage stage,
1216 int idx);
1217
1218 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1219
1220 struct radv_graphics_pipeline_create_info {
1221 bool use_rectlist;
1222 bool db_depth_clear;
1223 bool db_stencil_clear;
1224 bool db_depth_disable_expclear;
1225 bool db_stencil_disable_expclear;
1226 bool db_flush_depth_inplace;
1227 bool db_flush_stencil_inplace;
1228 bool db_resummarize;
1229 uint32_t custom_blend_mode;
1230 };
1231
1232 VkResult
1233 radv_graphics_pipeline_create(VkDevice device,
1234 VkPipelineCache cache,
1235 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1236 const struct radv_graphics_pipeline_create_info *extra,
1237 const VkAllocationCallbacks *alloc,
1238 VkPipeline *pPipeline);
1239
1240 struct vk_format_description;
1241 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1242 int first_non_void);
1243 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1244 int first_non_void);
1245 uint32_t radv_translate_colorformat(VkFormat format);
1246 uint32_t radv_translate_color_numformat(VkFormat format,
1247 const struct vk_format_description *desc,
1248 int first_non_void);
1249 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1250 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1251 uint32_t radv_translate_dbformat(VkFormat format);
1252 uint32_t radv_translate_tex_dataformat(VkFormat format,
1253 const struct vk_format_description *desc,
1254 int first_non_void);
1255 uint32_t radv_translate_tex_numformat(VkFormat format,
1256 const struct vk_format_description *desc,
1257 int first_non_void);
1258 bool radv_format_pack_clear_color(VkFormat format,
1259 uint32_t clear_vals[2],
1260 VkClearColorValue *value);
1261 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1262 bool radv_dcc_formats_compatible(VkFormat format1,
1263 VkFormat format2);
1264
1265 struct radv_fmask_info {
1266 uint64_t offset;
1267 uint64_t size;
1268 unsigned alignment;
1269 unsigned pitch_in_pixels;
1270 unsigned bank_height;
1271 unsigned slice_tile_max;
1272 unsigned tile_mode_index;
1273 unsigned tile_swizzle;
1274 };
1275
1276 struct radv_cmask_info {
1277 uint64_t offset;
1278 uint64_t size;
1279 unsigned alignment;
1280 unsigned slice_tile_max;
1281 };
1282
1283 struct radv_image {
1284 VkImageType type;
1285 /* The original VkFormat provided by the client. This may not match any
1286 * of the actual surface formats.
1287 */
1288 VkFormat vk_format;
1289 VkImageAspectFlags aspects;
1290 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1291 struct ac_surf_info info;
1292 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1293 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1294
1295 VkDeviceSize size;
1296 uint32_t alignment;
1297
1298 unsigned queue_family_mask;
1299 bool exclusive;
1300 bool shareable;
1301
1302 /* Set when bound */
1303 struct radeon_winsys_bo *bo;
1304 VkDeviceSize offset;
1305 uint64_t dcc_offset;
1306 uint64_t htile_offset;
1307 bool tc_compatible_htile;
1308 struct radeon_surf surface;
1309
1310 struct radv_fmask_info fmask;
1311 struct radv_cmask_info cmask;
1312 uint64_t clear_value_offset;
1313 uint64_t dcc_pred_offset;
1314 };
1315
1316 /* Whether the image has a htile that is known consistent with the contents of
1317 * the image. */
1318 bool radv_layout_has_htile(const struct radv_image *image,
1319 VkImageLayout layout,
1320 unsigned queue_mask);
1321
1322 /* Whether the image has a htile that is known consistent with the contents of
1323 * the image and is allowed to be in compressed form.
1324 *
1325 * If this is false reads that don't use the htile should be able to return
1326 * correct results.
1327 */
1328 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1329 VkImageLayout layout,
1330 unsigned queue_mask);
1331
1332 bool radv_layout_can_fast_clear(const struct radv_image *image,
1333 VkImageLayout layout,
1334 unsigned queue_mask);
1335
1336 static inline bool
1337 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1338 {
1339 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1340 }
1341
1342 static inline bool
1343 radv_htile_enabled(const struct radv_image *image, unsigned level)
1344 {
1345 return image->surface.htile_size && level == 0;
1346 }
1347
1348 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1349
1350 static inline uint32_t
1351 radv_get_layerCount(const struct radv_image *image,
1352 const VkImageSubresourceRange *range)
1353 {
1354 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1355 image->info.array_size - range->baseArrayLayer : range->layerCount;
1356 }
1357
1358 static inline uint32_t
1359 radv_get_levelCount(const struct radv_image *image,
1360 const VkImageSubresourceRange *range)
1361 {
1362 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1363 image->info.levels - range->baseMipLevel : range->levelCount;
1364 }
1365
1366 struct radeon_bo_metadata;
1367 void
1368 radv_init_metadata(struct radv_device *device,
1369 struct radv_image *image,
1370 struct radeon_bo_metadata *metadata);
1371
1372 struct radv_image_view {
1373 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1374 struct radeon_winsys_bo *bo;
1375
1376 VkImageViewType type;
1377 VkImageAspectFlags aspect_mask;
1378 VkFormat vk_format;
1379 uint32_t base_layer;
1380 uint32_t layer_count;
1381 uint32_t base_mip;
1382 uint32_t level_count;
1383 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1384
1385 uint32_t descriptor[16];
1386
1387 /* Descriptor for use as a storage image as opposed to a sampled image.
1388 * This has a few differences for cube maps (e.g. type).
1389 */
1390 uint32_t storage_descriptor[16];
1391 };
1392
1393 struct radv_image_create_info {
1394 const VkImageCreateInfo *vk_info;
1395 bool scanout;
1396 };
1397
1398 VkResult radv_image_create(VkDevice _device,
1399 const struct radv_image_create_info *info,
1400 const VkAllocationCallbacks* alloc,
1401 VkImage *pImage);
1402
1403 void radv_image_view_init(struct radv_image_view *view,
1404 struct radv_device *device,
1405 const VkImageViewCreateInfo* pCreateInfo);
1406
1407 struct radv_buffer_view {
1408 struct radeon_winsys_bo *bo;
1409 VkFormat vk_format;
1410 uint64_t range; /**< VkBufferViewCreateInfo::range */
1411 uint32_t state[4];
1412 };
1413 void radv_buffer_view_init(struct radv_buffer_view *view,
1414 struct radv_device *device,
1415 const VkBufferViewCreateInfo* pCreateInfo);
1416
1417 static inline struct VkExtent3D
1418 radv_sanitize_image_extent(const VkImageType imageType,
1419 const struct VkExtent3D imageExtent)
1420 {
1421 switch (imageType) {
1422 case VK_IMAGE_TYPE_1D:
1423 return (VkExtent3D) { imageExtent.width, 1, 1 };
1424 case VK_IMAGE_TYPE_2D:
1425 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1426 case VK_IMAGE_TYPE_3D:
1427 return imageExtent;
1428 default:
1429 unreachable("invalid image type");
1430 }
1431 }
1432
1433 static inline struct VkOffset3D
1434 radv_sanitize_image_offset(const VkImageType imageType,
1435 const struct VkOffset3D imageOffset)
1436 {
1437 switch (imageType) {
1438 case VK_IMAGE_TYPE_1D:
1439 return (VkOffset3D) { imageOffset.x, 0, 0 };
1440 case VK_IMAGE_TYPE_2D:
1441 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1442 case VK_IMAGE_TYPE_3D:
1443 return imageOffset;
1444 default:
1445 unreachable("invalid image type");
1446 }
1447 }
1448
1449 static inline bool
1450 radv_image_extent_compare(const struct radv_image *image,
1451 const VkExtent3D *extent)
1452 {
1453 if (extent->width != image->info.width ||
1454 extent->height != image->info.height ||
1455 extent->depth != image->info.depth)
1456 return false;
1457 return true;
1458 }
1459
1460 struct radv_sampler {
1461 uint32_t state[4];
1462 };
1463
1464 struct radv_color_buffer_info {
1465 uint64_t cb_color_base;
1466 uint64_t cb_color_cmask;
1467 uint64_t cb_color_fmask;
1468 uint64_t cb_dcc_base;
1469 uint32_t cb_color_pitch;
1470 uint32_t cb_color_slice;
1471 uint32_t cb_color_view;
1472 uint32_t cb_color_info;
1473 uint32_t cb_color_attrib;
1474 uint32_t cb_color_attrib2;
1475 uint32_t cb_dcc_control;
1476 uint32_t cb_color_cmask_slice;
1477 uint32_t cb_color_fmask_slice;
1478 uint32_t cb_clear_value0;
1479 uint32_t cb_clear_value1;
1480 };
1481
1482 struct radv_ds_buffer_info {
1483 uint64_t db_z_read_base;
1484 uint64_t db_stencil_read_base;
1485 uint64_t db_z_write_base;
1486 uint64_t db_stencil_write_base;
1487 uint64_t db_htile_data_base;
1488 uint32_t db_depth_info;
1489 uint32_t db_z_info;
1490 uint32_t db_stencil_info;
1491 uint32_t db_depth_view;
1492 uint32_t db_depth_size;
1493 uint32_t db_depth_slice;
1494 uint32_t db_htile_surface;
1495 uint32_t pa_su_poly_offset_db_fmt_cntl;
1496 uint32_t db_z_info2;
1497 uint32_t db_stencil_info2;
1498 float offset_scale;
1499 };
1500
1501 struct radv_attachment_info {
1502 union {
1503 struct radv_color_buffer_info cb;
1504 struct radv_ds_buffer_info ds;
1505 };
1506 struct radv_image_view *attachment;
1507 };
1508
1509 struct radv_framebuffer {
1510 uint32_t width;
1511 uint32_t height;
1512 uint32_t layers;
1513
1514 uint32_t attachment_count;
1515 struct radv_attachment_info attachments[0];
1516 };
1517
1518 struct radv_subpass_barrier {
1519 VkPipelineStageFlags src_stage_mask;
1520 VkAccessFlags src_access_mask;
1521 VkAccessFlags dst_access_mask;
1522 };
1523
1524 struct radv_subpass {
1525 uint32_t input_count;
1526 uint32_t color_count;
1527 VkAttachmentReference * input_attachments;
1528 VkAttachmentReference * color_attachments;
1529 VkAttachmentReference * resolve_attachments;
1530 VkAttachmentReference depth_stencil_attachment;
1531
1532 /** Subpass has at least one resolve attachment */
1533 bool has_resolve;
1534
1535 struct radv_subpass_barrier start_barrier;
1536
1537 uint32_t view_mask;
1538 };
1539
1540 struct radv_render_pass_attachment {
1541 VkFormat format;
1542 uint32_t samples;
1543 VkAttachmentLoadOp load_op;
1544 VkAttachmentLoadOp stencil_load_op;
1545 VkImageLayout initial_layout;
1546 VkImageLayout final_layout;
1547 uint32_t view_mask;
1548 };
1549
1550 struct radv_render_pass {
1551 uint32_t attachment_count;
1552 uint32_t subpass_count;
1553 VkAttachmentReference * subpass_attachments;
1554 struct radv_render_pass_attachment * attachments;
1555 struct radv_subpass_barrier end_barrier;
1556 struct radv_subpass subpasses[0];
1557 };
1558
1559 VkResult radv_device_init_meta(struct radv_device *device);
1560 void radv_device_finish_meta(struct radv_device *device);
1561
1562 struct radv_query_pool {
1563 struct radeon_winsys_bo *bo;
1564 uint32_t stride;
1565 uint32_t availability_offset;
1566 char *ptr;
1567 VkQueryType type;
1568 uint32_t pipeline_stats_mask;
1569 };
1570
1571 struct radv_semaphore {
1572 /* use a winsys sem for non-exportable */
1573 struct radeon_winsys_sem *sem;
1574 uint32_t syncobj;
1575 uint32_t temp_syncobj;
1576 };
1577
1578 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1579 int num_wait_sems,
1580 const VkSemaphore *wait_sems,
1581 int num_signal_sems,
1582 const VkSemaphore *signal_sems,
1583 VkFence fence);
1584 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1585
1586 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1587 struct radv_descriptor_set *set,
1588 unsigned idx);
1589
1590 void
1591 radv_update_descriptor_sets(struct radv_device *device,
1592 struct radv_cmd_buffer *cmd_buffer,
1593 VkDescriptorSet overrideSet,
1594 uint32_t descriptorWriteCount,
1595 const VkWriteDescriptorSet *pDescriptorWrites,
1596 uint32_t descriptorCopyCount,
1597 const VkCopyDescriptorSet *pDescriptorCopies);
1598
1599 void
1600 radv_update_descriptor_set_with_template(struct radv_device *device,
1601 struct radv_cmd_buffer *cmd_buffer,
1602 struct radv_descriptor_set *set,
1603 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1604 const void *pData);
1605
1606 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1607 VkPipelineBindPoint pipelineBindPoint,
1608 VkPipelineLayout _layout,
1609 uint32_t set,
1610 uint32_t descriptorWriteCount,
1611 const VkWriteDescriptorSet *pDescriptorWrites);
1612
1613 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1614 struct radv_image *image, uint32_t value);
1615 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1616 struct radv_image *image, uint32_t value);
1617
1618 struct radv_fence {
1619 struct radeon_winsys_fence *fence;
1620 bool submitted;
1621 bool signalled;
1622
1623 uint32_t syncobj;
1624 uint32_t temp_syncobj;
1625 };
1626
1627 struct radeon_winsys_sem;
1628
1629 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1630 \
1631 static inline struct __radv_type * \
1632 __radv_type ## _from_handle(__VkType _handle) \
1633 { \
1634 return (struct __radv_type *) _handle; \
1635 } \
1636 \
1637 static inline __VkType \
1638 __radv_type ## _to_handle(struct __radv_type *_obj) \
1639 { \
1640 return (__VkType) _obj; \
1641 }
1642
1643 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1644 \
1645 static inline struct __radv_type * \
1646 __radv_type ## _from_handle(__VkType _handle) \
1647 { \
1648 return (struct __radv_type *)(uintptr_t) _handle; \
1649 } \
1650 \
1651 static inline __VkType \
1652 __radv_type ## _to_handle(struct __radv_type *_obj) \
1653 { \
1654 return (__VkType)(uintptr_t) _obj; \
1655 }
1656
1657 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1658 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1659
1660 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1661 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1662 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1663 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1664 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1665
1666 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1667 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1668 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1669 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1670 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1671 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1672 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1673 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1674 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1675 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1676 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1677 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1678 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1679 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1680 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1681 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1682 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1683 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1684 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1685 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1686 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1687
1688 #endif /* RADV_PRIVATE_H */