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radv: Add mapping between dynamic state mask and external enum.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275 bool cpdma_prefetch_writes_memory;
276 bool has_scissor_bug;
277
278 /* This is the drivers on-disk cache used as a fallback as opposed to
279 * the pipeline cache defined by apps.
280 */
281 struct disk_cache * disk_cache;
282
283 VkPhysicalDeviceMemoryProperties memory_properties;
284 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
285 };
286
287 struct radv_instance {
288 VK_LOADER_DATA _loader_data;
289
290 VkAllocationCallbacks alloc;
291
292 uint32_t apiVersion;
293 int physicalDeviceCount;
294 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
295
296 uint64_t debug_flags;
297 uint64_t perftest_flags;
298 };
299
300 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
301 void radv_finish_wsi(struct radv_physical_device *physical_device);
302
303 bool radv_instance_extension_supported(const char *name);
304 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
305 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
306 const char *name);
307
308 struct cache_entry;
309
310 struct radv_pipeline_cache {
311 struct radv_device * device;
312 pthread_mutex_t mutex;
313
314 uint32_t total_size;
315 uint32_t table_size;
316 uint32_t kernel_count;
317 struct cache_entry ** hash_table;
318 bool modified;
319
320 VkAllocationCallbacks alloc;
321 };
322
323 struct radv_pipeline_key {
324 uint32_t instance_rate_inputs;
325 unsigned tess_input_vertices;
326 uint32_t col_format;
327 uint32_t is_int8;
328 uint32_t is_int10;
329 uint32_t multisample : 1;
330 uint32_t has_multiview_view_index : 1;
331 };
332
333 void
334 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
335 struct radv_device *device);
336 void
337 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
338 void
339 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
340 const void *data, size_t size);
341
342 struct radv_shader_variant;
343
344 bool
345 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
346 struct radv_pipeline_cache *cache,
347 const unsigned char *sha1,
348 struct radv_shader_variant **variants);
349
350 void
351 radv_pipeline_cache_insert_shaders(struct radv_device *device,
352 struct radv_pipeline_cache *cache,
353 const unsigned char *sha1,
354 struct radv_shader_variant **variants,
355 const void *const *codes,
356 const unsigned *code_sizes);
357
358 enum radv_blit_ds_layout {
359 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
360 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
361 RADV_BLIT_DS_LAYOUT_COUNT,
362 };
363
364 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
365 {
366 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
367 }
368
369 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
370 {
371 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
372 }
373
374 enum radv_meta_dst_layout {
375 RADV_META_DST_LAYOUT_GENERAL,
376 RADV_META_DST_LAYOUT_OPTIMAL,
377 RADV_META_DST_LAYOUT_COUNT,
378 };
379
380 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
381 {
382 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
383 }
384
385 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
386 {
387 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
388 }
389
390 struct radv_meta_state {
391 VkAllocationCallbacks alloc;
392
393 struct radv_pipeline_cache cache;
394
395 /**
396 * Use array element `i` for images with `2^i` samples.
397 */
398 struct {
399 VkRenderPass render_pass[NUM_META_FS_KEYS];
400 VkPipeline color_pipelines[NUM_META_FS_KEYS];
401
402 VkRenderPass depthstencil_rp;
403 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
404 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
405 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
406 } clear[1 + MAX_SAMPLES_LOG2];
407
408 VkPipelineLayout clear_color_p_layout;
409 VkPipelineLayout clear_depth_p_layout;
410 struct {
411 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
412
413 /** Pipeline that blits from a 1D image. */
414 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
415
416 /** Pipeline that blits from a 2D image. */
417 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
418
419 /** Pipeline that blits from a 3D image. */
420 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
421
422 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
423 VkPipeline depth_only_1d_pipeline;
424 VkPipeline depth_only_2d_pipeline;
425 VkPipeline depth_only_3d_pipeline;
426
427 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
428 VkPipeline stencil_only_1d_pipeline;
429 VkPipeline stencil_only_2d_pipeline;
430 VkPipeline stencil_only_3d_pipeline;
431 VkPipelineLayout pipeline_layout;
432 VkDescriptorSetLayout ds_layout;
433 } blit;
434
435 struct {
436 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
437
438 VkPipelineLayout p_layouts[3];
439 VkDescriptorSetLayout ds_layouts[3];
440 VkPipeline pipelines[3][NUM_META_FS_KEYS];
441
442 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
443 VkPipeline depth_only_pipeline[3];
444
445 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
446 VkPipeline stencil_only_pipeline[3];
447 } blit2d;
448
449 struct {
450 VkPipelineLayout img_p_layout;
451 VkDescriptorSetLayout img_ds_layout;
452 VkPipeline pipeline;
453 VkPipeline pipeline_3d;
454 } itob;
455 struct {
456 VkPipelineLayout img_p_layout;
457 VkDescriptorSetLayout img_ds_layout;
458 VkPipeline pipeline;
459 VkPipeline pipeline_3d;
460 } btoi;
461 struct {
462 VkPipelineLayout img_p_layout;
463 VkDescriptorSetLayout img_ds_layout;
464 VkPipeline pipeline;
465 VkPipeline pipeline_3d;
466 } itoi;
467 struct {
468 VkPipelineLayout img_p_layout;
469 VkDescriptorSetLayout img_ds_layout;
470 VkPipeline pipeline;
471 VkPipeline pipeline_3d;
472 } cleari;
473
474 struct {
475 VkPipelineLayout p_layout;
476 VkPipeline pipeline;
477 VkRenderPass pass;
478 } resolve;
479
480 struct {
481 VkDescriptorSetLayout ds_layout;
482 VkPipelineLayout p_layout;
483 struct {
484 VkPipeline pipeline;
485 VkPipeline i_pipeline;
486 VkPipeline srgb_pipeline;
487 } rc[MAX_SAMPLES_LOG2];
488 } resolve_compute;
489
490 struct {
491 VkDescriptorSetLayout ds_layout;
492 VkPipelineLayout p_layout;
493
494 struct {
495 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
496 VkPipeline pipeline[NUM_META_FS_KEYS];
497 } rc[MAX_SAMPLES_LOG2];
498 } resolve_fragment;
499
500 struct {
501 VkPipelineLayout p_layout;
502 VkPipeline decompress_pipeline;
503 VkPipeline resummarize_pipeline;
504 VkRenderPass pass;
505 } depth_decomp[1 + MAX_SAMPLES_LOG2];
506
507 struct {
508 VkPipelineLayout p_layout;
509 VkPipeline cmask_eliminate_pipeline;
510 VkPipeline fmask_decompress_pipeline;
511 VkPipeline dcc_decompress_pipeline;
512 VkRenderPass pass;
513
514 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
515 VkPipelineLayout dcc_decompress_compute_p_layout;
516 VkPipeline dcc_decompress_compute_pipeline;
517 } fast_clear_flush;
518
519 struct {
520 VkPipelineLayout fill_p_layout;
521 VkPipelineLayout copy_p_layout;
522 VkDescriptorSetLayout fill_ds_layout;
523 VkDescriptorSetLayout copy_ds_layout;
524 VkPipeline fill_pipeline;
525 VkPipeline copy_pipeline;
526 } buffer;
527
528 struct {
529 VkDescriptorSetLayout ds_layout;
530 VkPipelineLayout p_layout;
531 VkPipeline occlusion_query_pipeline;
532 VkPipeline pipeline_statistics_query_pipeline;
533 } query;
534 };
535
536 /* queue types */
537 #define RADV_QUEUE_GENERAL 0
538 #define RADV_QUEUE_COMPUTE 1
539 #define RADV_QUEUE_TRANSFER 2
540
541 #define RADV_MAX_QUEUE_FAMILIES 3
542
543 enum ring_type radv_queue_family_to_ring(int f);
544
545 struct radv_queue {
546 VK_LOADER_DATA _loader_data;
547 struct radv_device * device;
548 struct radeon_winsys_ctx *hw_ctx;
549 enum radeon_ctx_priority priority;
550 uint32_t queue_family_index;
551 int queue_idx;
552
553 uint32_t scratch_size;
554 uint32_t compute_scratch_size;
555 uint32_t esgs_ring_size;
556 uint32_t gsvs_ring_size;
557 bool has_tess_rings;
558 bool has_sample_positions;
559
560 struct radeon_winsys_bo *scratch_bo;
561 struct radeon_winsys_bo *descriptor_bo;
562 struct radeon_winsys_bo *compute_scratch_bo;
563 struct radeon_winsys_bo *esgs_ring_bo;
564 struct radeon_winsys_bo *gsvs_ring_bo;
565 struct radeon_winsys_bo *tess_factor_ring_bo;
566 struct radeon_winsys_bo *tess_offchip_ring_bo;
567 struct radeon_winsys_cs *initial_preamble_cs;
568 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
569 struct radeon_winsys_cs *continue_preamble_cs;
570 };
571
572 struct radv_device {
573 VK_LOADER_DATA _loader_data;
574
575 VkAllocationCallbacks alloc;
576
577 struct radv_instance * instance;
578 struct radeon_winsys *ws;
579
580 struct radv_meta_state meta_state;
581
582 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
583 int queue_count[RADV_MAX_QUEUE_FAMILIES];
584 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
585
586 bool llvm_supports_spill;
587 bool has_distributed_tess;
588 bool pbb_allowed;
589 bool dfsm_allowed;
590 uint32_t tess_offchip_block_dw_size;
591 uint32_t scratch_waves;
592 uint32_t dispatch_initiator;
593
594 uint32_t gs_table_depth;
595
596 /* MSAA sample locations.
597 * The first index is the sample index.
598 * The second index is the coordinate: X, Y. */
599 float sample_locations_1x[1][2];
600 float sample_locations_2x[2][2];
601 float sample_locations_4x[4][2];
602 float sample_locations_8x[8][2];
603 float sample_locations_16x[16][2];
604
605 /* CIK and later */
606 uint32_t gfx_init_size_dw;
607 struct radeon_winsys_bo *gfx_init;
608
609 struct radeon_winsys_bo *trace_bo;
610 uint32_t *trace_id_ptr;
611
612 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
613 bool keep_shader_info;
614
615 struct radv_physical_device *physical_device;
616
617 /* Backup in-memory cache to be used if the app doesn't provide one */
618 struct radv_pipeline_cache * mem_cache;
619
620 /*
621 * use different counters so MSAA MRTs get consecutive surface indices,
622 * even if MASK is allocated in between.
623 */
624 uint32_t image_mrt_offset_counter;
625 uint32_t fmask_mrt_offset_counter;
626 struct list_head shader_slabs;
627 mtx_t shader_slab_mutex;
628
629 /* For detecting VM faults reported by dmesg. */
630 uint64_t dmesg_timestamp;
631 };
632
633 struct radv_device_memory {
634 struct radeon_winsys_bo *bo;
635 /* for dedicated allocations */
636 struct radv_image *image;
637 struct radv_buffer *buffer;
638 uint32_t type_index;
639 VkDeviceSize map_size;
640 void * map;
641 };
642
643
644 struct radv_descriptor_range {
645 uint64_t va;
646 uint32_t size;
647 };
648
649 struct radv_descriptor_set {
650 const struct radv_descriptor_set_layout *layout;
651 uint32_t size;
652
653 struct radeon_winsys_bo *bo;
654 uint64_t va;
655 uint32_t *mapped_ptr;
656 struct radv_descriptor_range *dynamic_descriptors;
657
658 struct radeon_winsys_bo *descriptors[0];
659 };
660
661 struct radv_push_descriptor_set
662 {
663 struct radv_descriptor_set set;
664 uint32_t capacity;
665 };
666
667 struct radv_descriptor_pool_entry {
668 uint32_t offset;
669 uint32_t size;
670 struct radv_descriptor_set *set;
671 };
672
673 struct radv_descriptor_pool {
674 struct radeon_winsys_bo *bo;
675 uint8_t *mapped_ptr;
676 uint64_t current_offset;
677 uint64_t size;
678
679 uint8_t *host_memory_base;
680 uint8_t *host_memory_ptr;
681 uint8_t *host_memory_end;
682
683 uint32_t entry_count;
684 uint32_t max_entry_count;
685 struct radv_descriptor_pool_entry entries[0];
686 };
687
688 struct radv_descriptor_update_template_entry {
689 VkDescriptorType descriptor_type;
690
691 /* The number of descriptors to update */
692 uint32_t descriptor_count;
693
694 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
695 uint32_t dst_offset;
696
697 /* In dwords. Not valid/used for dynamic descriptors */
698 uint32_t dst_stride;
699
700 uint32_t buffer_offset;
701
702 /* Only valid for combined image samplers and samplers */
703 uint16_t has_sampler;
704
705 /* In bytes */
706 size_t src_offset;
707 size_t src_stride;
708
709 /* For push descriptors */
710 const uint32_t *immutable_samplers;
711 };
712
713 struct radv_descriptor_update_template {
714 uint32_t entry_count;
715 struct radv_descriptor_update_template_entry entry[0];
716 };
717
718 struct radv_buffer {
719 struct radv_device * device;
720 VkDeviceSize size;
721
722 VkBufferUsageFlags usage;
723 VkBufferCreateFlags flags;
724
725 /* Set when bound */
726 struct radeon_winsys_bo * bo;
727 VkDeviceSize offset;
728
729 bool shareable;
730 };
731
732 enum radv_dynamic_state_bits {
733 RADV_DYNAMIC_VIEWPORT = 1 << 0,
734 RADV_DYNAMIC_SCISSOR = 1 << 1,
735 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
736 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
737 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
738 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
739 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
740 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
741 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
742 RADV_DYNAMIC_ALL = (1 << 9) - 1,
743 };
744
745 enum radv_cmd_dirty_bits {
746 /* Keep the dynamic state dirty bits in sync with
747 * enum radv_dynamic_state_bits */
748 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
749 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
750 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
751 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
752 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
753 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
754 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
755 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
756 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
757 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
758 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
759 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
760 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
761 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
762 };
763
764 enum radv_cmd_flush_bits {
765 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
766 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
767 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
768 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
769 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
770 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
771 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
772 /* Same as above, but only writes back and doesn't invalidate */
773 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
774 /* Framebuffer caches */
775 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
776 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
777 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
778 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
779 /* Engine synchronization. */
780 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
781 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
782 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
783 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
784
785 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
786 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
787 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
788 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
789 };
790
791 struct radv_vertex_binding {
792 struct radv_buffer * buffer;
793 VkDeviceSize offset;
794 };
795
796 struct radv_viewport_state {
797 uint32_t count;
798 VkViewport viewports[MAX_VIEWPORTS];
799 };
800
801 struct radv_scissor_state {
802 uint32_t count;
803 VkRect2D scissors[MAX_SCISSORS];
804 };
805
806 struct radv_dynamic_state {
807 /**
808 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
809 * Defines the set of saved dynamic state.
810 */
811 uint32_t mask;
812
813 struct radv_viewport_state viewport;
814
815 struct radv_scissor_state scissor;
816
817 float line_width;
818
819 struct {
820 float bias;
821 float clamp;
822 float slope;
823 } depth_bias;
824
825 float blend_constants[4];
826
827 struct {
828 float min;
829 float max;
830 } depth_bounds;
831
832 struct {
833 uint32_t front;
834 uint32_t back;
835 } stencil_compare_mask;
836
837 struct {
838 uint32_t front;
839 uint32_t back;
840 } stencil_write_mask;
841
842 struct {
843 uint32_t front;
844 uint32_t back;
845 } stencil_reference;
846 };
847
848 extern const struct radv_dynamic_state default_dynamic_state;
849
850 const char *
851 radv_get_debug_option_name(int id);
852
853 const char *
854 radv_get_perftest_option_name(int id);
855
856 /**
857 * Attachment state when recording a renderpass instance.
858 *
859 * The clear value is valid only if there exists a pending clear.
860 */
861 struct radv_attachment_state {
862 VkImageAspectFlags pending_clear_aspects;
863 uint32_t cleared_views;
864 VkClearValue clear_value;
865 VkImageLayout current_layout;
866 };
867
868 struct radv_cmd_state {
869 /* Vertex descriptors */
870 bool vb_prefetch_dirty;
871 uint64_t vb_va;
872 unsigned vb_size;
873
874 bool push_descriptors_dirty;
875 bool predicating;
876 uint32_t dirty;
877
878 struct radv_pipeline * pipeline;
879 struct radv_pipeline * emitted_pipeline;
880 struct radv_pipeline * compute_pipeline;
881 struct radv_pipeline * emitted_compute_pipeline;
882 struct radv_framebuffer * framebuffer;
883 struct radv_render_pass * pass;
884 const struct radv_subpass * subpass;
885 struct radv_dynamic_state dynamic;
886 struct radv_attachment_state * attachments;
887 VkRect2D render_area;
888
889 /* Index buffer */
890 struct radv_buffer *index_buffer;
891 uint64_t index_offset;
892 uint32_t index_type;
893 uint32_t max_index_count;
894 uint64_t index_va;
895 int32_t last_index_type;
896
897 int32_t last_primitive_reset_en;
898 uint32_t last_primitive_reset_index;
899 enum radv_cmd_flush_bits flush_bits;
900 unsigned active_occlusion_queries;
901 float offset_scale;
902 uint32_t descriptors_dirty;
903 uint32_t valid_descriptors;
904 uint32_t trace_id;
905 uint32_t last_ia_multi_vgt_param;
906 };
907
908 struct radv_cmd_pool {
909 VkAllocationCallbacks alloc;
910 struct list_head cmd_buffers;
911 struct list_head free_cmd_buffers;
912 uint32_t queue_family_index;
913 };
914
915 struct radv_cmd_buffer_upload {
916 uint8_t *map;
917 unsigned offset;
918 uint64_t size;
919 struct radeon_winsys_bo *upload_bo;
920 struct list_head list;
921 };
922
923 enum radv_cmd_buffer_status {
924 RADV_CMD_BUFFER_STATUS_INVALID,
925 RADV_CMD_BUFFER_STATUS_INITIAL,
926 RADV_CMD_BUFFER_STATUS_RECORDING,
927 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
928 RADV_CMD_BUFFER_STATUS_PENDING,
929 };
930
931 struct radv_cmd_buffer {
932 VK_LOADER_DATA _loader_data;
933
934 struct radv_device * device;
935
936 struct radv_cmd_pool * pool;
937 struct list_head pool_link;
938
939 VkCommandBufferUsageFlags usage_flags;
940 VkCommandBufferLevel level;
941 enum radv_cmd_buffer_status status;
942 struct radeon_winsys_cs *cs;
943 struct radv_cmd_state state;
944 struct radv_vertex_binding vertex_bindings[MAX_VBS];
945 uint32_t queue_family_index;
946
947 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
948 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
949 VkShaderStageFlags push_constant_stages;
950 struct radv_push_descriptor_set push_descriptors;
951 struct radv_descriptor_set meta_push_descriptors;
952 struct radv_descriptor_set *descriptors[MAX_SETS];
953
954 struct radv_cmd_buffer_upload upload;
955
956 uint32_t scratch_size_needed;
957 uint32_t compute_scratch_size_needed;
958 uint32_t esgs_ring_size_needed;
959 uint32_t gsvs_ring_size_needed;
960 bool tess_rings_needed;
961 bool sample_positions_needed;
962
963 VkResult record_result;
964
965 int ring_offsets_idx; /* just used for verification */
966 uint32_t gfx9_fence_offset;
967 struct radeon_winsys_bo *gfx9_fence_bo;
968 uint32_t gfx9_fence_idx;
969 };
970
971 struct radv_image;
972
973 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
974
975 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
976 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
977
978 void cik_create_gfx_config(struct radv_device *device);
979
980 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
981 int count, const VkViewport *viewports);
982 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
983 int count, const VkRect2D *scissors,
984 const VkViewport *viewports, bool can_use_guardband);
985 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
986 bool instanced_draw, bool indirect_draw,
987 uint32_t draw_vertex_count);
988 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
989 bool predicated,
990 enum chip_class chip_class,
991 bool is_mec,
992 unsigned event, unsigned event_flags,
993 unsigned data_sel,
994 uint64_t va,
995 uint32_t old_fence,
996 uint32_t new_fence);
997
998 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
999 bool predicated,
1000 uint64_t va, uint32_t ref,
1001 uint32_t mask);
1002 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1003 bool predicated,
1004 enum chip_class chip_class,
1005 uint32_t *fence_ptr, uint64_t va,
1006 bool is_mec,
1007 enum radv_cmd_flush_bits flush_bits);
1008 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1009 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1010 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1011 uint64_t src_va, uint64_t dest_va,
1012 uint64_t size);
1013 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1014 unsigned size);
1015 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1016 uint64_t size, unsigned value);
1017 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1018 bool
1019 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1020 unsigned size,
1021 unsigned alignment,
1022 unsigned *out_offset,
1023 void **ptr);
1024 void
1025 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1026 const struct radv_subpass *subpass,
1027 bool transitions);
1028 bool
1029 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1030 unsigned size, unsigned alignmnet,
1031 const void *data, unsigned *out_offset);
1032
1033 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1034 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1035 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1036 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1037 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1038 unsigned radv_cayman_get_maxdist(int log_samples);
1039 void radv_device_init_msaa(struct radv_device *device);
1040 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1041 struct radv_image *image,
1042 VkClearDepthStencilValue ds_clear_value,
1043 VkImageAspectFlags aspects);
1044 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1045 struct radv_image *image,
1046 int idx,
1047 uint32_t color_values[2]);
1048 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1049 struct radv_image *image,
1050 bool value);
1051 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1052 struct radeon_winsys_bo *bo,
1053 uint64_t offset, uint64_t size, uint32_t value);
1054 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1055 bool radv_get_memory_fd(struct radv_device *device,
1056 struct radv_device_memory *memory,
1057 int *pFD);
1058
1059 /*
1060 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1061 *
1062 * Limitations: Can't call normal dispatch functions without binding or rebinding
1063 * the compute pipeline.
1064 */
1065 void radv_unaligned_dispatch(
1066 struct radv_cmd_buffer *cmd_buffer,
1067 uint32_t x,
1068 uint32_t y,
1069 uint32_t z);
1070
1071 struct radv_event {
1072 struct radeon_winsys_bo *bo;
1073 uint64_t *map;
1074 };
1075
1076 struct radv_shader_module;
1077
1078 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1079 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1080 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1081 void
1082 radv_hash_shaders(unsigned char *hash,
1083 const VkPipelineShaderStageCreateInfo **stages,
1084 const struct radv_pipeline_layout *layout,
1085 const struct radv_pipeline_key *key,
1086 uint32_t flags);
1087
1088 static inline gl_shader_stage
1089 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1090 {
1091 assert(__builtin_popcount(vk_stage) == 1);
1092 return ffs(vk_stage) - 1;
1093 }
1094
1095 static inline VkShaderStageFlagBits
1096 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1097 {
1098 return (1 << mesa_stage);
1099 }
1100
1101 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1102
1103 #define radv_foreach_stage(stage, stage_bits) \
1104 for (gl_shader_stage stage, \
1105 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1106 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1107 __tmp &= ~(1 << (stage)))
1108
1109 struct radv_depth_stencil_state {
1110 uint32_t db_depth_control;
1111 uint32_t db_stencil_control;
1112 uint32_t db_render_control;
1113 uint32_t db_render_override2;
1114 };
1115
1116 struct radv_blend_state {
1117 uint32_t cb_color_control;
1118 uint32_t cb_target_mask;
1119 uint32_t sx_mrt_blend_opt[8];
1120 uint32_t cb_blend_control[8];
1121
1122 uint32_t spi_shader_col_format;
1123 uint32_t cb_shader_mask;
1124 uint32_t db_alpha_to_mask;
1125 };
1126
1127 unsigned radv_format_meta_fs_key(VkFormat format);
1128
1129 struct radv_raster_state {
1130 uint32_t pa_cl_clip_cntl;
1131 uint32_t spi_interp_control;
1132 uint32_t pa_su_vtx_cntl;
1133 uint32_t pa_su_sc_mode_cntl;
1134 };
1135
1136 struct radv_multisample_state {
1137 uint32_t db_eqaa;
1138 uint32_t pa_sc_line_cntl;
1139 uint32_t pa_sc_mode_cntl_0;
1140 uint32_t pa_sc_mode_cntl_1;
1141 uint32_t pa_sc_aa_config;
1142 uint32_t pa_sc_aa_mask[2];
1143 unsigned num_samples;
1144 };
1145
1146 struct radv_prim_vertex_count {
1147 uint8_t min;
1148 uint8_t incr;
1149 };
1150
1151 struct radv_tessellation_state {
1152 uint32_t ls_hs_config;
1153 uint32_t tcs_in_layout;
1154 uint32_t tcs_out_layout;
1155 uint32_t tcs_out_offsets;
1156 uint32_t offchip_layout;
1157 unsigned num_patches;
1158 unsigned lds_size;
1159 unsigned num_tcs_input_cp;
1160 uint32_t tf_param;
1161 };
1162
1163 struct radv_gs_state {
1164 uint32_t vgt_gs_onchip_cntl;
1165 uint32_t vgt_gs_max_prims_per_subgroup;
1166 uint32_t vgt_esgs_ring_itemsize;
1167 uint32_t lds_size;
1168 };
1169
1170 struct radv_vertex_elements_info {
1171 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1172 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1173 uint32_t binding[MAX_VERTEX_ATTRIBS];
1174 uint32_t offset[MAX_VERTEX_ATTRIBS];
1175 uint32_t count;
1176 };
1177
1178 struct radv_vs_state {
1179 uint32_t pa_cl_vs_out_cntl;
1180 uint32_t spi_shader_pos_format;
1181 uint32_t spi_vs_out_config;
1182 uint32_t vgt_reuse_off;
1183 };
1184
1185 struct radv_binning_state {
1186 uint32_t pa_sc_binner_cntl_0;
1187 uint32_t db_dfsm_control;
1188 };
1189
1190 #define SI_GS_PER_ES 128
1191
1192 struct radv_pipeline {
1193 struct radv_device * device;
1194 struct radv_dynamic_state dynamic_state;
1195
1196 struct radv_pipeline_layout * layout;
1197
1198 bool needs_data_cache;
1199 bool need_indirect_descriptor_sets;
1200 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1201 struct radv_shader_variant *gs_copy_shader;
1202 VkShaderStageFlags active_stages;
1203
1204 struct radv_vertex_elements_info vertex_elements;
1205
1206 uint32_t binding_stride[MAX_VBS];
1207
1208 uint32_t user_data_0[MESA_SHADER_STAGES];
1209 union {
1210 struct {
1211 struct radv_blend_state blend;
1212 struct radv_depth_stencil_state ds;
1213 struct radv_raster_state raster;
1214 struct radv_multisample_state ms;
1215 struct radv_tessellation_state tess;
1216 struct radv_gs_state gs;
1217 struct radv_vs_state vs;
1218 struct radv_binning_state bin;
1219 uint32_t db_shader_control;
1220 uint32_t shader_z_format;
1221 unsigned prim;
1222 unsigned gs_out;
1223 uint32_t vgt_gs_mode;
1224 bool vgt_primitiveid_en;
1225 bool prim_restart_enable;
1226 bool partial_es_wave;
1227 uint8_t primgroup_size;
1228 unsigned esgs_ring_size;
1229 unsigned gsvs_ring_size;
1230 uint32_t ps_input_cntl[32];
1231 uint32_t ps_input_cntl_num;
1232 uint32_t vgt_shader_stages_en;
1233 uint32_t vtx_base_sgpr;
1234 uint32_t base_ia_multi_vgt_param;
1235 bool wd_switch_on_eop;
1236 bool ia_switch_on_eoi;
1237 bool partial_vs_wave;
1238 uint8_t vtx_emit_num;
1239 uint32_t vtx_reuse_depth;
1240 struct radv_prim_vertex_count prim_vertex_count;
1241 bool can_use_guardband;
1242 } graphics;
1243 };
1244
1245 unsigned max_waves;
1246 unsigned scratch_bytes_per_wave;
1247 };
1248
1249 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1250 {
1251 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1252 }
1253
1254 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1255 {
1256 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1257 }
1258
1259 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1260 gl_shader_stage stage,
1261 int idx);
1262
1263 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1264
1265 struct radv_graphics_pipeline_create_info {
1266 bool use_rectlist;
1267 bool db_depth_clear;
1268 bool db_stencil_clear;
1269 bool db_depth_disable_expclear;
1270 bool db_stencil_disable_expclear;
1271 bool db_flush_depth_inplace;
1272 bool db_flush_stencil_inplace;
1273 bool db_resummarize;
1274 uint32_t custom_blend_mode;
1275 };
1276
1277 VkResult
1278 radv_graphics_pipeline_create(VkDevice device,
1279 VkPipelineCache cache,
1280 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1281 const struct radv_graphics_pipeline_create_info *extra,
1282 const VkAllocationCallbacks *alloc,
1283 VkPipeline *pPipeline);
1284
1285 struct vk_format_description;
1286 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1287 int first_non_void);
1288 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1289 int first_non_void);
1290 uint32_t radv_translate_colorformat(VkFormat format);
1291 uint32_t radv_translate_color_numformat(VkFormat format,
1292 const struct vk_format_description *desc,
1293 int first_non_void);
1294 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1295 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1296 uint32_t radv_translate_dbformat(VkFormat format);
1297 uint32_t radv_translate_tex_dataformat(VkFormat format,
1298 const struct vk_format_description *desc,
1299 int first_non_void);
1300 uint32_t radv_translate_tex_numformat(VkFormat format,
1301 const struct vk_format_description *desc,
1302 int first_non_void);
1303 bool radv_format_pack_clear_color(VkFormat format,
1304 uint32_t clear_vals[2],
1305 VkClearColorValue *value);
1306 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1307 bool radv_dcc_formats_compatible(VkFormat format1,
1308 VkFormat format2);
1309
1310 struct radv_fmask_info {
1311 uint64_t offset;
1312 uint64_t size;
1313 unsigned alignment;
1314 unsigned pitch_in_pixels;
1315 unsigned bank_height;
1316 unsigned slice_tile_max;
1317 unsigned tile_mode_index;
1318 unsigned tile_swizzle;
1319 };
1320
1321 struct radv_cmask_info {
1322 uint64_t offset;
1323 uint64_t size;
1324 unsigned alignment;
1325 unsigned slice_tile_max;
1326 };
1327
1328 struct radv_image {
1329 VkImageType type;
1330 /* The original VkFormat provided by the client. This may not match any
1331 * of the actual surface formats.
1332 */
1333 VkFormat vk_format;
1334 VkImageAspectFlags aspects;
1335 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1336 struct ac_surf_info info;
1337 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1338 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1339
1340 VkDeviceSize size;
1341 uint32_t alignment;
1342
1343 unsigned queue_family_mask;
1344 bool exclusive;
1345 bool shareable;
1346
1347 /* Set when bound */
1348 struct radeon_winsys_bo *bo;
1349 VkDeviceSize offset;
1350 uint64_t dcc_offset;
1351 uint64_t htile_offset;
1352 bool tc_compatible_htile;
1353 struct radeon_surf surface;
1354
1355 struct radv_fmask_info fmask;
1356 struct radv_cmask_info cmask;
1357 uint64_t clear_value_offset;
1358 uint64_t dcc_pred_offset;
1359 };
1360
1361 /* Whether the image has a htile that is known consistent with the contents of
1362 * the image. */
1363 bool radv_layout_has_htile(const struct radv_image *image,
1364 VkImageLayout layout,
1365 unsigned queue_mask);
1366
1367 /* Whether the image has a htile that is known consistent with the contents of
1368 * the image and is allowed to be in compressed form.
1369 *
1370 * If this is false reads that don't use the htile should be able to return
1371 * correct results.
1372 */
1373 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1374 VkImageLayout layout,
1375 unsigned queue_mask);
1376
1377 bool radv_layout_can_fast_clear(const struct radv_image *image,
1378 VkImageLayout layout,
1379 unsigned queue_mask);
1380
1381 bool radv_layout_dcc_compressed(const struct radv_image *image,
1382 VkImageLayout layout,
1383 unsigned queue_mask);
1384
1385 static inline bool
1386 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1387 {
1388 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1389 }
1390
1391 static inline bool
1392 radv_htile_enabled(const struct radv_image *image, unsigned level)
1393 {
1394 return image->surface.htile_size && level == 0;
1395 }
1396
1397 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1398
1399 static inline uint32_t
1400 radv_get_layerCount(const struct radv_image *image,
1401 const VkImageSubresourceRange *range)
1402 {
1403 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1404 image->info.array_size - range->baseArrayLayer : range->layerCount;
1405 }
1406
1407 static inline uint32_t
1408 radv_get_levelCount(const struct radv_image *image,
1409 const VkImageSubresourceRange *range)
1410 {
1411 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1412 image->info.levels - range->baseMipLevel : range->levelCount;
1413 }
1414
1415 struct radeon_bo_metadata;
1416 void
1417 radv_init_metadata(struct radv_device *device,
1418 struct radv_image *image,
1419 struct radeon_bo_metadata *metadata);
1420
1421 struct radv_image_view {
1422 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1423 struct radeon_winsys_bo *bo;
1424
1425 VkImageViewType type;
1426 VkImageAspectFlags aspect_mask;
1427 VkFormat vk_format;
1428 uint32_t base_layer;
1429 uint32_t layer_count;
1430 uint32_t base_mip;
1431 uint32_t level_count;
1432 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1433
1434 uint32_t descriptor[16];
1435
1436 /* Descriptor for use as a storage image as opposed to a sampled image.
1437 * This has a few differences for cube maps (e.g. type).
1438 */
1439 uint32_t storage_descriptor[16];
1440 };
1441
1442 struct radv_image_create_info {
1443 const VkImageCreateInfo *vk_info;
1444 bool scanout;
1445 };
1446
1447 VkResult radv_image_create(VkDevice _device,
1448 const struct radv_image_create_info *info,
1449 const VkAllocationCallbacks* alloc,
1450 VkImage *pImage);
1451
1452 void radv_image_view_init(struct radv_image_view *view,
1453 struct radv_device *device,
1454 const VkImageViewCreateInfo* pCreateInfo);
1455
1456 struct radv_buffer_view {
1457 struct radeon_winsys_bo *bo;
1458 VkFormat vk_format;
1459 uint64_t range; /**< VkBufferViewCreateInfo::range */
1460 uint32_t state[4];
1461 };
1462 void radv_buffer_view_init(struct radv_buffer_view *view,
1463 struct radv_device *device,
1464 const VkBufferViewCreateInfo* pCreateInfo);
1465
1466 static inline struct VkExtent3D
1467 radv_sanitize_image_extent(const VkImageType imageType,
1468 const struct VkExtent3D imageExtent)
1469 {
1470 switch (imageType) {
1471 case VK_IMAGE_TYPE_1D:
1472 return (VkExtent3D) { imageExtent.width, 1, 1 };
1473 case VK_IMAGE_TYPE_2D:
1474 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1475 case VK_IMAGE_TYPE_3D:
1476 return imageExtent;
1477 default:
1478 unreachable("invalid image type");
1479 }
1480 }
1481
1482 static inline struct VkOffset3D
1483 radv_sanitize_image_offset(const VkImageType imageType,
1484 const struct VkOffset3D imageOffset)
1485 {
1486 switch (imageType) {
1487 case VK_IMAGE_TYPE_1D:
1488 return (VkOffset3D) { imageOffset.x, 0, 0 };
1489 case VK_IMAGE_TYPE_2D:
1490 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1491 case VK_IMAGE_TYPE_3D:
1492 return imageOffset;
1493 default:
1494 unreachable("invalid image type");
1495 }
1496 }
1497
1498 static inline bool
1499 radv_image_extent_compare(const struct radv_image *image,
1500 const VkExtent3D *extent)
1501 {
1502 if (extent->width != image->info.width ||
1503 extent->height != image->info.height ||
1504 extent->depth != image->info.depth)
1505 return false;
1506 return true;
1507 }
1508
1509 struct radv_sampler {
1510 uint32_t state[4];
1511 };
1512
1513 struct radv_color_buffer_info {
1514 uint64_t cb_color_base;
1515 uint64_t cb_color_cmask;
1516 uint64_t cb_color_fmask;
1517 uint64_t cb_dcc_base;
1518 uint32_t cb_color_pitch;
1519 uint32_t cb_color_slice;
1520 uint32_t cb_color_view;
1521 uint32_t cb_color_info;
1522 uint32_t cb_color_attrib;
1523 uint32_t cb_color_attrib2;
1524 uint32_t cb_dcc_control;
1525 uint32_t cb_color_cmask_slice;
1526 uint32_t cb_color_fmask_slice;
1527 };
1528
1529 struct radv_ds_buffer_info {
1530 uint64_t db_z_read_base;
1531 uint64_t db_stencil_read_base;
1532 uint64_t db_z_write_base;
1533 uint64_t db_stencil_write_base;
1534 uint64_t db_htile_data_base;
1535 uint32_t db_depth_info;
1536 uint32_t db_z_info;
1537 uint32_t db_stencil_info;
1538 uint32_t db_depth_view;
1539 uint32_t db_depth_size;
1540 uint32_t db_depth_slice;
1541 uint32_t db_htile_surface;
1542 uint32_t pa_su_poly_offset_db_fmt_cntl;
1543 uint32_t db_z_info2;
1544 uint32_t db_stencil_info2;
1545 float offset_scale;
1546 };
1547
1548 struct radv_attachment_info {
1549 union {
1550 struct radv_color_buffer_info cb;
1551 struct radv_ds_buffer_info ds;
1552 };
1553 struct radv_image_view *attachment;
1554 };
1555
1556 struct radv_framebuffer {
1557 uint32_t width;
1558 uint32_t height;
1559 uint32_t layers;
1560
1561 uint32_t attachment_count;
1562 struct radv_attachment_info attachments[0];
1563 };
1564
1565 struct radv_subpass_barrier {
1566 VkPipelineStageFlags src_stage_mask;
1567 VkAccessFlags src_access_mask;
1568 VkAccessFlags dst_access_mask;
1569 };
1570
1571 struct radv_subpass {
1572 uint32_t input_count;
1573 uint32_t color_count;
1574 VkAttachmentReference * input_attachments;
1575 VkAttachmentReference * color_attachments;
1576 VkAttachmentReference * resolve_attachments;
1577 VkAttachmentReference depth_stencil_attachment;
1578
1579 /** Subpass has at least one resolve attachment */
1580 bool has_resolve;
1581
1582 struct radv_subpass_barrier start_barrier;
1583
1584 uint32_t view_mask;
1585 };
1586
1587 struct radv_render_pass_attachment {
1588 VkFormat format;
1589 uint32_t samples;
1590 VkAttachmentLoadOp load_op;
1591 VkAttachmentLoadOp stencil_load_op;
1592 VkImageLayout initial_layout;
1593 VkImageLayout final_layout;
1594 uint32_t view_mask;
1595 };
1596
1597 struct radv_render_pass {
1598 uint32_t attachment_count;
1599 uint32_t subpass_count;
1600 VkAttachmentReference * subpass_attachments;
1601 struct radv_render_pass_attachment * attachments;
1602 struct radv_subpass_barrier end_barrier;
1603 struct radv_subpass subpasses[0];
1604 };
1605
1606 VkResult radv_device_init_meta(struct radv_device *device);
1607 void radv_device_finish_meta(struct radv_device *device);
1608
1609 struct radv_query_pool {
1610 struct radeon_winsys_bo *bo;
1611 uint32_t stride;
1612 uint32_t availability_offset;
1613 char *ptr;
1614 VkQueryType type;
1615 uint32_t pipeline_stats_mask;
1616 };
1617
1618 struct radv_semaphore {
1619 /* use a winsys sem for non-exportable */
1620 struct radeon_winsys_sem *sem;
1621 uint32_t syncobj;
1622 uint32_t temp_syncobj;
1623 };
1624
1625 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1626 int num_wait_sems,
1627 const VkSemaphore *wait_sems,
1628 int num_signal_sems,
1629 const VkSemaphore *signal_sems,
1630 VkFence fence);
1631 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1632
1633 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1634 struct radv_descriptor_set *set,
1635 unsigned idx);
1636
1637 void
1638 radv_update_descriptor_sets(struct radv_device *device,
1639 struct radv_cmd_buffer *cmd_buffer,
1640 VkDescriptorSet overrideSet,
1641 uint32_t descriptorWriteCount,
1642 const VkWriteDescriptorSet *pDescriptorWrites,
1643 uint32_t descriptorCopyCount,
1644 const VkCopyDescriptorSet *pDescriptorCopies);
1645
1646 void
1647 radv_update_descriptor_set_with_template(struct radv_device *device,
1648 struct radv_cmd_buffer *cmd_buffer,
1649 struct radv_descriptor_set *set,
1650 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1651 const void *pData);
1652
1653 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1654 VkPipelineBindPoint pipelineBindPoint,
1655 VkPipelineLayout _layout,
1656 uint32_t set,
1657 uint32_t descriptorWriteCount,
1658 const VkWriteDescriptorSet *pDescriptorWrites);
1659
1660 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1661 struct radv_image *image, uint32_t value);
1662 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1663 struct radv_image *image, uint32_t value);
1664
1665 struct radv_fence {
1666 struct radeon_winsys_fence *fence;
1667 bool submitted;
1668 bool signalled;
1669
1670 uint32_t syncobj;
1671 uint32_t temp_syncobj;
1672 };
1673
1674 struct radeon_winsys_sem;
1675
1676 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1677 \
1678 static inline struct __radv_type * \
1679 __radv_type ## _from_handle(__VkType _handle) \
1680 { \
1681 return (struct __radv_type *) _handle; \
1682 } \
1683 \
1684 static inline __VkType \
1685 __radv_type ## _to_handle(struct __radv_type *_obj) \
1686 { \
1687 return (__VkType) _obj; \
1688 }
1689
1690 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1691 \
1692 static inline struct __radv_type * \
1693 __radv_type ## _from_handle(__VkType _handle) \
1694 { \
1695 return (struct __radv_type *)(uintptr_t) _handle; \
1696 } \
1697 \
1698 static inline __VkType \
1699 __radv_type ## _to_handle(struct __radv_type *_obj) \
1700 { \
1701 return (__VkType)(uintptr_t) _obj; \
1702 }
1703
1704 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1705 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1706
1707 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1708 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1709 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1710 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1711 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1712
1713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1715 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1716 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1719 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1720 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1721 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1722 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1723 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1724 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1725 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1726 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1727 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1728 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1729 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1730 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1731 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1732 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1733 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1734
1735 #endif /* RADV_PRIVATE_H */