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radv: add support for NV_dedicated_allocation
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_SAMPLES_LOG2 4
83 #define NUM_META_FS_KEYS 11
84 #define RADV_MAX_DRM_DEVICES 8
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 enum radv_mem_heap {
89 RADV_MEM_HEAP_VRAM,
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
91 RADV_MEM_HEAP_GTT,
92 RADV_MEM_HEAP_COUNT
93 };
94
95 enum radv_mem_type {
96 RADV_MEM_TYPE_VRAM,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
99 RADV_MEM_TYPE_GTT_CACHED,
100 RADV_MEM_TYPE_COUNT
101 };
102
103
104 enum {
105 RADV_DEBUG_NO_FAST_CLEARS = 0x1,
106 RADV_DEBUG_NO_DCC = 0x2,
107 RADV_DEBUG_DUMP_SHADERS = 0x4,
108 RADV_DEBUG_NO_CACHE = 0x8,
109 RADV_DEBUG_DUMP_SHADER_STATS = 0x10,
110 RADV_DEBUG_NO_HIZ = 0x20,
111 RADV_DEBUG_NO_COMPUTE_QUEUE = 0x40,
112 RADV_DEBUG_UNSAFE_MATH = 0x80,
113 };
114
115 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
116
117 static inline uint32_t
118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint32_t
125 align_u32_npot(uint32_t v, uint32_t a)
126 {
127 return (v + a - 1) / a * a;
128 }
129
130 static inline uint64_t
131 align_u64(uint64_t v, uint64_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline int32_t
138 align_i32(int32_t v, int32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 /** Alignment must be a power of 2. */
145 static inline bool
146 radv_is_aligned(uintmax_t n, uintmax_t a)
147 {
148 assert(a == (a & -a));
149 return (n & (a - 1)) == 0;
150 }
151
152 static inline uint32_t
153 round_up_u32(uint32_t v, uint32_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint64_t
159 round_up_u64(uint64_t v, uint64_t a)
160 {
161 return (v + a - 1) / a;
162 }
163
164 static inline uint32_t
165 radv_minify(uint32_t n, uint32_t levels)
166 {
167 if (unlikely(n == 0))
168 return 0;
169 else
170 return MAX2(n >> levels, 1);
171 }
172 static inline float
173 radv_clamp_f(float f, float min, float max)
174 {
175 assert(min < max);
176
177 if (f > max)
178 return max;
179 else if (f < min)
180 return min;
181 else
182 return f;
183 }
184
185 static inline bool
186 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
187 {
188 if (*inout_mask & clear_mask) {
189 *inout_mask &= ~clear_mask;
190 return true;
191 } else {
192 return false;
193 }
194 }
195
196 #define for_each_bit(b, dword) \
197 for (uint32_t __dword = (dword); \
198 (b) = __builtin_ffs(__dword) - 1, __dword; \
199 __dword &= ~(1 << (b)))
200
201 #define typed_memcpy(dest, src, count) ({ \
202 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
203 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 })
205
206 #define zero(x) (memset(&(x), 0, sizeof(x)))
207
208 /* Whenever we generate an error, pass it through this function. Useful for
209 * debugging, where we can break on it. Only call at error site, not when
210 * propagating errors. Might be useful to plug in a stack trace here.
211 */
212
213 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
214
215 #ifdef DEBUG
216 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
217 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
218 #else
219 #define vk_error(error) error
220 #define vk_errorf(error, format, ...) error
221 #endif
222
223 void __radv_finishme(const char *file, int line, const char *format, ...)
224 radv_printflike(3, 4);
225 void radv_loge(const char *format, ...) radv_printflike(1, 2);
226 void radv_loge_v(const char *format, va_list va);
227
228 /**
229 * Print a FINISHME message, including its source location.
230 */
231 #define radv_finishme(format, ...) \
232 do { \
233 static bool reported = false; \
234 if (!reported) { \
235 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 reported = true; \
237 } \
238 } while (0)
239
240 /* A non-fatal assert. Useful for debugging. */
241 #ifdef DEBUG
242 #define radv_assert(x) ({ \
243 if (unlikely(!(x))) \
244 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
245 })
246 #else
247 #define radv_assert(x)
248 #endif
249
250 #define stub_return(v) \
251 do { \
252 radv_finishme("stub %s", __func__); \
253 return (v); \
254 } while (0)
255
256 #define stub() \
257 do { \
258 radv_finishme("stub %s", __func__); \
259 return; \
260 } while (0)
261
262 void *radv_lookup_entrypoint(const char *name);
263
264 struct radv_extensions {
265 VkExtensionProperties *ext_array;
266 uint32_t num_ext;
267 };
268
269 struct radv_physical_device {
270 VK_LOADER_DATA _loader_data;
271
272 struct radv_instance * instance;
273
274 struct radeon_winsys *ws;
275 struct radeon_info rad_info;
276 char path[20];
277 const char * name;
278 uint8_t uuid[VK_UUID_SIZE];
279
280 int local_fd;
281 struct wsi_device wsi_device;
282 struct radv_extensions extensions;
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 };
296
297 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
298 void radv_finish_wsi(struct radv_physical_device *physical_device);
299
300 struct cache_entry;
301
302 struct radv_pipeline_cache {
303 struct radv_device * device;
304 pthread_mutex_t mutex;
305
306 uint32_t total_size;
307 uint32_t table_size;
308 uint32_t kernel_count;
309 struct cache_entry ** hash_table;
310 bool modified;
311
312 VkAllocationCallbacks alloc;
313 };
314
315 void
316 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
317 struct radv_device *device);
318 void
319 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
320 void
321 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
322 const void *data, size_t size);
323
324 struct radv_shader_variant *
325 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
326 struct radv_pipeline_cache *cache,
327 const unsigned char *sha1);
328
329 struct radv_shader_variant *
330 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
331 const unsigned char *sha1,
332 struct radv_shader_variant *variant,
333 const void *code, unsigned code_size);
334
335 void radv_shader_variant_destroy(struct radv_device *device,
336 struct radv_shader_variant *variant);
337
338 struct radv_meta_state {
339 VkAllocationCallbacks alloc;
340
341 struct radv_pipeline_cache cache;
342
343 /**
344 * Use array element `i` for images with `2^i` samples.
345 */
346 struct {
347 VkRenderPass render_pass[NUM_META_FS_KEYS];
348 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
349
350 VkRenderPass depthstencil_rp;
351 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
352 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
353 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
354 } clear[1 + MAX_SAMPLES_LOG2];
355
356 struct {
357 VkRenderPass render_pass[NUM_META_FS_KEYS];
358
359 /** Pipeline that blits from a 1D image. */
360 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
361
362 /** Pipeline that blits from a 2D image. */
363 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
364
365 /** Pipeline that blits from a 3D image. */
366 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
367
368 VkRenderPass depth_only_rp;
369 VkPipeline depth_only_1d_pipeline;
370 VkPipeline depth_only_2d_pipeline;
371 VkPipeline depth_only_3d_pipeline;
372
373 VkRenderPass stencil_only_rp;
374 VkPipeline stencil_only_1d_pipeline;
375 VkPipeline stencil_only_2d_pipeline;
376 VkPipeline stencil_only_3d_pipeline;
377 VkPipelineLayout pipeline_layout;
378 VkDescriptorSetLayout ds_layout;
379 } blit;
380
381 struct {
382 VkRenderPass render_passes[NUM_META_FS_KEYS];
383
384 VkPipelineLayout p_layouts[2];
385 VkDescriptorSetLayout ds_layouts[2];
386 VkPipeline pipelines[2][NUM_META_FS_KEYS];
387
388 VkRenderPass depth_only_rp;
389 VkPipeline depth_only_pipeline[2];
390
391 VkRenderPass stencil_only_rp;
392 VkPipeline stencil_only_pipeline[2];
393 } blit2d;
394
395 struct {
396 VkPipelineLayout img_p_layout;
397 VkDescriptorSetLayout img_ds_layout;
398 VkPipeline pipeline;
399 } itob;
400 struct {
401 VkRenderPass render_pass;
402 VkPipelineLayout img_p_layout;
403 VkDescriptorSetLayout img_ds_layout;
404 VkPipeline pipeline;
405 } btoi;
406 struct {
407 VkPipelineLayout img_p_layout;
408 VkDescriptorSetLayout img_ds_layout;
409 VkPipeline pipeline;
410 } itoi;
411 struct {
412 VkPipelineLayout img_p_layout;
413 VkDescriptorSetLayout img_ds_layout;
414 VkPipeline pipeline;
415 } cleari;
416
417 struct {
418 VkPipeline pipeline;
419 VkRenderPass pass;
420 } resolve;
421
422 struct {
423 VkDescriptorSetLayout ds_layout;
424 VkPipelineLayout p_layout;
425 struct {
426 VkPipeline pipeline;
427 VkPipeline i_pipeline;
428 } rc[MAX_SAMPLES_LOG2];
429 } resolve_compute;
430
431 struct {
432 VkPipeline decompress_pipeline;
433 VkPipeline resummarize_pipeline;
434 VkRenderPass pass;
435 } depth_decomp;
436
437 struct {
438 VkPipeline cmask_eliminate_pipeline;
439 VkPipeline fmask_decompress_pipeline;
440 VkRenderPass pass;
441 } fast_clear_flush;
442
443 struct {
444 VkPipelineLayout fill_p_layout;
445 VkPipelineLayout copy_p_layout;
446 VkDescriptorSetLayout fill_ds_layout;
447 VkDescriptorSetLayout copy_ds_layout;
448 VkPipeline fill_pipeline;
449 VkPipeline copy_pipeline;
450 } buffer;
451 };
452
453 /* queue types */
454 #define RADV_QUEUE_GENERAL 0
455 #define RADV_QUEUE_COMPUTE 1
456 #define RADV_QUEUE_TRANSFER 2
457
458 #define RADV_MAX_QUEUE_FAMILIES 3
459
460 enum ring_type radv_queue_family_to_ring(int f);
461
462 struct radv_queue {
463 VK_LOADER_DATA _loader_data;
464 struct radv_device * device;
465 struct radeon_winsys_ctx *hw_ctx;
466 int queue_family_index;
467 int queue_idx;
468
469 uint32_t scratch_size;
470 uint32_t compute_scratch_size;
471 uint32_t esgs_ring_size;
472 uint32_t gsvs_ring_size;
473
474 struct radeon_winsys_bo *scratch_bo;
475 struct radeon_winsys_bo *descriptor_bo;
476 struct radeon_winsys_bo *compute_scratch_bo;
477 struct radeon_winsys_bo *esgs_ring_bo;
478 struct radeon_winsys_bo *gsvs_ring_bo;
479 struct radeon_winsys_cs *initial_preamble_cs;
480 struct radeon_winsys_cs *continue_preamble_cs;
481 };
482
483 struct radv_device {
484 VK_LOADER_DATA _loader_data;
485
486 VkAllocationCallbacks alloc;
487
488 struct radv_instance * instance;
489 struct radeon_winsys *ws;
490
491 struct radv_meta_state meta_state;
492
493 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
494 int queue_count[RADV_MAX_QUEUE_FAMILIES];
495 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
496 struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
497
498 uint64_t debug_flags;
499
500 bool llvm_supports_spill;
501 uint32_t scratch_waves;
502
503 uint32_t gs_table_depth;
504
505 /* MSAA sample locations.
506 * The first index is the sample index.
507 * The second index is the coordinate: X, Y. */
508 float sample_locations_1x[1][2];
509 float sample_locations_2x[2][2];
510 float sample_locations_4x[4][2];
511 float sample_locations_8x[8][2];
512 float sample_locations_16x[16][2];
513
514 /* CIK and later */
515 uint32_t gfx_init_size_dw;
516 struct radeon_winsys_bo *gfx_init;
517
518 struct radeon_winsys_bo *trace_bo;
519 uint32_t *trace_id_ptr;
520
521 struct radv_physical_device *physical_device;
522 };
523
524 struct radv_device_memory {
525 struct radeon_winsys_bo *bo;
526 /* for dedicated allocations */
527 struct radv_image *image;
528 struct radv_buffer *buffer;
529 uint32_t type_index;
530 VkDeviceSize map_size;
531 void * map;
532 };
533
534
535 struct radv_descriptor_range {
536 uint64_t va;
537 uint32_t size;
538 };
539
540 struct radv_descriptor_set {
541 const struct radv_descriptor_set_layout *layout;
542 uint32_t size;
543
544 struct radv_buffer_view *buffer_views;
545 struct radeon_winsys_bo *bo;
546 uint64_t va;
547 uint32_t *mapped_ptr;
548 struct radv_descriptor_range *dynamic_descriptors;
549
550 struct list_head vram_list;
551
552 struct radeon_winsys_bo *descriptors[0];
553 };
554
555 struct radv_descriptor_pool {
556 struct radeon_winsys_bo *bo;
557 uint8_t *mapped_ptr;
558 uint64_t current_offset;
559 uint64_t size;
560
561 struct list_head vram_list;
562 };
563
564 struct radv_buffer {
565 struct radv_device * device;
566 VkDeviceSize size;
567
568 VkBufferUsageFlags usage;
569
570 /* Set when bound */
571 struct radeon_winsys_bo * bo;
572 VkDeviceSize offset;
573 };
574
575
576 enum radv_cmd_dirty_bits {
577 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
578 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
579 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
580 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
581 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
582 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
583 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
584 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
585 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
586 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
587 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
588 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
589 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
590 };
591 typedef uint32_t radv_cmd_dirty_mask_t;
592
593 enum radv_cmd_flush_bits {
594 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
595 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
596 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
597 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
598 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
599 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
600 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
601 /* Framebuffer caches */
602 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
603 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
604 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
605 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
606 /* Engine synchronization. */
607 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
608 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
609 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
610 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
611
612 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
613 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
614 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
615 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
616 };
617
618 struct radv_vertex_binding {
619 struct radv_buffer * buffer;
620 VkDeviceSize offset;
621 };
622
623 struct radv_dynamic_state {
624 struct {
625 uint32_t count;
626 VkViewport viewports[MAX_VIEWPORTS];
627 } viewport;
628
629 struct {
630 uint32_t count;
631 VkRect2D scissors[MAX_SCISSORS];
632 } scissor;
633
634 float line_width;
635
636 struct {
637 float bias;
638 float clamp;
639 float slope;
640 } depth_bias;
641
642 float blend_constants[4];
643
644 struct {
645 float min;
646 float max;
647 } depth_bounds;
648
649 struct {
650 uint32_t front;
651 uint32_t back;
652 } stencil_compare_mask;
653
654 struct {
655 uint32_t front;
656 uint32_t back;
657 } stencil_write_mask;
658
659 struct {
660 uint32_t front;
661 uint32_t back;
662 } stencil_reference;
663 };
664
665 extern const struct radv_dynamic_state default_dynamic_state;
666
667 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
668 const struct radv_dynamic_state *src,
669 uint32_t copy_mask);
670 /**
671 * Attachment state when recording a renderpass instance.
672 *
673 * The clear value is valid only if there exists a pending clear.
674 */
675 struct radv_attachment_state {
676 VkImageAspectFlags pending_clear_aspects;
677 VkClearValue clear_value;
678 VkImageLayout current_layout;
679 };
680
681 struct radv_cmd_state {
682 uint32_t vb_dirty;
683 radv_cmd_dirty_mask_t dirty;
684 bool vertex_descriptors_dirty;
685
686 struct radv_pipeline * pipeline;
687 struct radv_pipeline * emitted_pipeline;
688 struct radv_pipeline * compute_pipeline;
689 struct radv_pipeline * emitted_compute_pipeline;
690 struct radv_framebuffer * framebuffer;
691 struct radv_render_pass * pass;
692 const struct radv_subpass * subpass;
693 struct radv_dynamic_state dynamic;
694 struct radv_vertex_binding vertex_bindings[MAX_VBS];
695 struct radv_descriptor_set * descriptors[MAX_SETS];
696 struct radv_attachment_state * attachments;
697 VkRect2D render_area;
698 struct radv_buffer * index_buffer;
699 uint32_t index_type;
700 uint32_t index_offset;
701 uint32_t last_primitive_reset_index;
702 enum radv_cmd_flush_bits flush_bits;
703 unsigned active_occlusion_queries;
704 float offset_scale;
705 uint32_t descriptors_dirty;
706 uint32_t trace_id;
707 uint32_t last_ia_multi_vgt_param;
708 };
709
710 struct radv_cmd_pool {
711 VkAllocationCallbacks alloc;
712 struct list_head cmd_buffers;
713 uint32_t queue_family_index;
714 };
715
716 struct radv_cmd_buffer_upload {
717 uint8_t *map;
718 unsigned offset;
719 uint64_t size;
720 struct radeon_winsys_bo *upload_bo;
721 struct list_head list;
722 };
723
724 struct radv_cmd_buffer {
725 VK_LOADER_DATA _loader_data;
726
727 struct radv_device * device;
728
729 struct radv_cmd_pool * pool;
730 struct list_head pool_link;
731
732 VkCommandBufferUsageFlags usage_flags;
733 VkCommandBufferLevel level;
734 struct radeon_winsys_cs *cs;
735 struct radv_cmd_state state;
736 uint32_t queue_family_index;
737
738 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
739 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
740 VkShaderStageFlags push_constant_stages;
741
742 struct radv_cmd_buffer_upload upload;
743
744 bool record_fail;
745
746 uint32_t scratch_size_needed;
747 uint32_t compute_scratch_size_needed;
748 uint32_t esgs_ring_size_needed;
749 uint32_t gsvs_ring_size_needed;
750
751 int ring_offsets_idx; /* just used for verification */
752 };
753
754 struct radv_image;
755
756 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
757
758 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
759 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
760
761 void cik_create_gfx_config(struct radv_device *device);
762
763 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
764 int count, const VkViewport *viewports);
765 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
766 int count, const VkRect2D *scissors);
767 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
768 bool instanced_or_indirect_draw, uint32_t draw_vertex_count);
769 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
770 enum chip_class chip_class,
771 bool is_mec,
772 enum radv_cmd_flush_bits flush_bits);
773 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
774 enum chip_class chip_class,
775 bool is_mec,
776 enum radv_cmd_flush_bits flush_bits);
777 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
778 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
779 uint64_t src_va, uint64_t dest_va,
780 uint64_t size);
781 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
782 uint64_t size, unsigned value);
783 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
784 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
785 struct radv_descriptor_set *set,
786 unsigned idx);
787 bool
788 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
789 unsigned size,
790 unsigned alignment,
791 unsigned *out_offset,
792 void **ptr);
793 void
794 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
795 const struct radv_subpass *subpass,
796 bool transitions);
797 bool
798 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
799 unsigned size, unsigned alignmnet,
800 const void *data, unsigned *out_offset);
801 void
802 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
803 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
804 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
805 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
806 unsigned radv_cayman_get_maxdist(int log_samples);
807 void radv_device_init_msaa(struct radv_device *device);
808 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
809 struct radv_image *image,
810 VkClearDepthStencilValue ds_clear_value,
811 VkImageAspectFlags aspects);
812 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
813 struct radv_image *image,
814 int idx,
815 uint32_t color_values[2]);
816 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
817 struct radeon_winsys_bo *bo,
818 uint64_t offset, uint64_t size, uint32_t value);
819 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
820 bool radv_get_memory_fd(struct radv_device *device,
821 struct radv_device_memory *memory,
822 int *pFD);
823 /*
824 * Takes x,y,z as exact numbers of invocations, instead of blocks.
825 *
826 * Limitations: Can't call normal dispatch functions without binding or rebinding
827 * the compute pipeline.
828 */
829 void radv_unaligned_dispatch(
830 struct radv_cmd_buffer *cmd_buffer,
831 uint32_t x,
832 uint32_t y,
833 uint32_t z);
834
835 struct radv_event {
836 struct radeon_winsys_bo *bo;
837 uint64_t *map;
838 };
839
840 struct nir_shader;
841
842 struct radv_shader_module {
843 struct nir_shader * nir;
844 unsigned char sha1[20];
845 uint32_t size;
846 char data[0];
847 };
848
849 union ac_shader_variant_key;
850
851 void
852 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
853 const char *entrypoint,
854 const VkSpecializationInfo *spec_info,
855 const struct radv_pipeline_layout *layout,
856 const union ac_shader_variant_key *key,
857 uint32_t is_geom_copy_shader);
858
859 static inline gl_shader_stage
860 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
861 {
862 assert(__builtin_popcount(vk_stage) == 1);
863 return ffs(vk_stage) - 1;
864 }
865
866 static inline VkShaderStageFlagBits
867 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
868 {
869 return (1 << mesa_stage);
870 }
871
872 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
873
874 #define radv_foreach_stage(stage, stage_bits) \
875 for (gl_shader_stage stage, \
876 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
877 stage = __builtin_ffs(__tmp) - 1, __tmp; \
878 __tmp &= ~(1 << (stage)))
879
880 struct radv_shader_variant {
881 uint32_t ref_count;
882
883 struct radeon_winsys_bo *bo;
884 struct ac_shader_config config;
885 struct ac_shader_variant_info info;
886 unsigned rsrc1;
887 unsigned rsrc2;
888 uint32_t code_size;
889 };
890
891 struct radv_depth_stencil_state {
892 uint32_t db_depth_control;
893 uint32_t db_stencil_control;
894 uint32_t db_render_control;
895 uint32_t db_render_override2;
896 };
897
898 struct radv_blend_state {
899 uint32_t cb_color_control;
900 uint32_t cb_target_mask;
901 uint32_t sx_mrt0_blend_opt[8];
902 uint32_t cb_blend_control[8];
903
904 uint32_t spi_shader_col_format;
905 uint32_t cb_shader_mask;
906 uint32_t db_alpha_to_mask;
907 };
908
909 unsigned radv_format_meta_fs_key(VkFormat format);
910
911 struct radv_raster_state {
912 uint32_t pa_cl_clip_cntl;
913 uint32_t pa_cl_vs_out_cntl;
914 uint32_t spi_interp_control;
915 uint32_t pa_su_point_size;
916 uint32_t pa_su_point_minmax;
917 uint32_t pa_su_line_cntl;
918 uint32_t pa_su_vtx_cntl;
919 uint32_t pa_su_sc_mode_cntl;
920 };
921
922 struct radv_multisample_state {
923 uint32_t db_eqaa;
924 uint32_t pa_sc_line_cntl;
925 uint32_t pa_sc_mode_cntl_0;
926 uint32_t pa_sc_mode_cntl_1;
927 uint32_t pa_sc_aa_config;
928 uint32_t pa_sc_aa_mask[2];
929 unsigned num_samples;
930 };
931
932 struct radv_prim_vertex_count {
933 uint8_t min;
934 uint8_t incr;
935 };
936
937 struct radv_pipeline {
938 struct radv_device * device;
939 uint32_t dynamic_state_mask;
940 struct radv_dynamic_state dynamic_state;
941
942 struct radv_pipeline_layout * layout;
943
944 bool needs_data_cache;
945
946 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
947 struct radv_shader_variant *gs_copy_shader;
948 VkShaderStageFlags active_stages;
949
950 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
951 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
952 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
953 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
954 uint32_t num_vertex_attribs;
955 uint32_t binding_stride[MAX_VBS];
956
957 union {
958 struct {
959 struct radv_blend_state blend;
960 struct radv_depth_stencil_state ds;
961 struct radv_raster_state raster;
962 struct radv_multisample_state ms;
963 unsigned prim;
964 unsigned gs_out;
965 bool prim_restart_enable;
966 unsigned esgs_ring_size;
967 unsigned gsvs_ring_size;
968 struct radv_prim_vertex_count prim_vertex_count;
969 } graphics;
970 };
971
972 unsigned max_waves;
973 unsigned scratch_bytes_per_wave;
974 };
975
976 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
977 {
978 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
979 }
980
981 struct radv_graphics_pipeline_create_info {
982 bool use_rectlist;
983 bool db_depth_clear;
984 bool db_stencil_clear;
985 bool db_depth_disable_expclear;
986 bool db_stencil_disable_expclear;
987 bool db_flush_depth_inplace;
988 bool db_flush_stencil_inplace;
989 bool db_resummarize;
990 uint32_t custom_blend_mode;
991 };
992
993 VkResult
994 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
995 struct radv_pipeline_cache *cache,
996 const VkGraphicsPipelineCreateInfo *pCreateInfo,
997 const struct radv_graphics_pipeline_create_info *extra,
998 const VkAllocationCallbacks *alloc);
999
1000 VkResult
1001 radv_graphics_pipeline_create(VkDevice device,
1002 VkPipelineCache cache,
1003 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1004 const struct radv_graphics_pipeline_create_info *extra,
1005 const VkAllocationCallbacks *alloc,
1006 VkPipeline *pPipeline);
1007
1008 struct vk_format_description;
1009 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1010 int first_non_void);
1011 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1012 int first_non_void);
1013 uint32_t radv_translate_colorformat(VkFormat format);
1014 uint32_t radv_translate_color_numformat(VkFormat format,
1015 const struct vk_format_description *desc,
1016 int first_non_void);
1017 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1018 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1019 uint32_t radv_translate_dbformat(VkFormat format);
1020 uint32_t radv_translate_tex_dataformat(VkFormat format,
1021 const struct vk_format_description *desc,
1022 int first_non_void);
1023 uint32_t radv_translate_tex_numformat(VkFormat format,
1024 const struct vk_format_description *desc,
1025 int first_non_void);
1026 bool radv_format_pack_clear_color(VkFormat format,
1027 uint32_t clear_vals[2],
1028 VkClearColorValue *value);
1029 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1030
1031 struct radv_fmask_info {
1032 uint64_t offset;
1033 uint64_t size;
1034 unsigned alignment;
1035 unsigned pitch_in_pixels;
1036 unsigned bank_height;
1037 unsigned slice_tile_max;
1038 unsigned tile_mode_index;
1039 };
1040
1041 struct radv_cmask_info {
1042 uint64_t offset;
1043 uint64_t size;
1044 unsigned alignment;
1045 unsigned slice_tile_max;
1046 unsigned base_address_reg;
1047 };
1048
1049 struct r600_htile_info {
1050 uint64_t offset;
1051 uint64_t size;
1052 unsigned pitch;
1053 unsigned height;
1054 unsigned xalign;
1055 unsigned yalign;
1056 };
1057
1058 struct radv_image {
1059 VkImageType type;
1060 /* The original VkFormat provided by the client. This may not match any
1061 * of the actual surface formats.
1062 */
1063 VkFormat vk_format;
1064 VkImageAspectFlags aspects;
1065 VkExtent3D extent;
1066 uint32_t levels;
1067 uint32_t array_size;
1068 uint32_t samples; /**< VkImageCreateInfo::samples */
1069 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1070 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1071
1072 VkDeviceSize size;
1073 uint32_t alignment;
1074
1075 bool exclusive;
1076 unsigned queue_family_mask;
1077
1078 /* Set when bound */
1079 struct radeon_winsys_bo *bo;
1080 VkDeviceSize offset;
1081 uint32_t dcc_offset;
1082 struct radeon_surf surface;
1083
1084 struct radv_fmask_info fmask;
1085 struct radv_cmask_info cmask;
1086 uint32_t clear_value_offset;
1087
1088 /* Depth buffer compression and fast clear. */
1089 struct r600_htile_info htile;
1090 };
1091
1092 bool radv_layout_has_htile(const struct radv_image *image,
1093 VkImageLayout layout);
1094 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1095 VkImageLayout layout);
1096 bool radv_layout_can_expclear(const struct radv_image *image,
1097 VkImageLayout layout);
1098 bool radv_layout_can_fast_clear(const struct radv_image *image,
1099 VkImageLayout layout,
1100 unsigned queue_mask);
1101
1102
1103 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1104
1105 static inline uint32_t
1106 radv_get_layerCount(const struct radv_image *image,
1107 const VkImageSubresourceRange *range)
1108 {
1109 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1110 image->array_size - range->baseArrayLayer : range->layerCount;
1111 }
1112
1113 static inline uint32_t
1114 radv_get_levelCount(const struct radv_image *image,
1115 const VkImageSubresourceRange *range)
1116 {
1117 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1118 image->levels - range->baseMipLevel : range->levelCount;
1119 }
1120
1121 struct radeon_bo_metadata;
1122 void
1123 radv_init_metadata(struct radv_device *device,
1124 struct radv_image *image,
1125 struct radeon_bo_metadata *metadata);
1126
1127 struct radv_image_view {
1128 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1129 struct radeon_winsys_bo *bo;
1130
1131 VkImageViewType type;
1132 VkImageAspectFlags aspect_mask;
1133 VkFormat vk_format;
1134 uint32_t base_layer;
1135 uint32_t layer_count;
1136 uint32_t base_mip;
1137 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1138
1139 uint32_t descriptor[8];
1140 uint32_t fmask_descriptor[8];
1141 };
1142
1143 struct radv_image_create_info {
1144 const VkImageCreateInfo *vk_info;
1145 uint32_t stride;
1146 bool scanout;
1147 };
1148
1149 VkResult radv_image_create(VkDevice _device,
1150 const struct radv_image_create_info *info,
1151 const VkAllocationCallbacks* alloc,
1152 VkImage *pImage);
1153
1154 void radv_image_view_init(struct radv_image_view *view,
1155 struct radv_device *device,
1156 const VkImageViewCreateInfo* pCreateInfo,
1157 struct radv_cmd_buffer *cmd_buffer,
1158 VkImageUsageFlags usage_mask);
1159 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1160 struct radv_image *image, uint32_t micro_tile_mode);
1161 struct radv_buffer_view {
1162 struct radeon_winsys_bo *bo;
1163 VkFormat vk_format;
1164 uint64_t range; /**< VkBufferViewCreateInfo::range */
1165 uint32_t state[4];
1166 };
1167 void radv_buffer_view_init(struct radv_buffer_view *view,
1168 struct radv_device *device,
1169 const VkBufferViewCreateInfo* pCreateInfo,
1170 struct radv_cmd_buffer *cmd_buffer);
1171
1172 static inline struct VkExtent3D
1173 radv_sanitize_image_extent(const VkImageType imageType,
1174 const struct VkExtent3D imageExtent)
1175 {
1176 switch (imageType) {
1177 case VK_IMAGE_TYPE_1D:
1178 return (VkExtent3D) { imageExtent.width, 1, 1 };
1179 case VK_IMAGE_TYPE_2D:
1180 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1181 case VK_IMAGE_TYPE_3D:
1182 return imageExtent;
1183 default:
1184 unreachable("invalid image type");
1185 }
1186 }
1187
1188 static inline struct VkOffset3D
1189 radv_sanitize_image_offset(const VkImageType imageType,
1190 const struct VkOffset3D imageOffset)
1191 {
1192 switch (imageType) {
1193 case VK_IMAGE_TYPE_1D:
1194 return (VkOffset3D) { imageOffset.x, 0, 0 };
1195 case VK_IMAGE_TYPE_2D:
1196 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1197 case VK_IMAGE_TYPE_3D:
1198 return imageOffset;
1199 default:
1200 unreachable("invalid image type");
1201 }
1202 }
1203
1204 struct radv_sampler {
1205 uint32_t state[4];
1206 };
1207
1208 struct radv_color_buffer_info {
1209 uint32_t cb_color_base;
1210 uint32_t cb_color_pitch;
1211 uint32_t cb_color_slice;
1212 uint32_t cb_color_view;
1213 uint32_t cb_color_info;
1214 uint32_t cb_color_attrib;
1215 uint32_t cb_dcc_control;
1216 uint32_t cb_color_cmask;
1217 uint32_t cb_color_cmask_slice;
1218 uint32_t cb_color_fmask;
1219 uint32_t cb_color_fmask_slice;
1220 uint32_t cb_clear_value0;
1221 uint32_t cb_clear_value1;
1222 uint32_t cb_dcc_base;
1223 uint32_t micro_tile_mode;
1224 };
1225
1226 struct radv_ds_buffer_info {
1227 uint32_t db_depth_info;
1228 uint32_t db_z_info;
1229 uint32_t db_stencil_info;
1230 uint32_t db_z_read_base;
1231 uint32_t db_stencil_read_base;
1232 uint32_t db_z_write_base;
1233 uint32_t db_stencil_write_base;
1234 uint32_t db_depth_view;
1235 uint32_t db_depth_size;
1236 uint32_t db_depth_slice;
1237 uint32_t db_htile_surface;
1238 uint32_t db_htile_data_base;
1239 uint32_t pa_su_poly_offset_db_fmt_cntl;
1240 float offset_scale;
1241 };
1242
1243 struct radv_attachment_info {
1244 union {
1245 struct radv_color_buffer_info cb;
1246 struct radv_ds_buffer_info ds;
1247 };
1248 struct radv_image_view *attachment;
1249 };
1250
1251 struct radv_framebuffer {
1252 uint32_t width;
1253 uint32_t height;
1254 uint32_t layers;
1255
1256 uint32_t attachment_count;
1257 struct radv_attachment_info attachments[0];
1258 };
1259
1260 struct radv_subpass_barrier {
1261 VkPipelineStageFlags src_stage_mask;
1262 VkAccessFlags src_access_mask;
1263 VkAccessFlags dst_access_mask;
1264 };
1265
1266 struct radv_subpass {
1267 uint32_t input_count;
1268 VkAttachmentReference * input_attachments;
1269 uint32_t color_count;
1270 VkAttachmentReference * color_attachments;
1271 VkAttachmentReference * resolve_attachments;
1272 VkAttachmentReference depth_stencil_attachment;
1273
1274 /** Subpass has at least one resolve attachment */
1275 bool has_resolve;
1276
1277 struct radv_subpass_barrier start_barrier;
1278 };
1279
1280 struct radv_render_pass_attachment {
1281 VkFormat format;
1282 uint32_t samples;
1283 VkAttachmentLoadOp load_op;
1284 VkAttachmentLoadOp stencil_load_op;
1285 VkImageLayout initial_layout;
1286 VkImageLayout final_layout;
1287 };
1288
1289 struct radv_render_pass {
1290 uint32_t attachment_count;
1291 uint32_t subpass_count;
1292 VkAttachmentReference * subpass_attachments;
1293 struct radv_render_pass_attachment * attachments;
1294 struct radv_subpass_barrier end_barrier;
1295 struct radv_subpass subpasses[0];
1296 };
1297
1298 VkResult radv_device_init_meta(struct radv_device *device);
1299 void radv_device_finish_meta(struct radv_device *device);
1300
1301 struct radv_query_pool {
1302 struct radeon_winsys_bo *bo;
1303 uint32_t stride;
1304 uint32_t availability_offset;
1305 char *ptr;
1306 VkQueryType type;
1307 };
1308
1309 VkResult
1310 radv_temp_descriptor_set_create(struct radv_device *device,
1311 struct radv_cmd_buffer *cmd_buffer,
1312 VkDescriptorSetLayout _layout,
1313 VkDescriptorSet *_set);
1314
1315 void
1316 radv_temp_descriptor_set_destroy(struct radv_device *device,
1317 VkDescriptorSet _set);
1318 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1319 struct radv_image *image, uint32_t value);
1320 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1321 struct radv_image *image, uint32_t value);
1322
1323 struct radv_fence {
1324 struct radeon_winsys_fence *fence;
1325 bool submitted;
1326 bool signalled;
1327 };
1328
1329 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1330 \
1331 static inline struct __radv_type * \
1332 __radv_type ## _from_handle(__VkType _handle) \
1333 { \
1334 return (struct __radv_type *) _handle; \
1335 } \
1336 \
1337 static inline __VkType \
1338 __radv_type ## _to_handle(struct __radv_type *_obj) \
1339 { \
1340 return (__VkType) _obj; \
1341 }
1342
1343 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1344 \
1345 static inline struct __radv_type * \
1346 __radv_type ## _from_handle(__VkType _handle) \
1347 { \
1348 return (struct __radv_type *)(uintptr_t) _handle; \
1349 } \
1350 \
1351 static inline __VkType \
1352 __radv_type ## _to_handle(struct __radv_type *_obj) \
1353 { \
1354 return (__VkType)(uintptr_t) _obj; \
1355 }
1356
1357 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1358 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1359
1360 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1361 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1362 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1363 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1364 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1365
1366 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1367 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1368 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1369 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1370 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1371 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1372 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1373 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1374 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1375 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1376 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1377 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1378 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1379 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1380 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1381 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1382 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1383 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1384 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1385
1386 #endif /* RADV_PRIVATE_H */