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radv: Make color meta operations layout aware.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280
281 VkPhysicalDeviceMemoryProperties memory_properties;
282 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 uint64_t perftest_flags;
296 };
297
298 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
299 void radv_finish_wsi(struct radv_physical_device *physical_device);
300
301 bool radv_instance_extension_supported(const char *name);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
303 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
304 const char *name);
305
306 struct cache_entry;
307
308 struct radv_pipeline_cache {
309 struct radv_device * device;
310 pthread_mutex_t mutex;
311
312 uint32_t total_size;
313 uint32_t table_size;
314 uint32_t kernel_count;
315 struct cache_entry ** hash_table;
316 bool modified;
317
318 VkAllocationCallbacks alloc;
319 };
320
321 struct radv_pipeline_key {
322 uint32_t instance_rate_inputs;
323 unsigned tess_input_vertices;
324 uint32_t col_format;
325 uint32_t is_int8;
326 uint32_t is_int10;
327 uint32_t multisample : 1;
328 uint32_t has_multiview_view_index : 1;
329 };
330
331 void
332 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
333 struct radv_device *device);
334 void
335 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
336 void
337 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
338 const void *data, size_t size);
339
340 struct radv_shader_variant;
341
342 bool
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
344 struct radv_pipeline_cache *cache,
345 const unsigned char *sha1,
346 struct radv_shader_variant **variants);
347
348 void
349 radv_pipeline_cache_insert_shaders(struct radv_device *device,
350 struct radv_pipeline_cache *cache,
351 const unsigned char *sha1,
352 struct radv_shader_variant **variants,
353 const void *const *codes,
354 const unsigned *code_sizes);
355
356 enum radv_blit_ds_layout {
357 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
358 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
359 RADV_BLIT_DS_LAYOUT_COUNT,
360 };
361
362 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
363 {
364 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
365 }
366
367 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
368 {
369 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
370 }
371
372 enum radv_meta_dst_layout {
373 RADV_META_DST_LAYOUT_GENERAL,
374 RADV_META_DST_LAYOUT_OPTIMAL,
375 RADV_META_DST_LAYOUT_COUNT,
376 };
377
378 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
379 {
380 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
381 }
382
383 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
384 {
385 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
386 }
387
388 struct radv_meta_state {
389 VkAllocationCallbacks alloc;
390
391 struct radv_pipeline_cache cache;
392
393 /**
394 * Use array element `i` for images with `2^i` samples.
395 */
396 struct {
397 VkRenderPass render_pass[NUM_META_FS_KEYS];
398 VkPipeline color_pipelines[NUM_META_FS_KEYS];
399
400 VkRenderPass depthstencil_rp;
401 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
402 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
403 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
404 } clear[1 + MAX_SAMPLES_LOG2];
405
406 VkPipelineLayout clear_color_p_layout;
407 VkPipelineLayout clear_depth_p_layout;
408 struct {
409 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
410
411 /** Pipeline that blits from a 1D image. */
412 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
413
414 /** Pipeline that blits from a 2D image. */
415 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
416
417 /** Pipeline that blits from a 3D image. */
418 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
419
420 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
421 VkPipeline depth_only_1d_pipeline;
422 VkPipeline depth_only_2d_pipeline;
423 VkPipeline depth_only_3d_pipeline;
424
425 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
426 VkPipeline stencil_only_1d_pipeline;
427 VkPipeline stencil_only_2d_pipeline;
428 VkPipeline stencil_only_3d_pipeline;
429 VkPipelineLayout pipeline_layout;
430 VkDescriptorSetLayout ds_layout;
431 } blit;
432
433 struct {
434 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
435
436 VkPipelineLayout p_layouts[3];
437 VkDescriptorSetLayout ds_layouts[3];
438 VkPipeline pipelines[3][NUM_META_FS_KEYS];
439
440 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
441 VkPipeline depth_only_pipeline[3];
442
443 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
444 VkPipeline stencil_only_pipeline[3];
445 } blit2d;
446
447 struct {
448 VkPipelineLayout img_p_layout;
449 VkDescriptorSetLayout img_ds_layout;
450 VkPipeline pipeline;
451 VkPipeline pipeline_3d;
452 } itob;
453 struct {
454 VkPipelineLayout img_p_layout;
455 VkDescriptorSetLayout img_ds_layout;
456 VkPipeline pipeline;
457 VkPipeline pipeline_3d;
458 } btoi;
459 struct {
460 VkPipelineLayout img_p_layout;
461 VkDescriptorSetLayout img_ds_layout;
462 VkPipeline pipeline;
463 VkPipeline pipeline_3d;
464 } itoi;
465 struct {
466 VkPipelineLayout img_p_layout;
467 VkDescriptorSetLayout img_ds_layout;
468 VkPipeline pipeline;
469 VkPipeline pipeline_3d;
470 } cleari;
471
472 struct {
473 VkPipelineLayout p_layout;
474 VkPipeline pipeline;
475 VkRenderPass pass;
476 } resolve;
477
478 struct {
479 VkDescriptorSetLayout ds_layout;
480 VkPipelineLayout p_layout;
481 struct {
482 VkPipeline pipeline;
483 VkPipeline i_pipeline;
484 VkPipeline srgb_pipeline;
485 } rc[MAX_SAMPLES_LOG2];
486 } resolve_compute;
487
488 struct {
489 VkDescriptorSetLayout ds_layout;
490 VkPipelineLayout p_layout;
491
492 struct {
493 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
494 VkPipeline pipeline[NUM_META_FS_KEYS];
495 } rc[MAX_SAMPLES_LOG2];
496 } resolve_fragment;
497
498 struct {
499 VkPipelineLayout p_layout;
500 VkPipeline decompress_pipeline;
501 VkPipeline resummarize_pipeline;
502 VkRenderPass pass;
503 } depth_decomp[1 + MAX_SAMPLES_LOG2];
504
505 struct {
506 VkPipelineLayout p_layout;
507 VkPipeline cmask_eliminate_pipeline;
508 VkPipeline fmask_decompress_pipeline;
509 VkPipeline dcc_decompress_pipeline;
510 VkRenderPass pass;
511
512 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
513 VkPipelineLayout dcc_decompress_compute_p_layout;
514 VkPipeline dcc_decompress_compute_pipeline;
515 } fast_clear_flush;
516
517 struct {
518 VkPipelineLayout fill_p_layout;
519 VkPipelineLayout copy_p_layout;
520 VkDescriptorSetLayout fill_ds_layout;
521 VkDescriptorSetLayout copy_ds_layout;
522 VkPipeline fill_pipeline;
523 VkPipeline copy_pipeline;
524 } buffer;
525
526 struct {
527 VkDescriptorSetLayout ds_layout;
528 VkPipelineLayout p_layout;
529 VkPipeline occlusion_query_pipeline;
530 VkPipeline pipeline_statistics_query_pipeline;
531 } query;
532 };
533
534 /* queue types */
535 #define RADV_QUEUE_GENERAL 0
536 #define RADV_QUEUE_COMPUTE 1
537 #define RADV_QUEUE_TRANSFER 2
538
539 #define RADV_MAX_QUEUE_FAMILIES 3
540
541 enum ring_type radv_queue_family_to_ring(int f);
542
543 struct radv_queue {
544 VK_LOADER_DATA _loader_data;
545 struct radv_device * device;
546 struct radeon_winsys_ctx *hw_ctx;
547 enum radeon_ctx_priority priority;
548 uint32_t queue_family_index;
549 int queue_idx;
550
551 uint32_t scratch_size;
552 uint32_t compute_scratch_size;
553 uint32_t esgs_ring_size;
554 uint32_t gsvs_ring_size;
555 bool has_tess_rings;
556 bool has_sample_positions;
557
558 struct radeon_winsys_bo *scratch_bo;
559 struct radeon_winsys_bo *descriptor_bo;
560 struct radeon_winsys_bo *compute_scratch_bo;
561 struct radeon_winsys_bo *esgs_ring_bo;
562 struct radeon_winsys_bo *gsvs_ring_bo;
563 struct radeon_winsys_bo *tess_factor_ring_bo;
564 struct radeon_winsys_bo *tess_offchip_ring_bo;
565 struct radeon_winsys_cs *initial_preamble_cs;
566 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
567 struct radeon_winsys_cs *continue_preamble_cs;
568 };
569
570 struct radv_device {
571 VK_LOADER_DATA _loader_data;
572
573 VkAllocationCallbacks alloc;
574
575 struct radv_instance * instance;
576 struct radeon_winsys *ws;
577
578 struct radv_meta_state meta_state;
579
580 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
581 int queue_count[RADV_MAX_QUEUE_FAMILIES];
582 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
583
584 bool llvm_supports_spill;
585 bool has_distributed_tess;
586 bool dfsm_allowed;
587 uint32_t tess_offchip_block_dw_size;
588 uint32_t scratch_waves;
589 uint32_t dispatch_initiator;
590
591 uint32_t gs_table_depth;
592
593 /* MSAA sample locations.
594 * The first index is the sample index.
595 * The second index is the coordinate: X, Y. */
596 float sample_locations_1x[1][2];
597 float sample_locations_2x[2][2];
598 float sample_locations_4x[4][2];
599 float sample_locations_8x[8][2];
600 float sample_locations_16x[16][2];
601
602 /* CIK and later */
603 uint32_t gfx_init_size_dw;
604 struct radeon_winsys_bo *gfx_init;
605
606 struct radeon_winsys_bo *trace_bo;
607 uint32_t *trace_id_ptr;
608
609 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
610 bool keep_shader_info;
611
612 struct radv_physical_device *physical_device;
613
614 /* Backup in-memory cache to be used if the app doesn't provide one */
615 struct radv_pipeline_cache * mem_cache;
616
617 /*
618 * use different counters so MSAA MRTs get consecutive surface indices,
619 * even if MASK is allocated in between.
620 */
621 uint32_t image_mrt_offset_counter;
622 uint32_t fmask_mrt_offset_counter;
623 struct list_head shader_slabs;
624 mtx_t shader_slab_mutex;
625
626 /* For detecting VM faults reported by dmesg. */
627 uint64_t dmesg_timestamp;
628 };
629
630 struct radv_device_memory {
631 struct radeon_winsys_bo *bo;
632 /* for dedicated allocations */
633 struct radv_image *image;
634 struct radv_buffer *buffer;
635 uint32_t type_index;
636 VkDeviceSize map_size;
637 void * map;
638 };
639
640
641 struct radv_descriptor_range {
642 uint64_t va;
643 uint32_t size;
644 };
645
646 struct radv_descriptor_set {
647 const struct radv_descriptor_set_layout *layout;
648 uint32_t size;
649
650 struct radeon_winsys_bo *bo;
651 uint64_t va;
652 uint32_t *mapped_ptr;
653 struct radv_descriptor_range *dynamic_descriptors;
654
655 struct radeon_winsys_bo *descriptors[0];
656 };
657
658 struct radv_push_descriptor_set
659 {
660 struct radv_descriptor_set set;
661 uint32_t capacity;
662 };
663
664 struct radv_descriptor_pool_entry {
665 uint32_t offset;
666 uint32_t size;
667 struct radv_descriptor_set *set;
668 };
669
670 struct radv_descriptor_pool {
671 struct radeon_winsys_bo *bo;
672 uint8_t *mapped_ptr;
673 uint64_t current_offset;
674 uint64_t size;
675
676 uint8_t *host_memory_base;
677 uint8_t *host_memory_ptr;
678 uint8_t *host_memory_end;
679
680 uint32_t entry_count;
681 uint32_t max_entry_count;
682 struct radv_descriptor_pool_entry entries[0];
683 };
684
685 struct radv_descriptor_update_template_entry {
686 VkDescriptorType descriptor_type;
687
688 /* The number of descriptors to update */
689 uint32_t descriptor_count;
690
691 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
692 uint32_t dst_offset;
693
694 /* In dwords. Not valid/used for dynamic descriptors */
695 uint32_t dst_stride;
696
697 uint32_t buffer_offset;
698
699 /* Only valid for combined image samplers and samplers */
700 uint16_t has_sampler;
701
702 /* In bytes */
703 size_t src_offset;
704 size_t src_stride;
705
706 /* For push descriptors */
707 const uint32_t *immutable_samplers;
708 };
709
710 struct radv_descriptor_update_template {
711 uint32_t entry_count;
712 struct radv_descriptor_update_template_entry entry[0];
713 };
714
715 struct radv_buffer {
716 struct radv_device * device;
717 VkDeviceSize size;
718
719 VkBufferUsageFlags usage;
720 VkBufferCreateFlags flags;
721
722 /* Set when bound */
723 struct radeon_winsys_bo * bo;
724 VkDeviceSize offset;
725
726 bool shareable;
727 };
728
729
730 enum radv_cmd_dirty_bits {
731 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
732 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
733 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
734 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
735 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
736 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
737 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
738 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
739 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
740 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
741 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
742 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
743 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
744 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
745 };
746
747 enum radv_cmd_flush_bits {
748 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
749 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
750 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
751 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
752 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
753 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
754 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
755 /* Same as above, but only writes back and doesn't invalidate */
756 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
757 /* Framebuffer caches */
758 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
759 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
760 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
761 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
762 /* Engine synchronization. */
763 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
764 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
765 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
766 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
767
768 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
769 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
770 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
771 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
772 };
773
774 struct radv_vertex_binding {
775 struct radv_buffer * buffer;
776 VkDeviceSize offset;
777 };
778
779 struct radv_viewport_state {
780 uint32_t count;
781 VkViewport viewports[MAX_VIEWPORTS];
782 };
783
784 struct radv_scissor_state {
785 uint32_t count;
786 VkRect2D scissors[MAX_SCISSORS];
787 };
788
789 struct radv_dynamic_state {
790 /**
791 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
792 * Defines the set of saved dynamic state.
793 */
794 uint32_t mask;
795
796 struct radv_viewport_state viewport;
797
798 struct radv_scissor_state scissor;
799
800 float line_width;
801
802 struct {
803 float bias;
804 float clamp;
805 float slope;
806 } depth_bias;
807
808 float blend_constants[4];
809
810 struct {
811 float min;
812 float max;
813 } depth_bounds;
814
815 struct {
816 uint32_t front;
817 uint32_t back;
818 } stencil_compare_mask;
819
820 struct {
821 uint32_t front;
822 uint32_t back;
823 } stencil_write_mask;
824
825 struct {
826 uint32_t front;
827 uint32_t back;
828 } stencil_reference;
829 };
830
831 extern const struct radv_dynamic_state default_dynamic_state;
832
833 const char *
834 radv_get_debug_option_name(int id);
835
836 const char *
837 radv_get_perftest_option_name(int id);
838
839 /**
840 * Attachment state when recording a renderpass instance.
841 *
842 * The clear value is valid only if there exists a pending clear.
843 */
844 struct radv_attachment_state {
845 VkImageAspectFlags pending_clear_aspects;
846 uint32_t cleared_views;
847 VkClearValue clear_value;
848 VkImageLayout current_layout;
849 };
850
851 struct radv_cmd_state {
852 /* Vertex descriptors */
853 bool vb_prefetch_dirty;
854 uint64_t vb_va;
855 unsigned vb_size;
856
857 bool push_descriptors_dirty;
858 bool predicating;
859 uint32_t dirty;
860
861 struct radv_pipeline * pipeline;
862 struct radv_pipeline * emitted_pipeline;
863 struct radv_pipeline * compute_pipeline;
864 struct radv_pipeline * emitted_compute_pipeline;
865 struct radv_framebuffer * framebuffer;
866 struct radv_render_pass * pass;
867 const struct radv_subpass * subpass;
868 struct radv_dynamic_state dynamic;
869 struct radv_attachment_state * attachments;
870 VkRect2D render_area;
871
872 /* Index buffer */
873 struct radv_buffer *index_buffer;
874 uint64_t index_offset;
875 uint32_t index_type;
876 uint32_t max_index_count;
877 uint64_t index_va;
878 int32_t last_index_type;
879
880 int32_t last_primitive_reset_en;
881 uint32_t last_primitive_reset_index;
882 enum radv_cmd_flush_bits flush_bits;
883 unsigned active_occlusion_queries;
884 float offset_scale;
885 uint32_t descriptors_dirty;
886 uint32_t valid_descriptors;
887 uint32_t trace_id;
888 uint32_t last_ia_multi_vgt_param;
889 };
890
891 struct radv_cmd_pool {
892 VkAllocationCallbacks alloc;
893 struct list_head cmd_buffers;
894 struct list_head free_cmd_buffers;
895 uint32_t queue_family_index;
896 };
897
898 struct radv_cmd_buffer_upload {
899 uint8_t *map;
900 unsigned offset;
901 uint64_t size;
902 struct radeon_winsys_bo *upload_bo;
903 struct list_head list;
904 };
905
906 enum radv_cmd_buffer_status {
907 RADV_CMD_BUFFER_STATUS_INVALID,
908 RADV_CMD_BUFFER_STATUS_INITIAL,
909 RADV_CMD_BUFFER_STATUS_RECORDING,
910 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
911 RADV_CMD_BUFFER_STATUS_PENDING,
912 };
913
914 struct radv_cmd_buffer {
915 VK_LOADER_DATA _loader_data;
916
917 struct radv_device * device;
918
919 struct radv_cmd_pool * pool;
920 struct list_head pool_link;
921
922 VkCommandBufferUsageFlags usage_flags;
923 VkCommandBufferLevel level;
924 enum radv_cmd_buffer_status status;
925 struct radeon_winsys_cs *cs;
926 struct radv_cmd_state state;
927 struct radv_vertex_binding vertex_bindings[MAX_VBS];
928 uint32_t queue_family_index;
929
930 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
931 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
932 VkShaderStageFlags push_constant_stages;
933 struct radv_push_descriptor_set push_descriptors;
934 struct radv_descriptor_set meta_push_descriptors;
935 struct radv_descriptor_set *descriptors[MAX_SETS];
936
937 struct radv_cmd_buffer_upload upload;
938
939 uint32_t scratch_size_needed;
940 uint32_t compute_scratch_size_needed;
941 uint32_t esgs_ring_size_needed;
942 uint32_t gsvs_ring_size_needed;
943 bool tess_rings_needed;
944 bool sample_positions_needed;
945
946 VkResult record_result;
947
948 int ring_offsets_idx; /* just used for verification */
949 uint32_t gfx9_fence_offset;
950 struct radeon_winsys_bo *gfx9_fence_bo;
951 uint32_t gfx9_fence_idx;
952 };
953
954 struct radv_image;
955
956 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
957
958 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
959 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
960
961 void cik_create_gfx_config(struct radv_device *device);
962
963 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
964 int count, const VkViewport *viewports);
965 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
966 int count, const VkRect2D *scissors,
967 const VkViewport *viewports, bool can_use_guardband);
968 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
969 bool instanced_draw, bool indirect_draw,
970 uint32_t draw_vertex_count);
971 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
972 bool predicated,
973 enum chip_class chip_class,
974 bool is_mec,
975 unsigned event, unsigned event_flags,
976 unsigned data_sel,
977 uint64_t va,
978 uint32_t old_fence,
979 uint32_t new_fence);
980
981 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
982 bool predicated,
983 uint64_t va, uint32_t ref,
984 uint32_t mask);
985 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
986 bool predicated,
987 enum chip_class chip_class,
988 uint32_t *fence_ptr, uint64_t va,
989 bool is_mec,
990 enum radv_cmd_flush_bits flush_bits);
991 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
992 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
993 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
994 uint64_t src_va, uint64_t dest_va,
995 uint64_t size);
996 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
997 unsigned size);
998 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
999 uint64_t size, unsigned value);
1000 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1001 bool
1002 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1003 unsigned size,
1004 unsigned alignment,
1005 unsigned *out_offset,
1006 void **ptr);
1007 void
1008 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1009 const struct radv_subpass *subpass,
1010 bool transitions);
1011 bool
1012 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1013 unsigned size, unsigned alignmnet,
1014 const void *data, unsigned *out_offset);
1015
1016 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1017 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1018 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1019 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1020 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1021 unsigned radv_cayman_get_maxdist(int log_samples);
1022 void radv_device_init_msaa(struct radv_device *device);
1023 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1024 struct radv_image *image,
1025 VkClearDepthStencilValue ds_clear_value,
1026 VkImageAspectFlags aspects);
1027 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1028 struct radv_image *image,
1029 int idx,
1030 uint32_t color_values[2]);
1031 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1032 struct radv_image *image,
1033 bool value);
1034 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1035 struct radeon_winsys_bo *bo,
1036 uint64_t offset, uint64_t size, uint32_t value);
1037 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1038 bool radv_get_memory_fd(struct radv_device *device,
1039 struct radv_device_memory *memory,
1040 int *pFD);
1041
1042 /*
1043 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1044 *
1045 * Limitations: Can't call normal dispatch functions without binding or rebinding
1046 * the compute pipeline.
1047 */
1048 void radv_unaligned_dispatch(
1049 struct radv_cmd_buffer *cmd_buffer,
1050 uint32_t x,
1051 uint32_t y,
1052 uint32_t z);
1053
1054 struct radv_event {
1055 struct radeon_winsys_bo *bo;
1056 uint64_t *map;
1057 };
1058
1059 struct radv_shader_module;
1060
1061 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1062 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1063 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1064 void
1065 radv_hash_shaders(unsigned char *hash,
1066 const VkPipelineShaderStageCreateInfo **stages,
1067 const struct radv_pipeline_layout *layout,
1068 const struct radv_pipeline_key *key,
1069 uint32_t flags);
1070
1071 static inline gl_shader_stage
1072 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1073 {
1074 assert(__builtin_popcount(vk_stage) == 1);
1075 return ffs(vk_stage) - 1;
1076 }
1077
1078 static inline VkShaderStageFlagBits
1079 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1080 {
1081 return (1 << mesa_stage);
1082 }
1083
1084 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1085
1086 #define radv_foreach_stage(stage, stage_bits) \
1087 for (gl_shader_stage stage, \
1088 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1089 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1090 __tmp &= ~(1 << (stage)))
1091
1092 struct radv_depth_stencil_state {
1093 uint32_t db_depth_control;
1094 uint32_t db_stencil_control;
1095 uint32_t db_render_control;
1096 uint32_t db_render_override2;
1097 };
1098
1099 struct radv_blend_state {
1100 uint32_t cb_color_control;
1101 uint32_t cb_target_mask;
1102 uint32_t sx_mrt_blend_opt[8];
1103 uint32_t cb_blend_control[8];
1104
1105 uint32_t spi_shader_col_format;
1106 uint32_t cb_shader_mask;
1107 uint32_t db_alpha_to_mask;
1108 };
1109
1110 unsigned radv_format_meta_fs_key(VkFormat format);
1111
1112 struct radv_raster_state {
1113 uint32_t pa_cl_clip_cntl;
1114 uint32_t spi_interp_control;
1115 uint32_t pa_su_vtx_cntl;
1116 uint32_t pa_su_sc_mode_cntl;
1117 };
1118
1119 struct radv_multisample_state {
1120 uint32_t db_eqaa;
1121 uint32_t pa_sc_line_cntl;
1122 uint32_t pa_sc_mode_cntl_0;
1123 uint32_t pa_sc_mode_cntl_1;
1124 uint32_t pa_sc_aa_config;
1125 uint32_t pa_sc_aa_mask[2];
1126 unsigned num_samples;
1127 };
1128
1129 struct radv_prim_vertex_count {
1130 uint8_t min;
1131 uint8_t incr;
1132 };
1133
1134 struct radv_tessellation_state {
1135 uint32_t ls_hs_config;
1136 uint32_t tcs_in_layout;
1137 uint32_t tcs_out_layout;
1138 uint32_t tcs_out_offsets;
1139 uint32_t offchip_layout;
1140 unsigned num_patches;
1141 unsigned lds_size;
1142 unsigned num_tcs_input_cp;
1143 uint32_t tf_param;
1144 };
1145
1146 struct radv_gs_state {
1147 uint32_t vgt_gs_onchip_cntl;
1148 uint32_t vgt_gs_max_prims_per_subgroup;
1149 uint32_t vgt_esgs_ring_itemsize;
1150 uint32_t lds_size;
1151 };
1152
1153 struct radv_vertex_elements_info {
1154 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1155 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1156 uint32_t binding[MAX_VERTEX_ATTRIBS];
1157 uint32_t offset[MAX_VERTEX_ATTRIBS];
1158 uint32_t count;
1159 };
1160
1161 struct radv_vs_state {
1162 uint32_t pa_cl_vs_out_cntl;
1163 uint32_t spi_shader_pos_format;
1164 uint32_t spi_vs_out_config;
1165 uint32_t vgt_reuse_off;
1166 };
1167
1168 #define SI_GS_PER_ES 128
1169
1170 struct radv_pipeline {
1171 struct radv_device * device;
1172 struct radv_dynamic_state dynamic_state;
1173
1174 struct radv_pipeline_layout * layout;
1175
1176 bool needs_data_cache;
1177 bool need_indirect_descriptor_sets;
1178 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1179 struct radv_shader_variant *gs_copy_shader;
1180 VkShaderStageFlags active_stages;
1181
1182 struct radv_vertex_elements_info vertex_elements;
1183
1184 uint32_t binding_stride[MAX_VBS];
1185
1186 uint32_t user_data_0[MESA_SHADER_STAGES];
1187 union {
1188 struct {
1189 struct radv_blend_state blend;
1190 struct radv_depth_stencil_state ds;
1191 struct radv_raster_state raster;
1192 struct radv_multisample_state ms;
1193 struct radv_tessellation_state tess;
1194 struct radv_gs_state gs;
1195 struct radv_vs_state vs;
1196 uint32_t db_shader_control;
1197 uint32_t shader_z_format;
1198 unsigned prim;
1199 unsigned gs_out;
1200 uint32_t vgt_gs_mode;
1201 bool vgt_primitiveid_en;
1202 bool prim_restart_enable;
1203 bool partial_es_wave;
1204 uint8_t primgroup_size;
1205 unsigned esgs_ring_size;
1206 unsigned gsvs_ring_size;
1207 uint32_t ps_input_cntl[32];
1208 uint32_t ps_input_cntl_num;
1209 uint32_t vgt_shader_stages_en;
1210 uint32_t vtx_base_sgpr;
1211 uint32_t base_ia_multi_vgt_param;
1212 bool wd_switch_on_eop;
1213 bool ia_switch_on_eoi;
1214 bool partial_vs_wave;
1215 uint8_t vtx_emit_num;
1216 uint32_t vtx_reuse_depth;
1217 struct radv_prim_vertex_count prim_vertex_count;
1218 bool can_use_guardband;
1219 } graphics;
1220 };
1221
1222 unsigned max_waves;
1223 unsigned scratch_bytes_per_wave;
1224 };
1225
1226 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1227 {
1228 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1229 }
1230
1231 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1232 {
1233 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1234 }
1235
1236 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1237 gl_shader_stage stage,
1238 int idx);
1239
1240 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1241
1242 struct radv_graphics_pipeline_create_info {
1243 bool use_rectlist;
1244 bool db_depth_clear;
1245 bool db_stencil_clear;
1246 bool db_depth_disable_expclear;
1247 bool db_stencil_disable_expclear;
1248 bool db_flush_depth_inplace;
1249 bool db_flush_stencil_inplace;
1250 bool db_resummarize;
1251 uint32_t custom_blend_mode;
1252 };
1253
1254 VkResult
1255 radv_graphics_pipeline_create(VkDevice device,
1256 VkPipelineCache cache,
1257 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1258 const struct radv_graphics_pipeline_create_info *extra,
1259 const VkAllocationCallbacks *alloc,
1260 VkPipeline *pPipeline);
1261
1262 struct vk_format_description;
1263 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1264 int first_non_void);
1265 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1266 int first_non_void);
1267 uint32_t radv_translate_colorformat(VkFormat format);
1268 uint32_t radv_translate_color_numformat(VkFormat format,
1269 const struct vk_format_description *desc,
1270 int first_non_void);
1271 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1272 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1273 uint32_t radv_translate_dbformat(VkFormat format);
1274 uint32_t radv_translate_tex_dataformat(VkFormat format,
1275 const struct vk_format_description *desc,
1276 int first_non_void);
1277 uint32_t radv_translate_tex_numformat(VkFormat format,
1278 const struct vk_format_description *desc,
1279 int first_non_void);
1280 bool radv_format_pack_clear_color(VkFormat format,
1281 uint32_t clear_vals[2],
1282 VkClearColorValue *value);
1283 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1284 bool radv_dcc_formats_compatible(VkFormat format1,
1285 VkFormat format2);
1286
1287 struct radv_fmask_info {
1288 uint64_t offset;
1289 uint64_t size;
1290 unsigned alignment;
1291 unsigned pitch_in_pixels;
1292 unsigned bank_height;
1293 unsigned slice_tile_max;
1294 unsigned tile_mode_index;
1295 unsigned tile_swizzle;
1296 };
1297
1298 struct radv_cmask_info {
1299 uint64_t offset;
1300 uint64_t size;
1301 unsigned alignment;
1302 unsigned slice_tile_max;
1303 };
1304
1305 struct radv_image {
1306 VkImageType type;
1307 /* The original VkFormat provided by the client. This may not match any
1308 * of the actual surface formats.
1309 */
1310 VkFormat vk_format;
1311 VkImageAspectFlags aspects;
1312 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1313 struct ac_surf_info info;
1314 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1315 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1316
1317 VkDeviceSize size;
1318 uint32_t alignment;
1319
1320 unsigned queue_family_mask;
1321 bool exclusive;
1322 bool shareable;
1323
1324 /* Set when bound */
1325 struct radeon_winsys_bo *bo;
1326 VkDeviceSize offset;
1327 uint64_t dcc_offset;
1328 uint64_t htile_offset;
1329 bool tc_compatible_htile;
1330 struct radeon_surf surface;
1331
1332 struct radv_fmask_info fmask;
1333 struct radv_cmask_info cmask;
1334 uint64_t clear_value_offset;
1335 uint64_t dcc_pred_offset;
1336 };
1337
1338 /* Whether the image has a htile that is known consistent with the contents of
1339 * the image. */
1340 bool radv_layout_has_htile(const struct radv_image *image,
1341 VkImageLayout layout,
1342 unsigned queue_mask);
1343
1344 /* Whether the image has a htile that is known consistent with the contents of
1345 * the image and is allowed to be in compressed form.
1346 *
1347 * If this is false reads that don't use the htile should be able to return
1348 * correct results.
1349 */
1350 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1351 VkImageLayout layout,
1352 unsigned queue_mask);
1353
1354 bool radv_layout_can_fast_clear(const struct radv_image *image,
1355 VkImageLayout layout,
1356 unsigned queue_mask);
1357
1358 static inline bool
1359 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1360 {
1361 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1362 }
1363
1364 static inline bool
1365 radv_htile_enabled(const struct radv_image *image, unsigned level)
1366 {
1367 return image->surface.htile_size && level == 0;
1368 }
1369
1370 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1371
1372 static inline uint32_t
1373 radv_get_layerCount(const struct radv_image *image,
1374 const VkImageSubresourceRange *range)
1375 {
1376 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1377 image->info.array_size - range->baseArrayLayer : range->layerCount;
1378 }
1379
1380 static inline uint32_t
1381 radv_get_levelCount(const struct radv_image *image,
1382 const VkImageSubresourceRange *range)
1383 {
1384 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1385 image->info.levels - range->baseMipLevel : range->levelCount;
1386 }
1387
1388 struct radeon_bo_metadata;
1389 void
1390 radv_init_metadata(struct radv_device *device,
1391 struct radv_image *image,
1392 struct radeon_bo_metadata *metadata);
1393
1394 struct radv_image_view {
1395 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1396 struct radeon_winsys_bo *bo;
1397
1398 VkImageViewType type;
1399 VkImageAspectFlags aspect_mask;
1400 VkFormat vk_format;
1401 uint32_t base_layer;
1402 uint32_t layer_count;
1403 uint32_t base_mip;
1404 uint32_t level_count;
1405 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1406
1407 uint32_t descriptor[16];
1408
1409 /* Descriptor for use as a storage image as opposed to a sampled image.
1410 * This has a few differences for cube maps (e.g. type).
1411 */
1412 uint32_t storage_descriptor[16];
1413 };
1414
1415 struct radv_image_create_info {
1416 const VkImageCreateInfo *vk_info;
1417 bool scanout;
1418 };
1419
1420 VkResult radv_image_create(VkDevice _device,
1421 const struct radv_image_create_info *info,
1422 const VkAllocationCallbacks* alloc,
1423 VkImage *pImage);
1424
1425 void radv_image_view_init(struct radv_image_view *view,
1426 struct radv_device *device,
1427 const VkImageViewCreateInfo* pCreateInfo);
1428
1429 struct radv_buffer_view {
1430 struct radeon_winsys_bo *bo;
1431 VkFormat vk_format;
1432 uint64_t range; /**< VkBufferViewCreateInfo::range */
1433 uint32_t state[4];
1434 };
1435 void radv_buffer_view_init(struct radv_buffer_view *view,
1436 struct radv_device *device,
1437 const VkBufferViewCreateInfo* pCreateInfo);
1438
1439 static inline struct VkExtent3D
1440 radv_sanitize_image_extent(const VkImageType imageType,
1441 const struct VkExtent3D imageExtent)
1442 {
1443 switch (imageType) {
1444 case VK_IMAGE_TYPE_1D:
1445 return (VkExtent3D) { imageExtent.width, 1, 1 };
1446 case VK_IMAGE_TYPE_2D:
1447 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1448 case VK_IMAGE_TYPE_3D:
1449 return imageExtent;
1450 default:
1451 unreachable("invalid image type");
1452 }
1453 }
1454
1455 static inline struct VkOffset3D
1456 radv_sanitize_image_offset(const VkImageType imageType,
1457 const struct VkOffset3D imageOffset)
1458 {
1459 switch (imageType) {
1460 case VK_IMAGE_TYPE_1D:
1461 return (VkOffset3D) { imageOffset.x, 0, 0 };
1462 case VK_IMAGE_TYPE_2D:
1463 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1464 case VK_IMAGE_TYPE_3D:
1465 return imageOffset;
1466 default:
1467 unreachable("invalid image type");
1468 }
1469 }
1470
1471 static inline bool
1472 radv_image_extent_compare(const struct radv_image *image,
1473 const VkExtent3D *extent)
1474 {
1475 if (extent->width != image->info.width ||
1476 extent->height != image->info.height ||
1477 extent->depth != image->info.depth)
1478 return false;
1479 return true;
1480 }
1481
1482 struct radv_sampler {
1483 uint32_t state[4];
1484 };
1485
1486 struct radv_color_buffer_info {
1487 uint64_t cb_color_base;
1488 uint64_t cb_color_cmask;
1489 uint64_t cb_color_fmask;
1490 uint64_t cb_dcc_base;
1491 uint32_t cb_color_pitch;
1492 uint32_t cb_color_slice;
1493 uint32_t cb_color_view;
1494 uint32_t cb_color_info;
1495 uint32_t cb_color_attrib;
1496 uint32_t cb_color_attrib2;
1497 uint32_t cb_dcc_control;
1498 uint32_t cb_color_cmask_slice;
1499 uint32_t cb_color_fmask_slice;
1500 uint32_t cb_clear_value0;
1501 uint32_t cb_clear_value1;
1502 };
1503
1504 struct radv_ds_buffer_info {
1505 uint64_t db_z_read_base;
1506 uint64_t db_stencil_read_base;
1507 uint64_t db_z_write_base;
1508 uint64_t db_stencil_write_base;
1509 uint64_t db_htile_data_base;
1510 uint32_t db_depth_info;
1511 uint32_t db_z_info;
1512 uint32_t db_stencil_info;
1513 uint32_t db_depth_view;
1514 uint32_t db_depth_size;
1515 uint32_t db_depth_slice;
1516 uint32_t db_htile_surface;
1517 uint32_t pa_su_poly_offset_db_fmt_cntl;
1518 uint32_t db_z_info2;
1519 uint32_t db_stencil_info2;
1520 float offset_scale;
1521 };
1522
1523 struct radv_attachment_info {
1524 union {
1525 struct radv_color_buffer_info cb;
1526 struct radv_ds_buffer_info ds;
1527 };
1528 struct radv_image_view *attachment;
1529 };
1530
1531 struct radv_framebuffer {
1532 uint32_t width;
1533 uint32_t height;
1534 uint32_t layers;
1535
1536 uint32_t attachment_count;
1537 struct radv_attachment_info attachments[0];
1538 };
1539
1540 struct radv_subpass_barrier {
1541 VkPipelineStageFlags src_stage_mask;
1542 VkAccessFlags src_access_mask;
1543 VkAccessFlags dst_access_mask;
1544 };
1545
1546 struct radv_subpass {
1547 uint32_t input_count;
1548 uint32_t color_count;
1549 VkAttachmentReference * input_attachments;
1550 VkAttachmentReference * color_attachments;
1551 VkAttachmentReference * resolve_attachments;
1552 VkAttachmentReference depth_stencil_attachment;
1553
1554 /** Subpass has at least one resolve attachment */
1555 bool has_resolve;
1556
1557 struct radv_subpass_barrier start_barrier;
1558
1559 uint32_t view_mask;
1560 };
1561
1562 struct radv_render_pass_attachment {
1563 VkFormat format;
1564 uint32_t samples;
1565 VkAttachmentLoadOp load_op;
1566 VkAttachmentLoadOp stencil_load_op;
1567 VkImageLayout initial_layout;
1568 VkImageLayout final_layout;
1569 uint32_t view_mask;
1570 };
1571
1572 struct radv_render_pass {
1573 uint32_t attachment_count;
1574 uint32_t subpass_count;
1575 VkAttachmentReference * subpass_attachments;
1576 struct radv_render_pass_attachment * attachments;
1577 struct radv_subpass_barrier end_barrier;
1578 struct radv_subpass subpasses[0];
1579 };
1580
1581 VkResult radv_device_init_meta(struct radv_device *device);
1582 void radv_device_finish_meta(struct radv_device *device);
1583
1584 struct radv_query_pool {
1585 struct radeon_winsys_bo *bo;
1586 uint32_t stride;
1587 uint32_t availability_offset;
1588 char *ptr;
1589 VkQueryType type;
1590 uint32_t pipeline_stats_mask;
1591 };
1592
1593 struct radv_semaphore {
1594 /* use a winsys sem for non-exportable */
1595 struct radeon_winsys_sem *sem;
1596 uint32_t syncobj;
1597 uint32_t temp_syncobj;
1598 };
1599
1600 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1601 int num_wait_sems,
1602 const VkSemaphore *wait_sems,
1603 int num_signal_sems,
1604 const VkSemaphore *signal_sems,
1605 VkFence fence);
1606 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1607
1608 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1609 struct radv_descriptor_set *set,
1610 unsigned idx);
1611
1612 void
1613 radv_update_descriptor_sets(struct radv_device *device,
1614 struct radv_cmd_buffer *cmd_buffer,
1615 VkDescriptorSet overrideSet,
1616 uint32_t descriptorWriteCount,
1617 const VkWriteDescriptorSet *pDescriptorWrites,
1618 uint32_t descriptorCopyCount,
1619 const VkCopyDescriptorSet *pDescriptorCopies);
1620
1621 void
1622 radv_update_descriptor_set_with_template(struct radv_device *device,
1623 struct radv_cmd_buffer *cmd_buffer,
1624 struct radv_descriptor_set *set,
1625 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1626 const void *pData);
1627
1628 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1629 VkPipelineBindPoint pipelineBindPoint,
1630 VkPipelineLayout _layout,
1631 uint32_t set,
1632 uint32_t descriptorWriteCount,
1633 const VkWriteDescriptorSet *pDescriptorWrites);
1634
1635 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1636 struct radv_image *image, uint32_t value);
1637 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1638 struct radv_image *image, uint32_t value);
1639
1640 struct radv_fence {
1641 struct radeon_winsys_fence *fence;
1642 bool submitted;
1643 bool signalled;
1644
1645 uint32_t syncobj;
1646 uint32_t temp_syncobj;
1647 };
1648
1649 struct radeon_winsys_sem;
1650
1651 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1652 \
1653 static inline struct __radv_type * \
1654 __radv_type ## _from_handle(__VkType _handle) \
1655 { \
1656 return (struct __radv_type *) _handle; \
1657 } \
1658 \
1659 static inline __VkType \
1660 __radv_type ## _to_handle(struct __radv_type *_obj) \
1661 { \
1662 return (__VkType) _obj; \
1663 }
1664
1665 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1666 \
1667 static inline struct __radv_type * \
1668 __radv_type ## _from_handle(__VkType _handle) \
1669 { \
1670 return (struct __radv_type *)(uintptr_t) _handle; \
1671 } \
1672 \
1673 static inline __VkType \
1674 __radv_type ## _to_handle(struct __radv_type *_obj) \
1675 { \
1676 return (__VkType)(uintptr_t) _obj; \
1677 }
1678
1679 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1680 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1681
1682 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1683 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1684 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1685 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1686 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1687
1688 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1689 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1690 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1691 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1692 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1693 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1694 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1695 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1696 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1697 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1698 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1699 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1700 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1701 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1702 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1703 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1704 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1705 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1706 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1709
1710 #endif /* RADV_PRIVATE_H */