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radv: implement clear operations for R32G32B32
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102
103 #define NUM_DEPTH_CLEAR_PIPELINES 3
104
105 /*
106 * This is the point we switch from using CP to compute shader
107 * for certain buffer operations.
108 */
109 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
110
111 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
112
113 enum radv_mem_heap {
114 RADV_MEM_HEAP_VRAM,
115 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
116 RADV_MEM_HEAP_GTT,
117 RADV_MEM_HEAP_COUNT
118 };
119
120 enum radv_mem_type {
121 RADV_MEM_TYPE_VRAM,
122 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
123 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
124 RADV_MEM_TYPE_GTT_CACHED,
125 RADV_MEM_TYPE_COUNT
126 };
127
128 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 radv_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 radv_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 radv_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; \
212 __dword &= ~(1 << (b)))
213
214 #define typed_memcpy(dest, src, count) ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 /* Whenever we generate an error, pass it through this function. Useful for
220 * debugging, where we can break on it. Only call at error site, not when
221 * propagating errors. Might be useful to plug in a stack trace here.
222 */
223
224 struct radv_instance;
225
226 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
227
228 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
229 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
230
231 void __radv_finishme(const char *file, int line, const char *format, ...)
232 radv_printflike(3, 4);
233 void radv_loge(const char *format, ...) radv_printflike(1, 2);
234 void radv_loge_v(const char *format, va_list va);
235 void radv_logi(const char *format, ...) radv_printflike(1, 2);
236 void radv_logi_v(const char *format, va_list va);
237
238 /**
239 * Print a FINISHME message, including its source location.
240 */
241 #define radv_finishme(format, ...) \
242 do { \
243 static bool reported = false; \
244 if (!reported) { \
245 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
246 reported = true; \
247 } \
248 } while (0)
249
250 /* A non-fatal assert. Useful for debugging. */
251 #ifdef DEBUG
252 #define radv_assert(x) ({ \
253 if (unlikely(!(x))) \
254 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
255 })
256 #else
257 #define radv_assert(x)
258 #endif
259
260 #define stub_return(v) \
261 do { \
262 radv_finishme("stub %s", __func__); \
263 return (v); \
264 } while (0)
265
266 #define stub() \
267 do { \
268 radv_finishme("stub %s", __func__); \
269 return; \
270 } while (0)
271
272 void *radv_lookup_entrypoint_unchecked(const char *name);
273 void *radv_lookup_entrypoint_checked(const char *name,
274 uint32_t core_version,
275 const struct radv_instance_extension_table *instance,
276 const struct radv_device_extension_table *device);
277
278 struct radv_physical_device {
279 VK_LOADER_DATA _loader_data;
280
281 struct radv_instance * instance;
282
283 struct radeon_winsys *ws;
284 struct radeon_info rad_info;
285 char path[20];
286 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
287 uint8_t driver_uuid[VK_UUID_SIZE];
288 uint8_t device_uuid[VK_UUID_SIZE];
289 uint8_t cache_uuid[VK_UUID_SIZE];
290
291 int local_fd;
292 int master_fd;
293 struct wsi_device wsi_device;
294
295 bool has_rbplus; /* if RB+ register exist */
296 bool rbplus_allowed; /* if RB+ is allowed */
297 bool has_clear_state;
298 bool cpdma_prefetch_writes_memory;
299 bool has_scissor_bug;
300
301 bool has_out_of_order_rast;
302 bool out_of_order_rast_allowed;
303
304 /* Whether DCC should be enabled for MSAA textures. */
305 bool dcc_msaa_allowed;
306
307 /* This is the drivers on-disk cache used as a fallback as opposed to
308 * the pipeline cache defined by apps.
309 */
310 struct disk_cache * disk_cache;
311
312 VkPhysicalDeviceMemoryProperties memory_properties;
313 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
314
315 struct radv_device_extension_table supported_extensions;
316 };
317
318 struct radv_instance {
319 VK_LOADER_DATA _loader_data;
320
321 VkAllocationCallbacks alloc;
322
323 uint32_t apiVersion;
324 int physicalDeviceCount;
325 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
326
327 uint64_t debug_flags;
328 uint64_t perftest_flags;
329
330 struct vk_debug_report_instance debug_report_callbacks;
331
332 struct radv_instance_extension_table enabled_extensions;
333 };
334
335 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
336 void radv_finish_wsi(struct radv_physical_device *physical_device);
337
338 bool radv_instance_extension_supported(const char *name);
339 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
340 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
341 const char *name);
342
343 struct cache_entry;
344
345 struct radv_pipeline_cache {
346 struct radv_device * device;
347 pthread_mutex_t mutex;
348
349 uint32_t total_size;
350 uint32_t table_size;
351 uint32_t kernel_count;
352 struct cache_entry ** hash_table;
353 bool modified;
354
355 VkAllocationCallbacks alloc;
356 };
357
358 struct radv_pipeline_key {
359 uint32_t instance_rate_inputs;
360 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
361 uint64_t vertex_alpha_adjust;
362 unsigned tess_input_vertices;
363 uint32_t col_format;
364 uint32_t is_int8;
365 uint32_t is_int10;
366 uint8_t log2_ps_iter_samples;
367 uint8_t num_samples;
368 uint32_t has_multiview_view_index : 1;
369 uint32_t optimisations_disabled : 1;
370 };
371
372 void
373 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
374 struct radv_device *device);
375 void
376 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
377 bool
378 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
379 const void *data, size_t size);
380
381 struct radv_shader_variant;
382
383 bool
384 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
385 struct radv_pipeline_cache *cache,
386 const unsigned char *sha1,
387 struct radv_shader_variant **variants);
388
389 void
390 radv_pipeline_cache_insert_shaders(struct radv_device *device,
391 struct radv_pipeline_cache *cache,
392 const unsigned char *sha1,
393 struct radv_shader_variant **variants,
394 const void *const *codes,
395 const unsigned *code_sizes);
396
397 enum radv_blit_ds_layout {
398 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
399 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
400 RADV_BLIT_DS_LAYOUT_COUNT,
401 };
402
403 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
404 {
405 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
406 }
407
408 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
409 {
410 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
411 }
412
413 enum radv_meta_dst_layout {
414 RADV_META_DST_LAYOUT_GENERAL,
415 RADV_META_DST_LAYOUT_OPTIMAL,
416 RADV_META_DST_LAYOUT_COUNT,
417 };
418
419 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
420 {
421 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
422 }
423
424 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
425 {
426 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
427 }
428
429 struct radv_meta_state {
430 VkAllocationCallbacks alloc;
431
432 struct radv_pipeline_cache cache;
433
434 /*
435 * For on-demand pipeline creation, makes sure that
436 * only one thread tries to build a pipeline at the same time.
437 */
438 mtx_t mtx;
439
440 /**
441 * Use array element `i` for images with `2^i` samples.
442 */
443 struct {
444 VkRenderPass render_pass[NUM_META_FS_KEYS];
445 VkPipeline color_pipelines[NUM_META_FS_KEYS];
446
447 VkRenderPass depthstencil_rp;
448 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
449 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
450 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
451 } clear[1 + MAX_SAMPLES_LOG2];
452
453 VkPipelineLayout clear_color_p_layout;
454 VkPipelineLayout clear_depth_p_layout;
455 struct {
456 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
457
458 /** Pipeline that blits from a 1D image. */
459 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
460
461 /** Pipeline that blits from a 2D image. */
462 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
463
464 /** Pipeline that blits from a 3D image. */
465 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
466
467 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
468 VkPipeline depth_only_1d_pipeline;
469 VkPipeline depth_only_2d_pipeline;
470 VkPipeline depth_only_3d_pipeline;
471
472 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
473 VkPipeline stencil_only_1d_pipeline;
474 VkPipeline stencil_only_2d_pipeline;
475 VkPipeline stencil_only_3d_pipeline;
476 VkPipelineLayout pipeline_layout;
477 VkDescriptorSetLayout ds_layout;
478 } blit;
479
480 struct {
481 VkPipelineLayout p_layouts[5];
482 VkDescriptorSetLayout ds_layouts[5];
483 VkPipeline pipelines[5][NUM_META_FS_KEYS];
484
485 VkPipeline depth_only_pipeline[5];
486
487 VkPipeline stencil_only_pipeline[5];
488 } blit2d[1 + MAX_SAMPLES_LOG2];
489
490 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
491 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
492 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
493
494 struct {
495 VkPipelineLayout img_p_layout;
496 VkDescriptorSetLayout img_ds_layout;
497 VkPipeline pipeline;
498 VkPipeline pipeline_3d;
499 } itob;
500 struct {
501 VkPipelineLayout img_p_layout;
502 VkDescriptorSetLayout img_ds_layout;
503 VkPipeline pipeline;
504 VkPipeline pipeline_3d;
505 } btoi;
506 struct {
507 VkPipelineLayout img_p_layout;
508 VkDescriptorSetLayout img_ds_layout;
509 VkPipeline pipeline;
510 VkPipeline pipeline_3d;
511 } itoi;
512 struct {
513 VkPipelineLayout img_p_layout;
514 VkDescriptorSetLayout img_ds_layout;
515 VkPipeline pipeline;
516 VkPipeline pipeline_3d;
517 } cleari;
518 struct {
519 VkPipelineLayout img_p_layout;
520 VkDescriptorSetLayout img_ds_layout;
521 VkPipeline pipeline;
522 } cleari_r32g32b32;
523
524 struct {
525 VkPipelineLayout p_layout;
526 VkPipeline pipeline[NUM_META_FS_KEYS];
527 VkRenderPass pass[NUM_META_FS_KEYS];
528 } resolve;
529
530 struct {
531 VkDescriptorSetLayout ds_layout;
532 VkPipelineLayout p_layout;
533 struct {
534 VkPipeline pipeline;
535 VkPipeline i_pipeline;
536 VkPipeline srgb_pipeline;
537 } rc[MAX_SAMPLES_LOG2];
538 } resolve_compute;
539
540 struct {
541 VkDescriptorSetLayout ds_layout;
542 VkPipelineLayout p_layout;
543
544 struct {
545 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
546 VkPipeline pipeline[NUM_META_FS_KEYS];
547 } rc[MAX_SAMPLES_LOG2];
548 } resolve_fragment;
549
550 struct {
551 VkPipelineLayout p_layout;
552 VkPipeline decompress_pipeline;
553 VkPipeline resummarize_pipeline;
554 VkRenderPass pass;
555 } depth_decomp[1 + MAX_SAMPLES_LOG2];
556
557 struct {
558 VkPipelineLayout p_layout;
559 VkPipeline cmask_eliminate_pipeline;
560 VkPipeline fmask_decompress_pipeline;
561 VkPipeline dcc_decompress_pipeline;
562 VkRenderPass pass;
563
564 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
565 VkPipelineLayout dcc_decompress_compute_p_layout;
566 VkPipeline dcc_decompress_compute_pipeline;
567 } fast_clear_flush;
568
569 struct {
570 VkPipelineLayout fill_p_layout;
571 VkPipelineLayout copy_p_layout;
572 VkDescriptorSetLayout fill_ds_layout;
573 VkDescriptorSetLayout copy_ds_layout;
574 VkPipeline fill_pipeline;
575 VkPipeline copy_pipeline;
576 } buffer;
577
578 struct {
579 VkDescriptorSetLayout ds_layout;
580 VkPipelineLayout p_layout;
581 VkPipeline occlusion_query_pipeline;
582 VkPipeline pipeline_statistics_query_pipeline;
583 } query;
584 };
585
586 /* queue types */
587 #define RADV_QUEUE_GENERAL 0
588 #define RADV_QUEUE_COMPUTE 1
589 #define RADV_QUEUE_TRANSFER 2
590
591 #define RADV_MAX_QUEUE_FAMILIES 3
592
593 enum ring_type radv_queue_family_to_ring(int f);
594
595 struct radv_queue {
596 VK_LOADER_DATA _loader_data;
597 struct radv_device * device;
598 struct radeon_winsys_ctx *hw_ctx;
599 enum radeon_ctx_priority priority;
600 uint32_t queue_family_index;
601 int queue_idx;
602 VkDeviceQueueCreateFlags flags;
603
604 uint32_t scratch_size;
605 uint32_t compute_scratch_size;
606 uint32_t esgs_ring_size;
607 uint32_t gsvs_ring_size;
608 bool has_tess_rings;
609 bool has_sample_positions;
610
611 struct radeon_winsys_bo *scratch_bo;
612 struct radeon_winsys_bo *descriptor_bo;
613 struct radeon_winsys_bo *compute_scratch_bo;
614 struct radeon_winsys_bo *esgs_ring_bo;
615 struct radeon_winsys_bo *gsvs_ring_bo;
616 struct radeon_winsys_bo *tess_rings_bo;
617 struct radeon_cmdbuf *initial_preamble_cs;
618 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
619 struct radeon_cmdbuf *continue_preamble_cs;
620 };
621
622 struct radv_bo_list {
623 struct radv_winsys_bo_list list;
624 unsigned capacity;
625 pthread_mutex_t mutex;
626 };
627
628 struct radv_device {
629 VK_LOADER_DATA _loader_data;
630
631 VkAllocationCallbacks alloc;
632
633 struct radv_instance * instance;
634 struct radeon_winsys *ws;
635
636 struct radv_meta_state meta_state;
637
638 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
639 int queue_count[RADV_MAX_QUEUE_FAMILIES];
640 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
641
642 bool always_use_syncobj;
643 bool has_distributed_tess;
644 bool pbb_allowed;
645 bool dfsm_allowed;
646 uint32_t tess_offchip_block_dw_size;
647 uint32_t scratch_waves;
648 uint32_t dispatch_initiator;
649
650 uint32_t gs_table_depth;
651
652 /* MSAA sample locations.
653 * The first index is the sample index.
654 * The second index is the coordinate: X, Y. */
655 float sample_locations_1x[1][2];
656 float sample_locations_2x[2][2];
657 float sample_locations_4x[4][2];
658 float sample_locations_8x[8][2];
659 float sample_locations_16x[16][2];
660
661 /* CIK and later */
662 uint32_t gfx_init_size_dw;
663 struct radeon_winsys_bo *gfx_init;
664
665 struct radeon_winsys_bo *trace_bo;
666 uint32_t *trace_id_ptr;
667
668 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
669 bool keep_shader_info;
670
671 struct radv_physical_device *physical_device;
672
673 /* Backup in-memory cache to be used if the app doesn't provide one */
674 struct radv_pipeline_cache * mem_cache;
675
676 /*
677 * use different counters so MSAA MRTs get consecutive surface indices,
678 * even if MASK is allocated in between.
679 */
680 uint32_t image_mrt_offset_counter;
681 uint32_t fmask_mrt_offset_counter;
682 struct list_head shader_slabs;
683 mtx_t shader_slab_mutex;
684
685 /* For detecting VM faults reported by dmesg. */
686 uint64_t dmesg_timestamp;
687
688 struct radv_device_extension_table enabled_extensions;
689
690 /* Whether the driver uses a global BO list. */
691 bool use_global_bo_list;
692
693 struct radv_bo_list bo_list;
694
695 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
696 int force_aniso;
697 };
698
699 struct radv_device_memory {
700 struct radeon_winsys_bo *bo;
701 /* for dedicated allocations */
702 struct radv_image *image;
703 struct radv_buffer *buffer;
704 uint32_t type_index;
705 VkDeviceSize map_size;
706 void * map;
707 void * user_ptr;
708 };
709
710
711 struct radv_descriptor_range {
712 uint64_t va;
713 uint32_t size;
714 };
715
716 struct radv_descriptor_set {
717 const struct radv_descriptor_set_layout *layout;
718 uint32_t size;
719
720 struct radeon_winsys_bo *bo;
721 uint64_t va;
722 uint32_t *mapped_ptr;
723 struct radv_descriptor_range *dynamic_descriptors;
724
725 struct radeon_winsys_bo *descriptors[0];
726 };
727
728 struct radv_push_descriptor_set
729 {
730 struct radv_descriptor_set set;
731 uint32_t capacity;
732 };
733
734 struct radv_descriptor_pool_entry {
735 uint32_t offset;
736 uint32_t size;
737 struct radv_descriptor_set *set;
738 };
739
740 struct radv_descriptor_pool {
741 struct radeon_winsys_bo *bo;
742 uint8_t *mapped_ptr;
743 uint64_t current_offset;
744 uint64_t size;
745
746 uint8_t *host_memory_base;
747 uint8_t *host_memory_ptr;
748 uint8_t *host_memory_end;
749
750 uint32_t entry_count;
751 uint32_t max_entry_count;
752 struct radv_descriptor_pool_entry entries[0];
753 };
754
755 struct radv_descriptor_update_template_entry {
756 VkDescriptorType descriptor_type;
757
758 /* The number of descriptors to update */
759 uint32_t descriptor_count;
760
761 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
762 uint32_t dst_offset;
763
764 /* In dwords. Not valid/used for dynamic descriptors */
765 uint32_t dst_stride;
766
767 uint32_t buffer_offset;
768
769 /* Only valid for combined image samplers and samplers */
770 uint16_t has_sampler;
771
772 /* In bytes */
773 size_t src_offset;
774 size_t src_stride;
775
776 /* For push descriptors */
777 const uint32_t *immutable_samplers;
778 };
779
780 struct radv_descriptor_update_template {
781 uint32_t entry_count;
782 VkPipelineBindPoint bind_point;
783 struct radv_descriptor_update_template_entry entry[0];
784 };
785
786 struct radv_buffer {
787 VkDeviceSize size;
788
789 VkBufferUsageFlags usage;
790 VkBufferCreateFlags flags;
791
792 /* Set when bound */
793 struct radeon_winsys_bo * bo;
794 VkDeviceSize offset;
795
796 bool shareable;
797 };
798
799 enum radv_dynamic_state_bits {
800 RADV_DYNAMIC_VIEWPORT = 1 << 0,
801 RADV_DYNAMIC_SCISSOR = 1 << 1,
802 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
803 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
804 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
805 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
806 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
807 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
808 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
809 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
810 RADV_DYNAMIC_ALL = (1 << 10) - 1,
811 };
812
813 enum radv_cmd_dirty_bits {
814 /* Keep the dynamic state dirty bits in sync with
815 * enum radv_dynamic_state_bits */
816 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
817 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
818 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
819 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
820 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
821 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
822 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
823 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
824 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
825 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
826 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
827 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
828 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
829 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
830 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
831 };
832
833 enum radv_cmd_flush_bits {
834 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
835 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
836 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
837 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
838 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
839 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
840 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
841 /* Same as above, but only writes back and doesn't invalidate */
842 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
843 /* Framebuffer caches */
844 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
845 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
846 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
847 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
848 /* Engine synchronization. */
849 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
850 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
851 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
852 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
853 /* Pipeline query controls. */
854 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
855 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
856
857 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
858 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
859 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
860 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
861 };
862
863 struct radv_vertex_binding {
864 struct radv_buffer * buffer;
865 VkDeviceSize offset;
866 };
867
868 struct radv_viewport_state {
869 uint32_t count;
870 VkViewport viewports[MAX_VIEWPORTS];
871 };
872
873 struct radv_scissor_state {
874 uint32_t count;
875 VkRect2D scissors[MAX_SCISSORS];
876 };
877
878 struct radv_discard_rectangle_state {
879 uint32_t count;
880 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
881 };
882
883 struct radv_dynamic_state {
884 /**
885 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
886 * Defines the set of saved dynamic state.
887 */
888 uint32_t mask;
889
890 struct radv_viewport_state viewport;
891
892 struct radv_scissor_state scissor;
893
894 float line_width;
895
896 struct {
897 float bias;
898 float clamp;
899 float slope;
900 } depth_bias;
901
902 float blend_constants[4];
903
904 struct {
905 float min;
906 float max;
907 } depth_bounds;
908
909 struct {
910 uint32_t front;
911 uint32_t back;
912 } stencil_compare_mask;
913
914 struct {
915 uint32_t front;
916 uint32_t back;
917 } stencil_write_mask;
918
919 struct {
920 uint32_t front;
921 uint32_t back;
922 } stencil_reference;
923
924 struct radv_discard_rectangle_state discard_rectangle;
925 };
926
927 extern const struct radv_dynamic_state default_dynamic_state;
928
929 const char *
930 radv_get_debug_option_name(int id);
931
932 const char *
933 radv_get_perftest_option_name(int id);
934
935 /**
936 * Attachment state when recording a renderpass instance.
937 *
938 * The clear value is valid only if there exists a pending clear.
939 */
940 struct radv_attachment_state {
941 VkImageAspectFlags pending_clear_aspects;
942 uint32_t cleared_views;
943 VkClearValue clear_value;
944 VkImageLayout current_layout;
945 };
946
947 struct radv_descriptor_state {
948 struct radv_descriptor_set *sets[MAX_SETS];
949 uint32_t dirty;
950 uint32_t valid;
951 struct radv_push_descriptor_set push_set;
952 bool push_dirty;
953 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
954 };
955
956 struct radv_cmd_state {
957 /* Vertex descriptors */
958 uint64_t vb_va;
959 unsigned vb_size;
960
961 bool predicating;
962 uint32_t dirty;
963
964 uint32_t prefetch_L2_mask;
965
966 struct radv_pipeline * pipeline;
967 struct radv_pipeline * emitted_pipeline;
968 struct radv_pipeline * compute_pipeline;
969 struct radv_pipeline * emitted_compute_pipeline;
970 struct radv_framebuffer * framebuffer;
971 struct radv_render_pass * pass;
972 const struct radv_subpass * subpass;
973 struct radv_dynamic_state dynamic;
974 struct radv_attachment_state * attachments;
975 VkRect2D render_area;
976
977 /* Index buffer */
978 struct radv_buffer *index_buffer;
979 uint64_t index_offset;
980 uint32_t index_type;
981 uint32_t max_index_count;
982 uint64_t index_va;
983 int32_t last_index_type;
984
985 int32_t last_primitive_reset_en;
986 uint32_t last_primitive_reset_index;
987 enum radv_cmd_flush_bits flush_bits;
988 unsigned active_occlusion_queries;
989 bool perfect_occlusion_queries_enabled;
990 unsigned active_pipeline_queries;
991 float offset_scale;
992 uint32_t trace_id;
993 uint32_t last_ia_multi_vgt_param;
994
995 uint32_t last_num_instances;
996 uint32_t last_first_instance;
997 uint32_t last_vertex_offset;
998
999 /* Whether CP DMA is busy/idle. */
1000 bool dma_is_busy;
1001
1002 /* Conditional rendering info. */
1003 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1004 uint64_t predication_va;
1005 };
1006
1007 struct radv_cmd_pool {
1008 VkAllocationCallbacks alloc;
1009 struct list_head cmd_buffers;
1010 struct list_head free_cmd_buffers;
1011 uint32_t queue_family_index;
1012 };
1013
1014 struct radv_cmd_buffer_upload {
1015 uint8_t *map;
1016 unsigned offset;
1017 uint64_t size;
1018 struct radeon_winsys_bo *upload_bo;
1019 struct list_head list;
1020 };
1021
1022 enum radv_cmd_buffer_status {
1023 RADV_CMD_BUFFER_STATUS_INVALID,
1024 RADV_CMD_BUFFER_STATUS_INITIAL,
1025 RADV_CMD_BUFFER_STATUS_RECORDING,
1026 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1027 RADV_CMD_BUFFER_STATUS_PENDING,
1028 };
1029
1030 struct radv_cmd_buffer {
1031 VK_LOADER_DATA _loader_data;
1032
1033 struct radv_device * device;
1034
1035 struct radv_cmd_pool * pool;
1036 struct list_head pool_link;
1037
1038 VkCommandBufferUsageFlags usage_flags;
1039 VkCommandBufferLevel level;
1040 enum radv_cmd_buffer_status status;
1041 struct radeon_cmdbuf *cs;
1042 struct radv_cmd_state state;
1043 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1044 uint32_t queue_family_index;
1045
1046 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1047 VkShaderStageFlags push_constant_stages;
1048 struct radv_descriptor_set meta_push_descriptors;
1049
1050 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1051
1052 struct radv_cmd_buffer_upload upload;
1053
1054 uint32_t scratch_size_needed;
1055 uint32_t compute_scratch_size_needed;
1056 uint32_t esgs_ring_size_needed;
1057 uint32_t gsvs_ring_size_needed;
1058 bool tess_rings_needed;
1059 bool sample_positions_needed;
1060
1061 VkResult record_result;
1062
1063 uint32_t gfx9_fence_offset;
1064 struct radeon_winsys_bo *gfx9_fence_bo;
1065 uint32_t gfx9_fence_idx;
1066 uint64_t gfx9_eop_bug_va;
1067
1068 /**
1069 * Whether a query pool has been resetted and we have to flush caches.
1070 */
1071 bool pending_reset_query;
1072 };
1073
1074 struct radv_image;
1075
1076 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1077
1078 void si_emit_graphics(struct radv_physical_device *physical_device,
1079 struct radeon_cmdbuf *cs);
1080 void si_emit_compute(struct radv_physical_device *physical_device,
1081 struct radeon_cmdbuf *cs);
1082
1083 void cik_create_gfx_config(struct radv_device *device);
1084
1085 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1086 int count, const VkViewport *viewports);
1087 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1088 int count, const VkRect2D *scissors,
1089 const VkViewport *viewports, bool can_use_guardband);
1090 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1091 bool instanced_draw, bool indirect_draw,
1092 uint32_t draw_vertex_count);
1093 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1094 enum chip_class chip_class,
1095 bool is_mec,
1096 unsigned event, unsigned event_flags,
1097 unsigned data_sel,
1098 uint64_t va,
1099 uint32_t old_fence,
1100 uint32_t new_fence,
1101 uint64_t gfx9_eop_bug_va);
1102
1103 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1104 uint64_t va, uint32_t ref,
1105 uint32_t mask);
1106 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1107 enum chip_class chip_class,
1108 uint32_t *fence_ptr, uint64_t va,
1109 bool is_mec,
1110 enum radv_cmd_flush_bits flush_bits,
1111 uint64_t gfx9_eop_bug_va);
1112 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1113 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1114 bool inverted, uint64_t va);
1115 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1116 uint64_t src_va, uint64_t dest_va,
1117 uint64_t size);
1118 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1119 unsigned size);
1120 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1121 uint64_t size, unsigned value);
1122 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1123
1124 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1125 bool
1126 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1127 unsigned size,
1128 unsigned alignment,
1129 unsigned *out_offset,
1130 void **ptr);
1131 void
1132 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1133 const struct radv_subpass *subpass,
1134 bool transitions);
1135 bool
1136 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1137 unsigned size, unsigned alignmnet,
1138 const void *data, unsigned *out_offset);
1139
1140 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1141 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1142 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1143 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1144 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1145 unsigned radv_cayman_get_maxdist(int log_samples);
1146 void radv_device_init_msaa(struct radv_device *device);
1147
1148 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1149 struct radv_image *image,
1150 VkClearDepthStencilValue ds_clear_value,
1151 VkImageAspectFlags aspects);
1152
1153 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1154 struct radv_image *image,
1155 int cb_idx,
1156 uint32_t color_values[2]);
1157
1158 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1159 struct radv_image *image,
1160 bool value);
1161 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1162 struct radeon_winsys_bo *bo,
1163 uint64_t offset, uint64_t size, uint32_t value);
1164 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1165 bool radv_get_memory_fd(struct radv_device *device,
1166 struct radv_device_memory *memory,
1167 int *pFD);
1168
1169 static inline void
1170 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1171 unsigned sh_offset, unsigned pointer_count,
1172 bool use_32bit_pointers)
1173 {
1174 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1175 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1176 }
1177
1178 static inline void
1179 radv_emit_shader_pointer_body(struct radv_device *device,
1180 struct radeon_cmdbuf *cs,
1181 uint64_t va, bool use_32bit_pointers)
1182 {
1183 radeon_emit(cs, va);
1184
1185 if (use_32bit_pointers) {
1186 assert(va == 0 ||
1187 (va >> 32) == device->physical_device->rad_info.address32_hi);
1188 } else {
1189 radeon_emit(cs, va >> 32);
1190 }
1191 }
1192
1193 static inline void
1194 radv_emit_shader_pointer(struct radv_device *device,
1195 struct radeon_cmdbuf *cs,
1196 uint32_t sh_offset, uint64_t va, bool global)
1197 {
1198 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1199
1200 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1201 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1202 }
1203
1204 static inline struct radv_descriptor_state *
1205 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1206 VkPipelineBindPoint bind_point)
1207 {
1208 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1209 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1210 return &cmd_buffer->descriptors[bind_point];
1211 }
1212
1213 /*
1214 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1215 *
1216 * Limitations: Can't call normal dispatch functions without binding or rebinding
1217 * the compute pipeline.
1218 */
1219 void radv_unaligned_dispatch(
1220 struct radv_cmd_buffer *cmd_buffer,
1221 uint32_t x,
1222 uint32_t y,
1223 uint32_t z);
1224
1225 struct radv_event {
1226 struct radeon_winsys_bo *bo;
1227 uint64_t *map;
1228 };
1229
1230 struct radv_shader_module;
1231
1232 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1233 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1234 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1235 void
1236 radv_hash_shaders(unsigned char *hash,
1237 const VkPipelineShaderStageCreateInfo **stages,
1238 const struct radv_pipeline_layout *layout,
1239 const struct radv_pipeline_key *key,
1240 uint32_t flags);
1241
1242 static inline gl_shader_stage
1243 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1244 {
1245 assert(__builtin_popcount(vk_stage) == 1);
1246 return ffs(vk_stage) - 1;
1247 }
1248
1249 static inline VkShaderStageFlagBits
1250 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1251 {
1252 return (1 << mesa_stage);
1253 }
1254
1255 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1256
1257 #define radv_foreach_stage(stage, stage_bits) \
1258 for (gl_shader_stage stage, \
1259 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1260 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1261 __tmp &= ~(1 << (stage)))
1262
1263 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1264 unsigned radv_format_meta_fs_key(VkFormat format);
1265
1266 struct radv_multisample_state {
1267 uint32_t db_eqaa;
1268 uint32_t pa_sc_line_cntl;
1269 uint32_t pa_sc_mode_cntl_0;
1270 uint32_t pa_sc_mode_cntl_1;
1271 uint32_t pa_sc_aa_config;
1272 uint32_t pa_sc_aa_mask[2];
1273 unsigned num_samples;
1274 };
1275
1276 struct radv_prim_vertex_count {
1277 uint8_t min;
1278 uint8_t incr;
1279 };
1280
1281 struct radv_vertex_elements_info {
1282 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1283 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1284 uint32_t binding[MAX_VERTEX_ATTRIBS];
1285 uint32_t offset[MAX_VERTEX_ATTRIBS];
1286 uint32_t count;
1287 };
1288
1289 struct radv_ia_multi_vgt_param_helpers {
1290 uint32_t base;
1291 bool partial_es_wave;
1292 uint8_t primgroup_size;
1293 bool wd_switch_on_eop;
1294 bool ia_switch_on_eoi;
1295 bool partial_vs_wave;
1296 };
1297
1298 #define SI_GS_PER_ES 128
1299
1300 struct radv_pipeline {
1301 struct radv_device * device;
1302 struct radv_dynamic_state dynamic_state;
1303
1304 struct radv_pipeline_layout * layout;
1305
1306 bool need_indirect_descriptor_sets;
1307 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1308 struct radv_shader_variant *gs_copy_shader;
1309 VkShaderStageFlags active_stages;
1310
1311 struct radeon_cmdbuf cs;
1312
1313 struct radv_vertex_elements_info vertex_elements;
1314
1315 uint32_t binding_stride[MAX_VBS];
1316
1317 uint32_t user_data_0[MESA_SHADER_STAGES];
1318 union {
1319 struct {
1320 struct radv_multisample_state ms;
1321 uint32_t spi_baryc_cntl;
1322 bool prim_restart_enable;
1323 unsigned esgs_ring_size;
1324 unsigned gsvs_ring_size;
1325 uint32_t vtx_base_sgpr;
1326 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1327 uint8_t vtx_emit_num;
1328 struct radv_prim_vertex_count prim_vertex_count;
1329 bool can_use_guardband;
1330 uint32_t needed_dynamic_state;
1331 bool disable_out_of_order_rast_for_occlusion;
1332
1333 /* Used for rbplus */
1334 uint32_t col_format;
1335 uint32_t cb_target_mask;
1336 } graphics;
1337 };
1338
1339 unsigned max_waves;
1340 unsigned scratch_bytes_per_wave;
1341 };
1342
1343 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1344 {
1345 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1346 }
1347
1348 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1349 {
1350 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1351 }
1352
1353 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1354 gl_shader_stage stage,
1355 int idx);
1356
1357 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1358 gl_shader_stage stage);
1359
1360 struct radv_graphics_pipeline_create_info {
1361 bool use_rectlist;
1362 bool db_depth_clear;
1363 bool db_stencil_clear;
1364 bool db_depth_disable_expclear;
1365 bool db_stencil_disable_expclear;
1366 bool db_flush_depth_inplace;
1367 bool db_flush_stencil_inplace;
1368 bool db_resummarize;
1369 uint32_t custom_blend_mode;
1370 };
1371
1372 VkResult
1373 radv_graphics_pipeline_create(VkDevice device,
1374 VkPipelineCache cache,
1375 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1376 const struct radv_graphics_pipeline_create_info *extra,
1377 const VkAllocationCallbacks *alloc,
1378 VkPipeline *pPipeline);
1379
1380 struct vk_format_description;
1381 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1382 int first_non_void);
1383 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1384 int first_non_void);
1385 uint32_t radv_translate_colorformat(VkFormat format);
1386 uint32_t radv_translate_color_numformat(VkFormat format,
1387 const struct vk_format_description *desc,
1388 int first_non_void);
1389 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1390 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1391 uint32_t radv_translate_dbformat(VkFormat format);
1392 uint32_t radv_translate_tex_dataformat(VkFormat format,
1393 const struct vk_format_description *desc,
1394 int first_non_void);
1395 uint32_t radv_translate_tex_numformat(VkFormat format,
1396 const struct vk_format_description *desc,
1397 int first_non_void);
1398 bool radv_format_pack_clear_color(VkFormat format,
1399 uint32_t clear_vals[2],
1400 VkClearColorValue *value);
1401 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1402 bool radv_dcc_formats_compatible(VkFormat format1,
1403 VkFormat format2);
1404
1405 struct radv_fmask_info {
1406 uint64_t offset;
1407 uint64_t size;
1408 unsigned alignment;
1409 unsigned pitch_in_pixels;
1410 unsigned bank_height;
1411 unsigned slice_tile_max;
1412 unsigned tile_mode_index;
1413 unsigned tile_swizzle;
1414 };
1415
1416 struct radv_cmask_info {
1417 uint64_t offset;
1418 uint64_t size;
1419 unsigned alignment;
1420 unsigned slice_tile_max;
1421 };
1422
1423 struct radv_image {
1424 VkImageType type;
1425 /* The original VkFormat provided by the client. This may not match any
1426 * of the actual surface formats.
1427 */
1428 VkFormat vk_format;
1429 VkImageAspectFlags aspects;
1430 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1431 struct ac_surf_info info;
1432 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1433 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1434
1435 VkDeviceSize size;
1436 uint32_t alignment;
1437
1438 unsigned queue_family_mask;
1439 bool exclusive;
1440 bool shareable;
1441
1442 /* Set when bound */
1443 struct radeon_winsys_bo *bo;
1444 VkDeviceSize offset;
1445 uint64_t dcc_offset;
1446 uint64_t htile_offset;
1447 bool tc_compatible_htile;
1448 struct radeon_surf surface;
1449
1450 struct radv_fmask_info fmask;
1451 struct radv_cmask_info cmask;
1452 uint64_t clear_value_offset;
1453 uint64_t dcc_pred_offset;
1454
1455 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1456 VkDeviceMemory owned_memory;
1457 };
1458
1459 /* Whether the image has a htile that is known consistent with the contents of
1460 * the image. */
1461 bool radv_layout_has_htile(const struct radv_image *image,
1462 VkImageLayout layout,
1463 unsigned queue_mask);
1464
1465 /* Whether the image has a htile that is known consistent with the contents of
1466 * the image and is allowed to be in compressed form.
1467 *
1468 * If this is false reads that don't use the htile should be able to return
1469 * correct results.
1470 */
1471 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1472 VkImageLayout layout,
1473 unsigned queue_mask);
1474
1475 bool radv_layout_can_fast_clear(const struct radv_image *image,
1476 VkImageLayout layout,
1477 unsigned queue_mask);
1478
1479 bool radv_layout_dcc_compressed(const struct radv_image *image,
1480 VkImageLayout layout,
1481 unsigned queue_mask);
1482
1483 /**
1484 * Return whether the image has CMASK metadata for color surfaces.
1485 */
1486 static inline bool
1487 radv_image_has_cmask(const struct radv_image *image)
1488 {
1489 return image->cmask.size;
1490 }
1491
1492 /**
1493 * Return whether the image has FMASK metadata for color surfaces.
1494 */
1495 static inline bool
1496 radv_image_has_fmask(const struct radv_image *image)
1497 {
1498 return image->fmask.size;
1499 }
1500
1501 /**
1502 * Return whether the image has DCC metadata for color surfaces.
1503 */
1504 static inline bool
1505 radv_image_has_dcc(const struct radv_image *image)
1506 {
1507 return image->surface.dcc_size;
1508 }
1509
1510 /**
1511 * Return whether DCC metadata is enabled for a level.
1512 */
1513 static inline bool
1514 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1515 {
1516 return radv_image_has_dcc(image) &&
1517 level < image->surface.num_dcc_levels;
1518 }
1519
1520 /**
1521 * Return whether the image has CB metadata.
1522 */
1523 static inline bool
1524 radv_image_has_CB_metadata(const struct radv_image *image)
1525 {
1526 return radv_image_has_cmask(image) ||
1527 radv_image_has_fmask(image) ||
1528 radv_image_has_dcc(image);
1529 }
1530
1531 /**
1532 * Return whether the image has HTILE metadata for depth surfaces.
1533 */
1534 static inline bool
1535 radv_image_has_htile(const struct radv_image *image)
1536 {
1537 return image->surface.htile_size;
1538 }
1539
1540 /**
1541 * Return whether HTILE metadata is enabled for a level.
1542 */
1543 static inline bool
1544 radv_htile_enabled(const struct radv_image *image, unsigned level)
1545 {
1546 return radv_image_has_htile(image) && level == 0;
1547 }
1548
1549 /**
1550 * Return whether the image is TC-compatible HTILE.
1551 */
1552 static inline bool
1553 radv_image_is_tc_compat_htile(const struct radv_image *image)
1554 {
1555 return radv_image_has_htile(image) && image->tc_compatible_htile;
1556 }
1557
1558 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1559
1560 static inline uint32_t
1561 radv_get_layerCount(const struct radv_image *image,
1562 const VkImageSubresourceRange *range)
1563 {
1564 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1565 image->info.array_size - range->baseArrayLayer : range->layerCount;
1566 }
1567
1568 static inline uint32_t
1569 radv_get_levelCount(const struct radv_image *image,
1570 const VkImageSubresourceRange *range)
1571 {
1572 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1573 image->info.levels - range->baseMipLevel : range->levelCount;
1574 }
1575
1576 struct radeon_bo_metadata;
1577 void
1578 radv_init_metadata(struct radv_device *device,
1579 struct radv_image *image,
1580 struct radeon_bo_metadata *metadata);
1581
1582 struct radv_image_view {
1583 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1584 struct radeon_winsys_bo *bo;
1585
1586 VkImageViewType type;
1587 VkImageAspectFlags aspect_mask;
1588 VkFormat vk_format;
1589 uint32_t base_layer;
1590 uint32_t layer_count;
1591 uint32_t base_mip;
1592 uint32_t level_count;
1593 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1594
1595 uint32_t descriptor[16];
1596
1597 /* Descriptor for use as a storage image as opposed to a sampled image.
1598 * This has a few differences for cube maps (e.g. type).
1599 */
1600 uint32_t storage_descriptor[16];
1601 };
1602
1603 struct radv_image_create_info {
1604 const VkImageCreateInfo *vk_info;
1605 bool scanout;
1606 bool no_metadata_planes;
1607 };
1608
1609 VkResult radv_image_create(VkDevice _device,
1610 const struct radv_image_create_info *info,
1611 const VkAllocationCallbacks* alloc,
1612 VkImage *pImage);
1613
1614 VkResult
1615 radv_image_from_gralloc(VkDevice device_h,
1616 const VkImageCreateInfo *base_info,
1617 const VkNativeBufferANDROID *gralloc_info,
1618 const VkAllocationCallbacks *alloc,
1619 VkImage *out_image_h);
1620
1621 void radv_image_view_init(struct radv_image_view *view,
1622 struct radv_device *device,
1623 const VkImageViewCreateInfo* pCreateInfo);
1624
1625 struct radv_buffer_view {
1626 struct radeon_winsys_bo *bo;
1627 VkFormat vk_format;
1628 uint64_t range; /**< VkBufferViewCreateInfo::range */
1629 uint32_t state[4];
1630 };
1631 void radv_buffer_view_init(struct radv_buffer_view *view,
1632 struct radv_device *device,
1633 const VkBufferViewCreateInfo* pCreateInfo);
1634
1635 static inline struct VkExtent3D
1636 radv_sanitize_image_extent(const VkImageType imageType,
1637 const struct VkExtent3D imageExtent)
1638 {
1639 switch (imageType) {
1640 case VK_IMAGE_TYPE_1D:
1641 return (VkExtent3D) { imageExtent.width, 1, 1 };
1642 case VK_IMAGE_TYPE_2D:
1643 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1644 case VK_IMAGE_TYPE_3D:
1645 return imageExtent;
1646 default:
1647 unreachable("invalid image type");
1648 }
1649 }
1650
1651 static inline struct VkOffset3D
1652 radv_sanitize_image_offset(const VkImageType imageType,
1653 const struct VkOffset3D imageOffset)
1654 {
1655 switch (imageType) {
1656 case VK_IMAGE_TYPE_1D:
1657 return (VkOffset3D) { imageOffset.x, 0, 0 };
1658 case VK_IMAGE_TYPE_2D:
1659 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1660 case VK_IMAGE_TYPE_3D:
1661 return imageOffset;
1662 default:
1663 unreachable("invalid image type");
1664 }
1665 }
1666
1667 static inline bool
1668 radv_image_extent_compare(const struct radv_image *image,
1669 const VkExtent3D *extent)
1670 {
1671 if (extent->width != image->info.width ||
1672 extent->height != image->info.height ||
1673 extent->depth != image->info.depth)
1674 return false;
1675 return true;
1676 }
1677
1678 struct radv_sampler {
1679 uint32_t state[4];
1680 };
1681
1682 struct radv_color_buffer_info {
1683 uint64_t cb_color_base;
1684 uint64_t cb_color_cmask;
1685 uint64_t cb_color_fmask;
1686 uint64_t cb_dcc_base;
1687 uint32_t cb_color_pitch;
1688 uint32_t cb_color_slice;
1689 uint32_t cb_color_view;
1690 uint32_t cb_color_info;
1691 uint32_t cb_color_attrib;
1692 uint32_t cb_color_attrib2;
1693 uint32_t cb_dcc_control;
1694 uint32_t cb_color_cmask_slice;
1695 uint32_t cb_color_fmask_slice;
1696 };
1697
1698 struct radv_ds_buffer_info {
1699 uint64_t db_z_read_base;
1700 uint64_t db_stencil_read_base;
1701 uint64_t db_z_write_base;
1702 uint64_t db_stencil_write_base;
1703 uint64_t db_htile_data_base;
1704 uint32_t db_depth_info;
1705 uint32_t db_z_info;
1706 uint32_t db_stencil_info;
1707 uint32_t db_depth_view;
1708 uint32_t db_depth_size;
1709 uint32_t db_depth_slice;
1710 uint32_t db_htile_surface;
1711 uint32_t pa_su_poly_offset_db_fmt_cntl;
1712 uint32_t db_z_info2;
1713 uint32_t db_stencil_info2;
1714 float offset_scale;
1715 };
1716
1717 struct radv_attachment_info {
1718 union {
1719 struct radv_color_buffer_info cb;
1720 struct radv_ds_buffer_info ds;
1721 };
1722 struct radv_image_view *attachment;
1723 };
1724
1725 struct radv_framebuffer {
1726 uint32_t width;
1727 uint32_t height;
1728 uint32_t layers;
1729
1730 uint32_t attachment_count;
1731 struct radv_attachment_info attachments[0];
1732 };
1733
1734 struct radv_subpass_barrier {
1735 VkPipelineStageFlags src_stage_mask;
1736 VkAccessFlags src_access_mask;
1737 VkAccessFlags dst_access_mask;
1738 };
1739
1740 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1741 const struct radv_subpass_barrier *barrier);
1742
1743 struct radv_subpass_attachment {
1744 uint32_t attachment;
1745 VkImageLayout layout;
1746 };
1747
1748 struct radv_subpass {
1749 uint32_t input_count;
1750 uint32_t color_count;
1751 struct radv_subpass_attachment * input_attachments;
1752 struct radv_subpass_attachment * color_attachments;
1753 struct radv_subpass_attachment * resolve_attachments;
1754 struct radv_subpass_attachment depth_stencil_attachment;
1755
1756 /** Subpass has at least one resolve attachment */
1757 bool has_resolve;
1758
1759 struct radv_subpass_barrier start_barrier;
1760
1761 uint32_t view_mask;
1762 VkSampleCountFlagBits max_sample_count;
1763 };
1764
1765 struct radv_render_pass_attachment {
1766 VkFormat format;
1767 uint32_t samples;
1768 VkAttachmentLoadOp load_op;
1769 VkAttachmentLoadOp stencil_load_op;
1770 VkImageLayout initial_layout;
1771 VkImageLayout final_layout;
1772 uint32_t view_mask;
1773 };
1774
1775 struct radv_render_pass {
1776 uint32_t attachment_count;
1777 uint32_t subpass_count;
1778 struct radv_subpass_attachment * subpass_attachments;
1779 struct radv_render_pass_attachment * attachments;
1780 struct radv_subpass_barrier end_barrier;
1781 struct radv_subpass subpasses[0];
1782 };
1783
1784 VkResult radv_device_init_meta(struct radv_device *device);
1785 void radv_device_finish_meta(struct radv_device *device);
1786
1787 struct radv_query_pool {
1788 struct radeon_winsys_bo *bo;
1789 uint32_t stride;
1790 uint32_t availability_offset;
1791 uint64_t size;
1792 char *ptr;
1793 VkQueryType type;
1794 uint32_t pipeline_stats_mask;
1795 };
1796
1797 struct radv_semaphore {
1798 /* use a winsys sem for non-exportable */
1799 struct radeon_winsys_sem *sem;
1800 uint32_t syncobj;
1801 uint32_t temp_syncobj;
1802 };
1803
1804 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1805 VkPipelineBindPoint bind_point,
1806 struct radv_descriptor_set *set,
1807 unsigned idx);
1808
1809 void
1810 radv_update_descriptor_sets(struct radv_device *device,
1811 struct radv_cmd_buffer *cmd_buffer,
1812 VkDescriptorSet overrideSet,
1813 uint32_t descriptorWriteCount,
1814 const VkWriteDescriptorSet *pDescriptorWrites,
1815 uint32_t descriptorCopyCount,
1816 const VkCopyDescriptorSet *pDescriptorCopies);
1817
1818 void
1819 radv_update_descriptor_set_with_template(struct radv_device *device,
1820 struct radv_cmd_buffer *cmd_buffer,
1821 struct radv_descriptor_set *set,
1822 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1823 const void *pData);
1824
1825 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1826 VkPipelineBindPoint pipelineBindPoint,
1827 VkPipelineLayout _layout,
1828 uint32_t set,
1829 uint32_t descriptorWriteCount,
1830 const VkWriteDescriptorSet *pDescriptorWrites);
1831
1832 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1833 struct radv_image *image, uint32_t value);
1834
1835 struct radv_fence {
1836 struct radeon_winsys_fence *fence;
1837 struct wsi_fence *fence_wsi;
1838 bool submitted;
1839 bool signalled;
1840
1841 uint32_t syncobj;
1842 uint32_t temp_syncobj;
1843 };
1844
1845 /* radv_nir_to_llvm.c */
1846 struct radv_shader_variant_info;
1847 struct radv_nir_compiler_options;
1848
1849 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1850 struct nir_shader *geom_shader,
1851 struct ac_shader_binary *binary,
1852 struct ac_shader_config *config,
1853 struct radv_shader_variant_info *shader_info,
1854 const struct radv_nir_compiler_options *option);
1855
1856 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1857 struct ac_shader_binary *binary,
1858 struct ac_shader_config *config,
1859 struct radv_shader_variant_info *shader_info,
1860 struct nir_shader *const *nir,
1861 int nir_count,
1862 const struct radv_nir_compiler_options *options);
1863
1864 /* radv_shader_info.h */
1865 struct radv_shader_info;
1866
1867 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1868 const struct radv_nir_compiler_options *options,
1869 struct radv_shader_info *info);
1870
1871 struct radeon_winsys_sem;
1872
1873 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1874 \
1875 static inline struct __radv_type * \
1876 __radv_type ## _from_handle(__VkType _handle) \
1877 { \
1878 return (struct __radv_type *) _handle; \
1879 } \
1880 \
1881 static inline __VkType \
1882 __radv_type ## _to_handle(struct __radv_type *_obj) \
1883 { \
1884 return (__VkType) _obj; \
1885 }
1886
1887 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1888 \
1889 static inline struct __radv_type * \
1890 __radv_type ## _from_handle(__VkType _handle) \
1891 { \
1892 return (struct __radv_type *)(uintptr_t) _handle; \
1893 } \
1894 \
1895 static inline __VkType \
1896 __radv_type ## _to_handle(struct __radv_type *_obj) \
1897 { \
1898 return (__VkType)(uintptr_t) _obj; \
1899 }
1900
1901 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1902 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1903
1904 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1905 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1906 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1907 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1908 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1909
1910 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1911 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1912 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1913 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1914 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1915 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1916 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1917 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1918 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1919 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1920 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1921 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1922 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1923 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1924 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1925 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1926 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1927 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1928 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1929 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1930 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1931
1932 #endif /* RADV_PRIVATE_H */