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radv/gfx10: implement radv_initialise_ds_surface()
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
65 #include "radv_cs.h"
66
67 #include <llvm-c/TargetMachine.h>
68
69 /* Pre-declarations needed for WSI entrypoints */
70 struct wl_surface;
71 struct wl_display;
72 typedef struct xcb_connection_t xcb_connection_t;
73 typedef uint32_t xcb_visualid_t;
74 typedef uint32_t xcb_window_t;
75
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 struct gfx10_format {
87 unsigned img_format:9;
88
89 /* Various formats are only supported with workarounds for vertex fetch,
90 * and some 32_32_32 formats are supported natively, but only for buffers
91 * (possibly with some image support, actually, but no filtering). */
92 bool buffers_only:1;
93 };
94
95 #include "gfx10_format_table.h"
96
97 #define ATI_VENDOR_ID 0x1002
98
99 #define MAX_VBS 32
100 #define MAX_VERTEX_ATTRIBS 32
101 #define MAX_RTS 8
102 #define MAX_VIEWPORTS 16
103 #define MAX_SCISSORS 16
104 #define MAX_DISCARD_RECTANGLES 4
105 #define MAX_SAMPLE_LOCATIONS 32
106 #define MAX_PUSH_CONSTANTS_SIZE 128
107 #define MAX_PUSH_DESCRIPTORS 32
108 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
109 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
110 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
111 #define MAX_SAMPLES_LOG2 4
112 #define NUM_META_FS_KEYS 12
113 #define RADV_MAX_DRM_DEVICES 8
114 #define MAX_VIEWS 8
115 #define MAX_SO_STREAMS 4
116 #define MAX_SO_BUFFERS 4
117 #define MAX_SO_OUTPUTS 64
118 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
119 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
120
121 #define NUM_DEPTH_CLEAR_PIPELINES 3
122
123 /*
124 * This is the point we switch from using CP to compute shader
125 * for certain buffer operations.
126 */
127 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
128
129 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
130
131 enum radv_mem_heap {
132 RADV_MEM_HEAP_VRAM,
133 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
134 RADV_MEM_HEAP_GTT,
135 RADV_MEM_HEAP_COUNT
136 };
137
138 enum radv_mem_type {
139 RADV_MEM_TYPE_VRAM,
140 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
141 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
142 RADV_MEM_TYPE_GTT_CACHED,
143 RADV_MEM_TYPE_COUNT
144 };
145
146 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
147
148 static inline uint32_t
149 align_u32(uint32_t v, uint32_t a)
150 {
151 assert(a != 0 && a == (a & -a));
152 return (v + a - 1) & ~(a - 1);
153 }
154
155 static inline uint32_t
156 align_u32_npot(uint32_t v, uint32_t a)
157 {
158 return (v + a - 1) / a * a;
159 }
160
161 static inline uint64_t
162 align_u64(uint64_t v, uint64_t a)
163 {
164 assert(a != 0 && a == (a & -a));
165 return (v + a - 1) & ~(a - 1);
166 }
167
168 static inline int32_t
169 align_i32(int32_t v, int32_t a)
170 {
171 assert(a != 0 && a == (a & -a));
172 return (v + a - 1) & ~(a - 1);
173 }
174
175 /** Alignment must be a power of 2. */
176 static inline bool
177 radv_is_aligned(uintmax_t n, uintmax_t a)
178 {
179 assert(a == (a & -a));
180 return (n & (a - 1)) == 0;
181 }
182
183 static inline uint32_t
184 round_up_u32(uint32_t v, uint32_t a)
185 {
186 return (v + a - 1) / a;
187 }
188
189 static inline uint64_t
190 round_up_u64(uint64_t v, uint64_t a)
191 {
192 return (v + a - 1) / a;
193 }
194
195 static inline uint32_t
196 radv_minify(uint32_t n, uint32_t levels)
197 {
198 if (unlikely(n == 0))
199 return 0;
200 else
201 return MAX2(n >> levels, 1);
202 }
203 static inline float
204 radv_clamp_f(float f, float min, float max)
205 {
206 assert(min < max);
207
208 if (f > max)
209 return max;
210 else if (f < min)
211 return min;
212 else
213 return f;
214 }
215
216 static inline bool
217 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
218 {
219 if (*inout_mask & clear_mask) {
220 *inout_mask &= ~clear_mask;
221 return true;
222 } else {
223 return false;
224 }
225 }
226
227 #define for_each_bit(b, dword) \
228 for (uint32_t __dword = (dword); \
229 (b) = __builtin_ffs(__dword) - 1, __dword; \
230 __dword &= ~(1 << (b)))
231
232 #define typed_memcpy(dest, src, count) ({ \
233 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
234 memcpy((dest), (src), (count) * sizeof(*(src))); \
235 })
236
237 /* Whenever we generate an error, pass it through this function. Useful for
238 * debugging, where we can break on it. Only call at error site, not when
239 * propagating errors. Might be useful to plug in a stack trace here.
240 */
241
242 struct radv_instance;
243
244 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
245
246 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
247 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
248
249 void __radv_finishme(const char *file, int line, const char *format, ...)
250 radv_printflike(3, 4);
251 void radv_loge(const char *format, ...) radv_printflike(1, 2);
252 void radv_loge_v(const char *format, va_list va);
253 void radv_logi(const char *format, ...) radv_printflike(1, 2);
254 void radv_logi_v(const char *format, va_list va);
255
256 /**
257 * Print a FINISHME message, including its source location.
258 */
259 #define radv_finishme(format, ...) \
260 do { \
261 static bool reported = false; \
262 if (!reported) { \
263 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
264 reported = true; \
265 } \
266 } while (0)
267
268 /* A non-fatal assert. Useful for debugging. */
269 #ifdef DEBUG
270 #define radv_assert(x) ({ \
271 if (unlikely(!(x))) \
272 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
273 })
274 #else
275 #define radv_assert(x)
276 #endif
277
278 #define stub_return(v) \
279 do { \
280 radv_finishme("stub %s", __func__); \
281 return (v); \
282 } while (0)
283
284 #define stub() \
285 do { \
286 radv_finishme("stub %s", __func__); \
287 return; \
288 } while (0)
289
290 void *radv_lookup_entrypoint_unchecked(const char *name);
291 void *radv_lookup_entrypoint_checked(const char *name,
292 uint32_t core_version,
293 const struct radv_instance_extension_table *instance,
294 const struct radv_device_extension_table *device);
295 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
296 uint32_t core_version,
297 const struct radv_instance_extension_table *instance);
298
299 struct radv_physical_device {
300 VK_LOADER_DATA _loader_data;
301
302 struct radv_instance * instance;
303
304 struct radeon_winsys *ws;
305 struct radeon_info rad_info;
306 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
307 uint8_t driver_uuid[VK_UUID_SIZE];
308 uint8_t device_uuid[VK_UUID_SIZE];
309 uint8_t cache_uuid[VK_UUID_SIZE];
310
311 int local_fd;
312 int master_fd;
313 struct wsi_device wsi_device;
314
315 bool has_rbplus; /* if RB+ register exist */
316 bool rbplus_allowed; /* if RB+ is allowed */
317 bool has_clear_state;
318 bool cpdma_prefetch_writes_memory;
319 bool has_scissor_bug;
320
321 bool has_out_of_order_rast;
322 bool out_of_order_rast_allowed;
323
324 /* Whether DCC should be enabled for MSAA textures. */
325 bool dcc_msaa_allowed;
326
327 /* Whether LOAD_CONTEXT_REG packets are supported. */
328 bool has_load_ctx_reg_pkt;
329
330 /* Whether to enable the AMD_shader_ballot extension */
331 bool use_shader_ballot;
332
333 /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
334 bool has_dcc_constant_encode;
335
336 /* This is the drivers on-disk cache used as a fallback as opposed to
337 * the pipeline cache defined by apps.
338 */
339 struct disk_cache * disk_cache;
340
341 VkPhysicalDeviceMemoryProperties memory_properties;
342 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
343
344 drmPciBusInfo bus_info;
345
346 struct radv_device_extension_table supported_extensions;
347 };
348
349 struct radv_instance {
350 VK_LOADER_DATA _loader_data;
351
352 VkAllocationCallbacks alloc;
353
354 uint32_t apiVersion;
355 int physicalDeviceCount;
356 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
357
358 uint64_t debug_flags;
359 uint64_t perftest_flags;
360
361 struct vk_debug_report_instance debug_report_callbacks;
362
363 struct radv_instance_extension_table enabled_extensions;
364
365 struct driOptionCache dri_options;
366 struct driOptionCache available_dri_options;
367 };
368
369 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
370 void radv_finish_wsi(struct radv_physical_device *physical_device);
371
372 bool radv_instance_extension_supported(const char *name);
373 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
374 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
375 const char *name);
376
377 struct cache_entry;
378
379 struct radv_pipeline_cache {
380 struct radv_device * device;
381 pthread_mutex_t mutex;
382
383 uint32_t total_size;
384 uint32_t table_size;
385 uint32_t kernel_count;
386 struct cache_entry ** hash_table;
387 bool modified;
388
389 VkAllocationCallbacks alloc;
390 };
391
392 struct radv_pipeline_key {
393 uint32_t instance_rate_inputs;
394 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
395 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
396 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
397 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
398 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
399 uint64_t vertex_alpha_adjust;
400 uint32_t vertex_post_shuffle;
401 unsigned tess_input_vertices;
402 uint32_t col_format;
403 uint32_t is_int8;
404 uint32_t is_int10;
405 uint8_t log2_ps_iter_samples;
406 uint8_t num_samples;
407 uint32_t has_multiview_view_index : 1;
408 uint32_t optimisations_disabled : 1;
409 };
410
411 struct radv_shader_binary;
412 struct radv_shader_variant;
413
414 void
415 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
416 struct radv_device *device);
417 void
418 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
419 bool
420 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
421 const void *data, size_t size);
422
423 bool
424 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
425 struct radv_pipeline_cache *cache,
426 const unsigned char *sha1,
427 struct radv_shader_variant **variants,
428 bool *found_in_application_cache);
429
430 void
431 radv_pipeline_cache_insert_shaders(struct radv_device *device,
432 struct radv_pipeline_cache *cache,
433 const unsigned char *sha1,
434 struct radv_shader_variant **variants,
435 struct radv_shader_binary *const *binaries);
436
437 enum radv_blit_ds_layout {
438 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
439 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
440 RADV_BLIT_DS_LAYOUT_COUNT,
441 };
442
443 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
444 {
445 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
446 }
447
448 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
449 {
450 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
451 }
452
453 enum radv_meta_dst_layout {
454 RADV_META_DST_LAYOUT_GENERAL,
455 RADV_META_DST_LAYOUT_OPTIMAL,
456 RADV_META_DST_LAYOUT_COUNT,
457 };
458
459 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
460 {
461 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
462 }
463
464 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
465 {
466 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
467 }
468
469 struct radv_meta_state {
470 VkAllocationCallbacks alloc;
471
472 struct radv_pipeline_cache cache;
473
474 /*
475 * For on-demand pipeline creation, makes sure that
476 * only one thread tries to build a pipeline at the same time.
477 */
478 mtx_t mtx;
479
480 /**
481 * Use array element `i` for images with `2^i` samples.
482 */
483 struct {
484 VkRenderPass render_pass[NUM_META_FS_KEYS];
485 VkPipeline color_pipelines[NUM_META_FS_KEYS];
486
487 VkRenderPass depthstencil_rp;
488 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
489 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
490 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
491 } clear[1 + MAX_SAMPLES_LOG2];
492
493 VkPipelineLayout clear_color_p_layout;
494 VkPipelineLayout clear_depth_p_layout;
495
496 /* Optimized compute fast HTILE clear for stencil or depth only. */
497 VkPipeline clear_htile_mask_pipeline;
498 VkPipelineLayout clear_htile_mask_p_layout;
499 VkDescriptorSetLayout clear_htile_mask_ds_layout;
500
501 struct {
502 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
503
504 /** Pipeline that blits from a 1D image. */
505 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
506
507 /** Pipeline that blits from a 2D image. */
508 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
509
510 /** Pipeline that blits from a 3D image. */
511 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
512
513 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
514 VkPipeline depth_only_1d_pipeline;
515 VkPipeline depth_only_2d_pipeline;
516 VkPipeline depth_only_3d_pipeline;
517
518 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
519 VkPipeline stencil_only_1d_pipeline;
520 VkPipeline stencil_only_2d_pipeline;
521 VkPipeline stencil_only_3d_pipeline;
522 VkPipelineLayout pipeline_layout;
523 VkDescriptorSetLayout ds_layout;
524 } blit;
525
526 struct {
527 VkPipelineLayout p_layouts[5];
528 VkDescriptorSetLayout ds_layouts[5];
529 VkPipeline pipelines[5][NUM_META_FS_KEYS];
530
531 VkPipeline depth_only_pipeline[5];
532
533 VkPipeline stencil_only_pipeline[5];
534 } blit2d[1 + MAX_SAMPLES_LOG2];
535
536 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
537 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
538 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
539
540 struct {
541 VkPipelineLayout img_p_layout;
542 VkDescriptorSetLayout img_ds_layout;
543 VkPipeline pipeline;
544 VkPipeline pipeline_3d;
545 } itob;
546 struct {
547 VkPipelineLayout img_p_layout;
548 VkDescriptorSetLayout img_ds_layout;
549 VkPipeline pipeline;
550 VkPipeline pipeline_3d;
551 } btoi;
552 struct {
553 VkPipelineLayout img_p_layout;
554 VkDescriptorSetLayout img_ds_layout;
555 VkPipeline pipeline;
556 } btoi_r32g32b32;
557 struct {
558 VkPipelineLayout img_p_layout;
559 VkDescriptorSetLayout img_ds_layout;
560 VkPipeline pipeline;
561 VkPipeline pipeline_3d;
562 } itoi;
563 struct {
564 VkPipelineLayout img_p_layout;
565 VkDescriptorSetLayout img_ds_layout;
566 VkPipeline pipeline;
567 } itoi_r32g32b32;
568 struct {
569 VkPipelineLayout img_p_layout;
570 VkDescriptorSetLayout img_ds_layout;
571 VkPipeline pipeline;
572 VkPipeline pipeline_3d;
573 } cleari;
574 struct {
575 VkPipelineLayout img_p_layout;
576 VkDescriptorSetLayout img_ds_layout;
577 VkPipeline pipeline;
578 } cleari_r32g32b32;
579
580 struct {
581 VkPipelineLayout p_layout;
582 VkPipeline pipeline[NUM_META_FS_KEYS];
583 VkRenderPass pass[NUM_META_FS_KEYS];
584 } resolve;
585
586 struct {
587 VkDescriptorSetLayout ds_layout;
588 VkPipelineLayout p_layout;
589 struct {
590 VkPipeline pipeline;
591 VkPipeline i_pipeline;
592 VkPipeline srgb_pipeline;
593 } rc[MAX_SAMPLES_LOG2];
594
595 VkPipeline depth_zero_pipeline;
596 struct {
597 VkPipeline average_pipeline;
598 VkPipeline max_pipeline;
599 VkPipeline min_pipeline;
600 } depth[MAX_SAMPLES_LOG2];
601
602 VkPipeline stencil_zero_pipeline;
603 struct {
604 VkPipeline max_pipeline;
605 VkPipeline min_pipeline;
606 } stencil[MAX_SAMPLES_LOG2];
607 } resolve_compute;
608
609 struct {
610 VkDescriptorSetLayout ds_layout;
611 VkPipelineLayout p_layout;
612
613 struct {
614 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
615 VkPipeline pipeline[NUM_META_FS_KEYS];
616 } rc[MAX_SAMPLES_LOG2];
617
618 VkRenderPass depth_render_pass;
619 VkPipeline depth_zero_pipeline;
620 struct {
621 VkPipeline average_pipeline;
622 VkPipeline max_pipeline;
623 VkPipeline min_pipeline;
624 } depth[MAX_SAMPLES_LOG2];
625
626 VkRenderPass stencil_render_pass;
627 VkPipeline stencil_zero_pipeline;
628 struct {
629 VkPipeline max_pipeline;
630 VkPipeline min_pipeline;
631 } stencil[MAX_SAMPLES_LOG2];
632 } resolve_fragment;
633
634 struct {
635 VkPipelineLayout p_layout;
636 VkPipeline decompress_pipeline;
637 VkPipeline resummarize_pipeline;
638 VkRenderPass pass;
639 } depth_decomp[1 + MAX_SAMPLES_LOG2];
640
641 struct {
642 VkPipelineLayout p_layout;
643 VkPipeline cmask_eliminate_pipeline;
644 VkPipeline fmask_decompress_pipeline;
645 VkPipeline dcc_decompress_pipeline;
646 VkRenderPass pass;
647
648 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
649 VkPipelineLayout dcc_decompress_compute_p_layout;
650 VkPipeline dcc_decompress_compute_pipeline;
651 } fast_clear_flush;
652
653 struct {
654 VkPipelineLayout fill_p_layout;
655 VkPipelineLayout copy_p_layout;
656 VkDescriptorSetLayout fill_ds_layout;
657 VkDescriptorSetLayout copy_ds_layout;
658 VkPipeline fill_pipeline;
659 VkPipeline copy_pipeline;
660 } buffer;
661
662 struct {
663 VkDescriptorSetLayout ds_layout;
664 VkPipelineLayout p_layout;
665 VkPipeline occlusion_query_pipeline;
666 VkPipeline pipeline_statistics_query_pipeline;
667 VkPipeline tfb_query_pipeline;
668 } query;
669
670 struct {
671 VkDescriptorSetLayout ds_layout;
672 VkPipelineLayout p_layout;
673 VkPipeline pipeline[MAX_SAMPLES_LOG2];
674 } fmask_expand;
675 };
676
677 /* queue types */
678 #define RADV_QUEUE_GENERAL 0
679 #define RADV_QUEUE_COMPUTE 1
680 #define RADV_QUEUE_TRANSFER 2
681
682 #define RADV_MAX_QUEUE_FAMILIES 3
683
684 enum ring_type radv_queue_family_to_ring(int f);
685
686 struct radv_queue {
687 VK_LOADER_DATA _loader_data;
688 struct radv_device * device;
689 struct radeon_winsys_ctx *hw_ctx;
690 enum radeon_ctx_priority priority;
691 uint32_t queue_family_index;
692 int queue_idx;
693 VkDeviceQueueCreateFlags flags;
694
695 uint32_t scratch_size;
696 uint32_t compute_scratch_size;
697 uint32_t esgs_ring_size;
698 uint32_t gsvs_ring_size;
699 bool has_tess_rings;
700 bool has_sample_positions;
701
702 struct radeon_winsys_bo *scratch_bo;
703 struct radeon_winsys_bo *descriptor_bo;
704 struct radeon_winsys_bo *compute_scratch_bo;
705 struct radeon_winsys_bo *esgs_ring_bo;
706 struct radeon_winsys_bo *gsvs_ring_bo;
707 struct radeon_winsys_bo *tess_rings_bo;
708 struct radeon_cmdbuf *initial_preamble_cs;
709 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
710 struct radeon_cmdbuf *continue_preamble_cs;
711 };
712
713 struct radv_bo_list {
714 struct radv_winsys_bo_list list;
715 unsigned capacity;
716 pthread_mutex_t mutex;
717 };
718
719 struct radv_device {
720 VK_LOADER_DATA _loader_data;
721
722 VkAllocationCallbacks alloc;
723
724 struct radv_instance * instance;
725 struct radeon_winsys *ws;
726
727 struct radv_meta_state meta_state;
728
729 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
730 int queue_count[RADV_MAX_QUEUE_FAMILIES];
731 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
732
733 bool always_use_syncobj;
734 bool has_distributed_tess;
735 bool pbb_allowed;
736 bool dfsm_allowed;
737 uint32_t tess_offchip_block_dw_size;
738 uint32_t scratch_waves;
739 uint32_t dispatch_initiator;
740
741 uint32_t gs_table_depth;
742
743 /* MSAA sample locations.
744 * The first index is the sample index.
745 * The second index is the coordinate: X, Y. */
746 float sample_locations_1x[1][2];
747 float sample_locations_2x[2][2];
748 float sample_locations_4x[4][2];
749 float sample_locations_8x[8][2];
750
751 /* GFX7 and later */
752 uint32_t gfx_init_size_dw;
753 struct radeon_winsys_bo *gfx_init;
754
755 struct radeon_winsys_bo *trace_bo;
756 uint32_t *trace_id_ptr;
757
758 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
759 bool keep_shader_info;
760
761 struct radv_physical_device *physical_device;
762
763 /* Backup in-memory cache to be used if the app doesn't provide one */
764 struct radv_pipeline_cache * mem_cache;
765
766 /*
767 * use different counters so MSAA MRTs get consecutive surface indices,
768 * even if MASK is allocated in between.
769 */
770 uint32_t image_mrt_offset_counter;
771 uint32_t fmask_mrt_offset_counter;
772 struct list_head shader_slabs;
773 mtx_t shader_slab_mutex;
774
775 /* For detecting VM faults reported by dmesg. */
776 uint64_t dmesg_timestamp;
777
778 struct radv_device_extension_table enabled_extensions;
779
780 /* Whether the driver uses a global BO list. */
781 bool use_global_bo_list;
782
783 struct radv_bo_list bo_list;
784
785 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
786 int force_aniso;
787 };
788
789 struct radv_device_memory {
790 struct radeon_winsys_bo *bo;
791 /* for dedicated allocations */
792 struct radv_image *image;
793 struct radv_buffer *buffer;
794 uint32_t type_index;
795 VkDeviceSize map_size;
796 void * map;
797 void * user_ptr;
798 };
799
800
801 struct radv_descriptor_range {
802 uint64_t va;
803 uint32_t size;
804 };
805
806 struct radv_descriptor_set {
807 const struct radv_descriptor_set_layout *layout;
808 uint32_t size;
809
810 struct radeon_winsys_bo *bo;
811 uint64_t va;
812 uint32_t *mapped_ptr;
813 struct radv_descriptor_range *dynamic_descriptors;
814
815 struct radeon_winsys_bo *descriptors[0];
816 };
817
818 struct radv_push_descriptor_set
819 {
820 struct radv_descriptor_set set;
821 uint32_t capacity;
822 };
823
824 struct radv_descriptor_pool_entry {
825 uint32_t offset;
826 uint32_t size;
827 struct radv_descriptor_set *set;
828 };
829
830 struct radv_descriptor_pool {
831 struct radeon_winsys_bo *bo;
832 uint8_t *mapped_ptr;
833 uint64_t current_offset;
834 uint64_t size;
835
836 uint8_t *host_memory_base;
837 uint8_t *host_memory_ptr;
838 uint8_t *host_memory_end;
839
840 uint32_t entry_count;
841 uint32_t max_entry_count;
842 struct radv_descriptor_pool_entry entries[0];
843 };
844
845 struct radv_descriptor_update_template_entry {
846 VkDescriptorType descriptor_type;
847
848 /* The number of descriptors to update */
849 uint32_t descriptor_count;
850
851 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
852 uint32_t dst_offset;
853
854 /* In dwords. Not valid/used for dynamic descriptors */
855 uint32_t dst_stride;
856
857 uint32_t buffer_offset;
858
859 /* Only valid for combined image samplers and samplers */
860 uint8_t has_sampler;
861 uint8_t sampler_offset;
862
863 /* In bytes */
864 size_t src_offset;
865 size_t src_stride;
866
867 /* For push descriptors */
868 const uint32_t *immutable_samplers;
869 };
870
871 struct radv_descriptor_update_template {
872 uint32_t entry_count;
873 VkPipelineBindPoint bind_point;
874 struct radv_descriptor_update_template_entry entry[0];
875 };
876
877 struct radv_buffer {
878 VkDeviceSize size;
879
880 VkBufferUsageFlags usage;
881 VkBufferCreateFlags flags;
882
883 /* Set when bound */
884 struct radeon_winsys_bo * bo;
885 VkDeviceSize offset;
886
887 bool shareable;
888 };
889
890 enum radv_dynamic_state_bits {
891 RADV_DYNAMIC_VIEWPORT = 1 << 0,
892 RADV_DYNAMIC_SCISSOR = 1 << 1,
893 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
894 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
895 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
896 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
897 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
898 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
899 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
900 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
901 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
902 RADV_DYNAMIC_ALL = (1 << 11) - 1,
903 };
904
905 enum radv_cmd_dirty_bits {
906 /* Keep the dynamic state dirty bits in sync with
907 * enum radv_dynamic_state_bits */
908 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
909 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
910 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
911 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
912 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
913 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
914 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
915 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
916 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
917 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
918 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
919 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
920 RADV_CMD_DIRTY_PIPELINE = 1 << 11,
921 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
922 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
923 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
924 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
925 };
926
927 enum radv_cmd_flush_bits {
928 /* Instruction cache. */
929 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
930 /* Scalar L1 cache. */
931 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
932 /* Vector L1 cache. */
933 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
934 /* L2 cache + L2 metadata cache writeback & invalidate.
935 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
936 RADV_CMD_FLAG_INV_L2 = 1 << 3,
937 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
938 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
939 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
940 RADV_CMD_FLAG_WB_L2 = 1 << 4,
941 /* Framebuffer caches */
942 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
943 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
944 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
945 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
946 /* Engine synchronization. */
947 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
948 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
949 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
950 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
951 /* Pipeline query controls. */
952 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
953 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
954 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
955
956 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
957 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
958 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
959 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
960 };
961
962 struct radv_vertex_binding {
963 struct radv_buffer * buffer;
964 VkDeviceSize offset;
965 };
966
967 struct radv_streamout_binding {
968 struct radv_buffer *buffer;
969 VkDeviceSize offset;
970 VkDeviceSize size;
971 };
972
973 struct radv_streamout_state {
974 /* Mask of bound streamout buffers. */
975 uint8_t enabled_mask;
976
977 /* External state that comes from the last vertex stage, it must be
978 * set explicitely when binding a new graphics pipeline.
979 */
980 uint16_t stride_in_dw[MAX_SO_BUFFERS];
981 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
982
983 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
984 uint32_t hw_enabled_mask;
985
986 /* State of VGT_STRMOUT_(CONFIG|EN) */
987 bool streamout_enabled;
988 };
989
990 struct radv_viewport_state {
991 uint32_t count;
992 VkViewport viewports[MAX_VIEWPORTS];
993 };
994
995 struct radv_scissor_state {
996 uint32_t count;
997 VkRect2D scissors[MAX_SCISSORS];
998 };
999
1000 struct radv_discard_rectangle_state {
1001 uint32_t count;
1002 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1003 };
1004
1005 struct radv_sample_locations_state {
1006 VkSampleCountFlagBits per_pixel;
1007 VkExtent2D grid_size;
1008 uint32_t count;
1009 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1010 };
1011
1012 struct radv_dynamic_state {
1013 /**
1014 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1015 * Defines the set of saved dynamic state.
1016 */
1017 uint32_t mask;
1018
1019 struct radv_viewport_state viewport;
1020
1021 struct radv_scissor_state scissor;
1022
1023 float line_width;
1024
1025 struct {
1026 float bias;
1027 float clamp;
1028 float slope;
1029 } depth_bias;
1030
1031 float blend_constants[4];
1032
1033 struct {
1034 float min;
1035 float max;
1036 } depth_bounds;
1037
1038 struct {
1039 uint32_t front;
1040 uint32_t back;
1041 } stencil_compare_mask;
1042
1043 struct {
1044 uint32_t front;
1045 uint32_t back;
1046 } stencil_write_mask;
1047
1048 struct {
1049 uint32_t front;
1050 uint32_t back;
1051 } stencil_reference;
1052
1053 struct radv_discard_rectangle_state discard_rectangle;
1054
1055 struct radv_sample_locations_state sample_location;
1056 };
1057
1058 extern const struct radv_dynamic_state default_dynamic_state;
1059
1060 const char *
1061 radv_get_debug_option_name(int id);
1062
1063 const char *
1064 radv_get_perftest_option_name(int id);
1065
1066 /**
1067 * Attachment state when recording a renderpass instance.
1068 *
1069 * The clear value is valid only if there exists a pending clear.
1070 */
1071 struct radv_attachment_state {
1072 VkImageAspectFlags pending_clear_aspects;
1073 uint32_t cleared_views;
1074 VkClearValue clear_value;
1075 VkImageLayout current_layout;
1076 struct radv_sample_locations_state sample_location;
1077 };
1078
1079 struct radv_descriptor_state {
1080 struct radv_descriptor_set *sets[MAX_SETS];
1081 uint32_t dirty;
1082 uint32_t valid;
1083 struct radv_push_descriptor_set push_set;
1084 bool push_dirty;
1085 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1086 };
1087
1088 struct radv_subpass_sample_locs_state {
1089 uint32_t subpass_idx;
1090 struct radv_sample_locations_state sample_location;
1091 };
1092
1093 struct radv_cmd_state {
1094 /* Vertex descriptors */
1095 uint64_t vb_va;
1096 unsigned vb_size;
1097
1098 bool predicating;
1099 uint32_t dirty;
1100
1101 uint32_t prefetch_L2_mask;
1102
1103 struct radv_pipeline * pipeline;
1104 struct radv_pipeline * emitted_pipeline;
1105 struct radv_pipeline * compute_pipeline;
1106 struct radv_pipeline * emitted_compute_pipeline;
1107 struct radv_framebuffer * framebuffer;
1108 struct radv_render_pass * pass;
1109 const struct radv_subpass * subpass;
1110 struct radv_dynamic_state dynamic;
1111 struct radv_attachment_state * attachments;
1112 struct radv_streamout_state streamout;
1113 VkRect2D render_area;
1114
1115 uint32_t num_subpass_sample_locs;
1116 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1117
1118 /* Index buffer */
1119 struct radv_buffer *index_buffer;
1120 uint64_t index_offset;
1121 uint32_t index_type;
1122 uint32_t max_index_count;
1123 uint64_t index_va;
1124 int32_t last_index_type;
1125
1126 int32_t last_primitive_reset_en;
1127 uint32_t last_primitive_reset_index;
1128 enum radv_cmd_flush_bits flush_bits;
1129 unsigned active_occlusion_queries;
1130 bool perfect_occlusion_queries_enabled;
1131 unsigned active_pipeline_queries;
1132 float offset_scale;
1133 uint32_t trace_id;
1134 uint32_t last_ia_multi_vgt_param;
1135
1136 uint32_t last_num_instances;
1137 uint32_t last_first_instance;
1138 uint32_t last_vertex_offset;
1139
1140 /* Whether CP DMA is busy/idle. */
1141 bool dma_is_busy;
1142
1143 /* Conditional rendering info. */
1144 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1145 uint64_t predication_va;
1146
1147 bool context_roll_without_scissor_emitted;
1148 };
1149
1150 struct radv_cmd_pool {
1151 VkAllocationCallbacks alloc;
1152 struct list_head cmd_buffers;
1153 struct list_head free_cmd_buffers;
1154 uint32_t queue_family_index;
1155 };
1156
1157 struct radv_cmd_buffer_upload {
1158 uint8_t *map;
1159 unsigned offset;
1160 uint64_t size;
1161 struct radeon_winsys_bo *upload_bo;
1162 struct list_head list;
1163 };
1164
1165 enum radv_cmd_buffer_status {
1166 RADV_CMD_BUFFER_STATUS_INVALID,
1167 RADV_CMD_BUFFER_STATUS_INITIAL,
1168 RADV_CMD_BUFFER_STATUS_RECORDING,
1169 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1170 RADV_CMD_BUFFER_STATUS_PENDING,
1171 };
1172
1173 struct radv_cmd_buffer {
1174 VK_LOADER_DATA _loader_data;
1175
1176 struct radv_device * device;
1177
1178 struct radv_cmd_pool * pool;
1179 struct list_head pool_link;
1180
1181 VkCommandBufferUsageFlags usage_flags;
1182 VkCommandBufferLevel level;
1183 enum radv_cmd_buffer_status status;
1184 struct radeon_cmdbuf *cs;
1185 struct radv_cmd_state state;
1186 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1187 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1188 uint32_t queue_family_index;
1189
1190 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1191 VkShaderStageFlags push_constant_stages;
1192 struct radv_descriptor_set meta_push_descriptors;
1193
1194 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1195
1196 struct radv_cmd_buffer_upload upload;
1197
1198 uint32_t scratch_size_needed;
1199 uint32_t compute_scratch_size_needed;
1200 uint32_t esgs_ring_size_needed;
1201 uint32_t gsvs_ring_size_needed;
1202 bool tess_rings_needed;
1203 bool sample_positions_needed;
1204
1205 VkResult record_result;
1206
1207 uint64_t gfx9_fence_va;
1208 uint32_t gfx9_fence_idx;
1209 uint64_t gfx9_eop_bug_va;
1210
1211 /**
1212 * Whether a query pool has been resetted and we have to flush caches.
1213 */
1214 bool pending_reset_query;
1215
1216 /**
1217 * Bitmask of pending active query flushes.
1218 */
1219 enum radv_cmd_flush_bits active_query_flush_bits;
1220 };
1221
1222 struct radv_image;
1223 struct radv_image_view;
1224
1225 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1226
1227 void si_emit_graphics(struct radv_physical_device *physical_device,
1228 struct radeon_cmdbuf *cs);
1229 void si_emit_compute(struct radv_physical_device *physical_device,
1230 struct radeon_cmdbuf *cs);
1231
1232 void cik_create_gfx_config(struct radv_device *device);
1233
1234 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1235 int count, const VkViewport *viewports);
1236 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1237 int count, const VkRect2D *scissors,
1238 const VkViewport *viewports, bool can_use_guardband);
1239 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1240 bool instanced_draw, bool indirect_draw,
1241 bool count_from_stream_output,
1242 uint32_t draw_vertex_count);
1243 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1244 enum chip_class chip_class,
1245 bool is_mec,
1246 unsigned event, unsigned event_flags,
1247 unsigned data_sel,
1248 uint64_t va,
1249 uint32_t new_fence,
1250 uint64_t gfx9_eop_bug_va);
1251
1252 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1253 uint32_t ref, uint32_t mask);
1254 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1255 enum chip_class chip_class,
1256 uint32_t *fence_ptr, uint64_t va,
1257 bool is_mec,
1258 enum radv_cmd_flush_bits flush_bits,
1259 uint64_t gfx9_eop_bug_va);
1260 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1261 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1262 bool inverted, uint64_t va);
1263 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1264 uint64_t src_va, uint64_t dest_va,
1265 uint64_t size);
1266 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1267 unsigned size);
1268 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1269 uint64_t size, unsigned value);
1270 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1271
1272 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1273 bool
1274 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1275 unsigned size,
1276 unsigned alignment,
1277 unsigned *out_offset,
1278 void **ptr);
1279 void
1280 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1281 const struct radv_subpass *subpass);
1282 bool
1283 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1284 unsigned size, unsigned alignmnet,
1285 const void *data, unsigned *out_offset);
1286
1287 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1288 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1289 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1290 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1291 VkImageAspectFlags aspects,
1292 VkResolveModeFlagBitsKHR resolve_mode);
1293 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1294 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1295 VkImageAspectFlags aspects,
1296 VkResolveModeFlagBitsKHR resolve_mode);
1297 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1298 unsigned radv_get_default_max_sample_dist(int log_samples);
1299 void radv_device_init_msaa(struct radv_device *device);
1300
1301 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1302 struct radv_image *image,
1303 VkClearDepthStencilValue ds_clear_value,
1304 VkImageAspectFlags aspects);
1305
1306 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1307 const struct radv_image_view *iview,
1308 int cb_idx,
1309 uint32_t color_values[2]);
1310
1311 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1312 struct radv_image *image,
1313 const VkImageSubresourceRange *range, bool value);
1314
1315 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1316 struct radv_image *image,
1317 const VkImageSubresourceRange *range, bool value);
1318
1319 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1320 struct radeon_winsys_bo *bo,
1321 uint64_t offset, uint64_t size, uint32_t value);
1322 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1323 bool radv_get_memory_fd(struct radv_device *device,
1324 struct radv_device_memory *memory,
1325 int *pFD);
1326
1327 static inline void
1328 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1329 unsigned sh_offset, unsigned pointer_count,
1330 bool use_32bit_pointers)
1331 {
1332 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1333 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1334 }
1335
1336 static inline void
1337 radv_emit_shader_pointer_body(struct radv_device *device,
1338 struct radeon_cmdbuf *cs,
1339 uint64_t va, bool use_32bit_pointers)
1340 {
1341 radeon_emit(cs, va);
1342
1343 if (use_32bit_pointers) {
1344 assert(va == 0 ||
1345 (va >> 32) == device->physical_device->rad_info.address32_hi);
1346 } else {
1347 radeon_emit(cs, va >> 32);
1348 }
1349 }
1350
1351 static inline void
1352 radv_emit_shader_pointer(struct radv_device *device,
1353 struct radeon_cmdbuf *cs,
1354 uint32_t sh_offset, uint64_t va, bool global)
1355 {
1356 bool use_32bit_pointers = !global;
1357
1358 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1359 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1360 }
1361
1362 static inline struct radv_descriptor_state *
1363 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1364 VkPipelineBindPoint bind_point)
1365 {
1366 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1367 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1368 return &cmd_buffer->descriptors[bind_point];
1369 }
1370
1371 /*
1372 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1373 *
1374 * Limitations: Can't call normal dispatch functions without binding or rebinding
1375 * the compute pipeline.
1376 */
1377 void radv_unaligned_dispatch(
1378 struct radv_cmd_buffer *cmd_buffer,
1379 uint32_t x,
1380 uint32_t y,
1381 uint32_t z);
1382
1383 struct radv_event {
1384 struct radeon_winsys_bo *bo;
1385 uint64_t *map;
1386 };
1387
1388 struct radv_shader_module;
1389
1390 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1391 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1392 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1393 void
1394 radv_hash_shaders(unsigned char *hash,
1395 const VkPipelineShaderStageCreateInfo **stages,
1396 const struct radv_pipeline_layout *layout,
1397 const struct radv_pipeline_key *key,
1398 uint32_t flags);
1399
1400 static inline gl_shader_stage
1401 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1402 {
1403 assert(__builtin_popcount(vk_stage) == 1);
1404 return ffs(vk_stage) - 1;
1405 }
1406
1407 static inline VkShaderStageFlagBits
1408 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1409 {
1410 return (1 << mesa_stage);
1411 }
1412
1413 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1414
1415 #define radv_foreach_stage(stage, stage_bits) \
1416 for (gl_shader_stage stage, \
1417 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1418 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1419 __tmp &= ~(1 << (stage)))
1420
1421 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1422 unsigned radv_format_meta_fs_key(VkFormat format);
1423
1424 struct radv_multisample_state {
1425 uint32_t db_eqaa;
1426 uint32_t pa_sc_line_cntl;
1427 uint32_t pa_sc_mode_cntl_0;
1428 uint32_t pa_sc_mode_cntl_1;
1429 uint32_t pa_sc_aa_config;
1430 uint32_t pa_sc_aa_mask[2];
1431 unsigned num_samples;
1432 };
1433
1434 struct radv_prim_vertex_count {
1435 uint8_t min;
1436 uint8_t incr;
1437 };
1438
1439 struct radv_vertex_elements_info {
1440 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1441 };
1442
1443 struct radv_ia_multi_vgt_param_helpers {
1444 uint32_t base;
1445 bool partial_es_wave;
1446 uint8_t primgroup_size;
1447 bool wd_switch_on_eop;
1448 bool ia_switch_on_eoi;
1449 bool partial_vs_wave;
1450 };
1451
1452 #define SI_GS_PER_ES 128
1453
1454 struct radv_pipeline {
1455 struct radv_device * device;
1456 struct radv_dynamic_state dynamic_state;
1457
1458 struct radv_pipeline_layout * layout;
1459
1460 bool need_indirect_descriptor_sets;
1461 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1462 struct radv_shader_variant *gs_copy_shader;
1463 VkShaderStageFlags active_stages;
1464
1465 struct radeon_cmdbuf cs;
1466 uint32_t ctx_cs_hash;
1467 struct radeon_cmdbuf ctx_cs;
1468
1469 struct radv_vertex_elements_info vertex_elements;
1470
1471 uint32_t binding_stride[MAX_VBS];
1472 uint8_t num_vertex_bindings;
1473
1474 uint32_t user_data_0[MESA_SHADER_STAGES];
1475 union {
1476 struct {
1477 struct radv_multisample_state ms;
1478 uint32_t spi_baryc_cntl;
1479 bool prim_restart_enable;
1480 unsigned esgs_ring_size;
1481 unsigned gsvs_ring_size;
1482 uint32_t vtx_base_sgpr;
1483 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1484 uint8_t vtx_emit_num;
1485 struct radv_prim_vertex_count prim_vertex_count;
1486 bool can_use_guardband;
1487 uint32_t needed_dynamic_state;
1488 bool disable_out_of_order_rast_for_occlusion;
1489
1490 /* Used for rbplus */
1491 uint32_t col_format;
1492 uint32_t cb_target_mask;
1493 } graphics;
1494 };
1495
1496 unsigned max_waves;
1497 unsigned scratch_bytes_per_wave;
1498
1499 /* Not NULL if graphics pipeline uses streamout. */
1500 struct radv_shader_variant *streamout_shader;
1501 };
1502
1503 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1504 {
1505 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1506 }
1507
1508 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1509 {
1510 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1511 }
1512
1513 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1514 gl_shader_stage stage,
1515 int idx);
1516
1517 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1518 gl_shader_stage stage);
1519
1520 struct radv_graphics_pipeline_create_info {
1521 bool use_rectlist;
1522 bool db_depth_clear;
1523 bool db_stencil_clear;
1524 bool db_depth_disable_expclear;
1525 bool db_stencil_disable_expclear;
1526 bool db_flush_depth_inplace;
1527 bool db_flush_stencil_inplace;
1528 bool db_resummarize;
1529 uint32_t custom_blend_mode;
1530 };
1531
1532 VkResult
1533 radv_graphics_pipeline_create(VkDevice device,
1534 VkPipelineCache cache,
1535 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1536 const struct radv_graphics_pipeline_create_info *extra,
1537 const VkAllocationCallbacks *alloc,
1538 VkPipeline *pPipeline);
1539
1540 struct vk_format_description;
1541 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1542 int first_non_void);
1543 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1544 int first_non_void);
1545 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1546 uint32_t radv_translate_colorformat(VkFormat format);
1547 uint32_t radv_translate_color_numformat(VkFormat format,
1548 const struct vk_format_description *desc,
1549 int first_non_void);
1550 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1551 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1552 uint32_t radv_translate_dbformat(VkFormat format);
1553 uint32_t radv_translate_tex_dataformat(VkFormat format,
1554 const struct vk_format_description *desc,
1555 int first_non_void);
1556 uint32_t radv_translate_tex_numformat(VkFormat format,
1557 const struct vk_format_description *desc,
1558 int first_non_void);
1559 bool radv_format_pack_clear_color(VkFormat format,
1560 uint32_t clear_vals[2],
1561 VkClearColorValue *value);
1562 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1563 bool radv_dcc_formats_compatible(VkFormat format1,
1564 VkFormat format2);
1565 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1566
1567 struct radv_fmask_info {
1568 uint64_t offset;
1569 uint64_t size;
1570 unsigned alignment;
1571 unsigned pitch_in_pixels;
1572 unsigned bank_height;
1573 unsigned slice_tile_max;
1574 unsigned tile_mode_index;
1575 unsigned tile_swizzle;
1576 uint64_t slice_size;
1577 };
1578
1579 struct radv_cmask_info {
1580 uint64_t offset;
1581 uint64_t size;
1582 unsigned alignment;
1583 unsigned slice_tile_max;
1584 unsigned slice_size;
1585 };
1586
1587
1588 struct radv_image_plane {
1589 VkFormat format;
1590 struct radeon_surf surface;
1591 uint64_t offset;
1592 };
1593
1594 struct radv_image {
1595 VkImageType type;
1596 /* The original VkFormat provided by the client. This may not match any
1597 * of the actual surface formats.
1598 */
1599 VkFormat vk_format;
1600 VkImageAspectFlags aspects;
1601 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1602 struct ac_surf_info info;
1603 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1604 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1605
1606 VkDeviceSize size;
1607 uint32_t alignment;
1608
1609 unsigned queue_family_mask;
1610 bool exclusive;
1611 bool shareable;
1612
1613 /* Set when bound */
1614 struct radeon_winsys_bo *bo;
1615 VkDeviceSize offset;
1616 uint64_t dcc_offset;
1617 uint64_t htile_offset;
1618 bool tc_compatible_htile;
1619 bool tc_compatible_cmask;
1620
1621 struct radv_fmask_info fmask;
1622 struct radv_cmask_info cmask;
1623 uint64_t clear_value_offset;
1624 uint64_t fce_pred_offset;
1625 uint64_t dcc_pred_offset;
1626
1627 /*
1628 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1629 * stored at this offset is UINT_MAX, the driver will emit
1630 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1631 * SET_CONTEXT_REG packet.
1632 */
1633 uint64_t tc_compat_zrange_offset;
1634
1635 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1636 VkDeviceMemory owned_memory;
1637
1638 unsigned plane_count;
1639 struct radv_image_plane planes[0];
1640 };
1641
1642 /* Whether the image has a htile that is known consistent with the contents of
1643 * the image. */
1644 bool radv_layout_has_htile(const struct radv_image *image,
1645 VkImageLayout layout,
1646 unsigned queue_mask);
1647
1648 /* Whether the image has a htile that is known consistent with the contents of
1649 * the image and is allowed to be in compressed form.
1650 *
1651 * If this is false reads that don't use the htile should be able to return
1652 * correct results.
1653 */
1654 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1655 VkImageLayout layout,
1656 unsigned queue_mask);
1657
1658 bool radv_layout_can_fast_clear(const struct radv_image *image,
1659 VkImageLayout layout,
1660 unsigned queue_mask);
1661
1662 bool radv_layout_dcc_compressed(const struct radv_image *image,
1663 VkImageLayout layout,
1664 unsigned queue_mask);
1665
1666 /**
1667 * Return whether the image has CMASK metadata for color surfaces.
1668 */
1669 static inline bool
1670 radv_image_has_cmask(const struct radv_image *image)
1671 {
1672 return image->cmask.size;
1673 }
1674
1675 /**
1676 * Return whether the image has FMASK metadata for color surfaces.
1677 */
1678 static inline bool
1679 radv_image_has_fmask(const struct radv_image *image)
1680 {
1681 return image->fmask.size;
1682 }
1683
1684 /**
1685 * Return whether the image has DCC metadata for color surfaces.
1686 */
1687 static inline bool
1688 radv_image_has_dcc(const struct radv_image *image)
1689 {
1690 return image->planes[0].surface.dcc_size;
1691 }
1692
1693 /**
1694 * Return whether the image is TC-compatible CMASK.
1695 */
1696 static inline bool
1697 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1698 {
1699 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1700 }
1701
1702 /**
1703 * Return whether DCC metadata is enabled for a level.
1704 */
1705 static inline bool
1706 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1707 {
1708 return radv_image_has_dcc(image) &&
1709 level < image->planes[0].surface.num_dcc_levels;
1710 }
1711
1712 /**
1713 * Return whether the image has CB metadata.
1714 */
1715 static inline bool
1716 radv_image_has_CB_metadata(const struct radv_image *image)
1717 {
1718 return radv_image_has_cmask(image) ||
1719 radv_image_has_fmask(image) ||
1720 radv_image_has_dcc(image);
1721 }
1722
1723 /**
1724 * Return whether the image has HTILE metadata for depth surfaces.
1725 */
1726 static inline bool
1727 radv_image_has_htile(const struct radv_image *image)
1728 {
1729 return image->planes[0].surface.htile_size;
1730 }
1731
1732 /**
1733 * Return whether HTILE metadata is enabled for a level.
1734 */
1735 static inline bool
1736 radv_htile_enabled(const struct radv_image *image, unsigned level)
1737 {
1738 return radv_image_has_htile(image) && level == 0;
1739 }
1740
1741 /**
1742 * Return whether the image is TC-compatible HTILE.
1743 */
1744 static inline bool
1745 radv_image_is_tc_compat_htile(const struct radv_image *image)
1746 {
1747 return radv_image_has_htile(image) && image->tc_compatible_htile;
1748 }
1749
1750 static inline uint64_t
1751 radv_image_get_fast_clear_va(const struct radv_image *image,
1752 uint32_t base_level)
1753 {
1754 uint64_t va = radv_buffer_get_va(image->bo);
1755 va += image->offset + image->clear_value_offset + base_level * 8;
1756 return va;
1757 }
1758
1759 static inline uint64_t
1760 radv_image_get_fce_pred_va(const struct radv_image *image,
1761 uint32_t base_level)
1762 {
1763 uint64_t va = radv_buffer_get_va(image->bo);
1764 va += image->offset + image->fce_pred_offset + base_level * 8;
1765 return va;
1766 }
1767
1768 static inline uint64_t
1769 radv_image_get_dcc_pred_va(const struct radv_image *image,
1770 uint32_t base_level)
1771 {
1772 uint64_t va = radv_buffer_get_va(image->bo);
1773 va += image->offset + image->dcc_pred_offset + base_level * 8;
1774 return va;
1775 }
1776
1777 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1778
1779 static inline uint32_t
1780 radv_get_layerCount(const struct radv_image *image,
1781 const VkImageSubresourceRange *range)
1782 {
1783 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1784 image->info.array_size - range->baseArrayLayer : range->layerCount;
1785 }
1786
1787 static inline uint32_t
1788 radv_get_levelCount(const struct radv_image *image,
1789 const VkImageSubresourceRange *range)
1790 {
1791 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1792 image->info.levels - range->baseMipLevel : range->levelCount;
1793 }
1794
1795 struct radeon_bo_metadata;
1796 void
1797 radv_init_metadata(struct radv_device *device,
1798 struct radv_image *image,
1799 struct radeon_bo_metadata *metadata);
1800
1801 void
1802 radv_image_override_offset_stride(struct radv_device *device,
1803 struct radv_image *image,
1804 uint64_t offset, uint32_t stride);
1805
1806 union radv_descriptor {
1807 struct {
1808 uint32_t plane0_descriptor[8];
1809 uint32_t fmask_descriptor[8];
1810 };
1811 struct {
1812 uint32_t plane_descriptors[3][8];
1813 };
1814 };
1815
1816 struct radv_image_view {
1817 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1818 struct radeon_winsys_bo *bo;
1819
1820 VkImageViewType type;
1821 VkImageAspectFlags aspect_mask;
1822 VkFormat vk_format;
1823 unsigned plane_id;
1824 bool multiple_planes;
1825 uint32_t base_layer;
1826 uint32_t layer_count;
1827 uint32_t base_mip;
1828 uint32_t level_count;
1829 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1830
1831 union radv_descriptor descriptor;
1832
1833 /* Descriptor for use as a storage image as opposed to a sampled image.
1834 * This has a few differences for cube maps (e.g. type).
1835 */
1836 union radv_descriptor storage_descriptor;
1837 };
1838
1839 struct radv_image_create_info {
1840 const VkImageCreateInfo *vk_info;
1841 bool scanout;
1842 bool no_metadata_planes;
1843 const struct radeon_bo_metadata *bo_metadata;
1844 };
1845
1846 VkResult radv_image_create(VkDevice _device,
1847 const struct radv_image_create_info *info,
1848 const VkAllocationCallbacks* alloc,
1849 VkImage *pImage);
1850
1851 VkResult
1852 radv_image_from_gralloc(VkDevice device_h,
1853 const VkImageCreateInfo *base_info,
1854 const VkNativeBufferANDROID *gralloc_info,
1855 const VkAllocationCallbacks *alloc,
1856 VkImage *out_image_h);
1857
1858 void radv_image_view_init(struct radv_image_view *view,
1859 struct radv_device *device,
1860 const VkImageViewCreateInfo* pCreateInfo);
1861
1862 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1863
1864 struct radv_sampler_ycbcr_conversion {
1865 VkFormat format;
1866 VkSamplerYcbcrModelConversion ycbcr_model;
1867 VkSamplerYcbcrRange ycbcr_range;
1868 VkComponentMapping components;
1869 VkChromaLocation chroma_offsets[2];
1870 VkFilter chroma_filter;
1871 };
1872
1873 struct radv_buffer_view {
1874 struct radeon_winsys_bo *bo;
1875 VkFormat vk_format;
1876 uint64_t range; /**< VkBufferViewCreateInfo::range */
1877 uint32_t state[4];
1878 };
1879 void radv_buffer_view_init(struct radv_buffer_view *view,
1880 struct radv_device *device,
1881 const VkBufferViewCreateInfo* pCreateInfo);
1882
1883 static inline struct VkExtent3D
1884 radv_sanitize_image_extent(const VkImageType imageType,
1885 const struct VkExtent3D imageExtent)
1886 {
1887 switch (imageType) {
1888 case VK_IMAGE_TYPE_1D:
1889 return (VkExtent3D) { imageExtent.width, 1, 1 };
1890 case VK_IMAGE_TYPE_2D:
1891 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1892 case VK_IMAGE_TYPE_3D:
1893 return imageExtent;
1894 default:
1895 unreachable("invalid image type");
1896 }
1897 }
1898
1899 static inline struct VkOffset3D
1900 radv_sanitize_image_offset(const VkImageType imageType,
1901 const struct VkOffset3D imageOffset)
1902 {
1903 switch (imageType) {
1904 case VK_IMAGE_TYPE_1D:
1905 return (VkOffset3D) { imageOffset.x, 0, 0 };
1906 case VK_IMAGE_TYPE_2D:
1907 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1908 case VK_IMAGE_TYPE_3D:
1909 return imageOffset;
1910 default:
1911 unreachable("invalid image type");
1912 }
1913 }
1914
1915 static inline bool
1916 radv_image_extent_compare(const struct radv_image *image,
1917 const VkExtent3D *extent)
1918 {
1919 if (extent->width != image->info.width ||
1920 extent->height != image->info.height ||
1921 extent->depth != image->info.depth)
1922 return false;
1923 return true;
1924 }
1925
1926 struct radv_sampler {
1927 uint32_t state[4];
1928 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1929 };
1930
1931 struct radv_color_buffer_info {
1932 uint64_t cb_color_base;
1933 uint64_t cb_color_cmask;
1934 uint64_t cb_color_fmask;
1935 uint64_t cb_dcc_base;
1936 uint32_t cb_color_slice;
1937 uint32_t cb_color_view;
1938 uint32_t cb_color_info;
1939 uint32_t cb_color_attrib;
1940 uint32_t cb_color_attrib2; /* GFX9 and later */
1941 uint32_t cb_color_attrib3; /* GFX10 and later */
1942 uint32_t cb_dcc_control;
1943 uint32_t cb_color_cmask_slice;
1944 uint32_t cb_color_fmask_slice;
1945 union {
1946 uint32_t cb_color_pitch; // GFX6-GFX8
1947 uint32_t cb_mrt_epitch; // GFX9+
1948 };
1949 };
1950
1951 struct radv_ds_buffer_info {
1952 uint64_t db_z_read_base;
1953 uint64_t db_stencil_read_base;
1954 uint64_t db_z_write_base;
1955 uint64_t db_stencil_write_base;
1956 uint64_t db_htile_data_base;
1957 uint32_t db_depth_info;
1958 uint32_t db_z_info;
1959 uint32_t db_stencil_info;
1960 uint32_t db_depth_view;
1961 uint32_t db_depth_size;
1962 uint32_t db_depth_slice;
1963 uint32_t db_htile_surface;
1964 uint32_t pa_su_poly_offset_db_fmt_cntl;
1965 uint32_t db_z_info2; /* GFX9 only */
1966 uint32_t db_stencil_info2; /* GFX9 only */
1967 float offset_scale;
1968 };
1969
1970 struct radv_attachment_info {
1971 union {
1972 struct radv_color_buffer_info cb;
1973 struct radv_ds_buffer_info ds;
1974 };
1975 struct radv_image_view *attachment;
1976 };
1977
1978 struct radv_framebuffer {
1979 uint32_t width;
1980 uint32_t height;
1981 uint32_t layers;
1982
1983 uint32_t attachment_count;
1984 struct radv_attachment_info attachments[0];
1985 };
1986
1987 struct radv_subpass_barrier {
1988 VkPipelineStageFlags src_stage_mask;
1989 VkAccessFlags src_access_mask;
1990 VkAccessFlags dst_access_mask;
1991 };
1992
1993 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1994 const struct radv_subpass_barrier *barrier);
1995
1996 struct radv_subpass_attachment {
1997 uint32_t attachment;
1998 VkImageLayout layout;
1999 };
2000
2001 struct radv_subpass {
2002 uint32_t attachment_count;
2003 struct radv_subpass_attachment * attachments;
2004
2005 uint32_t input_count;
2006 uint32_t color_count;
2007 struct radv_subpass_attachment * input_attachments;
2008 struct radv_subpass_attachment * color_attachments;
2009 struct radv_subpass_attachment * resolve_attachments;
2010 struct radv_subpass_attachment * depth_stencil_attachment;
2011 struct radv_subpass_attachment * ds_resolve_attachment;
2012 VkResolveModeFlagBitsKHR depth_resolve_mode;
2013 VkResolveModeFlagBitsKHR stencil_resolve_mode;
2014
2015 /** Subpass has at least one color resolve attachment */
2016 bool has_color_resolve;
2017
2018 /** Subpass has at least one color attachment */
2019 bool has_color_att;
2020
2021 struct radv_subpass_barrier start_barrier;
2022
2023 uint32_t view_mask;
2024 VkSampleCountFlagBits max_sample_count;
2025 };
2026
2027 uint32_t
2028 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2029
2030 struct radv_render_pass_attachment {
2031 VkFormat format;
2032 uint32_t samples;
2033 VkAttachmentLoadOp load_op;
2034 VkAttachmentLoadOp stencil_load_op;
2035 VkImageLayout initial_layout;
2036 VkImageLayout final_layout;
2037
2038 /* The subpass id in which the attachment will be used first/last. */
2039 uint32_t first_subpass_idx;
2040 uint32_t last_subpass_idx;
2041 };
2042
2043 struct radv_render_pass {
2044 uint32_t attachment_count;
2045 uint32_t subpass_count;
2046 struct radv_subpass_attachment * subpass_attachments;
2047 struct radv_render_pass_attachment * attachments;
2048 struct radv_subpass_barrier end_barrier;
2049 struct radv_subpass subpasses[0];
2050 };
2051
2052 VkResult radv_device_init_meta(struct radv_device *device);
2053 void radv_device_finish_meta(struct radv_device *device);
2054
2055 struct radv_query_pool {
2056 struct radeon_winsys_bo *bo;
2057 uint32_t stride;
2058 uint32_t availability_offset;
2059 uint64_t size;
2060 char *ptr;
2061 VkQueryType type;
2062 uint32_t pipeline_stats_mask;
2063 };
2064
2065 struct radv_semaphore {
2066 /* use a winsys sem for non-exportable */
2067 struct radeon_winsys_sem *sem;
2068 uint32_t syncobj;
2069 uint32_t temp_syncobj;
2070 };
2071
2072 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2073 VkPipelineBindPoint bind_point,
2074 struct radv_descriptor_set *set,
2075 unsigned idx);
2076
2077 void
2078 radv_update_descriptor_sets(struct radv_device *device,
2079 struct radv_cmd_buffer *cmd_buffer,
2080 VkDescriptorSet overrideSet,
2081 uint32_t descriptorWriteCount,
2082 const VkWriteDescriptorSet *pDescriptorWrites,
2083 uint32_t descriptorCopyCount,
2084 const VkCopyDescriptorSet *pDescriptorCopies);
2085
2086 void
2087 radv_update_descriptor_set_with_template(struct radv_device *device,
2088 struct radv_cmd_buffer *cmd_buffer,
2089 struct radv_descriptor_set *set,
2090 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2091 const void *pData);
2092
2093 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2094 VkPipelineBindPoint pipelineBindPoint,
2095 VkPipelineLayout _layout,
2096 uint32_t set,
2097 uint32_t descriptorWriteCount,
2098 const VkWriteDescriptorSet *pDescriptorWrites);
2099
2100 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2101 struct radv_image *image,
2102 const VkImageSubresourceRange *range, uint32_t value);
2103
2104 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2105 struct radv_image *image,
2106 const VkImageSubresourceRange *range);
2107
2108 struct radv_fence {
2109 struct radeon_winsys_fence *fence;
2110 struct wsi_fence *fence_wsi;
2111
2112 uint32_t syncobj;
2113 uint32_t temp_syncobj;
2114 };
2115
2116 /* radv_nir_to_llvm.c */
2117 struct radv_shader_variant_info;
2118 struct radv_nir_compiler_options;
2119
2120 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2121 struct nir_shader *geom_shader,
2122 struct radv_shader_binary **rbinary,
2123 struct radv_shader_variant_info *shader_info,
2124 const struct radv_nir_compiler_options *option);
2125
2126 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2127 struct radv_shader_binary **rbinary,
2128 struct radv_shader_variant_info *shader_info,
2129 struct nir_shader *const *nir,
2130 int nir_count,
2131 const struct radv_nir_compiler_options *options);
2132
2133 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2134 const struct nir_shader *nir);
2135
2136 /* radv_shader_info.h */
2137 struct radv_shader_info;
2138
2139 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2140 const struct radv_nir_compiler_options *options,
2141 struct radv_shader_info *info);
2142
2143 void radv_nir_shader_info_init(struct radv_shader_info *info);
2144
2145 struct radeon_winsys_sem;
2146
2147 uint64_t radv_get_current_time(void);
2148
2149 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2150 \
2151 static inline struct __radv_type * \
2152 __radv_type ## _from_handle(__VkType _handle) \
2153 { \
2154 return (struct __radv_type *) _handle; \
2155 } \
2156 \
2157 static inline __VkType \
2158 __radv_type ## _to_handle(struct __radv_type *_obj) \
2159 { \
2160 return (__VkType) _obj; \
2161 }
2162
2163 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2164 \
2165 static inline struct __radv_type * \
2166 __radv_type ## _from_handle(__VkType _handle) \
2167 { \
2168 return (struct __radv_type *)(uintptr_t) _handle; \
2169 } \
2170 \
2171 static inline __VkType \
2172 __radv_type ## _to_handle(struct __radv_type *_obj) \
2173 { \
2174 return (__VkType)(uintptr_t) _obj; \
2175 }
2176
2177 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2178 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2179
2180 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2181 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2182 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2183 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2184 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2185
2186 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2187 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2188 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2189 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2190 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2191 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2192 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2193 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2194 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2195 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2196 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2197 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2198 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2199 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2200 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2201 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2202 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2203 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2204 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2205 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2206 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2207 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2208
2209 #endif /* RADV_PRIVATE_H */