2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
60 #include <llvm-c/TargetMachine.h>
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t
;
66 typedef uint32_t xcb_visualid_t
;
67 typedef uint32_t xcb_window_t
;
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
73 #include "radv_entrypoints.h"
75 #include "wsi_common.h"
77 #define ATI_VENDOR_ID 0x1002
80 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
105 RADV_MEM_TYPE_GTT_CACHED
,
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111 static inline uint32_t
112 align_u32(uint32_t v
, uint32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 static inline uint32_t
119 align_u32_npot(uint32_t v
, uint32_t a
)
121 return (v
+ a
- 1) / a
* a
;
124 static inline uint64_t
125 align_u64(uint64_t v
, uint64_t a
)
127 assert(a
!= 0 && a
== (a
& -a
));
128 return (v
+ a
- 1) & ~(a
- 1);
131 static inline int32_t
132 align_i32(int32_t v
, int32_t a
)
134 assert(a
!= 0 && a
== (a
& -a
));
135 return (v
+ a
- 1) & ~(a
- 1);
138 /** Alignment must be a power of 2. */
140 radv_is_aligned(uintmax_t n
, uintmax_t a
)
142 assert(a
== (a
& -a
));
143 return (n
& (a
- 1)) == 0;
146 static inline uint32_t
147 round_up_u32(uint32_t v
, uint32_t a
)
149 return (v
+ a
- 1) / a
;
152 static inline uint64_t
153 round_up_u64(uint64_t v
, uint64_t a
)
155 return (v
+ a
- 1) / a
;
158 static inline uint32_t
159 radv_minify(uint32_t n
, uint32_t levels
)
161 if (unlikely(n
== 0))
164 return MAX2(n
>> levels
, 1);
167 radv_clamp_f(float f
, float min
, float max
)
180 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
182 if (*inout_mask
& clear_mask
) {
183 *inout_mask
&= ~clear_mask
;
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
205 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
215 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format
, va_list va
);
221 * Print a FINISHME message, including its source location.
223 #define radv_finishme(format, ...) \
225 static bool reported = false; \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
232 /* A non-fatal assert. Useful for debugging. */
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
239 #define radv_assert(x)
242 #define stub_return(v) \
244 radv_finishme("stub %s", __func__); \
250 radv_finishme("stub %s", __func__); \
254 void *radv_lookup_entrypoint(const char *name
);
256 struct radv_physical_device
{
257 VK_LOADER_DATA _loader_data
;
259 struct radv_instance
* instance
;
261 struct radeon_winsys
*ws
;
262 struct radeon_info rad_info
;
265 uint8_t driver_uuid
[VK_UUID_SIZE
];
266 uint8_t device_uuid
[VK_UUID_SIZE
];
267 uint8_t cache_uuid
[VK_UUID_SIZE
];
270 struct wsi_device wsi_device
;
272 bool has_rbplus
; /* if RB+ register exist */
273 bool rbplus_allowed
; /* if RB+ is allowed */
274 bool has_clear_state
;
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
279 struct disk_cache
* disk_cache
;
282 struct radv_instance
{
283 VK_LOADER_DATA _loader_data
;
285 VkAllocationCallbacks alloc
;
288 int physicalDeviceCount
;
289 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
291 uint64_t debug_flags
;
292 uint64_t perftest_flags
;
295 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
296 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
298 bool radv_instance_extension_supported(const char *name
);
299 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
300 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
305 struct radv_pipeline_cache
{
306 struct radv_device
* device
;
307 pthread_mutex_t mutex
;
311 uint32_t kernel_count
;
312 struct cache_entry
** hash_table
;
315 VkAllocationCallbacks alloc
;
319 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
320 struct radv_device
*device
);
322 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
324 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
325 const void *data
, size_t size
);
327 struct radv_shader_variant
*
328 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
329 struct radv_pipeline_cache
*cache
,
330 const unsigned char *sha1
);
332 struct radv_shader_variant
*
333 radv_pipeline_cache_insert_shader(struct radv_device
*device
,
334 struct radv_pipeline_cache
*cache
,
335 const unsigned char *sha1
,
336 struct radv_shader_variant
*variant
,
337 const void *code
, unsigned code_size
);
340 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
341 struct radv_pipeline_cache
*cache
,
342 const unsigned char *sha1
,
343 struct radv_shader_variant
**variants
);
346 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
347 struct radv_pipeline_cache
*cache
,
348 const unsigned char *sha1
,
349 struct radv_shader_variant
**variants
,
350 const void *const *codes
,
351 const unsigned *code_sizes
);
353 struct radv_meta_state
{
354 VkAllocationCallbacks alloc
;
356 struct radv_pipeline_cache cache
;
359 * Use array element `i` for images with `2^i` samples.
362 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
363 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
365 VkRenderPass depthstencil_rp
;
366 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
367 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
368 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
369 } clear
[1 + MAX_SAMPLES_LOG2
];
371 VkPipelineLayout clear_color_p_layout
;
372 VkPipelineLayout clear_depth_p_layout
;
374 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
376 /** Pipeline that blits from a 1D image. */
377 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
379 /** Pipeline that blits from a 2D image. */
380 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
382 /** Pipeline that blits from a 3D image. */
383 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
385 VkRenderPass depth_only_rp
;
386 VkPipeline depth_only_1d_pipeline
;
387 VkPipeline depth_only_2d_pipeline
;
388 VkPipeline depth_only_3d_pipeline
;
390 VkRenderPass stencil_only_rp
;
391 VkPipeline stencil_only_1d_pipeline
;
392 VkPipeline stencil_only_2d_pipeline
;
393 VkPipeline stencil_only_3d_pipeline
;
394 VkPipelineLayout pipeline_layout
;
395 VkDescriptorSetLayout ds_layout
;
399 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
401 VkPipelineLayout p_layouts
[2];
402 VkDescriptorSetLayout ds_layouts
[2];
403 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
405 VkRenderPass depth_only_rp
;
406 VkPipeline depth_only_pipeline
[2];
408 VkRenderPass stencil_only_rp
;
409 VkPipeline stencil_only_pipeline
[2];
413 VkPipelineLayout img_p_layout
;
414 VkDescriptorSetLayout img_ds_layout
;
418 VkPipelineLayout img_p_layout
;
419 VkDescriptorSetLayout img_ds_layout
;
423 VkPipelineLayout img_p_layout
;
424 VkDescriptorSetLayout img_ds_layout
;
428 VkPipelineLayout img_p_layout
;
429 VkDescriptorSetLayout img_ds_layout
;
439 VkDescriptorSetLayout ds_layout
;
440 VkPipelineLayout p_layout
;
443 VkPipeline i_pipeline
;
444 VkPipeline srgb_pipeline
;
445 } rc
[MAX_SAMPLES_LOG2
];
449 VkDescriptorSetLayout ds_layout
;
450 VkPipelineLayout p_layout
;
453 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
454 VkPipeline pipeline
[NUM_META_FS_KEYS
];
455 } rc
[MAX_SAMPLES_LOG2
];
459 VkPipeline decompress_pipeline
;
460 VkPipeline resummarize_pipeline
;
462 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
465 VkPipeline cmask_eliminate_pipeline
;
466 VkPipeline fmask_decompress_pipeline
;
471 VkPipelineLayout fill_p_layout
;
472 VkPipelineLayout copy_p_layout
;
473 VkDescriptorSetLayout fill_ds_layout
;
474 VkDescriptorSetLayout copy_ds_layout
;
475 VkPipeline fill_pipeline
;
476 VkPipeline copy_pipeline
;
480 VkDescriptorSetLayout ds_layout
;
481 VkPipelineLayout p_layout
;
482 VkPipeline occlusion_query_pipeline
;
483 VkPipeline pipeline_statistics_query_pipeline
;
488 #define RADV_QUEUE_GENERAL 0
489 #define RADV_QUEUE_COMPUTE 1
490 #define RADV_QUEUE_TRANSFER 2
492 #define RADV_MAX_QUEUE_FAMILIES 3
494 enum ring_type
radv_queue_family_to_ring(int f
);
497 VK_LOADER_DATA _loader_data
;
498 struct radv_device
* device
;
499 struct radeon_winsys_ctx
*hw_ctx
;
500 int queue_family_index
;
503 uint32_t scratch_size
;
504 uint32_t compute_scratch_size
;
505 uint32_t esgs_ring_size
;
506 uint32_t gsvs_ring_size
;
508 bool has_sample_positions
;
510 struct radeon_winsys_bo
*scratch_bo
;
511 struct radeon_winsys_bo
*descriptor_bo
;
512 struct radeon_winsys_bo
*compute_scratch_bo
;
513 struct radeon_winsys_bo
*esgs_ring_bo
;
514 struct radeon_winsys_bo
*gsvs_ring_bo
;
515 struct radeon_winsys_bo
*tess_factor_ring_bo
;
516 struct radeon_winsys_bo
*tess_offchip_ring_bo
;
517 struct radeon_winsys_cs
*initial_preamble_cs
;
518 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
519 struct radeon_winsys_cs
*continue_preamble_cs
;
523 VK_LOADER_DATA _loader_data
;
525 VkAllocationCallbacks alloc
;
527 struct radv_instance
* instance
;
528 struct radeon_winsys
*ws
;
530 struct radv_meta_state meta_state
;
532 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
533 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
534 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
536 bool llvm_supports_spill
;
537 bool has_distributed_tess
;
538 uint32_t tess_offchip_block_dw_size
;
539 uint32_t scratch_waves
;
541 uint32_t gs_table_depth
;
543 /* MSAA sample locations.
544 * The first index is the sample index.
545 * The second index is the coordinate: X, Y. */
546 float sample_locations_1x
[1][2];
547 float sample_locations_2x
[2][2];
548 float sample_locations_4x
[4][2];
549 float sample_locations_8x
[8][2];
550 float sample_locations_16x
[16][2];
553 uint32_t gfx_init_size_dw
;
554 struct radeon_winsys_bo
*gfx_init
;
556 struct radeon_winsys_bo
*trace_bo
;
557 uint32_t *trace_id_ptr
;
559 struct radv_physical_device
*physical_device
;
561 /* Backup in-memory cache to be used if the app doesn't provide one */
562 struct radv_pipeline_cache
* mem_cache
;
565 * use different counters so MSAA MRTs get consecutive surface indices,
566 * even if MASK is allocated in between.
568 uint32_t image_mrt_offset_counter
;
569 uint32_t fmask_mrt_offset_counter
;
570 struct list_head shader_slabs
;
571 mtx_t shader_slab_mutex
;
573 /* For detecting VM faults reported by dmesg. */
574 uint64_t dmesg_timestamp
;
577 struct radv_device_memory
{
578 struct radeon_winsys_bo
*bo
;
579 /* for dedicated allocations */
580 struct radv_image
*image
;
581 struct radv_buffer
*buffer
;
583 VkDeviceSize map_size
;
588 struct radv_descriptor_range
{
593 struct radv_descriptor_set
{
594 const struct radv_descriptor_set_layout
*layout
;
597 struct radeon_winsys_bo
*bo
;
599 uint32_t *mapped_ptr
;
600 struct radv_descriptor_range
*dynamic_descriptors
;
602 struct list_head vram_list
;
604 struct radeon_winsys_bo
*descriptors
[0];
607 struct radv_push_descriptor_set
609 struct radv_descriptor_set set
;
613 struct radv_descriptor_pool
{
614 struct radeon_winsys_bo
*bo
;
616 uint64_t current_offset
;
619 struct list_head vram_list
;
621 uint8_t *host_memory_base
;
622 uint8_t *host_memory_ptr
;
623 uint8_t *host_memory_end
;
626 struct radv_descriptor_update_template_entry
{
627 VkDescriptorType descriptor_type
;
629 /* The number of descriptors to update */
630 uint32_t descriptor_count
;
632 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
635 /* In dwords. Not valid/used for dynamic descriptors */
638 uint32_t buffer_offset
;
640 /* Only valid for combined image samplers and samplers */
641 uint16_t has_sampler
;
647 /* For push descriptors */
648 const uint32_t *immutable_samplers
;
651 struct radv_descriptor_update_template
{
652 uint32_t entry_count
;
653 struct radv_descriptor_update_template_entry entry
[0];
657 struct radv_device
* device
;
660 VkBufferUsageFlags usage
;
661 VkBufferCreateFlags flags
;
664 struct radeon_winsys_bo
* bo
;
669 enum radv_cmd_dirty_bits
{
670 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
671 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
672 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
673 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
674 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
675 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
676 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
677 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
678 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
679 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
680 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
681 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
682 RADV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
684 typedef uint32_t radv_cmd_dirty_mask_t
;
686 enum radv_cmd_flush_bits
{
687 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
688 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
689 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
690 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
691 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
692 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
693 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
694 /* Same as above, but only writes back and doesn't invalidate */
695 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
696 /* Framebuffer caches */
697 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
698 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
699 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
700 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
701 /* Engine synchronization. */
702 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
703 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
704 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
705 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
707 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
708 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
709 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
710 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
713 struct radv_vertex_binding
{
714 struct radv_buffer
* buffer
;
718 struct radv_viewport_state
{
720 VkViewport viewports
[MAX_VIEWPORTS
];
723 struct radv_scissor_state
{
725 VkRect2D scissors
[MAX_SCISSORS
];
728 struct radv_dynamic_state
{
729 struct radv_viewport_state viewport
;
731 struct radv_scissor_state scissor
;
741 float blend_constants
[4];
751 } stencil_compare_mask
;
756 } stencil_write_mask
;
764 extern const struct radv_dynamic_state default_dynamic_state
;
767 radv_get_debug_option_name(int id
);
770 radv_get_perftest_option_name(int id
);
773 * Attachment state when recording a renderpass instance.
775 * The clear value is valid only if there exists a pending clear.
777 struct radv_attachment_state
{
778 VkImageAspectFlags pending_clear_aspects
;
779 uint32_t cleared_views
;
780 VkClearValue clear_value
;
781 VkImageLayout current_layout
;
784 struct radv_cmd_state
{
786 radv_cmd_dirty_mask_t dirty
;
787 bool push_descriptors_dirty
;
790 struct radv_pipeline
* pipeline
;
791 struct radv_pipeline
* emitted_pipeline
;
792 struct radv_pipeline
* compute_pipeline
;
793 struct radv_pipeline
* emitted_compute_pipeline
;
794 struct radv_framebuffer
* framebuffer
;
795 struct radv_render_pass
* pass
;
796 const struct radv_subpass
* subpass
;
797 struct radv_dynamic_state dynamic
;
798 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
799 struct radv_descriptor_set
* descriptors
[MAX_SETS
];
800 struct radv_attachment_state
* attachments
;
801 VkRect2D render_area
;
803 uint32_t max_index_count
;
805 int32_t last_primitive_reset_en
;
806 uint32_t last_primitive_reset_index
;
807 enum radv_cmd_flush_bits flush_bits
;
808 unsigned active_occlusion_queries
;
810 uint32_t descriptors_dirty
;
812 uint32_t last_ia_multi_vgt_param
;
815 struct radv_cmd_pool
{
816 VkAllocationCallbacks alloc
;
817 struct list_head cmd_buffers
;
818 struct list_head free_cmd_buffers
;
819 uint32_t queue_family_index
;
822 struct radv_cmd_buffer_upload
{
826 struct radeon_winsys_bo
*upload_bo
;
827 struct list_head list
;
830 struct radv_cmd_buffer
{
831 VK_LOADER_DATA _loader_data
;
833 struct radv_device
* device
;
835 struct radv_cmd_pool
* pool
;
836 struct list_head pool_link
;
838 VkCommandBufferUsageFlags usage_flags
;
839 VkCommandBufferLevel level
;
840 struct radeon_winsys_cs
*cs
;
841 struct radv_cmd_state state
;
842 uint32_t queue_family_index
;
844 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
845 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
846 VkShaderStageFlags push_constant_stages
;
847 struct radv_push_descriptor_set push_descriptors
;
848 struct radv_descriptor_set meta_push_descriptors
;
850 struct radv_cmd_buffer_upload upload
;
852 uint32_t scratch_size_needed
;
853 uint32_t compute_scratch_size_needed
;
854 uint32_t esgs_ring_size_needed
;
855 uint32_t gsvs_ring_size_needed
;
856 bool tess_rings_needed
;
857 bool sample_positions_needed
;
859 VkResult record_result
;
861 int ring_offsets_idx
; /* just used for verification */
862 uint32_t gfx9_fence_offset
;
863 struct radeon_winsys_bo
*gfx9_fence_bo
;
864 uint32_t gfx9_fence_idx
;
869 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
871 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
872 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
874 void cik_create_gfx_config(struct radv_device
*device
);
876 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
877 int count
, const VkViewport
*viewports
);
878 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
879 int count
, const VkRect2D
*scissors
,
880 const VkViewport
*viewports
, bool can_use_guardband
);
881 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
882 bool instanced_draw
, bool indirect_draw
,
883 uint32_t draw_vertex_count
);
884 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
886 enum chip_class chip_class
,
888 unsigned event
, unsigned event_flags
,
894 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
896 uint64_t va
, uint32_t ref
,
898 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
900 enum chip_class chip_class
,
901 uint32_t *fence_ptr
, uint64_t va
,
903 enum radv_cmd_flush_bits flush_bits
);
904 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
905 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
906 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
907 uint64_t src_va
, uint64_t dest_va
,
909 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
911 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
912 uint64_t size
, unsigned value
);
913 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
914 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
915 struct radv_descriptor_set
*set
,
918 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
921 unsigned *out_offset
,
924 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
925 const struct radv_subpass
*subpass
,
928 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
929 unsigned size
, unsigned alignmnet
,
930 const void *data
, unsigned *out_offset
);
932 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
933 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
934 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
935 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
936 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
937 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
938 unsigned radv_cayman_get_maxdist(int log_samples
);
939 void radv_device_init_msaa(struct radv_device
*device
);
940 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
941 struct radv_image
*image
,
942 VkClearDepthStencilValue ds_clear_value
,
943 VkImageAspectFlags aspects
);
944 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
945 struct radv_image
*image
,
947 uint32_t color_values
[2]);
948 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
949 struct radv_image
*image
,
951 void radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
952 struct radeon_winsys_bo
*bo
,
953 uint64_t offset
, uint64_t size
, uint32_t value
);
954 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
955 bool radv_get_memory_fd(struct radv_device
*device
,
956 struct radv_device_memory
*memory
,
959 * Takes x,y,z as exact numbers of invocations, instead of blocks.
961 * Limitations: Can't call normal dispatch functions without binding or rebinding
962 * the compute pipeline.
964 void radv_unaligned_dispatch(
965 struct radv_cmd_buffer
*cmd_buffer
,
971 struct radeon_winsys_bo
*bo
;
975 struct radv_shader_module
;
976 struct ac_shader_variant_key
;
978 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
979 #define RADV_HASH_SHADER_SISCHED (1 << 1)
980 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
982 radv_hash_shaders(unsigned char *hash
,
983 const VkPipelineShaderStageCreateInfo
**stages
,
984 const struct radv_pipeline_layout
*layout
,
985 const struct ac_shader_variant_key
*keys
,
988 static inline gl_shader_stage
989 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
991 assert(__builtin_popcount(vk_stage
) == 1);
992 return ffs(vk_stage
) - 1;
995 static inline VkShaderStageFlagBits
996 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
998 return (1 << mesa_stage
);
1001 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1003 #define radv_foreach_stage(stage, stage_bits) \
1004 for (gl_shader_stage stage, \
1005 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1006 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1007 __tmp &= ~(1 << (stage)))
1009 struct radv_depth_stencil_state
{
1010 uint32_t db_depth_control
;
1011 uint32_t db_stencil_control
;
1012 uint32_t db_render_control
;
1013 uint32_t db_render_override2
;
1016 struct radv_blend_state
{
1017 uint32_t cb_color_control
;
1018 uint32_t cb_target_mask
;
1019 uint32_t sx_mrt_blend_opt
[8];
1020 uint32_t cb_blend_control
[8];
1022 uint32_t spi_shader_col_format
;
1023 uint32_t cb_shader_mask
;
1024 uint32_t db_alpha_to_mask
;
1027 unsigned radv_format_meta_fs_key(VkFormat format
);
1029 struct radv_raster_state
{
1030 uint32_t pa_cl_clip_cntl
;
1031 uint32_t spi_interp_control
;
1032 uint32_t pa_su_vtx_cntl
;
1033 uint32_t pa_su_sc_mode_cntl
;
1036 struct radv_multisample_state
{
1038 uint32_t pa_sc_line_cntl
;
1039 uint32_t pa_sc_mode_cntl_0
;
1040 uint32_t pa_sc_mode_cntl_1
;
1041 uint32_t pa_sc_aa_config
;
1042 uint32_t pa_sc_aa_mask
[2];
1043 unsigned num_samples
;
1046 struct radv_prim_vertex_count
{
1051 struct radv_tessellation_state
{
1052 uint32_t ls_hs_config
;
1053 uint32_t tcs_in_layout
;
1054 uint32_t tcs_out_layout
;
1055 uint32_t tcs_out_offsets
;
1056 uint32_t offchip_layout
;
1057 unsigned num_patches
;
1059 unsigned num_tcs_input_cp
;
1063 struct radv_vertex_elements_info
{
1064 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1065 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1066 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1067 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1071 #define SI_GS_PER_ES 128
1073 struct radv_pipeline
{
1074 struct radv_device
* device
;
1075 uint32_t dynamic_state_mask
;
1076 struct radv_dynamic_state dynamic_state
;
1078 struct radv_pipeline_layout
* layout
;
1080 bool needs_data_cache
;
1081 bool need_indirect_descriptor_sets
;
1082 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1083 struct radv_shader_variant
*gs_copy_shader
;
1084 VkShaderStageFlags active_stages
;
1086 struct radv_vertex_elements_info vertex_elements
;
1088 uint32_t binding_stride
[MAX_VBS
];
1092 struct radv_blend_state blend
;
1093 struct radv_depth_stencil_state ds
;
1094 struct radv_raster_state raster
;
1095 struct radv_multisample_state ms
;
1096 struct radv_tessellation_state tess
;
1097 uint32_t db_shader_control
;
1098 uint32_t shader_z_format
;
1101 uint32_t vgt_gs_mode
;
1102 bool vgt_primitiveid_en
;
1103 bool prim_restart_enable
;
1104 bool partial_es_wave
;
1105 uint8_t primgroup_size
;
1106 unsigned esgs_ring_size
;
1107 unsigned gsvs_ring_size
;
1108 uint32_t ps_input_cntl
[32];
1109 uint32_t ps_input_cntl_num
;
1110 uint32_t pa_cl_vs_out_cntl
;
1111 uint32_t vgt_shader_stages_en
;
1112 uint32_t vtx_base_sgpr
;
1113 uint32_t base_ia_multi_vgt_param
;
1114 bool wd_switch_on_eop
;
1115 bool ia_switch_on_eoi
;
1116 bool partial_vs_wave
;
1117 uint8_t vtx_emit_num
;
1118 uint32_t vtx_reuse_depth
;
1119 struct radv_prim_vertex_count prim_vertex_count
;
1120 bool can_use_guardband
;
1125 unsigned scratch_bytes_per_wave
;
1128 static inline bool radv_pipeline_has_gs(struct radv_pipeline
*pipeline
)
1130 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1133 static inline bool radv_pipeline_has_tess(struct radv_pipeline
*pipeline
)
1135 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ? true : false;
1138 struct ac_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1139 gl_shader_stage stage
,
1142 struct radv_graphics_pipeline_create_info
{
1144 bool db_depth_clear
;
1145 bool db_stencil_clear
;
1146 bool db_depth_disable_expclear
;
1147 bool db_stencil_disable_expclear
;
1148 bool db_flush_depth_inplace
;
1149 bool db_flush_stencil_inplace
;
1150 bool db_resummarize
;
1151 uint32_t custom_blend_mode
;
1155 radv_graphics_pipeline_create(VkDevice device
,
1156 VkPipelineCache cache
,
1157 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1158 const struct radv_graphics_pipeline_create_info
*extra
,
1159 const VkAllocationCallbacks
*alloc
,
1160 VkPipeline
*pPipeline
);
1162 struct vk_format_description
;
1163 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1164 int first_non_void
);
1165 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1166 int first_non_void
);
1167 uint32_t radv_translate_colorformat(VkFormat format
);
1168 uint32_t radv_translate_color_numformat(VkFormat format
,
1169 const struct vk_format_description
*desc
,
1170 int first_non_void
);
1171 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1172 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1173 uint32_t radv_translate_dbformat(VkFormat format
);
1174 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1175 const struct vk_format_description
*desc
,
1176 int first_non_void
);
1177 uint32_t radv_translate_tex_numformat(VkFormat format
,
1178 const struct vk_format_description
*desc
,
1179 int first_non_void
);
1180 bool radv_format_pack_clear_color(VkFormat format
,
1181 uint32_t clear_vals
[2],
1182 VkClearColorValue
*value
);
1183 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1184 bool radv_dcc_formats_compatible(VkFormat format1
,
1187 struct radv_fmask_info
{
1191 unsigned pitch_in_pixels
;
1192 unsigned bank_height
;
1193 unsigned slice_tile_max
;
1194 unsigned tile_mode_index
;
1195 unsigned tile_swizzle
;
1198 struct radv_cmask_info
{
1202 unsigned slice_tile_max
;
1203 unsigned base_address_reg
;
1206 struct r600_htile_info
{
1217 /* The original VkFormat provided by the client. This may not match any
1218 * of the actual surface formats.
1221 VkImageAspectFlags aspects
;
1222 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1223 struct ac_surf_info info
;
1224 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1225 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1230 unsigned queue_family_mask
;
1234 /* Set when bound */
1235 struct radeon_winsys_bo
*bo
;
1236 VkDeviceSize offset
;
1237 uint64_t dcc_offset
;
1238 uint64_t htile_offset
;
1239 bool tc_compatible_htile
;
1240 struct radeon_surf surface
;
1242 struct radv_fmask_info fmask
;
1243 struct radv_cmask_info cmask
;
1244 uint64_t clear_value_offset
;
1245 uint64_t dcc_pred_offset
;
1248 /* Whether the image has a htile that is known consistent with the contents of
1250 bool radv_layout_has_htile(const struct radv_image
*image
,
1251 VkImageLayout layout
,
1252 unsigned queue_mask
);
1254 /* Whether the image has a htile that is known consistent with the contents of
1255 * the image and is allowed to be in compressed form.
1257 * If this is false reads that don't use the htile should be able to return
1260 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1261 VkImageLayout layout
,
1262 unsigned queue_mask
);
1264 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1265 VkImageLayout layout
,
1266 unsigned queue_mask
);
1269 radv_vi_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1271 return image
->surface
.dcc_size
&& level
< image
->surface
.num_dcc_levels
;
1275 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1277 return image
->surface
.htile_size
&& level
== 0;
1280 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1282 static inline uint32_t
1283 radv_get_layerCount(const struct radv_image
*image
,
1284 const VkImageSubresourceRange
*range
)
1286 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1287 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1290 static inline uint32_t
1291 radv_get_levelCount(const struct radv_image
*image
,
1292 const VkImageSubresourceRange
*range
)
1294 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1295 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1298 struct radeon_bo_metadata
;
1300 radv_init_metadata(struct radv_device
*device
,
1301 struct radv_image
*image
,
1302 struct radeon_bo_metadata
*metadata
);
1304 struct radv_image_view
{
1305 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1306 struct radeon_winsys_bo
*bo
;
1308 VkImageViewType type
;
1309 VkImageAspectFlags aspect_mask
;
1311 uint32_t base_layer
;
1312 uint32_t layer_count
;
1314 uint32_t level_count
;
1315 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1317 uint32_t descriptor
[8];
1318 uint32_t fmask_descriptor
[8];
1320 /* Descriptor for use as a storage image as opposed to a sampled image.
1321 * This has a few differences for cube maps (e.g. type).
1323 uint32_t storage_descriptor
[8];
1324 uint32_t storage_fmask_descriptor
[8];
1327 struct radv_image_create_info
{
1328 const VkImageCreateInfo
*vk_info
;
1332 VkResult
radv_image_create(VkDevice _device
,
1333 const struct radv_image_create_info
*info
,
1334 const VkAllocationCallbacks
* alloc
,
1337 void radv_image_view_init(struct radv_image_view
*view
,
1338 struct radv_device
*device
,
1339 const VkImageViewCreateInfo
* pCreateInfo
);
1341 struct radv_buffer_view
{
1342 struct radeon_winsys_bo
*bo
;
1344 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1347 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1348 struct radv_device
*device
,
1349 const VkBufferViewCreateInfo
* pCreateInfo
);
1351 static inline struct VkExtent3D
1352 radv_sanitize_image_extent(const VkImageType imageType
,
1353 const struct VkExtent3D imageExtent
)
1355 switch (imageType
) {
1356 case VK_IMAGE_TYPE_1D
:
1357 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1358 case VK_IMAGE_TYPE_2D
:
1359 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1360 case VK_IMAGE_TYPE_3D
:
1363 unreachable("invalid image type");
1367 static inline struct VkOffset3D
1368 radv_sanitize_image_offset(const VkImageType imageType
,
1369 const struct VkOffset3D imageOffset
)
1371 switch (imageType
) {
1372 case VK_IMAGE_TYPE_1D
:
1373 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1374 case VK_IMAGE_TYPE_2D
:
1375 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1376 case VK_IMAGE_TYPE_3D
:
1379 unreachable("invalid image type");
1384 radv_image_extent_compare(const struct radv_image
*image
,
1385 const VkExtent3D
*extent
)
1387 if (extent
->width
!= image
->info
.width
||
1388 extent
->height
!= image
->info
.height
||
1389 extent
->depth
!= image
->info
.depth
)
1394 struct radv_sampler
{
1398 struct radv_color_buffer_info
{
1399 uint64_t cb_color_base
;
1400 uint64_t cb_color_cmask
;
1401 uint64_t cb_color_fmask
;
1402 uint64_t cb_dcc_base
;
1403 uint32_t cb_color_pitch
;
1404 uint32_t cb_color_slice
;
1405 uint32_t cb_color_view
;
1406 uint32_t cb_color_info
;
1407 uint32_t cb_color_attrib
;
1408 uint32_t cb_color_attrib2
;
1409 uint32_t cb_dcc_control
;
1410 uint32_t cb_color_cmask_slice
;
1411 uint32_t cb_color_fmask_slice
;
1412 uint32_t cb_clear_value0
;
1413 uint32_t cb_clear_value1
;
1414 uint32_t micro_tile_mode
;
1415 uint32_t gfx9_epitch
;
1418 struct radv_ds_buffer_info
{
1419 uint64_t db_z_read_base
;
1420 uint64_t db_stencil_read_base
;
1421 uint64_t db_z_write_base
;
1422 uint64_t db_stencil_write_base
;
1423 uint64_t db_htile_data_base
;
1424 uint32_t db_depth_info
;
1426 uint32_t db_stencil_info
;
1427 uint32_t db_depth_view
;
1428 uint32_t db_depth_size
;
1429 uint32_t db_depth_slice
;
1430 uint32_t db_htile_surface
;
1431 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1432 uint32_t db_z_info2
;
1433 uint32_t db_stencil_info2
;
1437 struct radv_attachment_info
{
1439 struct radv_color_buffer_info cb
;
1440 struct radv_ds_buffer_info ds
;
1442 struct radv_image_view
*attachment
;
1445 struct radv_framebuffer
{
1450 uint32_t attachment_count
;
1451 struct radv_attachment_info attachments
[0];
1454 struct radv_subpass_barrier
{
1455 VkPipelineStageFlags src_stage_mask
;
1456 VkAccessFlags src_access_mask
;
1457 VkAccessFlags dst_access_mask
;
1460 struct radv_subpass
{
1461 uint32_t input_count
;
1462 uint32_t color_count
;
1463 VkAttachmentReference
* input_attachments
;
1464 VkAttachmentReference
* color_attachments
;
1465 VkAttachmentReference
* resolve_attachments
;
1466 VkAttachmentReference depth_stencil_attachment
;
1468 /** Subpass has at least one resolve attachment */
1471 struct radv_subpass_barrier start_barrier
;
1476 struct radv_render_pass_attachment
{
1479 VkAttachmentLoadOp load_op
;
1480 VkAttachmentLoadOp stencil_load_op
;
1481 VkImageLayout initial_layout
;
1482 VkImageLayout final_layout
;
1486 struct radv_render_pass
{
1487 uint32_t attachment_count
;
1488 uint32_t subpass_count
;
1489 VkAttachmentReference
* subpass_attachments
;
1490 struct radv_render_pass_attachment
* attachments
;
1491 struct radv_subpass_barrier end_barrier
;
1492 struct radv_subpass subpasses
[0];
1495 VkResult
radv_device_init_meta(struct radv_device
*device
);
1496 void radv_device_finish_meta(struct radv_device
*device
);
1498 struct radv_query_pool
{
1499 struct radeon_winsys_bo
*bo
;
1501 uint32_t availability_offset
;
1504 uint32_t pipeline_stats_mask
;
1507 struct radv_semaphore
{
1508 /* use a winsys sem for non-exportable */
1509 struct radeon_winsys_sem
*sem
;
1511 uint32_t temp_syncobj
;
1514 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1516 const VkSemaphore
*wait_sems
,
1517 int num_signal_sems
,
1518 const VkSemaphore
*signal_sems
);
1519 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1522 radv_update_descriptor_sets(struct radv_device
*device
,
1523 struct radv_cmd_buffer
*cmd_buffer
,
1524 VkDescriptorSet overrideSet
,
1525 uint32_t descriptorWriteCount
,
1526 const VkWriteDescriptorSet
*pDescriptorWrites
,
1527 uint32_t descriptorCopyCount
,
1528 const VkCopyDescriptorSet
*pDescriptorCopies
);
1531 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1532 struct radv_cmd_buffer
*cmd_buffer
,
1533 struct radv_descriptor_set
*set
,
1534 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1537 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1538 VkPipelineBindPoint pipelineBindPoint
,
1539 VkPipelineLayout _layout
,
1541 uint32_t descriptorWriteCount
,
1542 const VkWriteDescriptorSet
*pDescriptorWrites
);
1544 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1545 struct radv_image
*image
, uint32_t value
);
1546 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1547 struct radv_image
*image
, uint32_t value
);
1550 struct radeon_winsys_fence
*fence
;
1555 struct radeon_winsys_sem
;
1557 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1559 static inline struct __radv_type * \
1560 __radv_type ## _from_handle(__VkType _handle) \
1562 return (struct __radv_type *) _handle; \
1565 static inline __VkType \
1566 __radv_type ## _to_handle(struct __radv_type *_obj) \
1568 return (__VkType) _obj; \
1571 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1573 static inline struct __radv_type * \
1574 __radv_type ## _from_handle(__VkType _handle) \
1576 return (struct __radv_type *)(uintptr_t) _handle; \
1579 static inline __VkType \
1580 __radv_type ## _to_handle(struct __radv_type *_obj) \
1582 return (__VkType)(uintptr_t) _obj; \
1585 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1586 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1588 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1589 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1590 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1591 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1592 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1594 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1595 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1596 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1597 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1598 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1599 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1600 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1601 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1602 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1603 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1604 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1605 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1606 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1607 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1608 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1609 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1610 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1611 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1612 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1613 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1614 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1616 #endif /* RADV_PRIVATE_H */