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radv: allow to force anisotropy via RADV_TEX_ANISO
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102
103 #define NUM_DEPTH_CLEAR_PIPELINES 3
104
105 /*
106 * This is the point we switch from using CP to compute shader
107 * for certain buffer operations.
108 */
109 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
110
111 enum radv_mem_heap {
112 RADV_MEM_HEAP_VRAM,
113 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
114 RADV_MEM_HEAP_GTT,
115 RADV_MEM_HEAP_COUNT
116 };
117
118 enum radv_mem_type {
119 RADV_MEM_TYPE_VRAM,
120 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
121 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
122 RADV_MEM_TYPE_GTT_CACHED,
123 RADV_MEM_TYPE_COUNT
124 };
125
126 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
127
128 static inline uint32_t
129 align_u32(uint32_t v, uint32_t a)
130 {
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
133 }
134
135 static inline uint32_t
136 align_u32_npot(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a * a;
139 }
140
141 static inline uint64_t
142 align_u64(uint64_t v, uint64_t a)
143 {
144 assert(a != 0 && a == (a & -a));
145 return (v + a - 1) & ~(a - 1);
146 }
147
148 static inline int32_t
149 align_i32(int32_t v, int32_t a)
150 {
151 assert(a != 0 && a == (a & -a));
152 return (v + a - 1) & ~(a - 1);
153 }
154
155 /** Alignment must be a power of 2. */
156 static inline bool
157 radv_is_aligned(uintmax_t n, uintmax_t a)
158 {
159 assert(a == (a & -a));
160 return (n & (a - 1)) == 0;
161 }
162
163 static inline uint32_t
164 round_up_u32(uint32_t v, uint32_t a)
165 {
166 return (v + a - 1) / a;
167 }
168
169 static inline uint64_t
170 round_up_u64(uint64_t v, uint64_t a)
171 {
172 return (v + a - 1) / a;
173 }
174
175 static inline uint32_t
176 radv_minify(uint32_t n, uint32_t levels)
177 {
178 if (unlikely(n == 0))
179 return 0;
180 else
181 return MAX2(n >> levels, 1);
182 }
183 static inline float
184 radv_clamp_f(float f, float min, float max)
185 {
186 assert(min < max);
187
188 if (f > max)
189 return max;
190 else if (f < min)
191 return min;
192 else
193 return f;
194 }
195
196 static inline bool
197 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
198 {
199 if (*inout_mask & clear_mask) {
200 *inout_mask &= ~clear_mask;
201 return true;
202 } else {
203 return false;
204 }
205 }
206
207 #define for_each_bit(b, dword) \
208 for (uint32_t __dword = (dword); \
209 (b) = __builtin_ffs(__dword) - 1, __dword; \
210 __dword &= ~(1 << (b)))
211
212 #define typed_memcpy(dest, src, count) ({ \
213 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
214 memcpy((dest), (src), (count) * sizeof(*(src))); \
215 })
216
217 /* Whenever we generate an error, pass it through this function. Useful for
218 * debugging, where we can break on it. Only call at error site, not when
219 * propagating errors. Might be useful to plug in a stack trace here.
220 */
221
222 struct radv_instance;
223
224 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
225
226 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
227 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
228
229 void __radv_finishme(const char *file, int line, const char *format, ...)
230 radv_printflike(3, 4);
231 void radv_loge(const char *format, ...) radv_printflike(1, 2);
232 void radv_loge_v(const char *format, va_list va);
233 void radv_logi(const char *format, ...) radv_printflike(1, 2);
234 void radv_logi_v(const char *format, va_list va);
235
236 /**
237 * Print a FINISHME message, including its source location.
238 */
239 #define radv_finishme(format, ...) \
240 do { \
241 static bool reported = false; \
242 if (!reported) { \
243 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
244 reported = true; \
245 } \
246 } while (0)
247
248 /* A non-fatal assert. Useful for debugging. */
249 #ifdef DEBUG
250 #define radv_assert(x) ({ \
251 if (unlikely(!(x))) \
252 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
253 })
254 #else
255 #define radv_assert(x)
256 #endif
257
258 #define stub_return(v) \
259 do { \
260 radv_finishme("stub %s", __func__); \
261 return (v); \
262 } while (0)
263
264 #define stub() \
265 do { \
266 radv_finishme("stub %s", __func__); \
267 return; \
268 } while (0)
269
270 void *radv_lookup_entrypoint_unchecked(const char *name);
271 void *radv_lookup_entrypoint_checked(const char *name,
272 uint32_t core_version,
273 const struct radv_instance_extension_table *instance,
274 const struct radv_device_extension_table *device);
275
276 struct radv_physical_device {
277 VK_LOADER_DATA _loader_data;
278
279 struct radv_instance * instance;
280
281 struct radeon_winsys *ws;
282 struct radeon_info rad_info;
283 char path[20];
284 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
285 uint8_t driver_uuid[VK_UUID_SIZE];
286 uint8_t device_uuid[VK_UUID_SIZE];
287 uint8_t cache_uuid[VK_UUID_SIZE];
288
289 int local_fd;
290 int master_fd;
291 struct wsi_device wsi_device;
292
293 bool has_rbplus; /* if RB+ register exist */
294 bool rbplus_allowed; /* if RB+ is allowed */
295 bool has_clear_state;
296 bool cpdma_prefetch_writes_memory;
297 bool has_scissor_bug;
298
299 bool has_out_of_order_rast;
300 bool out_of_order_rast_allowed;
301
302 /* Whether DCC should be enabled for MSAA textures. */
303 bool dcc_msaa_allowed;
304
305 /* This is the drivers on-disk cache used as a fallback as opposed to
306 * the pipeline cache defined by apps.
307 */
308 struct disk_cache * disk_cache;
309
310 VkPhysicalDeviceMemoryProperties memory_properties;
311 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
312
313 struct radv_device_extension_table supported_extensions;
314 };
315
316 struct radv_instance {
317 VK_LOADER_DATA _loader_data;
318
319 VkAllocationCallbacks alloc;
320
321 uint32_t apiVersion;
322 int physicalDeviceCount;
323 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
324
325 uint64_t debug_flags;
326 uint64_t perftest_flags;
327
328 struct vk_debug_report_instance debug_report_callbacks;
329
330 struct radv_instance_extension_table enabled_extensions;
331 };
332
333 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
334 void radv_finish_wsi(struct radv_physical_device *physical_device);
335
336 bool radv_instance_extension_supported(const char *name);
337 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
338 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
339 const char *name);
340
341 struct cache_entry;
342
343 struct radv_pipeline_cache {
344 struct radv_device * device;
345 pthread_mutex_t mutex;
346
347 uint32_t total_size;
348 uint32_t table_size;
349 uint32_t kernel_count;
350 struct cache_entry ** hash_table;
351 bool modified;
352
353 VkAllocationCallbacks alloc;
354 };
355
356 struct radv_pipeline_key {
357 uint32_t instance_rate_inputs;
358 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
359 uint64_t vertex_alpha_adjust;
360 unsigned tess_input_vertices;
361 uint32_t col_format;
362 uint32_t is_int8;
363 uint32_t is_int10;
364 uint8_t log2_ps_iter_samples;
365 uint8_t num_samples;
366 uint32_t has_multiview_view_index : 1;
367 uint32_t optimisations_disabled : 1;
368 };
369
370 void
371 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
372 struct radv_device *device);
373 void
374 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
375 bool
376 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
377 const void *data, size_t size);
378
379 struct radv_shader_variant;
380
381 bool
382 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
383 struct radv_pipeline_cache *cache,
384 const unsigned char *sha1,
385 struct radv_shader_variant **variants);
386
387 void
388 radv_pipeline_cache_insert_shaders(struct radv_device *device,
389 struct radv_pipeline_cache *cache,
390 const unsigned char *sha1,
391 struct radv_shader_variant **variants,
392 const void *const *codes,
393 const unsigned *code_sizes);
394
395 enum radv_blit_ds_layout {
396 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
397 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
398 RADV_BLIT_DS_LAYOUT_COUNT,
399 };
400
401 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
402 {
403 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
404 }
405
406 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
407 {
408 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
409 }
410
411 enum radv_meta_dst_layout {
412 RADV_META_DST_LAYOUT_GENERAL,
413 RADV_META_DST_LAYOUT_OPTIMAL,
414 RADV_META_DST_LAYOUT_COUNT,
415 };
416
417 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
418 {
419 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
420 }
421
422 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
423 {
424 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
425 }
426
427 struct radv_meta_state {
428 VkAllocationCallbacks alloc;
429
430 struct radv_pipeline_cache cache;
431
432 /*
433 * For on-demand pipeline creation, makes sure that
434 * only one thread tries to build a pipeline at the same time.
435 */
436 mtx_t mtx;
437
438 /**
439 * Use array element `i` for images with `2^i` samples.
440 */
441 struct {
442 VkRenderPass render_pass[NUM_META_FS_KEYS];
443 VkPipeline color_pipelines[NUM_META_FS_KEYS];
444
445 VkRenderPass depthstencil_rp;
446 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
447 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
448 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
449 } clear[1 + MAX_SAMPLES_LOG2];
450
451 VkPipelineLayout clear_color_p_layout;
452 VkPipelineLayout clear_depth_p_layout;
453 struct {
454 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
455
456 /** Pipeline that blits from a 1D image. */
457 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
458
459 /** Pipeline that blits from a 2D image. */
460 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
461
462 /** Pipeline that blits from a 3D image. */
463 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
464
465 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
466 VkPipeline depth_only_1d_pipeline;
467 VkPipeline depth_only_2d_pipeline;
468 VkPipeline depth_only_3d_pipeline;
469
470 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
471 VkPipeline stencil_only_1d_pipeline;
472 VkPipeline stencil_only_2d_pipeline;
473 VkPipeline stencil_only_3d_pipeline;
474 VkPipelineLayout pipeline_layout;
475 VkDescriptorSetLayout ds_layout;
476 } blit;
477
478 struct {
479 VkPipelineLayout p_layouts[5];
480 VkDescriptorSetLayout ds_layouts[5];
481 VkPipeline pipelines[5][NUM_META_FS_KEYS];
482
483 VkPipeline depth_only_pipeline[5];
484
485 VkPipeline stencil_only_pipeline[5];
486 } blit2d[1 + MAX_SAMPLES_LOG2];
487
488 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
489 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
490 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
491
492 struct {
493 VkPipelineLayout img_p_layout;
494 VkDescriptorSetLayout img_ds_layout;
495 VkPipeline pipeline;
496 VkPipeline pipeline_3d;
497 } itob;
498 struct {
499 VkPipelineLayout img_p_layout;
500 VkDescriptorSetLayout img_ds_layout;
501 VkPipeline pipeline;
502 VkPipeline pipeline_3d;
503 } btoi;
504 struct {
505 VkPipelineLayout img_p_layout;
506 VkDescriptorSetLayout img_ds_layout;
507 VkPipeline pipeline;
508 VkPipeline pipeline_3d;
509 } itoi;
510 struct {
511 VkPipelineLayout img_p_layout;
512 VkDescriptorSetLayout img_ds_layout;
513 VkPipeline pipeline;
514 VkPipeline pipeline_3d;
515 } cleari;
516
517 struct {
518 VkPipelineLayout p_layout;
519 VkPipeline pipeline[NUM_META_FS_KEYS];
520 VkRenderPass pass[NUM_META_FS_KEYS];
521 } resolve;
522
523 struct {
524 VkDescriptorSetLayout ds_layout;
525 VkPipelineLayout p_layout;
526 struct {
527 VkPipeline pipeline;
528 VkPipeline i_pipeline;
529 VkPipeline srgb_pipeline;
530 } rc[MAX_SAMPLES_LOG2];
531 } resolve_compute;
532
533 struct {
534 VkDescriptorSetLayout ds_layout;
535 VkPipelineLayout p_layout;
536
537 struct {
538 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
539 VkPipeline pipeline[NUM_META_FS_KEYS];
540 } rc[MAX_SAMPLES_LOG2];
541 } resolve_fragment;
542
543 struct {
544 VkPipelineLayout p_layout;
545 VkPipeline decompress_pipeline;
546 VkPipeline resummarize_pipeline;
547 VkRenderPass pass;
548 } depth_decomp[1 + MAX_SAMPLES_LOG2];
549
550 struct {
551 VkPipelineLayout p_layout;
552 VkPipeline cmask_eliminate_pipeline;
553 VkPipeline fmask_decompress_pipeline;
554 VkPipeline dcc_decompress_pipeline;
555 VkRenderPass pass;
556
557 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
558 VkPipelineLayout dcc_decompress_compute_p_layout;
559 VkPipeline dcc_decompress_compute_pipeline;
560 } fast_clear_flush;
561
562 struct {
563 VkPipelineLayout fill_p_layout;
564 VkPipelineLayout copy_p_layout;
565 VkDescriptorSetLayout fill_ds_layout;
566 VkDescriptorSetLayout copy_ds_layout;
567 VkPipeline fill_pipeline;
568 VkPipeline copy_pipeline;
569 } buffer;
570
571 struct {
572 VkDescriptorSetLayout ds_layout;
573 VkPipelineLayout p_layout;
574 VkPipeline occlusion_query_pipeline;
575 VkPipeline pipeline_statistics_query_pipeline;
576 } query;
577 };
578
579 /* queue types */
580 #define RADV_QUEUE_GENERAL 0
581 #define RADV_QUEUE_COMPUTE 1
582 #define RADV_QUEUE_TRANSFER 2
583
584 #define RADV_MAX_QUEUE_FAMILIES 3
585
586 enum ring_type radv_queue_family_to_ring(int f);
587
588 struct radv_queue {
589 VK_LOADER_DATA _loader_data;
590 struct radv_device * device;
591 struct radeon_winsys_ctx *hw_ctx;
592 enum radeon_ctx_priority priority;
593 uint32_t queue_family_index;
594 int queue_idx;
595 VkDeviceQueueCreateFlags flags;
596
597 uint32_t scratch_size;
598 uint32_t compute_scratch_size;
599 uint32_t esgs_ring_size;
600 uint32_t gsvs_ring_size;
601 bool has_tess_rings;
602 bool has_sample_positions;
603
604 struct radeon_winsys_bo *scratch_bo;
605 struct radeon_winsys_bo *descriptor_bo;
606 struct radeon_winsys_bo *compute_scratch_bo;
607 struct radeon_winsys_bo *esgs_ring_bo;
608 struct radeon_winsys_bo *gsvs_ring_bo;
609 struct radeon_winsys_bo *tess_rings_bo;
610 struct radeon_cmdbuf *initial_preamble_cs;
611 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
612 struct radeon_cmdbuf *continue_preamble_cs;
613 };
614
615 struct radv_bo_list {
616 struct radv_winsys_bo_list list;
617 unsigned capacity;
618 pthread_mutex_t mutex;
619 };
620
621 struct radv_device {
622 VK_LOADER_DATA _loader_data;
623
624 VkAllocationCallbacks alloc;
625
626 struct radv_instance * instance;
627 struct radeon_winsys *ws;
628
629 struct radv_meta_state meta_state;
630
631 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
632 int queue_count[RADV_MAX_QUEUE_FAMILIES];
633 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
634
635 bool always_use_syncobj;
636 bool has_distributed_tess;
637 bool pbb_allowed;
638 bool dfsm_allowed;
639 uint32_t tess_offchip_block_dw_size;
640 uint32_t scratch_waves;
641 uint32_t dispatch_initiator;
642
643 uint32_t gs_table_depth;
644
645 /* MSAA sample locations.
646 * The first index is the sample index.
647 * The second index is the coordinate: X, Y. */
648 float sample_locations_1x[1][2];
649 float sample_locations_2x[2][2];
650 float sample_locations_4x[4][2];
651 float sample_locations_8x[8][2];
652 float sample_locations_16x[16][2];
653
654 /* CIK and later */
655 uint32_t gfx_init_size_dw;
656 struct radeon_winsys_bo *gfx_init;
657
658 struct radeon_winsys_bo *trace_bo;
659 uint32_t *trace_id_ptr;
660
661 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
662 bool keep_shader_info;
663
664 struct radv_physical_device *physical_device;
665
666 /* Backup in-memory cache to be used if the app doesn't provide one */
667 struct radv_pipeline_cache * mem_cache;
668
669 /*
670 * use different counters so MSAA MRTs get consecutive surface indices,
671 * even if MASK is allocated in between.
672 */
673 uint32_t image_mrt_offset_counter;
674 uint32_t fmask_mrt_offset_counter;
675 struct list_head shader_slabs;
676 mtx_t shader_slab_mutex;
677
678 /* For detecting VM faults reported by dmesg. */
679 uint64_t dmesg_timestamp;
680
681 struct radv_device_extension_table enabled_extensions;
682
683 /* Whether the driver uses a global BO list. */
684 bool use_global_bo_list;
685
686 struct radv_bo_list bo_list;
687
688 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
689 int force_aniso;
690 };
691
692 struct radv_device_memory {
693 struct radeon_winsys_bo *bo;
694 /* for dedicated allocations */
695 struct radv_image *image;
696 struct radv_buffer *buffer;
697 uint32_t type_index;
698 VkDeviceSize map_size;
699 void * map;
700 void * user_ptr;
701 };
702
703
704 struct radv_descriptor_range {
705 uint64_t va;
706 uint32_t size;
707 };
708
709 struct radv_descriptor_set {
710 const struct radv_descriptor_set_layout *layout;
711 uint32_t size;
712
713 struct radeon_winsys_bo *bo;
714 uint64_t va;
715 uint32_t *mapped_ptr;
716 struct radv_descriptor_range *dynamic_descriptors;
717
718 struct radeon_winsys_bo *descriptors[0];
719 };
720
721 struct radv_push_descriptor_set
722 {
723 struct radv_descriptor_set set;
724 uint32_t capacity;
725 };
726
727 struct radv_descriptor_pool_entry {
728 uint32_t offset;
729 uint32_t size;
730 struct radv_descriptor_set *set;
731 };
732
733 struct radv_descriptor_pool {
734 struct radeon_winsys_bo *bo;
735 uint8_t *mapped_ptr;
736 uint64_t current_offset;
737 uint64_t size;
738
739 uint8_t *host_memory_base;
740 uint8_t *host_memory_ptr;
741 uint8_t *host_memory_end;
742
743 uint32_t entry_count;
744 uint32_t max_entry_count;
745 struct radv_descriptor_pool_entry entries[0];
746 };
747
748 struct radv_descriptor_update_template_entry {
749 VkDescriptorType descriptor_type;
750
751 /* The number of descriptors to update */
752 uint32_t descriptor_count;
753
754 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
755 uint32_t dst_offset;
756
757 /* In dwords. Not valid/used for dynamic descriptors */
758 uint32_t dst_stride;
759
760 uint32_t buffer_offset;
761
762 /* Only valid for combined image samplers and samplers */
763 uint16_t has_sampler;
764
765 /* In bytes */
766 size_t src_offset;
767 size_t src_stride;
768
769 /* For push descriptors */
770 const uint32_t *immutable_samplers;
771 };
772
773 struct radv_descriptor_update_template {
774 uint32_t entry_count;
775 VkPipelineBindPoint bind_point;
776 struct radv_descriptor_update_template_entry entry[0];
777 };
778
779 struct radv_buffer {
780 VkDeviceSize size;
781
782 VkBufferUsageFlags usage;
783 VkBufferCreateFlags flags;
784
785 /* Set when bound */
786 struct radeon_winsys_bo * bo;
787 VkDeviceSize offset;
788
789 bool shareable;
790 };
791
792 enum radv_dynamic_state_bits {
793 RADV_DYNAMIC_VIEWPORT = 1 << 0,
794 RADV_DYNAMIC_SCISSOR = 1 << 1,
795 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
796 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
797 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
798 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
799 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
800 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
801 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
802 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
803 RADV_DYNAMIC_ALL = (1 << 10) - 1,
804 };
805
806 enum radv_cmd_dirty_bits {
807 /* Keep the dynamic state dirty bits in sync with
808 * enum radv_dynamic_state_bits */
809 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
810 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
811 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
812 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
813 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
814 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
815 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
816 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
817 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
818 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
819 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
820 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
821 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
822 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
823 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
824 };
825
826 enum radv_cmd_flush_bits {
827 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
828 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
829 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
830 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
831 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
832 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
833 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
834 /* Same as above, but only writes back and doesn't invalidate */
835 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
836 /* Framebuffer caches */
837 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
838 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
839 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
840 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
841 /* Engine synchronization. */
842 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
843 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
844 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
845 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
846 /* Pipeline query controls. */
847 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
848 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
849
850 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
851 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
852 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
853 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
854 };
855
856 struct radv_vertex_binding {
857 struct radv_buffer * buffer;
858 VkDeviceSize offset;
859 };
860
861 struct radv_viewport_state {
862 uint32_t count;
863 VkViewport viewports[MAX_VIEWPORTS];
864 };
865
866 struct radv_scissor_state {
867 uint32_t count;
868 VkRect2D scissors[MAX_SCISSORS];
869 };
870
871 struct radv_discard_rectangle_state {
872 uint32_t count;
873 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
874 };
875
876 struct radv_dynamic_state {
877 /**
878 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
879 * Defines the set of saved dynamic state.
880 */
881 uint32_t mask;
882
883 struct radv_viewport_state viewport;
884
885 struct radv_scissor_state scissor;
886
887 float line_width;
888
889 struct {
890 float bias;
891 float clamp;
892 float slope;
893 } depth_bias;
894
895 float blend_constants[4];
896
897 struct {
898 float min;
899 float max;
900 } depth_bounds;
901
902 struct {
903 uint32_t front;
904 uint32_t back;
905 } stencil_compare_mask;
906
907 struct {
908 uint32_t front;
909 uint32_t back;
910 } stencil_write_mask;
911
912 struct {
913 uint32_t front;
914 uint32_t back;
915 } stencil_reference;
916
917 struct radv_discard_rectangle_state discard_rectangle;
918 };
919
920 extern const struct radv_dynamic_state default_dynamic_state;
921
922 const char *
923 radv_get_debug_option_name(int id);
924
925 const char *
926 radv_get_perftest_option_name(int id);
927
928 /**
929 * Attachment state when recording a renderpass instance.
930 *
931 * The clear value is valid only if there exists a pending clear.
932 */
933 struct radv_attachment_state {
934 VkImageAspectFlags pending_clear_aspects;
935 uint32_t cleared_views;
936 VkClearValue clear_value;
937 VkImageLayout current_layout;
938 };
939
940 struct radv_descriptor_state {
941 struct radv_descriptor_set *sets[MAX_SETS];
942 uint32_t dirty;
943 uint32_t valid;
944 struct radv_push_descriptor_set push_set;
945 bool push_dirty;
946 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
947 };
948
949 struct radv_cmd_state {
950 /* Vertex descriptors */
951 uint64_t vb_va;
952 unsigned vb_size;
953
954 bool predicating;
955 uint32_t dirty;
956
957 uint32_t prefetch_L2_mask;
958
959 struct radv_pipeline * pipeline;
960 struct radv_pipeline * emitted_pipeline;
961 struct radv_pipeline * compute_pipeline;
962 struct radv_pipeline * emitted_compute_pipeline;
963 struct radv_framebuffer * framebuffer;
964 struct radv_render_pass * pass;
965 const struct radv_subpass * subpass;
966 struct radv_dynamic_state dynamic;
967 struct radv_attachment_state * attachments;
968 VkRect2D render_area;
969
970 /* Index buffer */
971 struct radv_buffer *index_buffer;
972 uint64_t index_offset;
973 uint32_t index_type;
974 uint32_t max_index_count;
975 uint64_t index_va;
976 int32_t last_index_type;
977
978 int32_t last_primitive_reset_en;
979 uint32_t last_primitive_reset_index;
980 enum radv_cmd_flush_bits flush_bits;
981 unsigned active_occlusion_queries;
982 bool perfect_occlusion_queries_enabled;
983 unsigned active_pipeline_queries;
984 float offset_scale;
985 uint32_t trace_id;
986 uint32_t last_ia_multi_vgt_param;
987
988 uint32_t last_num_instances;
989 uint32_t last_first_instance;
990 uint32_t last_vertex_offset;
991
992 /* Whether CP DMA is busy/idle. */
993 bool dma_is_busy;
994
995 /* Conditional rendering info. */
996 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
997 uint64_t predication_va;
998 };
999
1000 struct radv_cmd_pool {
1001 VkAllocationCallbacks alloc;
1002 struct list_head cmd_buffers;
1003 struct list_head free_cmd_buffers;
1004 uint32_t queue_family_index;
1005 };
1006
1007 struct radv_cmd_buffer_upload {
1008 uint8_t *map;
1009 unsigned offset;
1010 uint64_t size;
1011 struct radeon_winsys_bo *upload_bo;
1012 struct list_head list;
1013 };
1014
1015 enum radv_cmd_buffer_status {
1016 RADV_CMD_BUFFER_STATUS_INVALID,
1017 RADV_CMD_BUFFER_STATUS_INITIAL,
1018 RADV_CMD_BUFFER_STATUS_RECORDING,
1019 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1020 RADV_CMD_BUFFER_STATUS_PENDING,
1021 };
1022
1023 struct radv_cmd_buffer {
1024 VK_LOADER_DATA _loader_data;
1025
1026 struct radv_device * device;
1027
1028 struct radv_cmd_pool * pool;
1029 struct list_head pool_link;
1030
1031 VkCommandBufferUsageFlags usage_flags;
1032 VkCommandBufferLevel level;
1033 enum radv_cmd_buffer_status status;
1034 struct radeon_cmdbuf *cs;
1035 struct radv_cmd_state state;
1036 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1037 uint32_t queue_family_index;
1038
1039 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1040 VkShaderStageFlags push_constant_stages;
1041 struct radv_descriptor_set meta_push_descriptors;
1042
1043 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1044
1045 struct radv_cmd_buffer_upload upload;
1046
1047 uint32_t scratch_size_needed;
1048 uint32_t compute_scratch_size_needed;
1049 uint32_t esgs_ring_size_needed;
1050 uint32_t gsvs_ring_size_needed;
1051 bool tess_rings_needed;
1052 bool sample_positions_needed;
1053
1054 VkResult record_result;
1055
1056 uint32_t gfx9_fence_offset;
1057 struct radeon_winsys_bo *gfx9_fence_bo;
1058 uint32_t gfx9_fence_idx;
1059 uint64_t gfx9_eop_bug_va;
1060
1061 /**
1062 * Whether a query pool has been resetted and we have to flush caches.
1063 */
1064 bool pending_reset_query;
1065 };
1066
1067 struct radv_image;
1068
1069 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1070
1071 void si_emit_graphics(struct radv_physical_device *physical_device,
1072 struct radeon_cmdbuf *cs);
1073 void si_emit_compute(struct radv_physical_device *physical_device,
1074 struct radeon_cmdbuf *cs);
1075
1076 void cik_create_gfx_config(struct radv_device *device);
1077
1078 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1079 int count, const VkViewport *viewports);
1080 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1081 int count, const VkRect2D *scissors,
1082 const VkViewport *viewports, bool can_use_guardband);
1083 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1084 bool instanced_draw, bool indirect_draw,
1085 uint32_t draw_vertex_count);
1086 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1087 enum chip_class chip_class,
1088 bool is_mec,
1089 unsigned event, unsigned event_flags,
1090 unsigned data_sel,
1091 uint64_t va,
1092 uint32_t old_fence,
1093 uint32_t new_fence,
1094 uint64_t gfx9_eop_bug_va);
1095
1096 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1097 uint64_t va, uint32_t ref,
1098 uint32_t mask);
1099 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1100 enum chip_class chip_class,
1101 uint32_t *fence_ptr, uint64_t va,
1102 bool is_mec,
1103 enum radv_cmd_flush_bits flush_bits,
1104 uint64_t gfx9_eop_bug_va);
1105 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1106 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1107 bool inverted, uint64_t va);
1108 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1109 uint64_t src_va, uint64_t dest_va,
1110 uint64_t size);
1111 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1112 unsigned size);
1113 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1114 uint64_t size, unsigned value);
1115 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1116
1117 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1118 bool
1119 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1120 unsigned size,
1121 unsigned alignment,
1122 unsigned *out_offset,
1123 void **ptr);
1124 void
1125 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1126 const struct radv_subpass *subpass,
1127 bool transitions);
1128 bool
1129 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1130 unsigned size, unsigned alignmnet,
1131 const void *data, unsigned *out_offset);
1132
1133 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1134 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1135 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1136 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1137 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1138 unsigned radv_cayman_get_maxdist(int log_samples);
1139 void radv_device_init_msaa(struct radv_device *device);
1140
1141 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1142 struct radv_image *image,
1143 VkClearDepthStencilValue ds_clear_value,
1144 VkImageAspectFlags aspects);
1145
1146 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1147 struct radv_image *image,
1148 int cb_idx,
1149 uint32_t color_values[2]);
1150
1151 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1152 struct radv_image *image,
1153 bool value);
1154 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1155 struct radeon_winsys_bo *bo,
1156 uint64_t offset, uint64_t size, uint32_t value);
1157 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1158 bool radv_get_memory_fd(struct radv_device *device,
1159 struct radv_device_memory *memory,
1160 int *pFD);
1161
1162 static inline void
1163 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1164 unsigned sh_offset, unsigned pointer_count,
1165 bool use_32bit_pointers)
1166 {
1167 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1168 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1169 }
1170
1171 static inline void
1172 radv_emit_shader_pointer_body(struct radv_device *device,
1173 struct radeon_cmdbuf *cs,
1174 uint64_t va, bool use_32bit_pointers)
1175 {
1176 radeon_emit(cs, va);
1177
1178 if (use_32bit_pointers) {
1179 assert(va == 0 ||
1180 (va >> 32) == device->physical_device->rad_info.address32_hi);
1181 } else {
1182 radeon_emit(cs, va >> 32);
1183 }
1184 }
1185
1186 static inline void
1187 radv_emit_shader_pointer(struct radv_device *device,
1188 struct radeon_cmdbuf *cs,
1189 uint32_t sh_offset, uint64_t va, bool global)
1190 {
1191 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1192
1193 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1194 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1195 }
1196
1197 static inline struct radv_descriptor_state *
1198 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1199 VkPipelineBindPoint bind_point)
1200 {
1201 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1202 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1203 return &cmd_buffer->descriptors[bind_point];
1204 }
1205
1206 /*
1207 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1208 *
1209 * Limitations: Can't call normal dispatch functions without binding or rebinding
1210 * the compute pipeline.
1211 */
1212 void radv_unaligned_dispatch(
1213 struct radv_cmd_buffer *cmd_buffer,
1214 uint32_t x,
1215 uint32_t y,
1216 uint32_t z);
1217
1218 struct radv_event {
1219 struct radeon_winsys_bo *bo;
1220 uint64_t *map;
1221 };
1222
1223 struct radv_shader_module;
1224
1225 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1226 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1227 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1228 void
1229 radv_hash_shaders(unsigned char *hash,
1230 const VkPipelineShaderStageCreateInfo **stages,
1231 const struct radv_pipeline_layout *layout,
1232 const struct radv_pipeline_key *key,
1233 uint32_t flags);
1234
1235 static inline gl_shader_stage
1236 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1237 {
1238 assert(__builtin_popcount(vk_stage) == 1);
1239 return ffs(vk_stage) - 1;
1240 }
1241
1242 static inline VkShaderStageFlagBits
1243 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1244 {
1245 return (1 << mesa_stage);
1246 }
1247
1248 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1249
1250 #define radv_foreach_stage(stage, stage_bits) \
1251 for (gl_shader_stage stage, \
1252 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1253 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1254 __tmp &= ~(1 << (stage)))
1255
1256 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1257 unsigned radv_format_meta_fs_key(VkFormat format);
1258
1259 struct radv_multisample_state {
1260 uint32_t db_eqaa;
1261 uint32_t pa_sc_line_cntl;
1262 uint32_t pa_sc_mode_cntl_0;
1263 uint32_t pa_sc_mode_cntl_1;
1264 uint32_t pa_sc_aa_config;
1265 uint32_t pa_sc_aa_mask[2];
1266 unsigned num_samples;
1267 };
1268
1269 struct radv_prim_vertex_count {
1270 uint8_t min;
1271 uint8_t incr;
1272 };
1273
1274 struct radv_vertex_elements_info {
1275 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1276 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1277 uint32_t binding[MAX_VERTEX_ATTRIBS];
1278 uint32_t offset[MAX_VERTEX_ATTRIBS];
1279 uint32_t count;
1280 };
1281
1282 struct radv_ia_multi_vgt_param_helpers {
1283 uint32_t base;
1284 bool partial_es_wave;
1285 uint8_t primgroup_size;
1286 bool wd_switch_on_eop;
1287 bool ia_switch_on_eoi;
1288 bool partial_vs_wave;
1289 };
1290
1291 #define SI_GS_PER_ES 128
1292
1293 struct radv_pipeline {
1294 struct radv_device * device;
1295 struct radv_dynamic_state dynamic_state;
1296
1297 struct radv_pipeline_layout * layout;
1298
1299 bool need_indirect_descriptor_sets;
1300 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1301 struct radv_shader_variant *gs_copy_shader;
1302 VkShaderStageFlags active_stages;
1303
1304 struct radeon_cmdbuf cs;
1305
1306 struct radv_vertex_elements_info vertex_elements;
1307
1308 uint32_t binding_stride[MAX_VBS];
1309
1310 uint32_t user_data_0[MESA_SHADER_STAGES];
1311 union {
1312 struct {
1313 struct radv_multisample_state ms;
1314 uint32_t spi_baryc_cntl;
1315 bool prim_restart_enable;
1316 unsigned esgs_ring_size;
1317 unsigned gsvs_ring_size;
1318 uint32_t vtx_base_sgpr;
1319 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1320 uint8_t vtx_emit_num;
1321 struct radv_prim_vertex_count prim_vertex_count;
1322 bool can_use_guardband;
1323 uint32_t needed_dynamic_state;
1324 bool disable_out_of_order_rast_for_occlusion;
1325
1326 /* Used for rbplus */
1327 uint32_t col_format;
1328 uint32_t cb_target_mask;
1329 } graphics;
1330 };
1331
1332 unsigned max_waves;
1333 unsigned scratch_bytes_per_wave;
1334 };
1335
1336 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1337 {
1338 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1339 }
1340
1341 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1342 {
1343 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1344 }
1345
1346 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1347 gl_shader_stage stage,
1348 int idx);
1349
1350 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1351 gl_shader_stage stage);
1352
1353 struct radv_graphics_pipeline_create_info {
1354 bool use_rectlist;
1355 bool db_depth_clear;
1356 bool db_stencil_clear;
1357 bool db_depth_disable_expclear;
1358 bool db_stencil_disable_expclear;
1359 bool db_flush_depth_inplace;
1360 bool db_flush_stencil_inplace;
1361 bool db_resummarize;
1362 uint32_t custom_blend_mode;
1363 };
1364
1365 VkResult
1366 radv_graphics_pipeline_create(VkDevice device,
1367 VkPipelineCache cache,
1368 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1369 const struct radv_graphics_pipeline_create_info *extra,
1370 const VkAllocationCallbacks *alloc,
1371 VkPipeline *pPipeline);
1372
1373 struct vk_format_description;
1374 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1375 int first_non_void);
1376 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1377 int first_non_void);
1378 uint32_t radv_translate_colorformat(VkFormat format);
1379 uint32_t radv_translate_color_numformat(VkFormat format,
1380 const struct vk_format_description *desc,
1381 int first_non_void);
1382 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1383 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1384 uint32_t radv_translate_dbformat(VkFormat format);
1385 uint32_t radv_translate_tex_dataformat(VkFormat format,
1386 const struct vk_format_description *desc,
1387 int first_non_void);
1388 uint32_t radv_translate_tex_numformat(VkFormat format,
1389 const struct vk_format_description *desc,
1390 int first_non_void);
1391 bool radv_format_pack_clear_color(VkFormat format,
1392 uint32_t clear_vals[2],
1393 VkClearColorValue *value);
1394 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1395 bool radv_dcc_formats_compatible(VkFormat format1,
1396 VkFormat format2);
1397
1398 struct radv_fmask_info {
1399 uint64_t offset;
1400 uint64_t size;
1401 unsigned alignment;
1402 unsigned pitch_in_pixels;
1403 unsigned bank_height;
1404 unsigned slice_tile_max;
1405 unsigned tile_mode_index;
1406 unsigned tile_swizzle;
1407 };
1408
1409 struct radv_cmask_info {
1410 uint64_t offset;
1411 uint64_t size;
1412 unsigned alignment;
1413 unsigned slice_tile_max;
1414 };
1415
1416 struct radv_image {
1417 VkImageType type;
1418 /* The original VkFormat provided by the client. This may not match any
1419 * of the actual surface formats.
1420 */
1421 VkFormat vk_format;
1422 VkImageAspectFlags aspects;
1423 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1424 struct ac_surf_info info;
1425 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1426 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1427
1428 VkDeviceSize size;
1429 uint32_t alignment;
1430
1431 unsigned queue_family_mask;
1432 bool exclusive;
1433 bool shareable;
1434
1435 /* Set when bound */
1436 struct radeon_winsys_bo *bo;
1437 VkDeviceSize offset;
1438 uint64_t dcc_offset;
1439 uint64_t htile_offset;
1440 bool tc_compatible_htile;
1441 struct radeon_surf surface;
1442
1443 struct radv_fmask_info fmask;
1444 struct radv_cmask_info cmask;
1445 uint64_t clear_value_offset;
1446 uint64_t dcc_pred_offset;
1447
1448 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1449 VkDeviceMemory owned_memory;
1450 };
1451
1452 /* Whether the image has a htile that is known consistent with the contents of
1453 * the image. */
1454 bool radv_layout_has_htile(const struct radv_image *image,
1455 VkImageLayout layout,
1456 unsigned queue_mask);
1457
1458 /* Whether the image has a htile that is known consistent with the contents of
1459 * the image and is allowed to be in compressed form.
1460 *
1461 * If this is false reads that don't use the htile should be able to return
1462 * correct results.
1463 */
1464 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1465 VkImageLayout layout,
1466 unsigned queue_mask);
1467
1468 bool radv_layout_can_fast_clear(const struct radv_image *image,
1469 VkImageLayout layout,
1470 unsigned queue_mask);
1471
1472 bool radv_layout_dcc_compressed(const struct radv_image *image,
1473 VkImageLayout layout,
1474 unsigned queue_mask);
1475
1476 /**
1477 * Return whether the image has CMASK metadata for color surfaces.
1478 */
1479 static inline bool
1480 radv_image_has_cmask(const struct radv_image *image)
1481 {
1482 return image->cmask.size;
1483 }
1484
1485 /**
1486 * Return whether the image has FMASK metadata for color surfaces.
1487 */
1488 static inline bool
1489 radv_image_has_fmask(const struct radv_image *image)
1490 {
1491 return image->fmask.size;
1492 }
1493
1494 /**
1495 * Return whether the image has DCC metadata for color surfaces.
1496 */
1497 static inline bool
1498 radv_image_has_dcc(const struct radv_image *image)
1499 {
1500 return image->surface.dcc_size;
1501 }
1502
1503 /**
1504 * Return whether DCC metadata is enabled for a level.
1505 */
1506 static inline bool
1507 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1508 {
1509 return radv_image_has_dcc(image) &&
1510 level < image->surface.num_dcc_levels;
1511 }
1512
1513 /**
1514 * Return whether the image has CB metadata.
1515 */
1516 static inline bool
1517 radv_image_has_CB_metadata(const struct radv_image *image)
1518 {
1519 return radv_image_has_cmask(image) ||
1520 radv_image_has_fmask(image) ||
1521 radv_image_has_dcc(image);
1522 }
1523
1524 /**
1525 * Return whether the image has HTILE metadata for depth surfaces.
1526 */
1527 static inline bool
1528 radv_image_has_htile(const struct radv_image *image)
1529 {
1530 return image->surface.htile_size;
1531 }
1532
1533 /**
1534 * Return whether HTILE metadata is enabled for a level.
1535 */
1536 static inline bool
1537 radv_htile_enabled(const struct radv_image *image, unsigned level)
1538 {
1539 return radv_image_has_htile(image) && level == 0;
1540 }
1541
1542 /**
1543 * Return whether the image is TC-compatible HTILE.
1544 */
1545 static inline bool
1546 radv_image_is_tc_compat_htile(const struct radv_image *image)
1547 {
1548 return radv_image_has_htile(image) && image->tc_compatible_htile;
1549 }
1550
1551 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1552
1553 static inline uint32_t
1554 radv_get_layerCount(const struct radv_image *image,
1555 const VkImageSubresourceRange *range)
1556 {
1557 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1558 image->info.array_size - range->baseArrayLayer : range->layerCount;
1559 }
1560
1561 static inline uint32_t
1562 radv_get_levelCount(const struct radv_image *image,
1563 const VkImageSubresourceRange *range)
1564 {
1565 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1566 image->info.levels - range->baseMipLevel : range->levelCount;
1567 }
1568
1569 struct radeon_bo_metadata;
1570 void
1571 radv_init_metadata(struct radv_device *device,
1572 struct radv_image *image,
1573 struct radeon_bo_metadata *metadata);
1574
1575 struct radv_image_view {
1576 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1577 struct radeon_winsys_bo *bo;
1578
1579 VkImageViewType type;
1580 VkImageAspectFlags aspect_mask;
1581 VkFormat vk_format;
1582 uint32_t base_layer;
1583 uint32_t layer_count;
1584 uint32_t base_mip;
1585 uint32_t level_count;
1586 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1587
1588 uint32_t descriptor[16];
1589
1590 /* Descriptor for use as a storage image as opposed to a sampled image.
1591 * This has a few differences for cube maps (e.g. type).
1592 */
1593 uint32_t storage_descriptor[16];
1594 };
1595
1596 struct radv_image_create_info {
1597 const VkImageCreateInfo *vk_info;
1598 bool scanout;
1599 bool no_metadata_planes;
1600 };
1601
1602 VkResult radv_image_create(VkDevice _device,
1603 const struct radv_image_create_info *info,
1604 const VkAllocationCallbacks* alloc,
1605 VkImage *pImage);
1606
1607 VkResult
1608 radv_image_from_gralloc(VkDevice device_h,
1609 const VkImageCreateInfo *base_info,
1610 const VkNativeBufferANDROID *gralloc_info,
1611 const VkAllocationCallbacks *alloc,
1612 VkImage *out_image_h);
1613
1614 void radv_image_view_init(struct radv_image_view *view,
1615 struct radv_device *device,
1616 const VkImageViewCreateInfo* pCreateInfo);
1617
1618 struct radv_buffer_view {
1619 struct radeon_winsys_bo *bo;
1620 VkFormat vk_format;
1621 uint64_t range; /**< VkBufferViewCreateInfo::range */
1622 uint32_t state[4];
1623 };
1624 void radv_buffer_view_init(struct radv_buffer_view *view,
1625 struct radv_device *device,
1626 const VkBufferViewCreateInfo* pCreateInfo);
1627
1628 static inline struct VkExtent3D
1629 radv_sanitize_image_extent(const VkImageType imageType,
1630 const struct VkExtent3D imageExtent)
1631 {
1632 switch (imageType) {
1633 case VK_IMAGE_TYPE_1D:
1634 return (VkExtent3D) { imageExtent.width, 1, 1 };
1635 case VK_IMAGE_TYPE_2D:
1636 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1637 case VK_IMAGE_TYPE_3D:
1638 return imageExtent;
1639 default:
1640 unreachable("invalid image type");
1641 }
1642 }
1643
1644 static inline struct VkOffset3D
1645 radv_sanitize_image_offset(const VkImageType imageType,
1646 const struct VkOffset3D imageOffset)
1647 {
1648 switch (imageType) {
1649 case VK_IMAGE_TYPE_1D:
1650 return (VkOffset3D) { imageOffset.x, 0, 0 };
1651 case VK_IMAGE_TYPE_2D:
1652 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1653 case VK_IMAGE_TYPE_3D:
1654 return imageOffset;
1655 default:
1656 unreachable("invalid image type");
1657 }
1658 }
1659
1660 static inline bool
1661 radv_image_extent_compare(const struct radv_image *image,
1662 const VkExtent3D *extent)
1663 {
1664 if (extent->width != image->info.width ||
1665 extent->height != image->info.height ||
1666 extent->depth != image->info.depth)
1667 return false;
1668 return true;
1669 }
1670
1671 struct radv_sampler {
1672 uint32_t state[4];
1673 };
1674
1675 struct radv_color_buffer_info {
1676 uint64_t cb_color_base;
1677 uint64_t cb_color_cmask;
1678 uint64_t cb_color_fmask;
1679 uint64_t cb_dcc_base;
1680 uint32_t cb_color_pitch;
1681 uint32_t cb_color_slice;
1682 uint32_t cb_color_view;
1683 uint32_t cb_color_info;
1684 uint32_t cb_color_attrib;
1685 uint32_t cb_color_attrib2;
1686 uint32_t cb_dcc_control;
1687 uint32_t cb_color_cmask_slice;
1688 uint32_t cb_color_fmask_slice;
1689 };
1690
1691 struct radv_ds_buffer_info {
1692 uint64_t db_z_read_base;
1693 uint64_t db_stencil_read_base;
1694 uint64_t db_z_write_base;
1695 uint64_t db_stencil_write_base;
1696 uint64_t db_htile_data_base;
1697 uint32_t db_depth_info;
1698 uint32_t db_z_info;
1699 uint32_t db_stencil_info;
1700 uint32_t db_depth_view;
1701 uint32_t db_depth_size;
1702 uint32_t db_depth_slice;
1703 uint32_t db_htile_surface;
1704 uint32_t pa_su_poly_offset_db_fmt_cntl;
1705 uint32_t db_z_info2;
1706 uint32_t db_stencil_info2;
1707 float offset_scale;
1708 };
1709
1710 struct radv_attachment_info {
1711 union {
1712 struct radv_color_buffer_info cb;
1713 struct radv_ds_buffer_info ds;
1714 };
1715 struct radv_image_view *attachment;
1716 };
1717
1718 struct radv_framebuffer {
1719 uint32_t width;
1720 uint32_t height;
1721 uint32_t layers;
1722
1723 uint32_t attachment_count;
1724 struct radv_attachment_info attachments[0];
1725 };
1726
1727 struct radv_subpass_barrier {
1728 VkPipelineStageFlags src_stage_mask;
1729 VkAccessFlags src_access_mask;
1730 VkAccessFlags dst_access_mask;
1731 };
1732
1733 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1734 const struct radv_subpass_barrier *barrier);
1735
1736 struct radv_subpass_attachment {
1737 uint32_t attachment;
1738 VkImageLayout layout;
1739 };
1740
1741 struct radv_subpass {
1742 uint32_t input_count;
1743 uint32_t color_count;
1744 struct radv_subpass_attachment * input_attachments;
1745 struct radv_subpass_attachment * color_attachments;
1746 struct radv_subpass_attachment * resolve_attachments;
1747 struct radv_subpass_attachment depth_stencil_attachment;
1748
1749 /** Subpass has at least one resolve attachment */
1750 bool has_resolve;
1751
1752 struct radv_subpass_barrier start_barrier;
1753
1754 uint32_t view_mask;
1755 VkSampleCountFlagBits max_sample_count;
1756 };
1757
1758 struct radv_render_pass_attachment {
1759 VkFormat format;
1760 uint32_t samples;
1761 VkAttachmentLoadOp load_op;
1762 VkAttachmentLoadOp stencil_load_op;
1763 VkImageLayout initial_layout;
1764 VkImageLayout final_layout;
1765 uint32_t view_mask;
1766 };
1767
1768 struct radv_render_pass {
1769 uint32_t attachment_count;
1770 uint32_t subpass_count;
1771 struct radv_subpass_attachment * subpass_attachments;
1772 struct radv_render_pass_attachment * attachments;
1773 struct radv_subpass_barrier end_barrier;
1774 struct radv_subpass subpasses[0];
1775 };
1776
1777 VkResult radv_device_init_meta(struct radv_device *device);
1778 void radv_device_finish_meta(struct radv_device *device);
1779
1780 struct radv_query_pool {
1781 struct radeon_winsys_bo *bo;
1782 uint32_t stride;
1783 uint32_t availability_offset;
1784 uint64_t size;
1785 char *ptr;
1786 VkQueryType type;
1787 uint32_t pipeline_stats_mask;
1788 };
1789
1790 struct radv_semaphore {
1791 /* use a winsys sem for non-exportable */
1792 struct radeon_winsys_sem *sem;
1793 uint32_t syncobj;
1794 uint32_t temp_syncobj;
1795 };
1796
1797 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1798 VkPipelineBindPoint bind_point,
1799 struct radv_descriptor_set *set,
1800 unsigned idx);
1801
1802 void
1803 radv_update_descriptor_sets(struct radv_device *device,
1804 struct radv_cmd_buffer *cmd_buffer,
1805 VkDescriptorSet overrideSet,
1806 uint32_t descriptorWriteCount,
1807 const VkWriteDescriptorSet *pDescriptorWrites,
1808 uint32_t descriptorCopyCount,
1809 const VkCopyDescriptorSet *pDescriptorCopies);
1810
1811 void
1812 radv_update_descriptor_set_with_template(struct radv_device *device,
1813 struct radv_cmd_buffer *cmd_buffer,
1814 struct radv_descriptor_set *set,
1815 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1816 const void *pData);
1817
1818 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1819 VkPipelineBindPoint pipelineBindPoint,
1820 VkPipelineLayout _layout,
1821 uint32_t set,
1822 uint32_t descriptorWriteCount,
1823 const VkWriteDescriptorSet *pDescriptorWrites);
1824
1825 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1826 struct radv_image *image, uint32_t value);
1827
1828 struct radv_fence {
1829 struct radeon_winsys_fence *fence;
1830 struct wsi_fence *fence_wsi;
1831 bool submitted;
1832 bool signalled;
1833
1834 uint32_t syncobj;
1835 uint32_t temp_syncobj;
1836 };
1837
1838 /* radv_nir_to_llvm.c */
1839 struct radv_shader_variant_info;
1840 struct radv_nir_compiler_options;
1841
1842 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1843 struct nir_shader *geom_shader,
1844 struct ac_shader_binary *binary,
1845 struct ac_shader_config *config,
1846 struct radv_shader_variant_info *shader_info,
1847 const struct radv_nir_compiler_options *option);
1848
1849 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1850 struct ac_shader_binary *binary,
1851 struct ac_shader_config *config,
1852 struct radv_shader_variant_info *shader_info,
1853 struct nir_shader *const *nir,
1854 int nir_count,
1855 const struct radv_nir_compiler_options *options);
1856
1857 /* radv_shader_info.h */
1858 struct radv_shader_info;
1859
1860 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1861 const struct radv_nir_compiler_options *options,
1862 struct radv_shader_info *info);
1863
1864 struct radeon_winsys_sem;
1865
1866 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1867 \
1868 static inline struct __radv_type * \
1869 __radv_type ## _from_handle(__VkType _handle) \
1870 { \
1871 return (struct __radv_type *) _handle; \
1872 } \
1873 \
1874 static inline __VkType \
1875 __radv_type ## _to_handle(struct __radv_type *_obj) \
1876 { \
1877 return (__VkType) _obj; \
1878 }
1879
1880 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1881 \
1882 static inline struct __radv_type * \
1883 __radv_type ## _from_handle(__VkType _handle) \
1884 { \
1885 return (struct __radv_type *)(uintptr_t) _handle; \
1886 } \
1887 \
1888 static inline __VkType \
1889 __radv_type ## _to_handle(struct __radv_type *_obj) \
1890 { \
1891 return (__VkType)(uintptr_t) _obj; \
1892 }
1893
1894 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1895 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1896
1897 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1898 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1899 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1900 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1901 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1902
1903 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1904 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1905 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1906 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1907 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1908 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1909 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1910 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1911 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1912 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1913 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1914 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1915 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1916 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1917 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1918 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1919 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1920 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1921 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1922 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1923 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1924
1925 #endif /* RADV_PRIVATE_H */