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radv: Add option to print errors even in optimized builds.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "radv_descriptor_set.h"
62 #include "radv_extensions.h"
63 #include "radv_cs.h"
64
65 #include <llvm-c/TargetMachine.h>
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vk_icd.h>
77 #include <vulkan/vk_android_native_buffer.h>
78
79 #include "radv_entrypoints.h"
80
81 #include "wsi_common.h"
82
83 #define ATI_VENDOR_ID 0x1002
84
85 #define MAX_VBS 32
86 #define MAX_VERTEX_ATTRIBS 32
87 #define MAX_RTS 8
88 #define MAX_VIEWPORTS 16
89 #define MAX_SCISSORS 16
90 #define MAX_DISCARD_RECTANGLES 4
91 #define MAX_PUSH_CONSTANTS_SIZE 128
92 #define MAX_PUSH_DESCRIPTORS 32
93 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
94 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
95 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
96 #define MAX_SAMPLES_LOG2 4
97 #define NUM_META_FS_KEYS 13
98 #define RADV_MAX_DRM_DEVICES 8
99 #define MAX_VIEWS 8
100
101 #define NUM_DEPTH_CLEAR_PIPELINES 3
102
103 /*
104 * This is the point we switch from using CP to compute shader
105 * for certain buffer operations.
106 */
107 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
108
109 enum radv_mem_heap {
110 RADV_MEM_HEAP_VRAM,
111 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
112 RADV_MEM_HEAP_GTT,
113 RADV_MEM_HEAP_COUNT
114 };
115
116 enum radv_mem_type {
117 RADV_MEM_TYPE_VRAM,
118 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
119 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
120 RADV_MEM_TYPE_GTT_CACHED,
121 RADV_MEM_TYPE_COUNT
122 };
123
124 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
125
126 static inline uint32_t
127 align_u32(uint32_t v, uint32_t a)
128 {
129 assert(a != 0 && a == (a & -a));
130 return (v + a - 1) & ~(a - 1);
131 }
132
133 static inline uint32_t
134 align_u32_npot(uint32_t v, uint32_t a)
135 {
136 return (v + a - 1) / a * a;
137 }
138
139 static inline uint64_t
140 align_u64(uint64_t v, uint64_t a)
141 {
142 assert(a != 0 && a == (a & -a));
143 return (v + a - 1) & ~(a - 1);
144 }
145
146 static inline int32_t
147 align_i32(int32_t v, int32_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 /** Alignment must be a power of 2. */
154 static inline bool
155 radv_is_aligned(uintmax_t n, uintmax_t a)
156 {
157 assert(a == (a & -a));
158 return (n & (a - 1)) == 0;
159 }
160
161 static inline uint32_t
162 round_up_u32(uint32_t v, uint32_t a)
163 {
164 return (v + a - 1) / a;
165 }
166
167 static inline uint64_t
168 round_up_u64(uint64_t v, uint64_t a)
169 {
170 return (v + a - 1) / a;
171 }
172
173 static inline uint32_t
174 radv_minify(uint32_t n, uint32_t levels)
175 {
176 if (unlikely(n == 0))
177 return 0;
178 else
179 return MAX2(n >> levels, 1);
180 }
181 static inline float
182 radv_clamp_f(float f, float min, float max)
183 {
184 assert(min < max);
185
186 if (f > max)
187 return max;
188 else if (f < min)
189 return min;
190 else
191 return f;
192 }
193
194 static inline bool
195 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
196 {
197 if (*inout_mask & clear_mask) {
198 *inout_mask &= ~clear_mask;
199 return true;
200 } else {
201 return false;
202 }
203 }
204
205 #define for_each_bit(b, dword) \
206 for (uint32_t __dword = (dword); \
207 (b) = __builtin_ffs(__dword) - 1, __dword; \
208 __dword &= ~(1 << (b)))
209
210 #define typed_memcpy(dest, src, count) ({ \
211 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
212 memcpy((dest), (src), (count) * sizeof(*(src))); \
213 })
214
215 /* Whenever we generate an error, pass it through this function. Useful for
216 * debugging, where we can break on it. Only call at error site, not when
217 * propagating errors. Might be useful to plug in a stack trace here.
218 */
219
220 struct radv_instance;
221
222 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
223
224 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
225 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
226
227 void __radv_finishme(const char *file, int line, const char *format, ...)
228 radv_printflike(3, 4);
229 void radv_loge(const char *format, ...) radv_printflike(1, 2);
230 void radv_loge_v(const char *format, va_list va);
231
232 /**
233 * Print a FINISHME message, including its source location.
234 */
235 #define radv_finishme(format, ...) \
236 do { \
237 static bool reported = false; \
238 if (!reported) { \
239 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
240 reported = true; \
241 } \
242 } while (0)
243
244 /* A non-fatal assert. Useful for debugging. */
245 #ifdef DEBUG
246 #define radv_assert(x) ({ \
247 if (unlikely(!(x))) \
248 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
249 })
250 #else
251 #define radv_assert(x)
252 #endif
253
254 #define stub_return(v) \
255 do { \
256 radv_finishme("stub %s", __func__); \
257 return (v); \
258 } while (0)
259
260 #define stub() \
261 do { \
262 radv_finishme("stub %s", __func__); \
263 return; \
264 } while (0)
265
266 void *radv_lookup_entrypoint_unchecked(const char *name);
267 void *radv_lookup_entrypoint_checked(const char *name,
268 uint32_t core_version,
269 const struct radv_instance_extension_table *instance,
270 const struct radv_device_extension_table *device);
271
272 struct radv_physical_device {
273 VK_LOADER_DATA _loader_data;
274
275 struct radv_instance * instance;
276
277 struct radeon_winsys *ws;
278 struct radeon_info rad_info;
279 char path[20];
280 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
281 uint8_t driver_uuid[VK_UUID_SIZE];
282 uint8_t device_uuid[VK_UUID_SIZE];
283 uint8_t cache_uuid[VK_UUID_SIZE];
284
285 int local_fd;
286 struct wsi_device wsi_device;
287
288 bool has_rbplus; /* if RB+ register exist */
289 bool rbplus_allowed; /* if RB+ is allowed */
290 bool has_clear_state;
291 bool cpdma_prefetch_writes_memory;
292 bool has_scissor_bug;
293
294 bool has_out_of_order_rast;
295 bool out_of_order_rast_allowed;
296
297 /* Whether DCC should be enabled for MSAA textures. */
298 bool dcc_msaa_allowed;
299
300 /* This is the drivers on-disk cache used as a fallback as opposed to
301 * the pipeline cache defined by apps.
302 */
303 struct disk_cache * disk_cache;
304
305 VkPhysicalDeviceMemoryProperties memory_properties;
306 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
307
308 struct radv_device_extension_table supported_extensions;
309 };
310
311 struct radv_instance {
312 VK_LOADER_DATA _loader_data;
313
314 VkAllocationCallbacks alloc;
315
316 uint32_t apiVersion;
317 int physicalDeviceCount;
318 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
319
320 uint64_t debug_flags;
321 uint64_t perftest_flags;
322
323 struct vk_debug_report_instance debug_report_callbacks;
324
325 struct radv_instance_extension_table enabled_extensions;
326 };
327
328 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
329 void radv_finish_wsi(struct radv_physical_device *physical_device);
330
331 bool radv_instance_extension_supported(const char *name);
332 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
333 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
334 const char *name);
335
336 struct cache_entry;
337
338 struct radv_pipeline_cache {
339 struct radv_device * device;
340 pthread_mutex_t mutex;
341
342 uint32_t total_size;
343 uint32_t table_size;
344 uint32_t kernel_count;
345 struct cache_entry ** hash_table;
346 bool modified;
347
348 VkAllocationCallbacks alloc;
349 };
350
351 struct radv_pipeline_key {
352 uint32_t instance_rate_inputs;
353 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
354 uint64_t vertex_alpha_adjust;
355 unsigned tess_input_vertices;
356 uint32_t col_format;
357 uint32_t is_int8;
358 uint32_t is_int10;
359 uint8_t log2_ps_iter_samples;
360 uint8_t log2_num_samples;
361 uint32_t multisample : 1;
362 uint32_t has_multiview_view_index : 1;
363 uint32_t optimisations_disabled : 1;
364 };
365
366 void
367 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
368 struct radv_device *device);
369 void
370 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
371 void
372 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
373 const void *data, size_t size);
374
375 struct radv_shader_variant;
376
377 bool
378 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
379 struct radv_pipeline_cache *cache,
380 const unsigned char *sha1,
381 struct radv_shader_variant **variants);
382
383 void
384 radv_pipeline_cache_insert_shaders(struct radv_device *device,
385 struct radv_pipeline_cache *cache,
386 const unsigned char *sha1,
387 struct radv_shader_variant **variants,
388 const void *const *codes,
389 const unsigned *code_sizes);
390
391 enum radv_blit_ds_layout {
392 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
393 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
394 RADV_BLIT_DS_LAYOUT_COUNT,
395 };
396
397 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
398 {
399 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
400 }
401
402 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
403 {
404 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
405 }
406
407 enum radv_meta_dst_layout {
408 RADV_META_DST_LAYOUT_GENERAL,
409 RADV_META_DST_LAYOUT_OPTIMAL,
410 RADV_META_DST_LAYOUT_COUNT,
411 };
412
413 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
414 {
415 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
416 }
417
418 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
419 {
420 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
421 }
422
423 struct radv_meta_state {
424 VkAllocationCallbacks alloc;
425
426 struct radv_pipeline_cache cache;
427
428 /**
429 * Use array element `i` for images with `2^i` samples.
430 */
431 struct {
432 VkRenderPass render_pass[NUM_META_FS_KEYS];
433 VkPipeline color_pipelines[NUM_META_FS_KEYS];
434
435 VkRenderPass depthstencil_rp;
436 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
437 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
438 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
439 } clear[1 + MAX_SAMPLES_LOG2];
440
441 VkPipelineLayout clear_color_p_layout;
442 VkPipelineLayout clear_depth_p_layout;
443 struct {
444 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
445
446 /** Pipeline that blits from a 1D image. */
447 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
448
449 /** Pipeline that blits from a 2D image. */
450 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
451
452 /** Pipeline that blits from a 3D image. */
453 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
454
455 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
456 VkPipeline depth_only_1d_pipeline;
457 VkPipeline depth_only_2d_pipeline;
458 VkPipeline depth_only_3d_pipeline;
459
460 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
461 VkPipeline stencil_only_1d_pipeline;
462 VkPipeline stencil_only_2d_pipeline;
463 VkPipeline stencil_only_3d_pipeline;
464 VkPipelineLayout pipeline_layout;
465 VkDescriptorSetLayout ds_layout;
466 } blit;
467
468 struct {
469 VkPipelineLayout p_layouts[5];
470 VkDescriptorSetLayout ds_layouts[5];
471 VkPipeline pipelines[5][NUM_META_FS_KEYS];
472
473 VkPipeline depth_only_pipeline[5];
474
475 VkPipeline stencil_only_pipeline[5];
476 } blit2d[1 + MAX_SAMPLES_LOG2];
477
478 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
479 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
480 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
481
482 struct {
483 VkPipelineLayout img_p_layout;
484 VkDescriptorSetLayout img_ds_layout;
485 VkPipeline pipeline;
486 VkPipeline pipeline_3d;
487 } itob;
488 struct {
489 VkPipelineLayout img_p_layout;
490 VkDescriptorSetLayout img_ds_layout;
491 VkPipeline pipeline;
492 VkPipeline pipeline_3d;
493 } btoi;
494 struct {
495 VkPipelineLayout img_p_layout;
496 VkDescriptorSetLayout img_ds_layout;
497 VkPipeline pipeline;
498 VkPipeline pipeline_3d;
499 } itoi;
500 struct {
501 VkPipelineLayout img_p_layout;
502 VkDescriptorSetLayout img_ds_layout;
503 VkPipeline pipeline;
504 VkPipeline pipeline_3d;
505 } cleari;
506
507 struct {
508 VkPipelineLayout p_layout;
509 VkPipeline pipeline[NUM_META_FS_KEYS];
510 VkRenderPass pass[NUM_META_FS_KEYS];
511 } resolve;
512
513 struct {
514 VkDescriptorSetLayout ds_layout;
515 VkPipelineLayout p_layout;
516 struct {
517 VkPipeline pipeline;
518 VkPipeline i_pipeline;
519 VkPipeline srgb_pipeline;
520 } rc[MAX_SAMPLES_LOG2];
521 } resolve_compute;
522
523 struct {
524 VkDescriptorSetLayout ds_layout;
525 VkPipelineLayout p_layout;
526
527 struct {
528 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
529 VkPipeline pipeline[NUM_META_FS_KEYS];
530 } rc[MAX_SAMPLES_LOG2];
531 } resolve_fragment;
532
533 struct {
534 VkPipelineLayout p_layout;
535 VkPipeline decompress_pipeline;
536 VkPipeline resummarize_pipeline;
537 VkRenderPass pass;
538 } depth_decomp[1 + MAX_SAMPLES_LOG2];
539
540 struct {
541 VkPipelineLayout p_layout;
542 VkPipeline cmask_eliminate_pipeline;
543 VkPipeline fmask_decompress_pipeline;
544 VkPipeline dcc_decompress_pipeline;
545 VkRenderPass pass;
546
547 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
548 VkPipelineLayout dcc_decompress_compute_p_layout;
549 VkPipeline dcc_decompress_compute_pipeline;
550 } fast_clear_flush;
551
552 struct {
553 VkPipelineLayout fill_p_layout;
554 VkPipelineLayout copy_p_layout;
555 VkDescriptorSetLayout fill_ds_layout;
556 VkDescriptorSetLayout copy_ds_layout;
557 VkPipeline fill_pipeline;
558 VkPipeline copy_pipeline;
559 } buffer;
560
561 struct {
562 VkDescriptorSetLayout ds_layout;
563 VkPipelineLayout p_layout;
564 VkPipeline occlusion_query_pipeline;
565 VkPipeline pipeline_statistics_query_pipeline;
566 } query;
567 };
568
569 /* queue types */
570 #define RADV_QUEUE_GENERAL 0
571 #define RADV_QUEUE_COMPUTE 1
572 #define RADV_QUEUE_TRANSFER 2
573
574 #define RADV_MAX_QUEUE_FAMILIES 3
575
576 enum ring_type radv_queue_family_to_ring(int f);
577
578 struct radv_queue {
579 VK_LOADER_DATA _loader_data;
580 struct radv_device * device;
581 struct radeon_winsys_ctx *hw_ctx;
582 enum radeon_ctx_priority priority;
583 uint32_t queue_family_index;
584 int queue_idx;
585 VkDeviceQueueCreateFlags flags;
586
587 uint32_t scratch_size;
588 uint32_t compute_scratch_size;
589 uint32_t esgs_ring_size;
590 uint32_t gsvs_ring_size;
591 bool has_tess_rings;
592 bool has_sample_positions;
593
594 struct radeon_winsys_bo *scratch_bo;
595 struct radeon_winsys_bo *descriptor_bo;
596 struct radeon_winsys_bo *compute_scratch_bo;
597 struct radeon_winsys_bo *esgs_ring_bo;
598 struct radeon_winsys_bo *gsvs_ring_bo;
599 struct radeon_winsys_bo *tess_rings_bo;
600 struct radeon_winsys_cs *initial_preamble_cs;
601 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
602 struct radeon_winsys_cs *continue_preamble_cs;
603 };
604
605 struct radv_bo_list {
606 struct radv_winsys_bo_list list;
607 unsigned capacity;
608 pthread_mutex_t mutex;
609 };
610
611 struct radv_device {
612 VK_LOADER_DATA _loader_data;
613
614 VkAllocationCallbacks alloc;
615
616 struct radv_instance * instance;
617 struct radeon_winsys *ws;
618
619 struct radv_meta_state meta_state;
620
621 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
622 int queue_count[RADV_MAX_QUEUE_FAMILIES];
623 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
624
625 bool always_use_syncobj;
626 bool has_distributed_tess;
627 bool pbb_allowed;
628 bool dfsm_allowed;
629 uint32_t tess_offchip_block_dw_size;
630 uint32_t scratch_waves;
631 uint32_t dispatch_initiator;
632
633 uint32_t gs_table_depth;
634
635 /* MSAA sample locations.
636 * The first index is the sample index.
637 * The second index is the coordinate: X, Y. */
638 float sample_locations_1x[1][2];
639 float sample_locations_2x[2][2];
640 float sample_locations_4x[4][2];
641 float sample_locations_8x[8][2];
642 float sample_locations_16x[16][2];
643
644 /* CIK and later */
645 uint32_t gfx_init_size_dw;
646 struct radeon_winsys_bo *gfx_init;
647
648 struct radeon_winsys_bo *trace_bo;
649 uint32_t *trace_id_ptr;
650
651 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
652 bool keep_shader_info;
653
654 struct radv_physical_device *physical_device;
655
656 /* Backup in-memory cache to be used if the app doesn't provide one */
657 struct radv_pipeline_cache * mem_cache;
658
659 /*
660 * use different counters so MSAA MRTs get consecutive surface indices,
661 * even if MASK is allocated in between.
662 */
663 uint32_t image_mrt_offset_counter;
664 uint32_t fmask_mrt_offset_counter;
665 struct list_head shader_slabs;
666 mtx_t shader_slab_mutex;
667
668 /* For detecting VM faults reported by dmesg. */
669 uint64_t dmesg_timestamp;
670
671 struct radv_device_extension_table enabled_extensions;
672
673 /* Whether the driver uses a global BO list. */
674 bool use_global_bo_list;
675
676 struct radv_bo_list bo_list;
677 };
678
679 struct radv_device_memory {
680 struct radeon_winsys_bo *bo;
681 /* for dedicated allocations */
682 struct radv_image *image;
683 struct radv_buffer *buffer;
684 uint32_t type_index;
685 VkDeviceSize map_size;
686 void * map;
687 void * user_ptr;
688 };
689
690
691 struct radv_descriptor_range {
692 uint64_t va;
693 uint32_t size;
694 };
695
696 struct radv_descriptor_set {
697 const struct radv_descriptor_set_layout *layout;
698 uint32_t size;
699
700 struct radeon_winsys_bo *bo;
701 uint64_t va;
702 uint32_t *mapped_ptr;
703 struct radv_descriptor_range *dynamic_descriptors;
704
705 struct radeon_winsys_bo *descriptors[0];
706 };
707
708 struct radv_push_descriptor_set
709 {
710 struct radv_descriptor_set set;
711 uint32_t capacity;
712 };
713
714 struct radv_descriptor_pool_entry {
715 uint32_t offset;
716 uint32_t size;
717 struct radv_descriptor_set *set;
718 };
719
720 struct radv_descriptor_pool {
721 struct radeon_winsys_bo *bo;
722 uint8_t *mapped_ptr;
723 uint64_t current_offset;
724 uint64_t size;
725
726 uint8_t *host_memory_base;
727 uint8_t *host_memory_ptr;
728 uint8_t *host_memory_end;
729
730 uint32_t entry_count;
731 uint32_t max_entry_count;
732 struct radv_descriptor_pool_entry entries[0];
733 };
734
735 struct radv_descriptor_update_template_entry {
736 VkDescriptorType descriptor_type;
737
738 /* The number of descriptors to update */
739 uint32_t descriptor_count;
740
741 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
742 uint32_t dst_offset;
743
744 /* In dwords. Not valid/used for dynamic descriptors */
745 uint32_t dst_stride;
746
747 uint32_t buffer_offset;
748
749 /* Only valid for combined image samplers and samplers */
750 uint16_t has_sampler;
751
752 /* In bytes */
753 size_t src_offset;
754 size_t src_stride;
755
756 /* For push descriptors */
757 const uint32_t *immutable_samplers;
758 };
759
760 struct radv_descriptor_update_template {
761 uint32_t entry_count;
762 VkPipelineBindPoint bind_point;
763 struct radv_descriptor_update_template_entry entry[0];
764 };
765
766 struct radv_buffer {
767 VkDeviceSize size;
768
769 VkBufferUsageFlags usage;
770 VkBufferCreateFlags flags;
771
772 /* Set when bound */
773 struct radeon_winsys_bo * bo;
774 VkDeviceSize offset;
775
776 bool shareable;
777 };
778
779 enum radv_dynamic_state_bits {
780 RADV_DYNAMIC_VIEWPORT = 1 << 0,
781 RADV_DYNAMIC_SCISSOR = 1 << 1,
782 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
783 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
784 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
785 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
786 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
787 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
788 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
789 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
790 RADV_DYNAMIC_ALL = (1 << 10) - 1,
791 };
792
793 enum radv_cmd_dirty_bits {
794 /* Keep the dynamic state dirty bits in sync with
795 * enum radv_dynamic_state_bits */
796 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
797 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
798 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
799 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
800 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
801 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
802 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
803 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
804 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
805 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
806 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
807 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
808 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
809 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
810 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
811 };
812
813 enum radv_cmd_flush_bits {
814 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
815 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
816 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
817 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
818 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
819 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
820 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
821 /* Same as above, but only writes back and doesn't invalidate */
822 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
823 /* Framebuffer caches */
824 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
825 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
826 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
827 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
828 /* Engine synchronization. */
829 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
830 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
831 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
832 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
833
834 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
835 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
836 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
837 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
838 };
839
840 struct radv_vertex_binding {
841 struct radv_buffer * buffer;
842 VkDeviceSize offset;
843 };
844
845 struct radv_viewport_state {
846 uint32_t count;
847 VkViewport viewports[MAX_VIEWPORTS];
848 };
849
850 struct radv_scissor_state {
851 uint32_t count;
852 VkRect2D scissors[MAX_SCISSORS];
853 };
854
855 struct radv_discard_rectangle_state {
856 uint32_t count;
857 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
858 };
859
860 struct radv_dynamic_state {
861 /**
862 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
863 * Defines the set of saved dynamic state.
864 */
865 uint32_t mask;
866
867 struct radv_viewport_state viewport;
868
869 struct radv_scissor_state scissor;
870
871 float line_width;
872
873 struct {
874 float bias;
875 float clamp;
876 float slope;
877 } depth_bias;
878
879 float blend_constants[4];
880
881 struct {
882 float min;
883 float max;
884 } depth_bounds;
885
886 struct {
887 uint32_t front;
888 uint32_t back;
889 } stencil_compare_mask;
890
891 struct {
892 uint32_t front;
893 uint32_t back;
894 } stencil_write_mask;
895
896 struct {
897 uint32_t front;
898 uint32_t back;
899 } stencil_reference;
900
901 struct radv_discard_rectangle_state discard_rectangle;
902 };
903
904 extern const struct radv_dynamic_state default_dynamic_state;
905
906 const char *
907 radv_get_debug_option_name(int id);
908
909 const char *
910 radv_get_perftest_option_name(int id);
911
912 /**
913 * Attachment state when recording a renderpass instance.
914 *
915 * The clear value is valid only if there exists a pending clear.
916 */
917 struct radv_attachment_state {
918 VkImageAspectFlags pending_clear_aspects;
919 uint32_t cleared_views;
920 VkClearValue clear_value;
921 VkImageLayout current_layout;
922 };
923
924 struct radv_descriptor_state {
925 struct radv_descriptor_set *sets[MAX_SETS];
926 uint32_t dirty;
927 uint32_t valid;
928 struct radv_push_descriptor_set push_set;
929 bool push_dirty;
930 };
931
932 struct radv_cmd_state {
933 /* Vertex descriptors */
934 uint64_t vb_va;
935 unsigned vb_size;
936
937 bool predicating;
938 uint32_t dirty;
939
940 uint32_t prefetch_L2_mask;
941
942 struct radv_pipeline * pipeline;
943 struct radv_pipeline * emitted_pipeline;
944 struct radv_pipeline * compute_pipeline;
945 struct radv_pipeline * emitted_compute_pipeline;
946 struct radv_framebuffer * framebuffer;
947 struct radv_render_pass * pass;
948 const struct radv_subpass * subpass;
949 struct radv_dynamic_state dynamic;
950 struct radv_attachment_state * attachments;
951 VkRect2D render_area;
952
953 /* Index buffer */
954 struct radv_buffer *index_buffer;
955 uint64_t index_offset;
956 uint32_t index_type;
957 uint32_t max_index_count;
958 uint64_t index_va;
959 int32_t last_index_type;
960
961 int32_t last_primitive_reset_en;
962 uint32_t last_primitive_reset_index;
963 enum radv_cmd_flush_bits flush_bits;
964 unsigned active_occlusion_queries;
965 bool perfect_occlusion_queries_enabled;
966 float offset_scale;
967 uint32_t trace_id;
968 uint32_t last_ia_multi_vgt_param;
969
970 uint32_t last_num_instances;
971 uint32_t last_first_instance;
972 uint32_t last_vertex_offset;
973 };
974
975 struct radv_cmd_pool {
976 VkAllocationCallbacks alloc;
977 struct list_head cmd_buffers;
978 struct list_head free_cmd_buffers;
979 uint32_t queue_family_index;
980 };
981
982 struct radv_cmd_buffer_upload {
983 uint8_t *map;
984 unsigned offset;
985 uint64_t size;
986 struct radeon_winsys_bo *upload_bo;
987 struct list_head list;
988 };
989
990 enum radv_cmd_buffer_status {
991 RADV_CMD_BUFFER_STATUS_INVALID,
992 RADV_CMD_BUFFER_STATUS_INITIAL,
993 RADV_CMD_BUFFER_STATUS_RECORDING,
994 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
995 RADV_CMD_BUFFER_STATUS_PENDING,
996 };
997
998 struct radv_cmd_buffer {
999 VK_LOADER_DATA _loader_data;
1000
1001 struct radv_device * device;
1002
1003 struct radv_cmd_pool * pool;
1004 struct list_head pool_link;
1005
1006 VkCommandBufferUsageFlags usage_flags;
1007 VkCommandBufferLevel level;
1008 enum radv_cmd_buffer_status status;
1009 struct radeon_winsys_cs *cs;
1010 struct radv_cmd_state state;
1011 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1012 uint32_t queue_family_index;
1013
1014 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1015 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1016 VkShaderStageFlags push_constant_stages;
1017 struct radv_descriptor_set meta_push_descriptors;
1018
1019 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1020
1021 struct radv_cmd_buffer_upload upload;
1022
1023 uint32_t scratch_size_needed;
1024 uint32_t compute_scratch_size_needed;
1025 uint32_t esgs_ring_size_needed;
1026 uint32_t gsvs_ring_size_needed;
1027 bool tess_rings_needed;
1028 bool sample_positions_needed;
1029
1030 VkResult record_result;
1031
1032 int ring_offsets_idx; /* just used for verification */
1033 uint32_t gfx9_fence_offset;
1034 struct radeon_winsys_bo *gfx9_fence_bo;
1035 uint32_t gfx9_fence_idx;
1036
1037 /**
1038 * Whether a query pool has been resetted and we have to flush caches.
1039 */
1040 bool pending_reset_query;
1041 };
1042
1043 struct radv_image;
1044
1045 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1046
1047 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1048 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1049
1050 void cik_create_gfx_config(struct radv_device *device);
1051
1052 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1053 int count, const VkViewport *viewports);
1054 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1055 int count, const VkRect2D *scissors,
1056 const VkViewport *viewports, bool can_use_guardband);
1057 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1058 bool instanced_draw, bool indirect_draw,
1059 uint32_t draw_vertex_count);
1060 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1061 bool predicated,
1062 enum chip_class chip_class,
1063 bool is_mec,
1064 unsigned event, unsigned event_flags,
1065 unsigned data_sel,
1066 uint64_t va,
1067 uint32_t old_fence,
1068 uint32_t new_fence);
1069
1070 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1071 bool predicated,
1072 uint64_t va, uint32_t ref,
1073 uint32_t mask);
1074 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1075 enum chip_class chip_class,
1076 uint32_t *fence_ptr, uint64_t va,
1077 bool is_mec,
1078 enum radv_cmd_flush_bits flush_bits);
1079 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1080 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1081 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1082 uint64_t src_va, uint64_t dest_va,
1083 uint64_t size);
1084 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1085 unsigned size);
1086 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1087 uint64_t size, unsigned value);
1088 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1089 bool
1090 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1091 unsigned size,
1092 unsigned alignment,
1093 unsigned *out_offset,
1094 void **ptr);
1095 void
1096 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1097 const struct radv_subpass *subpass,
1098 bool transitions);
1099 bool
1100 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1101 unsigned size, unsigned alignmnet,
1102 const void *data, unsigned *out_offset);
1103
1104 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1105 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1106 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1107 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1108 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1109 unsigned radv_cayman_get_maxdist(int log_samples);
1110 void radv_device_init_msaa(struct radv_device *device);
1111 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1112 struct radv_image *image,
1113 VkClearDepthStencilValue ds_clear_value,
1114 VkImageAspectFlags aspects);
1115 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1116 struct radv_image *image,
1117 int idx,
1118 uint32_t color_values[2]);
1119 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1120 struct radv_image *image,
1121 bool value);
1122 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1123 struct radeon_winsys_bo *bo,
1124 uint64_t offset, uint64_t size, uint32_t value);
1125 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1126 bool radv_get_memory_fd(struct radv_device *device,
1127 struct radv_device_memory *memory,
1128 int *pFD);
1129
1130 static inline void
1131 radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
1132 unsigned sh_offset, unsigned pointer_count,
1133 bool use_32bit_pointers)
1134 {
1135 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1136 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1137 }
1138
1139 static inline void
1140 radv_emit_shader_pointer_body(struct radv_device *device,
1141 struct radeon_winsys_cs *cs,
1142 uint64_t va, bool use_32bit_pointers)
1143 {
1144 radeon_emit(cs, va);
1145
1146 if (use_32bit_pointers) {
1147 assert(va == 0 ||
1148 (va >> 32) == device->physical_device->rad_info.address32_hi);
1149 } else {
1150 radeon_emit(cs, va >> 32);
1151 }
1152 }
1153
1154 static inline void
1155 radv_emit_shader_pointer(struct radv_device *device,
1156 struct radeon_winsys_cs *cs,
1157 uint32_t sh_offset, uint64_t va, bool global)
1158 {
1159 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1160
1161 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1162 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1163 }
1164
1165 static inline struct radv_descriptor_state *
1166 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1167 VkPipelineBindPoint bind_point)
1168 {
1169 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1170 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1171 return &cmd_buffer->descriptors[bind_point];
1172 }
1173
1174 /*
1175 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1176 *
1177 * Limitations: Can't call normal dispatch functions without binding or rebinding
1178 * the compute pipeline.
1179 */
1180 void radv_unaligned_dispatch(
1181 struct radv_cmd_buffer *cmd_buffer,
1182 uint32_t x,
1183 uint32_t y,
1184 uint32_t z);
1185
1186 struct radv_event {
1187 struct radeon_winsys_bo *bo;
1188 uint64_t *map;
1189 };
1190
1191 struct radv_shader_module;
1192
1193 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1194 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1195 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1196 void
1197 radv_hash_shaders(unsigned char *hash,
1198 const VkPipelineShaderStageCreateInfo **stages,
1199 const struct radv_pipeline_layout *layout,
1200 const struct radv_pipeline_key *key,
1201 uint32_t flags);
1202
1203 static inline gl_shader_stage
1204 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1205 {
1206 assert(__builtin_popcount(vk_stage) == 1);
1207 return ffs(vk_stage) - 1;
1208 }
1209
1210 static inline VkShaderStageFlagBits
1211 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1212 {
1213 return (1 << mesa_stage);
1214 }
1215
1216 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1217
1218 #define radv_foreach_stage(stage, stage_bits) \
1219 for (gl_shader_stage stage, \
1220 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1221 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1222 __tmp &= ~(1 << (stage)))
1223
1224 unsigned radv_format_meta_fs_key(VkFormat format);
1225
1226 struct radv_multisample_state {
1227 uint32_t db_eqaa;
1228 uint32_t pa_sc_line_cntl;
1229 uint32_t pa_sc_mode_cntl_0;
1230 uint32_t pa_sc_mode_cntl_1;
1231 uint32_t pa_sc_aa_config;
1232 uint32_t pa_sc_aa_mask[2];
1233 unsigned num_samples;
1234 };
1235
1236 struct radv_prim_vertex_count {
1237 uint8_t min;
1238 uint8_t incr;
1239 };
1240
1241 struct radv_vertex_elements_info {
1242 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1243 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1244 uint32_t binding[MAX_VERTEX_ATTRIBS];
1245 uint32_t offset[MAX_VERTEX_ATTRIBS];
1246 uint32_t count;
1247 };
1248
1249 struct radv_ia_multi_vgt_param_helpers {
1250 uint32_t base;
1251 bool partial_es_wave;
1252 uint8_t primgroup_size;
1253 bool wd_switch_on_eop;
1254 bool ia_switch_on_eoi;
1255 bool partial_vs_wave;
1256 };
1257
1258 #define SI_GS_PER_ES 128
1259
1260 struct radv_pipeline {
1261 struct radv_device * device;
1262 struct radv_dynamic_state dynamic_state;
1263
1264 struct radv_pipeline_layout * layout;
1265
1266 bool need_indirect_descriptor_sets;
1267 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1268 struct radv_shader_variant *gs_copy_shader;
1269 VkShaderStageFlags active_stages;
1270
1271 struct radeon_winsys_cs cs;
1272
1273 struct radv_vertex_elements_info vertex_elements;
1274
1275 uint32_t binding_stride[MAX_VBS];
1276
1277 uint32_t user_data_0[MESA_SHADER_STAGES];
1278 union {
1279 struct {
1280 struct radv_multisample_state ms;
1281 uint32_t spi_baryc_cntl;
1282 bool prim_restart_enable;
1283 unsigned esgs_ring_size;
1284 unsigned gsvs_ring_size;
1285 uint32_t vtx_base_sgpr;
1286 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1287 uint8_t vtx_emit_num;
1288 struct radv_prim_vertex_count prim_vertex_count;
1289 bool can_use_guardband;
1290 uint32_t needed_dynamic_state;
1291 bool disable_out_of_order_rast_for_occlusion;
1292
1293 /* Used for rbplus */
1294 uint32_t col_format;
1295 uint32_t cb_target_mask;
1296 } graphics;
1297 };
1298
1299 unsigned max_waves;
1300 unsigned scratch_bytes_per_wave;
1301 };
1302
1303 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1304 {
1305 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1306 }
1307
1308 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1309 {
1310 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1311 }
1312
1313 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1314 gl_shader_stage stage,
1315 int idx);
1316
1317 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1318
1319 struct radv_graphics_pipeline_create_info {
1320 bool use_rectlist;
1321 bool db_depth_clear;
1322 bool db_stencil_clear;
1323 bool db_depth_disable_expclear;
1324 bool db_stencil_disable_expclear;
1325 bool db_flush_depth_inplace;
1326 bool db_flush_stencil_inplace;
1327 bool db_resummarize;
1328 uint32_t custom_blend_mode;
1329 };
1330
1331 VkResult
1332 radv_graphics_pipeline_create(VkDevice device,
1333 VkPipelineCache cache,
1334 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1335 const struct radv_graphics_pipeline_create_info *extra,
1336 const VkAllocationCallbacks *alloc,
1337 VkPipeline *pPipeline);
1338
1339 struct vk_format_description;
1340 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1341 int first_non_void);
1342 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1343 int first_non_void);
1344 uint32_t radv_translate_colorformat(VkFormat format);
1345 uint32_t radv_translate_color_numformat(VkFormat format,
1346 const struct vk_format_description *desc,
1347 int first_non_void);
1348 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1349 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1350 uint32_t radv_translate_dbformat(VkFormat format);
1351 uint32_t radv_translate_tex_dataformat(VkFormat format,
1352 const struct vk_format_description *desc,
1353 int first_non_void);
1354 uint32_t radv_translate_tex_numformat(VkFormat format,
1355 const struct vk_format_description *desc,
1356 int first_non_void);
1357 bool radv_format_pack_clear_color(VkFormat format,
1358 uint32_t clear_vals[2],
1359 VkClearColorValue *value);
1360 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1361 bool radv_dcc_formats_compatible(VkFormat format1,
1362 VkFormat format2);
1363
1364 struct radv_fmask_info {
1365 uint64_t offset;
1366 uint64_t size;
1367 unsigned alignment;
1368 unsigned pitch_in_pixels;
1369 unsigned bank_height;
1370 unsigned slice_tile_max;
1371 unsigned tile_mode_index;
1372 unsigned tile_swizzle;
1373 };
1374
1375 struct radv_cmask_info {
1376 uint64_t offset;
1377 uint64_t size;
1378 unsigned alignment;
1379 unsigned slice_tile_max;
1380 };
1381
1382 struct radv_image {
1383 VkImageType type;
1384 /* The original VkFormat provided by the client. This may not match any
1385 * of the actual surface formats.
1386 */
1387 VkFormat vk_format;
1388 VkImageAspectFlags aspects;
1389 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1390 struct ac_surf_info info;
1391 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1392 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1393
1394 VkDeviceSize size;
1395 uint32_t alignment;
1396
1397 unsigned queue_family_mask;
1398 bool exclusive;
1399 bool shareable;
1400
1401 /* Set when bound */
1402 struct radeon_winsys_bo *bo;
1403 VkDeviceSize offset;
1404 uint64_t dcc_offset;
1405 uint64_t htile_offset;
1406 bool tc_compatible_htile;
1407 struct radeon_surf surface;
1408
1409 struct radv_fmask_info fmask;
1410 struct radv_cmask_info cmask;
1411 uint64_t clear_value_offset;
1412 uint64_t dcc_pred_offset;
1413
1414 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1415 VkDeviceMemory owned_memory;
1416 };
1417
1418 /* Whether the image has a htile that is known consistent with the contents of
1419 * the image. */
1420 bool radv_layout_has_htile(const struct radv_image *image,
1421 VkImageLayout layout,
1422 unsigned queue_mask);
1423
1424 /* Whether the image has a htile that is known consistent with the contents of
1425 * the image and is allowed to be in compressed form.
1426 *
1427 * If this is false reads that don't use the htile should be able to return
1428 * correct results.
1429 */
1430 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1431 VkImageLayout layout,
1432 unsigned queue_mask);
1433
1434 bool radv_layout_can_fast_clear(const struct radv_image *image,
1435 VkImageLayout layout,
1436 unsigned queue_mask);
1437
1438 bool radv_layout_dcc_compressed(const struct radv_image *image,
1439 VkImageLayout layout,
1440 unsigned queue_mask);
1441
1442 /**
1443 * Return whether the image has CMASK metadata for color surfaces.
1444 */
1445 static inline bool
1446 radv_image_has_cmask(const struct radv_image *image)
1447 {
1448 return image->cmask.size;
1449 }
1450
1451 /**
1452 * Return whether the image has FMASK metadata for color surfaces.
1453 */
1454 static inline bool
1455 radv_image_has_fmask(const struct radv_image *image)
1456 {
1457 return image->fmask.size;
1458 }
1459
1460 /**
1461 * Return whether the image has DCC metadata for color surfaces.
1462 */
1463 static inline bool
1464 radv_image_has_dcc(const struct radv_image *image)
1465 {
1466 return image->surface.dcc_size;
1467 }
1468
1469 /**
1470 * Return whether DCC metadata is enabled for a level.
1471 */
1472 static inline bool
1473 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1474 {
1475 return radv_image_has_dcc(image) &&
1476 level < image->surface.num_dcc_levels;
1477 }
1478
1479 /**
1480 * Return whether the image has HTILE metadata for depth surfaces.
1481 */
1482 static inline bool
1483 radv_image_has_htile(const struct radv_image *image)
1484 {
1485 return image->surface.htile_size;
1486 }
1487
1488 /**
1489 * Return whether HTILE metadata is enabled for a level.
1490 */
1491 static inline bool
1492 radv_htile_enabled(const struct radv_image *image, unsigned level)
1493 {
1494 return radv_image_has_htile(image) && level == 0;
1495 }
1496
1497 /**
1498 * Return whether the image is TC-compatible HTILE.
1499 */
1500 static inline bool
1501 radv_image_is_tc_compat_htile(const struct radv_image *image)
1502 {
1503 return radv_image_has_htile(image) && image->tc_compatible_htile;
1504 }
1505
1506 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1507
1508 static inline uint32_t
1509 radv_get_layerCount(const struct radv_image *image,
1510 const VkImageSubresourceRange *range)
1511 {
1512 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1513 image->info.array_size - range->baseArrayLayer : range->layerCount;
1514 }
1515
1516 static inline uint32_t
1517 radv_get_levelCount(const struct radv_image *image,
1518 const VkImageSubresourceRange *range)
1519 {
1520 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1521 image->info.levels - range->baseMipLevel : range->levelCount;
1522 }
1523
1524 struct radeon_bo_metadata;
1525 void
1526 radv_init_metadata(struct radv_device *device,
1527 struct radv_image *image,
1528 struct radeon_bo_metadata *metadata);
1529
1530 struct radv_image_view {
1531 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1532 struct radeon_winsys_bo *bo;
1533
1534 VkImageViewType type;
1535 VkImageAspectFlags aspect_mask;
1536 VkFormat vk_format;
1537 uint32_t base_layer;
1538 uint32_t layer_count;
1539 uint32_t base_mip;
1540 uint32_t level_count;
1541 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1542
1543 uint32_t descriptor[16];
1544
1545 /* Descriptor for use as a storage image as opposed to a sampled image.
1546 * This has a few differences for cube maps (e.g. type).
1547 */
1548 uint32_t storage_descriptor[16];
1549 };
1550
1551 struct radv_image_create_info {
1552 const VkImageCreateInfo *vk_info;
1553 bool scanout;
1554 bool no_metadata_planes;
1555 };
1556
1557 VkResult radv_image_create(VkDevice _device,
1558 const struct radv_image_create_info *info,
1559 const VkAllocationCallbacks* alloc,
1560 VkImage *pImage);
1561
1562 VkResult
1563 radv_image_from_gralloc(VkDevice device_h,
1564 const VkImageCreateInfo *base_info,
1565 const VkNativeBufferANDROID *gralloc_info,
1566 const VkAllocationCallbacks *alloc,
1567 VkImage *out_image_h);
1568
1569 void radv_image_view_init(struct radv_image_view *view,
1570 struct radv_device *device,
1571 const VkImageViewCreateInfo* pCreateInfo);
1572
1573 struct radv_buffer_view {
1574 struct radeon_winsys_bo *bo;
1575 VkFormat vk_format;
1576 uint64_t range; /**< VkBufferViewCreateInfo::range */
1577 uint32_t state[4];
1578 };
1579 void radv_buffer_view_init(struct radv_buffer_view *view,
1580 struct radv_device *device,
1581 const VkBufferViewCreateInfo* pCreateInfo);
1582
1583 static inline struct VkExtent3D
1584 radv_sanitize_image_extent(const VkImageType imageType,
1585 const struct VkExtent3D imageExtent)
1586 {
1587 switch (imageType) {
1588 case VK_IMAGE_TYPE_1D:
1589 return (VkExtent3D) { imageExtent.width, 1, 1 };
1590 case VK_IMAGE_TYPE_2D:
1591 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1592 case VK_IMAGE_TYPE_3D:
1593 return imageExtent;
1594 default:
1595 unreachable("invalid image type");
1596 }
1597 }
1598
1599 static inline struct VkOffset3D
1600 radv_sanitize_image_offset(const VkImageType imageType,
1601 const struct VkOffset3D imageOffset)
1602 {
1603 switch (imageType) {
1604 case VK_IMAGE_TYPE_1D:
1605 return (VkOffset3D) { imageOffset.x, 0, 0 };
1606 case VK_IMAGE_TYPE_2D:
1607 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1608 case VK_IMAGE_TYPE_3D:
1609 return imageOffset;
1610 default:
1611 unreachable("invalid image type");
1612 }
1613 }
1614
1615 static inline bool
1616 radv_image_extent_compare(const struct radv_image *image,
1617 const VkExtent3D *extent)
1618 {
1619 if (extent->width != image->info.width ||
1620 extent->height != image->info.height ||
1621 extent->depth != image->info.depth)
1622 return false;
1623 return true;
1624 }
1625
1626 struct radv_sampler {
1627 uint32_t state[4];
1628 };
1629
1630 struct radv_color_buffer_info {
1631 uint64_t cb_color_base;
1632 uint64_t cb_color_cmask;
1633 uint64_t cb_color_fmask;
1634 uint64_t cb_dcc_base;
1635 uint32_t cb_color_pitch;
1636 uint32_t cb_color_slice;
1637 uint32_t cb_color_view;
1638 uint32_t cb_color_info;
1639 uint32_t cb_color_attrib;
1640 uint32_t cb_color_attrib2;
1641 uint32_t cb_dcc_control;
1642 uint32_t cb_color_cmask_slice;
1643 uint32_t cb_color_fmask_slice;
1644 };
1645
1646 struct radv_ds_buffer_info {
1647 uint64_t db_z_read_base;
1648 uint64_t db_stencil_read_base;
1649 uint64_t db_z_write_base;
1650 uint64_t db_stencil_write_base;
1651 uint64_t db_htile_data_base;
1652 uint32_t db_depth_info;
1653 uint32_t db_z_info;
1654 uint32_t db_stencil_info;
1655 uint32_t db_depth_view;
1656 uint32_t db_depth_size;
1657 uint32_t db_depth_slice;
1658 uint32_t db_htile_surface;
1659 uint32_t pa_su_poly_offset_db_fmt_cntl;
1660 uint32_t db_z_info2;
1661 uint32_t db_stencil_info2;
1662 float offset_scale;
1663 };
1664
1665 struct radv_attachment_info {
1666 union {
1667 struct radv_color_buffer_info cb;
1668 struct radv_ds_buffer_info ds;
1669 };
1670 struct radv_image_view *attachment;
1671 };
1672
1673 struct radv_framebuffer {
1674 uint32_t width;
1675 uint32_t height;
1676 uint32_t layers;
1677
1678 uint32_t attachment_count;
1679 struct radv_attachment_info attachments[0];
1680 };
1681
1682 struct radv_subpass_barrier {
1683 VkPipelineStageFlags src_stage_mask;
1684 VkAccessFlags src_access_mask;
1685 VkAccessFlags dst_access_mask;
1686 };
1687
1688 struct radv_subpass {
1689 uint32_t input_count;
1690 uint32_t color_count;
1691 VkAttachmentReference * input_attachments;
1692 VkAttachmentReference * color_attachments;
1693 VkAttachmentReference * resolve_attachments;
1694 VkAttachmentReference depth_stencil_attachment;
1695
1696 /** Subpass has at least one resolve attachment */
1697 bool has_resolve;
1698
1699 struct radv_subpass_barrier start_barrier;
1700
1701 uint32_t view_mask;
1702 VkSampleCountFlagBits max_sample_count;
1703 };
1704
1705 struct radv_render_pass_attachment {
1706 VkFormat format;
1707 uint32_t samples;
1708 VkAttachmentLoadOp load_op;
1709 VkAttachmentLoadOp stencil_load_op;
1710 VkImageLayout initial_layout;
1711 VkImageLayout final_layout;
1712 uint32_t view_mask;
1713 };
1714
1715 struct radv_render_pass {
1716 uint32_t attachment_count;
1717 uint32_t subpass_count;
1718 VkAttachmentReference * subpass_attachments;
1719 struct radv_render_pass_attachment * attachments;
1720 struct radv_subpass_barrier end_barrier;
1721 struct radv_subpass subpasses[0];
1722 };
1723
1724 VkResult radv_device_init_meta(struct radv_device *device);
1725 void radv_device_finish_meta(struct radv_device *device);
1726
1727 struct radv_query_pool {
1728 struct radeon_winsys_bo *bo;
1729 uint32_t stride;
1730 uint32_t availability_offset;
1731 uint64_t size;
1732 char *ptr;
1733 VkQueryType type;
1734 uint32_t pipeline_stats_mask;
1735 };
1736
1737 struct radv_semaphore {
1738 /* use a winsys sem for non-exportable */
1739 struct radeon_winsys_sem *sem;
1740 uint32_t syncobj;
1741 uint32_t temp_syncobj;
1742 };
1743
1744 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1745 VkPipelineBindPoint bind_point,
1746 struct radv_descriptor_set *set,
1747 unsigned idx);
1748
1749 void
1750 radv_update_descriptor_sets(struct radv_device *device,
1751 struct radv_cmd_buffer *cmd_buffer,
1752 VkDescriptorSet overrideSet,
1753 uint32_t descriptorWriteCount,
1754 const VkWriteDescriptorSet *pDescriptorWrites,
1755 uint32_t descriptorCopyCount,
1756 const VkCopyDescriptorSet *pDescriptorCopies);
1757
1758 void
1759 radv_update_descriptor_set_with_template(struct radv_device *device,
1760 struct radv_cmd_buffer *cmd_buffer,
1761 struct radv_descriptor_set *set,
1762 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1763 const void *pData);
1764
1765 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1766 VkPipelineBindPoint pipelineBindPoint,
1767 VkPipelineLayout _layout,
1768 uint32_t set,
1769 uint32_t descriptorWriteCount,
1770 const VkWriteDescriptorSet *pDescriptorWrites);
1771
1772 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1773 struct radv_image *image, uint32_t value);
1774
1775 struct radv_fence {
1776 struct radeon_winsys_fence *fence;
1777 bool submitted;
1778 bool signalled;
1779
1780 uint32_t syncobj;
1781 uint32_t temp_syncobj;
1782 };
1783
1784 /* radv_nir_to_llvm.c */
1785 struct radv_shader_variant_info;
1786 struct radv_nir_compiler_options;
1787
1788 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1789 struct nir_shader *geom_shader,
1790 struct ac_shader_binary *binary,
1791 struct ac_shader_config *config,
1792 struct radv_shader_variant_info *shader_info,
1793 const struct radv_nir_compiler_options *option);
1794
1795 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1796 struct ac_shader_binary *binary,
1797 struct ac_shader_config *config,
1798 struct radv_shader_variant_info *shader_info,
1799 struct nir_shader *const *nir,
1800 int nir_count,
1801 const struct radv_nir_compiler_options *options);
1802
1803 /* radv_shader_info.h */
1804 struct radv_shader_info;
1805
1806 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1807 const struct radv_nir_compiler_options *options,
1808 struct radv_shader_info *info);
1809
1810 struct radeon_winsys_sem;
1811
1812 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1813 \
1814 static inline struct __radv_type * \
1815 __radv_type ## _from_handle(__VkType _handle) \
1816 { \
1817 return (struct __radv_type *) _handle; \
1818 } \
1819 \
1820 static inline __VkType \
1821 __radv_type ## _to_handle(struct __radv_type *_obj) \
1822 { \
1823 return (__VkType) _obj; \
1824 }
1825
1826 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1827 \
1828 static inline struct __radv_type * \
1829 __radv_type ## _from_handle(__VkType _handle) \
1830 { \
1831 return (struct __radv_type *)(uintptr_t) _handle; \
1832 } \
1833 \
1834 static inline __VkType \
1835 __radv_type ## _to_handle(struct __radv_type *_obj) \
1836 { \
1837 return (__VkType)(uintptr_t) _obj; \
1838 }
1839
1840 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1841 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1842
1843 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1844 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1845 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1846 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1847 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1848
1849 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1850 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1851 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1852 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1853 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1854 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1855 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1856 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1857 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1858 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1859 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1860 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1861 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1862 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1863 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1864 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1865 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1866 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1867 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1868 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1869 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1870
1871 #endif /* RADV_PRIVATE_H */