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radv: add a predicate for reflecting DCC decompression state
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102 #define MAX_SO_STREAMS 4
103 #define MAX_SO_BUFFERS 4
104 #define MAX_SO_OUTPUTS 64
105
106 #define NUM_DEPTH_CLEAR_PIPELINES 3
107
108 /*
109 * This is the point we switch from using CP to compute shader
110 * for certain buffer operations.
111 */
112 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113
114 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
115
116 enum radv_mem_heap {
117 RADV_MEM_HEAP_VRAM,
118 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
119 RADV_MEM_HEAP_GTT,
120 RADV_MEM_HEAP_COUNT
121 };
122
123 enum radv_mem_type {
124 RADV_MEM_TYPE_VRAM,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
127 RADV_MEM_TYPE_GTT_CACHED,
128 RADV_MEM_TYPE_COUNT
129 };
130
131 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
132
133 static inline uint32_t
134 align_u32(uint32_t v, uint32_t a)
135 {
136 assert(a != 0 && a == (a & -a));
137 return (v + a - 1) & ~(a - 1);
138 }
139
140 static inline uint32_t
141 align_u32_npot(uint32_t v, uint32_t a)
142 {
143 return (v + a - 1) / a * a;
144 }
145
146 static inline uint64_t
147 align_u64(uint64_t v, uint64_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 static inline int32_t
154 align_i32(int32_t v, int32_t a)
155 {
156 assert(a != 0 && a == (a & -a));
157 return (v + a - 1) & ~(a - 1);
158 }
159
160 /** Alignment must be a power of 2. */
161 static inline bool
162 radv_is_aligned(uintmax_t n, uintmax_t a)
163 {
164 assert(a == (a & -a));
165 return (n & (a - 1)) == 0;
166 }
167
168 static inline uint32_t
169 round_up_u32(uint32_t v, uint32_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint64_t
175 round_up_u64(uint64_t v, uint64_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint32_t
181 radv_minify(uint32_t n, uint32_t levels)
182 {
183 if (unlikely(n == 0))
184 return 0;
185 else
186 return MAX2(n >> levels, 1);
187 }
188 static inline float
189 radv_clamp_f(float f, float min, float max)
190 {
191 assert(min < max);
192
193 if (f > max)
194 return max;
195 else if (f < min)
196 return min;
197 else
198 return f;
199 }
200
201 static inline bool
202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
203 {
204 if (*inout_mask & clear_mask) {
205 *inout_mask &= ~clear_mask;
206 return true;
207 } else {
208 return false;
209 }
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Whenever we generate an error, pass it through this function. Useful for
223 * debugging, where we can break on it. Only call at error site, not when
224 * propagating errors. Might be useful to plug in a stack trace here.
225 */
226
227 struct radv_instance;
228
229 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
230
231 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
232 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
233
234 void __radv_finishme(const char *file, int line, const char *format, ...)
235 radv_printflike(3, 4);
236 void radv_loge(const char *format, ...) radv_printflike(1, 2);
237 void radv_loge_v(const char *format, va_list va);
238 void radv_logi(const char *format, ...) radv_printflike(1, 2);
239 void radv_logi_v(const char *format, va_list va);
240
241 /**
242 * Print a FINISHME message, including its source location.
243 */
244 #define radv_finishme(format, ...) \
245 do { \
246 static bool reported = false; \
247 if (!reported) { \
248 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 reported = true; \
250 } \
251 } while (0)
252
253 /* A non-fatal assert. Useful for debugging. */
254 #ifdef DEBUG
255 #define radv_assert(x) ({ \
256 if (unlikely(!(x))) \
257 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
258 })
259 #else
260 #define radv_assert(x)
261 #endif
262
263 #define stub_return(v) \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return (v); \
267 } while (0)
268
269 #define stub() \
270 do { \
271 radv_finishme("stub %s", __func__); \
272 return; \
273 } while (0)
274
275 void *radv_lookup_entrypoint_unchecked(const char *name);
276 void *radv_lookup_entrypoint_checked(const char *name,
277 uint32_t core_version,
278 const struct radv_instance_extension_table *instance,
279 const struct radv_device_extension_table *device);
280
281 struct radv_physical_device {
282 VK_LOADER_DATA _loader_data;
283
284 struct radv_instance * instance;
285
286 struct radeon_winsys *ws;
287 struct radeon_info rad_info;
288 char path[20];
289 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
290 uint8_t driver_uuid[VK_UUID_SIZE];
291 uint8_t device_uuid[VK_UUID_SIZE];
292 uint8_t cache_uuid[VK_UUID_SIZE];
293
294 int local_fd;
295 int master_fd;
296 struct wsi_device wsi_device;
297
298 bool has_rbplus; /* if RB+ register exist */
299 bool rbplus_allowed; /* if RB+ is allowed */
300 bool has_clear_state;
301 bool cpdma_prefetch_writes_memory;
302 bool has_scissor_bug;
303
304 bool has_out_of_order_rast;
305 bool out_of_order_rast_allowed;
306
307 /* Whether DCC should be enabled for MSAA textures. */
308 bool dcc_msaa_allowed;
309
310 /* This is the drivers on-disk cache used as a fallback as opposed to
311 * the pipeline cache defined by apps.
312 */
313 struct disk_cache * disk_cache;
314
315 VkPhysicalDeviceMemoryProperties memory_properties;
316 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
317
318 drmPciBusInfo bus_info;
319
320 struct radv_device_extension_table supported_extensions;
321 };
322
323 struct radv_instance {
324 VK_LOADER_DATA _loader_data;
325
326 VkAllocationCallbacks alloc;
327
328 uint32_t apiVersion;
329 int physicalDeviceCount;
330 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
331
332 uint64_t debug_flags;
333 uint64_t perftest_flags;
334
335 struct vk_debug_report_instance debug_report_callbacks;
336
337 struct radv_instance_extension_table enabled_extensions;
338 };
339
340 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
341 void radv_finish_wsi(struct radv_physical_device *physical_device);
342
343 bool radv_instance_extension_supported(const char *name);
344 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
345 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
346 const char *name);
347
348 struct cache_entry;
349
350 struct radv_pipeline_cache {
351 struct radv_device * device;
352 pthread_mutex_t mutex;
353
354 uint32_t total_size;
355 uint32_t table_size;
356 uint32_t kernel_count;
357 struct cache_entry ** hash_table;
358 bool modified;
359
360 VkAllocationCallbacks alloc;
361 };
362
363 struct radv_pipeline_key {
364 uint32_t instance_rate_inputs;
365 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
366 uint64_t vertex_alpha_adjust;
367 unsigned tess_input_vertices;
368 uint32_t col_format;
369 uint32_t is_int8;
370 uint32_t is_int10;
371 uint8_t log2_ps_iter_samples;
372 uint8_t num_samples;
373 uint32_t has_multiview_view_index : 1;
374 uint32_t optimisations_disabled : 1;
375 };
376
377 void
378 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
379 struct radv_device *device);
380 void
381 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
382 bool
383 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
384 const void *data, size_t size);
385
386 struct radv_shader_variant;
387
388 bool
389 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
390 struct radv_pipeline_cache *cache,
391 const unsigned char *sha1,
392 struct radv_shader_variant **variants);
393
394 void
395 radv_pipeline_cache_insert_shaders(struct radv_device *device,
396 struct radv_pipeline_cache *cache,
397 const unsigned char *sha1,
398 struct radv_shader_variant **variants,
399 const void *const *codes,
400 const unsigned *code_sizes);
401
402 enum radv_blit_ds_layout {
403 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
404 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
405 RADV_BLIT_DS_LAYOUT_COUNT,
406 };
407
408 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
409 {
410 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
411 }
412
413 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
414 {
415 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
416 }
417
418 enum radv_meta_dst_layout {
419 RADV_META_DST_LAYOUT_GENERAL,
420 RADV_META_DST_LAYOUT_OPTIMAL,
421 RADV_META_DST_LAYOUT_COUNT,
422 };
423
424 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
425 {
426 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
427 }
428
429 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
430 {
431 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
432 }
433
434 struct radv_meta_state {
435 VkAllocationCallbacks alloc;
436
437 struct radv_pipeline_cache cache;
438
439 /*
440 * For on-demand pipeline creation, makes sure that
441 * only one thread tries to build a pipeline at the same time.
442 */
443 mtx_t mtx;
444
445 /**
446 * Use array element `i` for images with `2^i` samples.
447 */
448 struct {
449 VkRenderPass render_pass[NUM_META_FS_KEYS];
450 VkPipeline color_pipelines[NUM_META_FS_KEYS];
451
452 VkRenderPass depthstencil_rp;
453 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
454 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
455 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
456 } clear[1 + MAX_SAMPLES_LOG2];
457
458 VkPipelineLayout clear_color_p_layout;
459 VkPipelineLayout clear_depth_p_layout;
460
461 /* Optimized compute fast HTILE clear for stencil or depth only. */
462 VkPipeline clear_htile_mask_pipeline;
463 VkPipelineLayout clear_htile_mask_p_layout;
464 VkDescriptorSetLayout clear_htile_mask_ds_layout;
465
466 struct {
467 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
468
469 /** Pipeline that blits from a 1D image. */
470 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
471
472 /** Pipeline that blits from a 2D image. */
473 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
474
475 /** Pipeline that blits from a 3D image. */
476 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
477
478 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
479 VkPipeline depth_only_1d_pipeline;
480 VkPipeline depth_only_2d_pipeline;
481 VkPipeline depth_only_3d_pipeline;
482
483 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
484 VkPipeline stencil_only_1d_pipeline;
485 VkPipeline stencil_only_2d_pipeline;
486 VkPipeline stencil_only_3d_pipeline;
487 VkPipelineLayout pipeline_layout;
488 VkDescriptorSetLayout ds_layout;
489 } blit;
490
491 struct {
492 VkPipelineLayout p_layouts[5];
493 VkDescriptorSetLayout ds_layouts[5];
494 VkPipeline pipelines[5][NUM_META_FS_KEYS];
495
496 VkPipeline depth_only_pipeline[5];
497
498 VkPipeline stencil_only_pipeline[5];
499 } blit2d[1 + MAX_SAMPLES_LOG2];
500
501 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
502 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
503 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
504
505 struct {
506 VkPipelineLayout img_p_layout;
507 VkDescriptorSetLayout img_ds_layout;
508 VkPipeline pipeline;
509 VkPipeline pipeline_3d;
510 } itob;
511 struct {
512 VkPipelineLayout img_p_layout;
513 VkDescriptorSetLayout img_ds_layout;
514 VkPipeline pipeline;
515 VkPipeline pipeline_3d;
516 } btoi;
517 struct {
518 VkPipelineLayout img_p_layout;
519 VkDescriptorSetLayout img_ds_layout;
520 VkPipeline pipeline;
521 } btoi_r32g32b32;
522 struct {
523 VkPipelineLayout img_p_layout;
524 VkDescriptorSetLayout img_ds_layout;
525 VkPipeline pipeline;
526 VkPipeline pipeline_3d;
527 } itoi;
528 struct {
529 VkPipelineLayout img_p_layout;
530 VkDescriptorSetLayout img_ds_layout;
531 VkPipeline pipeline;
532 } itoi_r32g32b32;
533 struct {
534 VkPipelineLayout img_p_layout;
535 VkDescriptorSetLayout img_ds_layout;
536 VkPipeline pipeline;
537 VkPipeline pipeline_3d;
538 } cleari;
539 struct {
540 VkPipelineLayout img_p_layout;
541 VkDescriptorSetLayout img_ds_layout;
542 VkPipeline pipeline;
543 } cleari_r32g32b32;
544
545 struct {
546 VkPipelineLayout p_layout;
547 VkPipeline pipeline[NUM_META_FS_KEYS];
548 VkRenderPass pass[NUM_META_FS_KEYS];
549 } resolve;
550
551 struct {
552 VkDescriptorSetLayout ds_layout;
553 VkPipelineLayout p_layout;
554 struct {
555 VkPipeline pipeline;
556 VkPipeline i_pipeline;
557 VkPipeline srgb_pipeline;
558 } rc[MAX_SAMPLES_LOG2];
559 } resolve_compute;
560
561 struct {
562 VkDescriptorSetLayout ds_layout;
563 VkPipelineLayout p_layout;
564
565 struct {
566 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
567 VkPipeline pipeline[NUM_META_FS_KEYS];
568 } rc[MAX_SAMPLES_LOG2];
569 } resolve_fragment;
570
571 struct {
572 VkPipelineLayout p_layout;
573 VkPipeline decompress_pipeline;
574 VkPipeline resummarize_pipeline;
575 VkRenderPass pass;
576 } depth_decomp[1 + MAX_SAMPLES_LOG2];
577
578 struct {
579 VkPipelineLayout p_layout;
580 VkPipeline cmask_eliminate_pipeline;
581 VkPipeline fmask_decompress_pipeline;
582 VkPipeline dcc_decompress_pipeline;
583 VkRenderPass pass;
584
585 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
586 VkPipelineLayout dcc_decompress_compute_p_layout;
587 VkPipeline dcc_decompress_compute_pipeline;
588 } fast_clear_flush;
589
590 struct {
591 VkPipelineLayout fill_p_layout;
592 VkPipelineLayout copy_p_layout;
593 VkDescriptorSetLayout fill_ds_layout;
594 VkDescriptorSetLayout copy_ds_layout;
595 VkPipeline fill_pipeline;
596 VkPipeline copy_pipeline;
597 } buffer;
598
599 struct {
600 VkDescriptorSetLayout ds_layout;
601 VkPipelineLayout p_layout;
602 VkPipeline occlusion_query_pipeline;
603 VkPipeline pipeline_statistics_query_pipeline;
604 VkPipeline tfb_query_pipeline;
605 } query;
606 };
607
608 /* queue types */
609 #define RADV_QUEUE_GENERAL 0
610 #define RADV_QUEUE_COMPUTE 1
611 #define RADV_QUEUE_TRANSFER 2
612
613 #define RADV_MAX_QUEUE_FAMILIES 3
614
615 enum ring_type radv_queue_family_to_ring(int f);
616
617 struct radv_queue {
618 VK_LOADER_DATA _loader_data;
619 struct radv_device * device;
620 struct radeon_winsys_ctx *hw_ctx;
621 enum radeon_ctx_priority priority;
622 uint32_t queue_family_index;
623 int queue_idx;
624 VkDeviceQueueCreateFlags flags;
625
626 uint32_t scratch_size;
627 uint32_t compute_scratch_size;
628 uint32_t esgs_ring_size;
629 uint32_t gsvs_ring_size;
630 bool has_tess_rings;
631 bool has_sample_positions;
632
633 struct radeon_winsys_bo *scratch_bo;
634 struct radeon_winsys_bo *descriptor_bo;
635 struct radeon_winsys_bo *compute_scratch_bo;
636 struct radeon_winsys_bo *esgs_ring_bo;
637 struct radeon_winsys_bo *gsvs_ring_bo;
638 struct radeon_winsys_bo *tess_rings_bo;
639 struct radeon_cmdbuf *initial_preamble_cs;
640 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
641 struct radeon_cmdbuf *continue_preamble_cs;
642 };
643
644 struct radv_bo_list {
645 struct radv_winsys_bo_list list;
646 unsigned capacity;
647 pthread_mutex_t mutex;
648 };
649
650 struct radv_device {
651 VK_LOADER_DATA _loader_data;
652
653 VkAllocationCallbacks alloc;
654
655 struct radv_instance * instance;
656 struct radeon_winsys *ws;
657
658 struct radv_meta_state meta_state;
659
660 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
661 int queue_count[RADV_MAX_QUEUE_FAMILIES];
662 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
663
664 bool always_use_syncobj;
665 bool has_distributed_tess;
666 bool pbb_allowed;
667 bool dfsm_allowed;
668 uint32_t tess_offchip_block_dw_size;
669 uint32_t scratch_waves;
670 uint32_t dispatch_initiator;
671
672 uint32_t gs_table_depth;
673
674 /* MSAA sample locations.
675 * The first index is the sample index.
676 * The second index is the coordinate: X, Y. */
677 float sample_locations_1x[1][2];
678 float sample_locations_2x[2][2];
679 float sample_locations_4x[4][2];
680 float sample_locations_8x[8][2];
681 float sample_locations_16x[16][2];
682
683 /* CIK and later */
684 uint32_t gfx_init_size_dw;
685 struct radeon_winsys_bo *gfx_init;
686
687 struct radeon_winsys_bo *trace_bo;
688 uint32_t *trace_id_ptr;
689
690 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
691 bool keep_shader_info;
692
693 struct radv_physical_device *physical_device;
694
695 /* Backup in-memory cache to be used if the app doesn't provide one */
696 struct radv_pipeline_cache * mem_cache;
697
698 /*
699 * use different counters so MSAA MRTs get consecutive surface indices,
700 * even if MASK is allocated in between.
701 */
702 uint32_t image_mrt_offset_counter;
703 uint32_t fmask_mrt_offset_counter;
704 struct list_head shader_slabs;
705 mtx_t shader_slab_mutex;
706
707 /* For detecting VM faults reported by dmesg. */
708 uint64_t dmesg_timestamp;
709
710 struct radv_device_extension_table enabled_extensions;
711
712 /* Whether the driver uses a global BO list. */
713 bool use_global_bo_list;
714
715 struct radv_bo_list bo_list;
716
717 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
718 int force_aniso;
719 };
720
721 struct radv_device_memory {
722 struct radeon_winsys_bo *bo;
723 /* for dedicated allocations */
724 struct radv_image *image;
725 struct radv_buffer *buffer;
726 uint32_t type_index;
727 VkDeviceSize map_size;
728 void * map;
729 void * user_ptr;
730 };
731
732
733 struct radv_descriptor_range {
734 uint64_t va;
735 uint32_t size;
736 };
737
738 struct radv_descriptor_set {
739 const struct radv_descriptor_set_layout *layout;
740 uint32_t size;
741
742 struct radeon_winsys_bo *bo;
743 uint64_t va;
744 uint32_t *mapped_ptr;
745 struct radv_descriptor_range *dynamic_descriptors;
746
747 struct radeon_winsys_bo *descriptors[0];
748 };
749
750 struct radv_push_descriptor_set
751 {
752 struct radv_descriptor_set set;
753 uint32_t capacity;
754 };
755
756 struct radv_descriptor_pool_entry {
757 uint32_t offset;
758 uint32_t size;
759 struct radv_descriptor_set *set;
760 };
761
762 struct radv_descriptor_pool {
763 struct radeon_winsys_bo *bo;
764 uint8_t *mapped_ptr;
765 uint64_t current_offset;
766 uint64_t size;
767
768 uint8_t *host_memory_base;
769 uint8_t *host_memory_ptr;
770 uint8_t *host_memory_end;
771
772 uint32_t entry_count;
773 uint32_t max_entry_count;
774 struct radv_descriptor_pool_entry entries[0];
775 };
776
777 struct radv_descriptor_update_template_entry {
778 VkDescriptorType descriptor_type;
779
780 /* The number of descriptors to update */
781 uint32_t descriptor_count;
782
783 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
784 uint32_t dst_offset;
785
786 /* In dwords. Not valid/used for dynamic descriptors */
787 uint32_t dst_stride;
788
789 uint32_t buffer_offset;
790
791 /* Only valid for combined image samplers and samplers */
792 uint16_t has_sampler;
793
794 /* In bytes */
795 size_t src_offset;
796 size_t src_stride;
797
798 /* For push descriptors */
799 const uint32_t *immutable_samplers;
800 };
801
802 struct radv_descriptor_update_template {
803 uint32_t entry_count;
804 VkPipelineBindPoint bind_point;
805 struct radv_descriptor_update_template_entry entry[0];
806 };
807
808 struct radv_buffer {
809 VkDeviceSize size;
810
811 VkBufferUsageFlags usage;
812 VkBufferCreateFlags flags;
813
814 /* Set when bound */
815 struct radeon_winsys_bo * bo;
816 VkDeviceSize offset;
817
818 bool shareable;
819 };
820
821 enum radv_dynamic_state_bits {
822 RADV_DYNAMIC_VIEWPORT = 1 << 0,
823 RADV_DYNAMIC_SCISSOR = 1 << 1,
824 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
825 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
826 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
827 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
828 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
829 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
830 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
831 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
832 RADV_DYNAMIC_ALL = (1 << 10) - 1,
833 };
834
835 enum radv_cmd_dirty_bits {
836 /* Keep the dynamic state dirty bits in sync with
837 * enum radv_dynamic_state_bits */
838 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
839 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
840 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
841 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
842 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
843 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
844 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
845 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
846 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
847 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
848 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
849 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
850 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
851 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
852 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
853 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
854 };
855
856 enum radv_cmd_flush_bits {
857 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
858 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
859 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
860 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
861 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
862 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
863 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
864 /* Same as above, but only writes back and doesn't invalidate */
865 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
866 /* Framebuffer caches */
867 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
868 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
869 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
870 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
871 /* Engine synchronization. */
872 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
873 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
874 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
875 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
876 /* Pipeline query controls. */
877 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
878 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
879 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
880
881 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
882 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
883 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
884 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
885 };
886
887 struct radv_vertex_binding {
888 struct radv_buffer * buffer;
889 VkDeviceSize offset;
890 };
891
892 struct radv_streamout_binding {
893 struct radv_buffer *buffer;
894 VkDeviceSize offset;
895 VkDeviceSize size;
896 };
897
898 struct radv_streamout_state {
899 /* Mask of bound streamout buffers. */
900 uint8_t enabled_mask;
901
902 /* External state that comes from the last vertex stage, it must be
903 * set explicitely when binding a new graphics pipeline.
904 */
905 uint16_t stride_in_dw[MAX_SO_BUFFERS];
906 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
907
908 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
909 uint32_t hw_enabled_mask;
910
911 /* State of VGT_STRMOUT_(CONFIG|EN) */
912 bool streamout_enabled;
913 };
914
915 struct radv_viewport_state {
916 uint32_t count;
917 VkViewport viewports[MAX_VIEWPORTS];
918 };
919
920 struct radv_scissor_state {
921 uint32_t count;
922 VkRect2D scissors[MAX_SCISSORS];
923 };
924
925 struct radv_discard_rectangle_state {
926 uint32_t count;
927 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
928 };
929
930 struct radv_dynamic_state {
931 /**
932 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
933 * Defines the set of saved dynamic state.
934 */
935 uint32_t mask;
936
937 struct radv_viewport_state viewport;
938
939 struct radv_scissor_state scissor;
940
941 float line_width;
942
943 struct {
944 float bias;
945 float clamp;
946 float slope;
947 } depth_bias;
948
949 float blend_constants[4];
950
951 struct {
952 float min;
953 float max;
954 } depth_bounds;
955
956 struct {
957 uint32_t front;
958 uint32_t back;
959 } stencil_compare_mask;
960
961 struct {
962 uint32_t front;
963 uint32_t back;
964 } stencil_write_mask;
965
966 struct {
967 uint32_t front;
968 uint32_t back;
969 } stencil_reference;
970
971 struct radv_discard_rectangle_state discard_rectangle;
972 };
973
974 extern const struct radv_dynamic_state default_dynamic_state;
975
976 const char *
977 radv_get_debug_option_name(int id);
978
979 const char *
980 radv_get_perftest_option_name(int id);
981
982 /**
983 * Attachment state when recording a renderpass instance.
984 *
985 * The clear value is valid only if there exists a pending clear.
986 */
987 struct radv_attachment_state {
988 VkImageAspectFlags pending_clear_aspects;
989 uint32_t cleared_views;
990 VkClearValue clear_value;
991 VkImageLayout current_layout;
992 };
993
994 struct radv_descriptor_state {
995 struct radv_descriptor_set *sets[MAX_SETS];
996 uint32_t dirty;
997 uint32_t valid;
998 struct radv_push_descriptor_set push_set;
999 bool push_dirty;
1000 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1001 };
1002
1003 struct radv_cmd_state {
1004 /* Vertex descriptors */
1005 uint64_t vb_va;
1006 unsigned vb_size;
1007
1008 bool predicating;
1009 uint32_t dirty;
1010
1011 uint32_t prefetch_L2_mask;
1012
1013 struct radv_pipeline * pipeline;
1014 struct radv_pipeline * emitted_pipeline;
1015 struct radv_pipeline * compute_pipeline;
1016 struct radv_pipeline * emitted_compute_pipeline;
1017 struct radv_framebuffer * framebuffer;
1018 struct radv_render_pass * pass;
1019 const struct radv_subpass * subpass;
1020 struct radv_dynamic_state dynamic;
1021 struct radv_attachment_state * attachments;
1022 struct radv_streamout_state streamout;
1023 VkRect2D render_area;
1024
1025 /* Index buffer */
1026 struct radv_buffer *index_buffer;
1027 uint64_t index_offset;
1028 uint32_t index_type;
1029 uint32_t max_index_count;
1030 uint64_t index_va;
1031 int32_t last_index_type;
1032
1033 int32_t last_primitive_reset_en;
1034 uint32_t last_primitive_reset_index;
1035 enum radv_cmd_flush_bits flush_bits;
1036 unsigned active_occlusion_queries;
1037 bool perfect_occlusion_queries_enabled;
1038 unsigned active_pipeline_queries;
1039 float offset_scale;
1040 uint32_t trace_id;
1041 uint32_t last_ia_multi_vgt_param;
1042
1043 uint32_t last_num_instances;
1044 uint32_t last_first_instance;
1045 uint32_t last_vertex_offset;
1046
1047 /* Whether CP DMA is busy/idle. */
1048 bool dma_is_busy;
1049
1050 /* Conditional rendering info. */
1051 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1052 uint64_t predication_va;
1053 };
1054
1055 struct radv_cmd_pool {
1056 VkAllocationCallbacks alloc;
1057 struct list_head cmd_buffers;
1058 struct list_head free_cmd_buffers;
1059 uint32_t queue_family_index;
1060 };
1061
1062 struct radv_cmd_buffer_upload {
1063 uint8_t *map;
1064 unsigned offset;
1065 uint64_t size;
1066 struct radeon_winsys_bo *upload_bo;
1067 struct list_head list;
1068 };
1069
1070 enum radv_cmd_buffer_status {
1071 RADV_CMD_BUFFER_STATUS_INVALID,
1072 RADV_CMD_BUFFER_STATUS_INITIAL,
1073 RADV_CMD_BUFFER_STATUS_RECORDING,
1074 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1075 RADV_CMD_BUFFER_STATUS_PENDING,
1076 };
1077
1078 struct radv_cmd_buffer {
1079 VK_LOADER_DATA _loader_data;
1080
1081 struct radv_device * device;
1082
1083 struct radv_cmd_pool * pool;
1084 struct list_head pool_link;
1085
1086 VkCommandBufferUsageFlags usage_flags;
1087 VkCommandBufferLevel level;
1088 enum radv_cmd_buffer_status status;
1089 struct radeon_cmdbuf *cs;
1090 struct radv_cmd_state state;
1091 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1092 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1093 uint32_t queue_family_index;
1094
1095 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1096 VkShaderStageFlags push_constant_stages;
1097 struct radv_descriptor_set meta_push_descriptors;
1098
1099 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1100
1101 struct radv_cmd_buffer_upload upload;
1102
1103 uint32_t scratch_size_needed;
1104 uint32_t compute_scratch_size_needed;
1105 uint32_t esgs_ring_size_needed;
1106 uint32_t gsvs_ring_size_needed;
1107 bool tess_rings_needed;
1108 bool sample_positions_needed;
1109
1110 VkResult record_result;
1111
1112 uint32_t gfx9_fence_offset;
1113 struct radeon_winsys_bo *gfx9_fence_bo;
1114 uint32_t gfx9_fence_idx;
1115 uint64_t gfx9_eop_bug_va;
1116
1117 /**
1118 * Whether a query pool has been resetted and we have to flush caches.
1119 */
1120 bool pending_reset_query;
1121 };
1122
1123 struct radv_image;
1124
1125 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1126
1127 void si_emit_graphics(struct radv_physical_device *physical_device,
1128 struct radeon_cmdbuf *cs);
1129 void si_emit_compute(struct radv_physical_device *physical_device,
1130 struct radeon_cmdbuf *cs);
1131
1132 void cik_create_gfx_config(struct radv_device *device);
1133
1134 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1135 int count, const VkViewport *viewports);
1136 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1137 int count, const VkRect2D *scissors,
1138 const VkViewport *viewports, bool can_use_guardband);
1139 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1140 bool instanced_draw, bool indirect_draw,
1141 uint32_t draw_vertex_count);
1142 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1143 enum chip_class chip_class,
1144 bool is_mec,
1145 unsigned event, unsigned event_flags,
1146 unsigned data_sel,
1147 uint64_t va,
1148 uint32_t old_fence,
1149 uint32_t new_fence,
1150 uint64_t gfx9_eop_bug_va);
1151
1152 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1153 uint32_t ref, uint32_t mask);
1154 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1155 enum chip_class chip_class,
1156 uint32_t *fence_ptr, uint64_t va,
1157 bool is_mec,
1158 enum radv_cmd_flush_bits flush_bits,
1159 uint64_t gfx9_eop_bug_va);
1160 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1161 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1162 bool inverted, uint64_t va);
1163 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1164 uint64_t src_va, uint64_t dest_va,
1165 uint64_t size);
1166 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1167 unsigned size);
1168 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1169 uint64_t size, unsigned value);
1170 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1171
1172 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1173 bool
1174 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1175 unsigned size,
1176 unsigned alignment,
1177 unsigned *out_offset,
1178 void **ptr);
1179 void
1180 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1181 const struct radv_subpass *subpass,
1182 bool transitions);
1183 bool
1184 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1185 unsigned size, unsigned alignmnet,
1186 const void *data, unsigned *out_offset);
1187
1188 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1189 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1190 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1191 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1192 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1193 unsigned radv_cayman_get_maxdist(int log_samples);
1194 void radv_device_init_msaa(struct radv_device *device);
1195
1196 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1197 struct radv_image *image,
1198 VkClearDepthStencilValue ds_clear_value,
1199 VkImageAspectFlags aspects);
1200
1201 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1202 struct radv_image *image,
1203 int cb_idx,
1204 uint32_t color_values[2]);
1205
1206 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1207 struct radv_image *image, bool value);
1208
1209 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1210 struct radv_image *image, bool value);
1211
1212 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1213 struct radeon_winsys_bo *bo,
1214 uint64_t offset, uint64_t size, uint32_t value);
1215 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1216 bool radv_get_memory_fd(struct radv_device *device,
1217 struct radv_device_memory *memory,
1218 int *pFD);
1219
1220 static inline void
1221 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1222 unsigned sh_offset, unsigned pointer_count,
1223 bool use_32bit_pointers)
1224 {
1225 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1226 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1227 }
1228
1229 static inline void
1230 radv_emit_shader_pointer_body(struct radv_device *device,
1231 struct radeon_cmdbuf *cs,
1232 uint64_t va, bool use_32bit_pointers)
1233 {
1234 radeon_emit(cs, va);
1235
1236 if (use_32bit_pointers) {
1237 assert(va == 0 ||
1238 (va >> 32) == device->physical_device->rad_info.address32_hi);
1239 } else {
1240 radeon_emit(cs, va >> 32);
1241 }
1242 }
1243
1244 static inline void
1245 radv_emit_shader_pointer(struct radv_device *device,
1246 struct radeon_cmdbuf *cs,
1247 uint32_t sh_offset, uint64_t va, bool global)
1248 {
1249 bool use_32bit_pointers = !global;
1250
1251 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1252 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1253 }
1254
1255 static inline struct radv_descriptor_state *
1256 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1257 VkPipelineBindPoint bind_point)
1258 {
1259 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1260 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1261 return &cmd_buffer->descriptors[bind_point];
1262 }
1263
1264 /*
1265 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1266 *
1267 * Limitations: Can't call normal dispatch functions without binding or rebinding
1268 * the compute pipeline.
1269 */
1270 void radv_unaligned_dispatch(
1271 struct radv_cmd_buffer *cmd_buffer,
1272 uint32_t x,
1273 uint32_t y,
1274 uint32_t z);
1275
1276 struct radv_event {
1277 struct radeon_winsys_bo *bo;
1278 uint64_t *map;
1279 };
1280
1281 struct radv_shader_module;
1282
1283 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1284 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1285 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1286 void
1287 radv_hash_shaders(unsigned char *hash,
1288 const VkPipelineShaderStageCreateInfo **stages,
1289 const struct radv_pipeline_layout *layout,
1290 const struct radv_pipeline_key *key,
1291 uint32_t flags);
1292
1293 static inline gl_shader_stage
1294 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1295 {
1296 assert(__builtin_popcount(vk_stage) == 1);
1297 return ffs(vk_stage) - 1;
1298 }
1299
1300 static inline VkShaderStageFlagBits
1301 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1302 {
1303 return (1 << mesa_stage);
1304 }
1305
1306 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1307
1308 #define radv_foreach_stage(stage, stage_bits) \
1309 for (gl_shader_stage stage, \
1310 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1311 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1312 __tmp &= ~(1 << (stage)))
1313
1314 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1315 unsigned radv_format_meta_fs_key(VkFormat format);
1316
1317 struct radv_multisample_state {
1318 uint32_t db_eqaa;
1319 uint32_t pa_sc_line_cntl;
1320 uint32_t pa_sc_mode_cntl_0;
1321 uint32_t pa_sc_mode_cntl_1;
1322 uint32_t pa_sc_aa_config;
1323 uint32_t pa_sc_aa_mask[2];
1324 unsigned num_samples;
1325 };
1326
1327 struct radv_prim_vertex_count {
1328 uint8_t min;
1329 uint8_t incr;
1330 };
1331
1332 struct radv_vertex_elements_info {
1333 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1334 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1335 uint32_t binding[MAX_VERTEX_ATTRIBS];
1336 uint32_t offset[MAX_VERTEX_ATTRIBS];
1337 uint32_t count;
1338 };
1339
1340 struct radv_ia_multi_vgt_param_helpers {
1341 uint32_t base;
1342 bool partial_es_wave;
1343 uint8_t primgroup_size;
1344 bool wd_switch_on_eop;
1345 bool ia_switch_on_eoi;
1346 bool partial_vs_wave;
1347 };
1348
1349 #define SI_GS_PER_ES 128
1350
1351 struct radv_pipeline {
1352 struct radv_device * device;
1353 struct radv_dynamic_state dynamic_state;
1354
1355 struct radv_pipeline_layout * layout;
1356
1357 bool need_indirect_descriptor_sets;
1358 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1359 struct radv_shader_variant *gs_copy_shader;
1360 VkShaderStageFlags active_stages;
1361
1362 struct radeon_cmdbuf cs;
1363
1364 struct radv_vertex_elements_info vertex_elements;
1365
1366 uint32_t binding_stride[MAX_VBS];
1367
1368 uint32_t user_data_0[MESA_SHADER_STAGES];
1369 union {
1370 struct {
1371 struct radv_multisample_state ms;
1372 uint32_t spi_baryc_cntl;
1373 bool prim_restart_enable;
1374 unsigned esgs_ring_size;
1375 unsigned gsvs_ring_size;
1376 uint32_t vtx_base_sgpr;
1377 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1378 uint8_t vtx_emit_num;
1379 struct radv_prim_vertex_count prim_vertex_count;
1380 bool can_use_guardband;
1381 uint32_t needed_dynamic_state;
1382 bool disable_out_of_order_rast_for_occlusion;
1383
1384 /* Used for rbplus */
1385 uint32_t col_format;
1386 uint32_t cb_target_mask;
1387 } graphics;
1388 };
1389
1390 unsigned max_waves;
1391 unsigned scratch_bytes_per_wave;
1392
1393 /* Not NULL if graphics pipeline uses streamout. */
1394 struct radv_shader_variant *streamout_shader;
1395 };
1396
1397 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1398 {
1399 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1400 }
1401
1402 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1403 {
1404 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1405 }
1406
1407 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1408 gl_shader_stage stage,
1409 int idx);
1410
1411 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1412 gl_shader_stage stage);
1413
1414 struct radv_graphics_pipeline_create_info {
1415 bool use_rectlist;
1416 bool db_depth_clear;
1417 bool db_stencil_clear;
1418 bool db_depth_disable_expclear;
1419 bool db_stencil_disable_expclear;
1420 bool db_flush_depth_inplace;
1421 bool db_flush_stencil_inplace;
1422 bool db_resummarize;
1423 uint32_t custom_blend_mode;
1424 };
1425
1426 VkResult
1427 radv_graphics_pipeline_create(VkDevice device,
1428 VkPipelineCache cache,
1429 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1430 const struct radv_graphics_pipeline_create_info *extra,
1431 const VkAllocationCallbacks *alloc,
1432 VkPipeline *pPipeline);
1433
1434 struct vk_format_description;
1435 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1436 int first_non_void);
1437 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1438 int first_non_void);
1439 uint32_t radv_translate_colorformat(VkFormat format);
1440 uint32_t radv_translate_color_numformat(VkFormat format,
1441 const struct vk_format_description *desc,
1442 int first_non_void);
1443 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1444 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1445 uint32_t radv_translate_dbformat(VkFormat format);
1446 uint32_t radv_translate_tex_dataformat(VkFormat format,
1447 const struct vk_format_description *desc,
1448 int first_non_void);
1449 uint32_t radv_translate_tex_numformat(VkFormat format,
1450 const struct vk_format_description *desc,
1451 int first_non_void);
1452 bool radv_format_pack_clear_color(VkFormat format,
1453 uint32_t clear_vals[2],
1454 VkClearColorValue *value);
1455 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1456 bool radv_dcc_formats_compatible(VkFormat format1,
1457 VkFormat format2);
1458
1459 struct radv_fmask_info {
1460 uint64_t offset;
1461 uint64_t size;
1462 unsigned alignment;
1463 unsigned pitch_in_pixels;
1464 unsigned bank_height;
1465 unsigned slice_tile_max;
1466 unsigned tile_mode_index;
1467 unsigned tile_swizzle;
1468 };
1469
1470 struct radv_cmask_info {
1471 uint64_t offset;
1472 uint64_t size;
1473 unsigned alignment;
1474 unsigned slice_tile_max;
1475 };
1476
1477 struct radv_image {
1478 VkImageType type;
1479 /* The original VkFormat provided by the client. This may not match any
1480 * of the actual surface formats.
1481 */
1482 VkFormat vk_format;
1483 VkImageAspectFlags aspects;
1484 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1485 struct ac_surf_info info;
1486 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1487 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1488
1489 VkDeviceSize size;
1490 uint32_t alignment;
1491
1492 unsigned queue_family_mask;
1493 bool exclusive;
1494 bool shareable;
1495
1496 /* Set when bound */
1497 struct radeon_winsys_bo *bo;
1498 VkDeviceSize offset;
1499 uint64_t dcc_offset;
1500 uint64_t htile_offset;
1501 bool tc_compatible_htile;
1502 struct radeon_surf surface;
1503
1504 struct radv_fmask_info fmask;
1505 struct radv_cmask_info cmask;
1506 uint64_t clear_value_offset;
1507 uint64_t fce_pred_offset;
1508 uint64_t dcc_pred_offset;
1509
1510 /*
1511 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1512 * stored at this offset is UINT_MAX, the driver will emit
1513 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1514 * SET_CONTEXT_REG packet.
1515 */
1516 uint64_t tc_compat_zrange_offset;
1517
1518 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1519 VkDeviceMemory owned_memory;
1520 };
1521
1522 /* Whether the image has a htile that is known consistent with the contents of
1523 * the image. */
1524 bool radv_layout_has_htile(const struct radv_image *image,
1525 VkImageLayout layout,
1526 unsigned queue_mask);
1527
1528 /* Whether the image has a htile that is known consistent with the contents of
1529 * the image and is allowed to be in compressed form.
1530 *
1531 * If this is false reads that don't use the htile should be able to return
1532 * correct results.
1533 */
1534 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1535 VkImageLayout layout,
1536 unsigned queue_mask);
1537
1538 bool radv_layout_can_fast_clear(const struct radv_image *image,
1539 VkImageLayout layout,
1540 unsigned queue_mask);
1541
1542 bool radv_layout_dcc_compressed(const struct radv_image *image,
1543 VkImageLayout layout,
1544 unsigned queue_mask);
1545
1546 /**
1547 * Return whether the image has CMASK metadata for color surfaces.
1548 */
1549 static inline bool
1550 radv_image_has_cmask(const struct radv_image *image)
1551 {
1552 return image->cmask.size;
1553 }
1554
1555 /**
1556 * Return whether the image has FMASK metadata for color surfaces.
1557 */
1558 static inline bool
1559 radv_image_has_fmask(const struct radv_image *image)
1560 {
1561 return image->fmask.size;
1562 }
1563
1564 /**
1565 * Return whether the image has DCC metadata for color surfaces.
1566 */
1567 static inline bool
1568 radv_image_has_dcc(const struct radv_image *image)
1569 {
1570 return image->surface.dcc_size;
1571 }
1572
1573 /**
1574 * Return whether DCC metadata is enabled for a level.
1575 */
1576 static inline bool
1577 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1578 {
1579 return radv_image_has_dcc(image) &&
1580 level < image->surface.num_dcc_levels;
1581 }
1582
1583 /**
1584 * Return whether the image has CB metadata.
1585 */
1586 static inline bool
1587 radv_image_has_CB_metadata(const struct radv_image *image)
1588 {
1589 return radv_image_has_cmask(image) ||
1590 radv_image_has_fmask(image) ||
1591 radv_image_has_dcc(image);
1592 }
1593
1594 /**
1595 * Return whether the image has HTILE metadata for depth surfaces.
1596 */
1597 static inline bool
1598 radv_image_has_htile(const struct radv_image *image)
1599 {
1600 return image->surface.htile_size;
1601 }
1602
1603 /**
1604 * Return whether HTILE metadata is enabled for a level.
1605 */
1606 static inline bool
1607 radv_htile_enabled(const struct radv_image *image, unsigned level)
1608 {
1609 return radv_image_has_htile(image) && level == 0;
1610 }
1611
1612 /**
1613 * Return whether the image is TC-compatible HTILE.
1614 */
1615 static inline bool
1616 radv_image_is_tc_compat_htile(const struct radv_image *image)
1617 {
1618 return radv_image_has_htile(image) && image->tc_compatible_htile;
1619 }
1620
1621 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1622
1623 static inline uint32_t
1624 radv_get_layerCount(const struct radv_image *image,
1625 const VkImageSubresourceRange *range)
1626 {
1627 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1628 image->info.array_size - range->baseArrayLayer : range->layerCount;
1629 }
1630
1631 static inline uint32_t
1632 radv_get_levelCount(const struct radv_image *image,
1633 const VkImageSubresourceRange *range)
1634 {
1635 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1636 image->info.levels - range->baseMipLevel : range->levelCount;
1637 }
1638
1639 struct radeon_bo_metadata;
1640 void
1641 radv_init_metadata(struct radv_device *device,
1642 struct radv_image *image,
1643 struct radeon_bo_metadata *metadata);
1644
1645 struct radv_image_view {
1646 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1647 struct radeon_winsys_bo *bo;
1648
1649 VkImageViewType type;
1650 VkImageAspectFlags aspect_mask;
1651 VkFormat vk_format;
1652 uint32_t base_layer;
1653 uint32_t layer_count;
1654 uint32_t base_mip;
1655 uint32_t level_count;
1656 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1657
1658 uint32_t descriptor[16];
1659
1660 /* Descriptor for use as a storage image as opposed to a sampled image.
1661 * This has a few differences for cube maps (e.g. type).
1662 */
1663 uint32_t storage_descriptor[16];
1664 };
1665
1666 struct radv_image_create_info {
1667 const VkImageCreateInfo *vk_info;
1668 bool scanout;
1669 bool no_metadata_planes;
1670 };
1671
1672 VkResult radv_image_create(VkDevice _device,
1673 const struct radv_image_create_info *info,
1674 const VkAllocationCallbacks* alloc,
1675 VkImage *pImage);
1676
1677 VkResult
1678 radv_image_from_gralloc(VkDevice device_h,
1679 const VkImageCreateInfo *base_info,
1680 const VkNativeBufferANDROID *gralloc_info,
1681 const VkAllocationCallbacks *alloc,
1682 VkImage *out_image_h);
1683
1684 void radv_image_view_init(struct radv_image_view *view,
1685 struct radv_device *device,
1686 const VkImageViewCreateInfo* pCreateInfo);
1687
1688 struct radv_buffer_view {
1689 struct radeon_winsys_bo *bo;
1690 VkFormat vk_format;
1691 uint64_t range; /**< VkBufferViewCreateInfo::range */
1692 uint32_t state[4];
1693 };
1694 void radv_buffer_view_init(struct radv_buffer_view *view,
1695 struct radv_device *device,
1696 const VkBufferViewCreateInfo* pCreateInfo);
1697
1698 static inline struct VkExtent3D
1699 radv_sanitize_image_extent(const VkImageType imageType,
1700 const struct VkExtent3D imageExtent)
1701 {
1702 switch (imageType) {
1703 case VK_IMAGE_TYPE_1D:
1704 return (VkExtent3D) { imageExtent.width, 1, 1 };
1705 case VK_IMAGE_TYPE_2D:
1706 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1707 case VK_IMAGE_TYPE_3D:
1708 return imageExtent;
1709 default:
1710 unreachable("invalid image type");
1711 }
1712 }
1713
1714 static inline struct VkOffset3D
1715 radv_sanitize_image_offset(const VkImageType imageType,
1716 const struct VkOffset3D imageOffset)
1717 {
1718 switch (imageType) {
1719 case VK_IMAGE_TYPE_1D:
1720 return (VkOffset3D) { imageOffset.x, 0, 0 };
1721 case VK_IMAGE_TYPE_2D:
1722 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1723 case VK_IMAGE_TYPE_3D:
1724 return imageOffset;
1725 default:
1726 unreachable("invalid image type");
1727 }
1728 }
1729
1730 static inline bool
1731 radv_image_extent_compare(const struct radv_image *image,
1732 const VkExtent3D *extent)
1733 {
1734 if (extent->width != image->info.width ||
1735 extent->height != image->info.height ||
1736 extent->depth != image->info.depth)
1737 return false;
1738 return true;
1739 }
1740
1741 struct radv_sampler {
1742 uint32_t state[4];
1743 };
1744
1745 struct radv_color_buffer_info {
1746 uint64_t cb_color_base;
1747 uint64_t cb_color_cmask;
1748 uint64_t cb_color_fmask;
1749 uint64_t cb_dcc_base;
1750 uint32_t cb_color_pitch;
1751 uint32_t cb_color_slice;
1752 uint32_t cb_color_view;
1753 uint32_t cb_color_info;
1754 uint32_t cb_color_attrib;
1755 uint32_t cb_color_attrib2;
1756 uint32_t cb_dcc_control;
1757 uint32_t cb_color_cmask_slice;
1758 uint32_t cb_color_fmask_slice;
1759 };
1760
1761 struct radv_ds_buffer_info {
1762 uint64_t db_z_read_base;
1763 uint64_t db_stencil_read_base;
1764 uint64_t db_z_write_base;
1765 uint64_t db_stencil_write_base;
1766 uint64_t db_htile_data_base;
1767 uint32_t db_depth_info;
1768 uint32_t db_z_info;
1769 uint32_t db_stencil_info;
1770 uint32_t db_depth_view;
1771 uint32_t db_depth_size;
1772 uint32_t db_depth_slice;
1773 uint32_t db_htile_surface;
1774 uint32_t pa_su_poly_offset_db_fmt_cntl;
1775 uint32_t db_z_info2;
1776 uint32_t db_stencil_info2;
1777 float offset_scale;
1778 };
1779
1780 struct radv_attachment_info {
1781 union {
1782 struct radv_color_buffer_info cb;
1783 struct radv_ds_buffer_info ds;
1784 };
1785 struct radv_image_view *attachment;
1786 };
1787
1788 struct radv_framebuffer {
1789 uint32_t width;
1790 uint32_t height;
1791 uint32_t layers;
1792
1793 uint32_t attachment_count;
1794 struct radv_attachment_info attachments[0];
1795 };
1796
1797 struct radv_subpass_barrier {
1798 VkPipelineStageFlags src_stage_mask;
1799 VkAccessFlags src_access_mask;
1800 VkAccessFlags dst_access_mask;
1801 };
1802
1803 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1804 const struct radv_subpass_barrier *barrier);
1805
1806 struct radv_subpass_attachment {
1807 uint32_t attachment;
1808 VkImageLayout layout;
1809 };
1810
1811 struct radv_subpass {
1812 uint32_t input_count;
1813 uint32_t color_count;
1814 struct radv_subpass_attachment * input_attachments;
1815 struct radv_subpass_attachment * color_attachments;
1816 struct radv_subpass_attachment * resolve_attachments;
1817 struct radv_subpass_attachment depth_stencil_attachment;
1818
1819 /** Subpass has at least one resolve attachment */
1820 bool has_resolve;
1821
1822 struct radv_subpass_barrier start_barrier;
1823
1824 uint32_t view_mask;
1825 VkSampleCountFlagBits max_sample_count;
1826 };
1827
1828 struct radv_render_pass_attachment {
1829 VkFormat format;
1830 uint32_t samples;
1831 VkAttachmentLoadOp load_op;
1832 VkAttachmentLoadOp stencil_load_op;
1833 VkImageLayout initial_layout;
1834 VkImageLayout final_layout;
1835 uint32_t view_mask;
1836 };
1837
1838 struct radv_render_pass {
1839 uint32_t attachment_count;
1840 uint32_t subpass_count;
1841 struct radv_subpass_attachment * subpass_attachments;
1842 struct radv_render_pass_attachment * attachments;
1843 struct radv_subpass_barrier end_barrier;
1844 struct radv_subpass subpasses[0];
1845 };
1846
1847 VkResult radv_device_init_meta(struct radv_device *device);
1848 void radv_device_finish_meta(struct radv_device *device);
1849
1850 struct radv_query_pool {
1851 struct radeon_winsys_bo *bo;
1852 uint32_t stride;
1853 uint32_t availability_offset;
1854 uint64_t size;
1855 char *ptr;
1856 VkQueryType type;
1857 uint32_t pipeline_stats_mask;
1858 };
1859
1860 struct radv_semaphore {
1861 /* use a winsys sem for non-exportable */
1862 struct radeon_winsys_sem *sem;
1863 uint32_t syncobj;
1864 uint32_t temp_syncobj;
1865 };
1866
1867 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1868 VkPipelineBindPoint bind_point,
1869 struct radv_descriptor_set *set,
1870 unsigned idx);
1871
1872 void
1873 radv_update_descriptor_sets(struct radv_device *device,
1874 struct radv_cmd_buffer *cmd_buffer,
1875 VkDescriptorSet overrideSet,
1876 uint32_t descriptorWriteCount,
1877 const VkWriteDescriptorSet *pDescriptorWrites,
1878 uint32_t descriptorCopyCount,
1879 const VkCopyDescriptorSet *pDescriptorCopies);
1880
1881 void
1882 radv_update_descriptor_set_with_template(struct radv_device *device,
1883 struct radv_cmd_buffer *cmd_buffer,
1884 struct radv_descriptor_set *set,
1885 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1886 const void *pData);
1887
1888 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1889 VkPipelineBindPoint pipelineBindPoint,
1890 VkPipelineLayout _layout,
1891 uint32_t set,
1892 uint32_t descriptorWriteCount,
1893 const VkWriteDescriptorSet *pDescriptorWrites);
1894
1895 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1896 struct radv_image *image, uint32_t value);
1897
1898 struct radv_fence {
1899 struct radeon_winsys_fence *fence;
1900 struct wsi_fence *fence_wsi;
1901 bool submitted;
1902 bool signalled;
1903
1904 uint32_t syncobj;
1905 uint32_t temp_syncobj;
1906 };
1907
1908 /* radv_nir_to_llvm.c */
1909 struct radv_shader_variant_info;
1910 struct radv_nir_compiler_options;
1911
1912 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1913 struct nir_shader *geom_shader,
1914 struct ac_shader_binary *binary,
1915 struct ac_shader_config *config,
1916 struct radv_shader_variant_info *shader_info,
1917 const struct radv_nir_compiler_options *option);
1918
1919 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1920 struct ac_shader_binary *binary,
1921 struct ac_shader_config *config,
1922 struct radv_shader_variant_info *shader_info,
1923 struct nir_shader *const *nir,
1924 int nir_count,
1925 const struct radv_nir_compiler_options *options);
1926
1927 /* radv_shader_info.h */
1928 struct radv_shader_info;
1929
1930 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1931 const struct radv_nir_compiler_options *options,
1932 struct radv_shader_info *info);
1933
1934 struct radeon_winsys_sem;
1935
1936 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1937 \
1938 static inline struct __radv_type * \
1939 __radv_type ## _from_handle(__VkType _handle) \
1940 { \
1941 return (struct __radv_type *) _handle; \
1942 } \
1943 \
1944 static inline __VkType \
1945 __radv_type ## _to_handle(struct __radv_type *_obj) \
1946 { \
1947 return (__VkType) _obj; \
1948 }
1949
1950 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1951 \
1952 static inline struct __radv_type * \
1953 __radv_type ## _from_handle(__VkType _handle) \
1954 { \
1955 return (struct __radv_type *)(uintptr_t) _handle; \
1956 } \
1957 \
1958 static inline __VkType \
1959 __radv_type ## _to_handle(struct __radv_type *_obj) \
1960 { \
1961 return (__VkType)(uintptr_t) _obj; \
1962 }
1963
1964 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1965 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1966
1967 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1968 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1969 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1970 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1971 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1972
1973 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1974 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1975 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1976 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1977 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1978 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1979 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1980 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1981 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1982 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1983 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1984 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1985 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1986 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1987 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1988 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1989 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1990 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1991 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1992 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1993 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1994
1995 #endif /* RADV_PRIVATE_H */