projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Fix up 2_10_10_10 alpha sign.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "radv_descriptor_set.h"
61 #include "radv_extensions.h"
62
63 #include <llvm-c/TargetMachine.h>
64
65 /* Pre-declarations needed for WSI entrypoints */
66 struct wl_surface;
67 struct wl_display;
68 typedef struct xcb_connection_t xcb_connection_t;
69 typedef uint32_t xcb_visualid_t;
70 typedef uint32_t xcb_window_t;
71
72 #include <vulkan/vulkan.h>
73 #include <vulkan/vulkan_intel.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vk_android_native_buffer.h>
76
77 #include "radv_entrypoints.h"
78
79 #include "wsi_common.h"
80
81 #define ATI_VENDOR_ID 0x1002
82
83 #define MAX_VBS 32
84 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_RTS 8
86 #define MAX_VIEWPORTS 16
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
94 #define MAX_SAMPLES_LOG2 4
95 #define NUM_META_FS_KEYS 13
96 #define RADV_MAX_DRM_DEVICES 8
97 #define MAX_VIEWS 8
98
99 #define NUM_DEPTH_CLEAR_PIPELINES 3
100
101 /*
102 * This is the point we switch from using CP to compute shader
103 * for certain buffer operations.
104 */
105 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
106
107 enum radv_mem_heap {
108 RADV_MEM_HEAP_VRAM,
109 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
110 RADV_MEM_HEAP_GTT,
111 RADV_MEM_HEAP_COUNT
112 };
113
114 enum radv_mem_type {
115 RADV_MEM_TYPE_VRAM,
116 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
117 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
118 RADV_MEM_TYPE_GTT_CACHED,
119 RADV_MEM_TYPE_COUNT
120 };
121
122 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
123
124 static inline uint32_t
125 align_u32(uint32_t v, uint32_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline uint32_t
132 align_u32_npot(uint32_t v, uint32_t a)
133 {
134 return (v + a - 1) / a * a;
135 }
136
137 static inline uint64_t
138 align_u64(uint64_t v, uint64_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 static inline int32_t
145 align_i32(int32_t v, int32_t a)
146 {
147 assert(a != 0 && a == (a & -a));
148 return (v + a - 1) & ~(a - 1);
149 }
150
151 /** Alignment must be a power of 2. */
152 static inline bool
153 radv_is_aligned(uintmax_t n, uintmax_t a)
154 {
155 assert(a == (a & -a));
156 return (n & (a - 1)) == 0;
157 }
158
159 static inline uint32_t
160 round_up_u32(uint32_t v, uint32_t a)
161 {
162 return (v + a - 1) / a;
163 }
164
165 static inline uint64_t
166 round_up_u64(uint64_t v, uint64_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint32_t
172 radv_minify(uint32_t n, uint32_t levels)
173 {
174 if (unlikely(n == 0))
175 return 0;
176 else
177 return MAX2(n >> levels, 1);
178 }
179 static inline float
180 radv_clamp_f(float f, float min, float max)
181 {
182 assert(min < max);
183
184 if (f > max)
185 return max;
186 else if (f < min)
187 return min;
188 else
189 return f;
190 }
191
192 static inline bool
193 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
194 {
195 if (*inout_mask & clear_mask) {
196 *inout_mask &= ~clear_mask;
197 return true;
198 } else {
199 return false;
200 }
201 }
202
203 #define for_each_bit(b, dword) \
204 for (uint32_t __dword = (dword); \
205 (b) = __builtin_ffs(__dword) - 1, __dword; \
206 __dword &= ~(1 << (b)))
207
208 #define typed_memcpy(dest, src, count) ({ \
209 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
210 memcpy((dest), (src), (count) * sizeof(*(src))); \
211 })
212
213 /* Whenever we generate an error, pass it through this function. Useful for
214 * debugging, where we can break on it. Only call at error site, not when
215 * propagating errors. Might be useful to plug in a stack trace here.
216 */
217
218 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
219
220 #ifdef DEBUG
221 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
222 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
223 #else
224 #define vk_error(error) error
225 #define vk_errorf(error, format, ...) error
226 #endif
227
228 void __radv_finishme(const char *file, int line, const char *format, ...)
229 radv_printflike(3, 4);
230 void radv_loge(const char *format, ...) radv_printflike(1, 2);
231 void radv_loge_v(const char *format, va_list va);
232
233 /**
234 * Print a FINISHME message, including its source location.
235 */
236 #define radv_finishme(format, ...) \
237 do { \
238 static bool reported = false; \
239 if (!reported) { \
240 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
241 reported = true; \
242 } \
243 } while (0)
244
245 /* A non-fatal assert. Useful for debugging. */
246 #ifdef DEBUG
247 #define radv_assert(x) ({ \
248 if (unlikely(!(x))) \
249 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
250 })
251 #else
252 #define radv_assert(x)
253 #endif
254
255 #define stub_return(v) \
256 do { \
257 radv_finishme("stub %s", __func__); \
258 return (v); \
259 } while (0)
260
261 #define stub() \
262 do { \
263 radv_finishme("stub %s", __func__); \
264 return; \
265 } while (0)
266
267 void *radv_lookup_entrypoint_unchecked(const char *name);
268 void *radv_lookup_entrypoint_checked(const char *name,
269 uint32_t core_version,
270 const struct radv_instance_extension_table *instance,
271 const struct radv_device_extension_table *device);
272
273 struct radv_physical_device {
274 VK_LOADER_DATA _loader_data;
275
276 struct radv_instance * instance;
277
278 struct radeon_winsys *ws;
279 struct radeon_info rad_info;
280 char path[20];
281 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
282 uint8_t driver_uuid[VK_UUID_SIZE];
283 uint8_t device_uuid[VK_UUID_SIZE];
284 uint8_t cache_uuid[VK_UUID_SIZE];
285
286 int local_fd;
287 struct wsi_device wsi_device;
288
289 bool has_rbplus; /* if RB+ register exist */
290 bool rbplus_allowed; /* if RB+ is allowed */
291 bool has_clear_state;
292 bool cpdma_prefetch_writes_memory;
293 bool has_scissor_bug;
294
295 bool has_out_of_order_rast;
296 bool out_of_order_rast_allowed;
297
298 /* Whether DCC should be enabled for MSAA textures. */
299 bool dcc_msaa_allowed;
300
301 /* This is the drivers on-disk cache used as a fallback as opposed to
302 * the pipeline cache defined by apps.
303 */
304 struct disk_cache * disk_cache;
305
306 VkPhysicalDeviceMemoryProperties memory_properties;
307 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
308
309 struct radv_device_extension_table supported_extensions;
310 };
311
312 struct radv_instance {
313 VK_LOADER_DATA _loader_data;
314
315 VkAllocationCallbacks alloc;
316
317 uint32_t apiVersion;
318 int physicalDeviceCount;
319 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
320
321 uint64_t debug_flags;
322 uint64_t perftest_flags;
323
324 struct vk_debug_report_instance debug_report_callbacks;
325
326 struct radv_instance_extension_table enabled_extensions;
327 };
328
329 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
330 void radv_finish_wsi(struct radv_physical_device *physical_device);
331
332 bool radv_instance_extension_supported(const char *name);
333 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
334 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
335 const char *name);
336
337 struct cache_entry;
338
339 struct radv_pipeline_cache {
340 struct radv_device * device;
341 pthread_mutex_t mutex;
342
343 uint32_t total_size;
344 uint32_t table_size;
345 uint32_t kernel_count;
346 struct cache_entry ** hash_table;
347 bool modified;
348
349 VkAllocationCallbacks alloc;
350 };
351
352 struct radv_pipeline_key {
353 uint32_t instance_rate_inputs;
354 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
355 uint64_t vertex_alpha_adjust;
356 unsigned tess_input_vertices;
357 uint32_t col_format;
358 uint32_t is_int8;
359 uint32_t is_int10;
360 uint8_t log2_ps_iter_samples;
361 uint8_t log2_num_samples;
362 uint32_t multisample : 1;
363 uint32_t has_multiview_view_index : 1;
364 uint32_t optimisations_disabled : 1;
365 };
366
367 void
368 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
369 struct radv_device *device);
370 void
371 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
372 void
373 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
374 const void *data, size_t size);
375
376 struct radv_shader_variant;
377
378 bool
379 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
380 struct radv_pipeline_cache *cache,
381 const unsigned char *sha1,
382 struct radv_shader_variant **variants);
383
384 void
385 radv_pipeline_cache_insert_shaders(struct radv_device *device,
386 struct radv_pipeline_cache *cache,
387 const unsigned char *sha1,
388 struct radv_shader_variant **variants,
389 const void *const *codes,
390 const unsigned *code_sizes);
391
392 enum radv_blit_ds_layout {
393 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
394 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
395 RADV_BLIT_DS_LAYOUT_COUNT,
396 };
397
398 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
399 {
400 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
401 }
402
403 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
404 {
405 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
406 }
407
408 enum radv_meta_dst_layout {
409 RADV_META_DST_LAYOUT_GENERAL,
410 RADV_META_DST_LAYOUT_OPTIMAL,
411 RADV_META_DST_LAYOUT_COUNT,
412 };
413
414 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
415 {
416 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
417 }
418
419 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
420 {
421 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
422 }
423
424 struct radv_meta_state {
425 VkAllocationCallbacks alloc;
426
427 struct radv_pipeline_cache cache;
428
429 /**
430 * Use array element `i` for images with `2^i` samples.
431 */
432 struct {
433 VkRenderPass render_pass[NUM_META_FS_KEYS];
434 VkPipeline color_pipelines[NUM_META_FS_KEYS];
435
436 VkRenderPass depthstencil_rp;
437 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
438 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
439 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
440 } clear[1 + MAX_SAMPLES_LOG2];
441
442 VkPipelineLayout clear_color_p_layout;
443 VkPipelineLayout clear_depth_p_layout;
444 struct {
445 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
446
447 /** Pipeline that blits from a 1D image. */
448 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
449
450 /** Pipeline that blits from a 2D image. */
451 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
452
453 /** Pipeline that blits from a 3D image. */
454 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
455
456 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
457 VkPipeline depth_only_1d_pipeline;
458 VkPipeline depth_only_2d_pipeline;
459 VkPipeline depth_only_3d_pipeline;
460
461 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
462 VkPipeline stencil_only_1d_pipeline;
463 VkPipeline stencil_only_2d_pipeline;
464 VkPipeline stencil_only_3d_pipeline;
465 VkPipelineLayout pipeline_layout;
466 VkDescriptorSetLayout ds_layout;
467 } blit;
468
469 struct {
470 VkPipelineLayout p_layouts[5];
471 VkDescriptorSetLayout ds_layouts[5];
472 VkPipeline pipelines[5][NUM_META_FS_KEYS];
473
474 VkPipeline depth_only_pipeline[5];
475
476 VkPipeline stencil_only_pipeline[5];
477 } blit2d[1 + MAX_SAMPLES_LOG2];
478
479 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
480 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
481 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
482
483 struct {
484 VkPipelineLayout img_p_layout;
485 VkDescriptorSetLayout img_ds_layout;
486 VkPipeline pipeline;
487 VkPipeline pipeline_3d;
488 } itob;
489 struct {
490 VkPipelineLayout img_p_layout;
491 VkDescriptorSetLayout img_ds_layout;
492 VkPipeline pipeline;
493 VkPipeline pipeline_3d;
494 } btoi;
495 struct {
496 VkPipelineLayout img_p_layout;
497 VkDescriptorSetLayout img_ds_layout;
498 VkPipeline pipeline;
499 VkPipeline pipeline_3d;
500 } itoi;
501 struct {
502 VkPipelineLayout img_p_layout;
503 VkDescriptorSetLayout img_ds_layout;
504 VkPipeline pipeline;
505 VkPipeline pipeline_3d;
506 } cleari;
507
508 struct {
509 VkPipelineLayout p_layout;
510 VkPipeline pipeline[NUM_META_FS_KEYS];
511 VkRenderPass pass[NUM_META_FS_KEYS];
512 } resolve;
513
514 struct {
515 VkDescriptorSetLayout ds_layout;
516 VkPipelineLayout p_layout;
517 struct {
518 VkPipeline pipeline;
519 VkPipeline i_pipeline;
520 VkPipeline srgb_pipeline;
521 } rc[MAX_SAMPLES_LOG2];
522 } resolve_compute;
523
524 struct {
525 VkDescriptorSetLayout ds_layout;
526 VkPipelineLayout p_layout;
527
528 struct {
529 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
530 VkPipeline pipeline[NUM_META_FS_KEYS];
531 } rc[MAX_SAMPLES_LOG2];
532 } resolve_fragment;
533
534 struct {
535 VkPipelineLayout p_layout;
536 VkPipeline decompress_pipeline;
537 VkPipeline resummarize_pipeline;
538 VkRenderPass pass;
539 } depth_decomp[1 + MAX_SAMPLES_LOG2];
540
541 struct {
542 VkPipelineLayout p_layout;
543 VkPipeline cmask_eliminate_pipeline;
544 VkPipeline fmask_decompress_pipeline;
545 VkPipeline dcc_decompress_pipeline;
546 VkRenderPass pass;
547
548 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
549 VkPipelineLayout dcc_decompress_compute_p_layout;
550 VkPipeline dcc_decompress_compute_pipeline;
551 } fast_clear_flush;
552
553 struct {
554 VkPipelineLayout fill_p_layout;
555 VkPipelineLayout copy_p_layout;
556 VkDescriptorSetLayout fill_ds_layout;
557 VkDescriptorSetLayout copy_ds_layout;
558 VkPipeline fill_pipeline;
559 VkPipeline copy_pipeline;
560 } buffer;
561
562 struct {
563 VkDescriptorSetLayout ds_layout;
564 VkPipelineLayout p_layout;
565 VkPipeline occlusion_query_pipeline;
566 VkPipeline pipeline_statistics_query_pipeline;
567 } query;
568 };
569
570 /* queue types */
571 #define RADV_QUEUE_GENERAL 0
572 #define RADV_QUEUE_COMPUTE 1
573 #define RADV_QUEUE_TRANSFER 2
574
575 #define RADV_MAX_QUEUE_FAMILIES 3
576
577 enum ring_type radv_queue_family_to_ring(int f);
578
579 struct radv_queue {
580 VK_LOADER_DATA _loader_data;
581 struct radv_device * device;
582 struct radeon_winsys_ctx *hw_ctx;
583 enum radeon_ctx_priority priority;
584 uint32_t queue_family_index;
585 int queue_idx;
586 VkDeviceQueueCreateFlags flags;
587
588 uint32_t scratch_size;
589 uint32_t compute_scratch_size;
590 uint32_t esgs_ring_size;
591 uint32_t gsvs_ring_size;
592 bool has_tess_rings;
593 bool has_sample_positions;
594
595 struct radeon_winsys_bo *scratch_bo;
596 struct radeon_winsys_bo *descriptor_bo;
597 struct radeon_winsys_bo *compute_scratch_bo;
598 struct radeon_winsys_bo *esgs_ring_bo;
599 struct radeon_winsys_bo *gsvs_ring_bo;
600 struct radeon_winsys_bo *tess_rings_bo;
601 struct radeon_winsys_cs *initial_preamble_cs;
602 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
603 struct radeon_winsys_cs *continue_preamble_cs;
604 };
605
606 struct radv_bo_list {
607 struct radv_winsys_bo_list list;
608 unsigned capacity;
609 pthread_mutex_t mutex;
610 };
611
612 struct radv_device {
613 VK_LOADER_DATA _loader_data;
614
615 VkAllocationCallbacks alloc;
616
617 struct radv_instance * instance;
618 struct radeon_winsys *ws;
619
620 struct radv_meta_state meta_state;
621
622 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
623 int queue_count[RADV_MAX_QUEUE_FAMILIES];
624 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
625
626 bool always_use_syncobj;
627 bool llvm_supports_spill;
628 bool has_distributed_tess;
629 bool pbb_allowed;
630 bool dfsm_allowed;
631 uint32_t tess_offchip_block_dw_size;
632 uint32_t scratch_waves;
633 uint32_t dispatch_initiator;
634
635 uint32_t gs_table_depth;
636
637 /* MSAA sample locations.
638 * The first index is the sample index.
639 * The second index is the coordinate: X, Y. */
640 float sample_locations_1x[1][2];
641 float sample_locations_2x[2][2];
642 float sample_locations_4x[4][2];
643 float sample_locations_8x[8][2];
644 float sample_locations_16x[16][2];
645
646 /* CIK and later */
647 uint32_t gfx_init_size_dw;
648 struct radeon_winsys_bo *gfx_init;
649
650 struct radeon_winsys_bo *trace_bo;
651 uint32_t *trace_id_ptr;
652
653 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
654 bool keep_shader_info;
655
656 struct radv_physical_device *physical_device;
657
658 /* Backup in-memory cache to be used if the app doesn't provide one */
659 struct radv_pipeline_cache * mem_cache;
660
661 /*
662 * use different counters so MSAA MRTs get consecutive surface indices,
663 * even if MASK is allocated in between.
664 */
665 uint32_t image_mrt_offset_counter;
666 uint32_t fmask_mrt_offset_counter;
667 struct list_head shader_slabs;
668 mtx_t shader_slab_mutex;
669
670 /* For detecting VM faults reported by dmesg. */
671 uint64_t dmesg_timestamp;
672
673 struct radv_device_extension_table enabled_extensions;
674
675 /* Whether the driver uses a global BO list. */
676 bool use_global_bo_list;
677
678 struct radv_bo_list bo_list;
679 };
680
681 struct radv_device_memory {
682 struct radeon_winsys_bo *bo;
683 /* for dedicated allocations */
684 struct radv_image *image;
685 struct radv_buffer *buffer;
686 uint32_t type_index;
687 VkDeviceSize map_size;
688 void * map;
689 void * user_ptr;
690 };
691
692
693 struct radv_descriptor_range {
694 uint64_t va;
695 uint32_t size;
696 };
697
698 struct radv_descriptor_set {
699 const struct radv_descriptor_set_layout *layout;
700 uint32_t size;
701
702 struct radeon_winsys_bo *bo;
703 uint64_t va;
704 uint32_t *mapped_ptr;
705 struct radv_descriptor_range *dynamic_descriptors;
706
707 struct radeon_winsys_bo *descriptors[0];
708 };
709
710 struct radv_push_descriptor_set
711 {
712 struct radv_descriptor_set set;
713 uint32_t capacity;
714 };
715
716 struct radv_descriptor_pool_entry {
717 uint32_t offset;
718 uint32_t size;
719 struct radv_descriptor_set *set;
720 };
721
722 struct radv_descriptor_pool {
723 struct radeon_winsys_bo *bo;
724 uint8_t *mapped_ptr;
725 uint64_t current_offset;
726 uint64_t size;
727
728 uint8_t *host_memory_base;
729 uint8_t *host_memory_ptr;
730 uint8_t *host_memory_end;
731
732 uint32_t entry_count;
733 uint32_t max_entry_count;
734 struct radv_descriptor_pool_entry entries[0];
735 };
736
737 struct radv_descriptor_update_template_entry {
738 VkDescriptorType descriptor_type;
739
740 /* The number of descriptors to update */
741 uint32_t descriptor_count;
742
743 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
744 uint32_t dst_offset;
745
746 /* In dwords. Not valid/used for dynamic descriptors */
747 uint32_t dst_stride;
748
749 uint32_t buffer_offset;
750
751 /* Only valid for combined image samplers and samplers */
752 uint16_t has_sampler;
753
754 /* In bytes */
755 size_t src_offset;
756 size_t src_stride;
757
758 /* For push descriptors */
759 const uint32_t *immutable_samplers;
760 };
761
762 struct radv_descriptor_update_template {
763 uint32_t entry_count;
764 VkPipelineBindPoint bind_point;
765 struct radv_descriptor_update_template_entry entry[0];
766 };
767
768 struct radv_buffer {
769 VkDeviceSize size;
770
771 VkBufferUsageFlags usage;
772 VkBufferCreateFlags flags;
773
774 /* Set when bound */
775 struct radeon_winsys_bo * bo;
776 VkDeviceSize offset;
777
778 bool shareable;
779 };
780
781 enum radv_dynamic_state_bits {
782 RADV_DYNAMIC_VIEWPORT = 1 << 0,
783 RADV_DYNAMIC_SCISSOR = 1 << 1,
784 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
785 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
786 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
787 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
788 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
789 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
790 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
791 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
792 RADV_DYNAMIC_ALL = (1 << 10) - 1,
793 };
794
795 enum radv_cmd_dirty_bits {
796 /* Keep the dynamic state dirty bits in sync with
797 * enum radv_dynamic_state_bits */
798 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
799 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
800 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
801 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
802 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
803 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
804 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
805 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
806 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
807 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
808 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
809 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
810 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
811 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
812 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
813 };
814
815 enum radv_cmd_flush_bits {
816 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
817 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
818 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
819 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
820 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
821 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
822 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
823 /* Same as above, but only writes back and doesn't invalidate */
824 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
825 /* Framebuffer caches */
826 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
827 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
828 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
829 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
830 /* Engine synchronization. */
831 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
832 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
833 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
834 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
835
836 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
837 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
838 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
839 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
840 };
841
842 struct radv_vertex_binding {
843 struct radv_buffer * buffer;
844 VkDeviceSize offset;
845 };
846
847 struct radv_viewport_state {
848 uint32_t count;
849 VkViewport viewports[MAX_VIEWPORTS];
850 };
851
852 struct radv_scissor_state {
853 uint32_t count;
854 VkRect2D scissors[MAX_SCISSORS];
855 };
856
857 struct radv_discard_rectangle_state {
858 uint32_t count;
859 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
860 };
861
862 struct radv_dynamic_state {
863 /**
864 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
865 * Defines the set of saved dynamic state.
866 */
867 uint32_t mask;
868
869 struct radv_viewport_state viewport;
870
871 struct radv_scissor_state scissor;
872
873 float line_width;
874
875 struct {
876 float bias;
877 float clamp;
878 float slope;
879 } depth_bias;
880
881 float blend_constants[4];
882
883 struct {
884 float min;
885 float max;
886 } depth_bounds;
887
888 struct {
889 uint32_t front;
890 uint32_t back;
891 } stencil_compare_mask;
892
893 struct {
894 uint32_t front;
895 uint32_t back;
896 } stencil_write_mask;
897
898 struct {
899 uint32_t front;
900 uint32_t back;
901 } stencil_reference;
902
903 struct radv_discard_rectangle_state discard_rectangle;
904 };
905
906 extern const struct radv_dynamic_state default_dynamic_state;
907
908 const char *
909 radv_get_debug_option_name(int id);
910
911 const char *
912 radv_get_perftest_option_name(int id);
913
914 /**
915 * Attachment state when recording a renderpass instance.
916 *
917 * The clear value is valid only if there exists a pending clear.
918 */
919 struct radv_attachment_state {
920 VkImageAspectFlags pending_clear_aspects;
921 uint32_t cleared_views;
922 VkClearValue clear_value;
923 VkImageLayout current_layout;
924 };
925
926 struct radv_descriptor_state {
927 struct radv_descriptor_set *sets[MAX_SETS];
928 uint32_t dirty;
929 uint32_t valid;
930 struct radv_push_descriptor_set push_set;
931 bool push_dirty;
932 };
933
934 struct radv_cmd_state {
935 /* Vertex descriptors */
936 uint64_t vb_va;
937 unsigned vb_size;
938
939 bool predicating;
940 uint32_t dirty;
941
942 uint32_t prefetch_L2_mask;
943
944 struct radv_pipeline * pipeline;
945 struct radv_pipeline * emitted_pipeline;
946 struct radv_pipeline * compute_pipeline;
947 struct radv_pipeline * emitted_compute_pipeline;
948 struct radv_framebuffer * framebuffer;
949 struct radv_render_pass * pass;
950 const struct radv_subpass * subpass;
951 struct radv_dynamic_state dynamic;
952 struct radv_attachment_state * attachments;
953 VkRect2D render_area;
954
955 /* Index buffer */
956 struct radv_buffer *index_buffer;
957 uint64_t index_offset;
958 uint32_t index_type;
959 uint32_t max_index_count;
960 uint64_t index_va;
961 int32_t last_index_type;
962
963 int32_t last_primitive_reset_en;
964 uint32_t last_primitive_reset_index;
965 enum radv_cmd_flush_bits flush_bits;
966 unsigned active_occlusion_queries;
967 bool perfect_occlusion_queries_enabled;
968 float offset_scale;
969 uint32_t trace_id;
970 uint32_t last_ia_multi_vgt_param;
971
972 uint32_t last_num_instances;
973 uint32_t last_first_instance;
974 uint32_t last_vertex_offset;
975 };
976
977 struct radv_cmd_pool {
978 VkAllocationCallbacks alloc;
979 struct list_head cmd_buffers;
980 struct list_head free_cmd_buffers;
981 uint32_t queue_family_index;
982 };
983
984 struct radv_cmd_buffer_upload {
985 uint8_t *map;
986 unsigned offset;
987 uint64_t size;
988 struct radeon_winsys_bo *upload_bo;
989 struct list_head list;
990 };
991
992 enum radv_cmd_buffer_status {
993 RADV_CMD_BUFFER_STATUS_INVALID,
994 RADV_CMD_BUFFER_STATUS_INITIAL,
995 RADV_CMD_BUFFER_STATUS_RECORDING,
996 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
997 RADV_CMD_BUFFER_STATUS_PENDING,
998 };
999
1000 struct radv_cmd_buffer {
1001 VK_LOADER_DATA _loader_data;
1002
1003 struct radv_device * device;
1004
1005 struct radv_cmd_pool * pool;
1006 struct list_head pool_link;
1007
1008 VkCommandBufferUsageFlags usage_flags;
1009 VkCommandBufferLevel level;
1010 enum radv_cmd_buffer_status status;
1011 struct radeon_winsys_cs *cs;
1012 struct radv_cmd_state state;
1013 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1014 uint32_t queue_family_index;
1015
1016 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1017 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1018 VkShaderStageFlags push_constant_stages;
1019 struct radv_descriptor_set meta_push_descriptors;
1020
1021 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1022
1023 struct radv_cmd_buffer_upload upload;
1024
1025 uint32_t scratch_size_needed;
1026 uint32_t compute_scratch_size_needed;
1027 uint32_t esgs_ring_size_needed;
1028 uint32_t gsvs_ring_size_needed;
1029 bool tess_rings_needed;
1030 bool sample_positions_needed;
1031
1032 VkResult record_result;
1033
1034 int ring_offsets_idx; /* just used for verification */
1035 uint32_t gfx9_fence_offset;
1036 struct radeon_winsys_bo *gfx9_fence_bo;
1037 uint32_t gfx9_fence_idx;
1038
1039 /**
1040 * Whether a query pool has been resetted and we have to flush caches.
1041 */
1042 bool pending_reset_query;
1043 };
1044
1045 struct radv_image;
1046
1047 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1048
1049 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1050 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1051
1052 void cik_create_gfx_config(struct radv_device *device);
1053
1054 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1055 int count, const VkViewport *viewports);
1056 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1057 int count, const VkRect2D *scissors,
1058 const VkViewport *viewports, bool can_use_guardband);
1059 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1060 bool instanced_draw, bool indirect_draw,
1061 uint32_t draw_vertex_count);
1062 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1063 bool predicated,
1064 enum chip_class chip_class,
1065 bool is_mec,
1066 unsigned event, unsigned event_flags,
1067 unsigned data_sel,
1068 uint64_t va,
1069 uint32_t old_fence,
1070 uint32_t new_fence);
1071
1072 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1073 bool predicated,
1074 uint64_t va, uint32_t ref,
1075 uint32_t mask);
1076 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1077 enum chip_class chip_class,
1078 uint32_t *fence_ptr, uint64_t va,
1079 bool is_mec,
1080 enum radv_cmd_flush_bits flush_bits);
1081 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1082 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1083 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1084 uint64_t src_va, uint64_t dest_va,
1085 uint64_t size);
1086 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1087 unsigned size);
1088 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1089 uint64_t size, unsigned value);
1090 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1091 bool
1092 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1093 unsigned size,
1094 unsigned alignment,
1095 unsigned *out_offset,
1096 void **ptr);
1097 void
1098 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1099 const struct radv_subpass *subpass,
1100 bool transitions);
1101 bool
1102 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1103 unsigned size, unsigned alignmnet,
1104 const void *data, unsigned *out_offset);
1105
1106 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1107 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1108 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1109 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1110 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1111 unsigned radv_cayman_get_maxdist(int log_samples);
1112 void radv_device_init_msaa(struct radv_device *device);
1113 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1114 struct radv_image *image,
1115 VkClearDepthStencilValue ds_clear_value,
1116 VkImageAspectFlags aspects);
1117 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1118 struct radv_image *image,
1119 int idx,
1120 uint32_t color_values[2]);
1121 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1122 struct radv_image *image,
1123 bool value);
1124 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1125 struct radeon_winsys_bo *bo,
1126 uint64_t offset, uint64_t size, uint32_t value);
1127 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1128 bool radv_get_memory_fd(struct radv_device *device,
1129 struct radv_device_memory *memory,
1130 int *pFD);
1131
1132 static inline struct radv_descriptor_state *
1133 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1134 VkPipelineBindPoint bind_point)
1135 {
1136 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1137 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1138 return &cmd_buffer->descriptors[bind_point];
1139 }
1140
1141 /*
1142 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1143 *
1144 * Limitations: Can't call normal dispatch functions without binding or rebinding
1145 * the compute pipeline.
1146 */
1147 void radv_unaligned_dispatch(
1148 struct radv_cmd_buffer *cmd_buffer,
1149 uint32_t x,
1150 uint32_t y,
1151 uint32_t z);
1152
1153 struct radv_event {
1154 struct radeon_winsys_bo *bo;
1155 uint64_t *map;
1156 };
1157
1158 struct radv_shader_module;
1159
1160 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1161 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1162 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1163 void
1164 radv_hash_shaders(unsigned char *hash,
1165 const VkPipelineShaderStageCreateInfo **stages,
1166 const struct radv_pipeline_layout *layout,
1167 const struct radv_pipeline_key *key,
1168 uint32_t flags);
1169
1170 static inline gl_shader_stage
1171 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1172 {
1173 assert(__builtin_popcount(vk_stage) == 1);
1174 return ffs(vk_stage) - 1;
1175 }
1176
1177 static inline VkShaderStageFlagBits
1178 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1179 {
1180 return (1 << mesa_stage);
1181 }
1182
1183 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1184
1185 #define radv_foreach_stage(stage, stage_bits) \
1186 for (gl_shader_stage stage, \
1187 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1188 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1189 __tmp &= ~(1 << (stage)))
1190
1191 unsigned radv_format_meta_fs_key(VkFormat format);
1192
1193 struct radv_multisample_state {
1194 uint32_t db_eqaa;
1195 uint32_t pa_sc_line_cntl;
1196 uint32_t pa_sc_mode_cntl_0;
1197 uint32_t pa_sc_mode_cntl_1;
1198 uint32_t pa_sc_aa_config;
1199 uint32_t pa_sc_aa_mask[2];
1200 unsigned num_samples;
1201 };
1202
1203 struct radv_prim_vertex_count {
1204 uint8_t min;
1205 uint8_t incr;
1206 };
1207
1208 struct radv_vertex_elements_info {
1209 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1210 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1211 uint32_t binding[MAX_VERTEX_ATTRIBS];
1212 uint32_t offset[MAX_VERTEX_ATTRIBS];
1213 uint32_t count;
1214 };
1215
1216 struct radv_ia_multi_vgt_param_helpers {
1217 uint32_t base;
1218 bool partial_es_wave;
1219 uint8_t primgroup_size;
1220 bool wd_switch_on_eop;
1221 bool ia_switch_on_eoi;
1222 bool partial_vs_wave;
1223 };
1224
1225 #define SI_GS_PER_ES 128
1226
1227 struct radv_pipeline {
1228 struct radv_device * device;
1229 struct radv_dynamic_state dynamic_state;
1230
1231 struct radv_pipeline_layout * layout;
1232
1233 bool need_indirect_descriptor_sets;
1234 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1235 struct radv_shader_variant *gs_copy_shader;
1236 VkShaderStageFlags active_stages;
1237
1238 struct radeon_winsys_cs cs;
1239
1240 struct radv_vertex_elements_info vertex_elements;
1241
1242 uint32_t binding_stride[MAX_VBS];
1243
1244 uint32_t user_data_0[MESA_SHADER_STAGES];
1245 union {
1246 struct {
1247 struct radv_multisample_state ms;
1248 uint32_t spi_baryc_cntl;
1249 bool prim_restart_enable;
1250 unsigned esgs_ring_size;
1251 unsigned gsvs_ring_size;
1252 uint32_t vtx_base_sgpr;
1253 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1254 uint8_t vtx_emit_num;
1255 struct radv_prim_vertex_count prim_vertex_count;
1256 bool can_use_guardband;
1257 uint32_t needed_dynamic_state;
1258 bool disable_out_of_order_rast_for_occlusion;
1259
1260 /* Used for rbplus */
1261 uint32_t col_format;
1262 uint32_t cb_target_mask;
1263 } graphics;
1264 };
1265
1266 unsigned max_waves;
1267 unsigned scratch_bytes_per_wave;
1268 };
1269
1270 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1271 {
1272 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1273 }
1274
1275 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1276 {
1277 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1278 }
1279
1280 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1281 gl_shader_stage stage,
1282 int idx);
1283
1284 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1285
1286 struct radv_graphics_pipeline_create_info {
1287 bool use_rectlist;
1288 bool db_depth_clear;
1289 bool db_stencil_clear;
1290 bool db_depth_disable_expclear;
1291 bool db_stencil_disable_expclear;
1292 bool db_flush_depth_inplace;
1293 bool db_flush_stencil_inplace;
1294 bool db_resummarize;
1295 uint32_t custom_blend_mode;
1296 };
1297
1298 VkResult
1299 radv_graphics_pipeline_create(VkDevice device,
1300 VkPipelineCache cache,
1301 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1302 const struct radv_graphics_pipeline_create_info *extra,
1303 const VkAllocationCallbacks *alloc,
1304 VkPipeline *pPipeline);
1305
1306 struct vk_format_description;
1307 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1308 int first_non_void);
1309 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1310 int first_non_void);
1311 uint32_t radv_translate_colorformat(VkFormat format);
1312 uint32_t radv_translate_color_numformat(VkFormat format,
1313 const struct vk_format_description *desc,
1314 int first_non_void);
1315 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1316 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1317 uint32_t radv_translate_dbformat(VkFormat format);
1318 uint32_t radv_translate_tex_dataformat(VkFormat format,
1319 const struct vk_format_description *desc,
1320 int first_non_void);
1321 uint32_t radv_translate_tex_numformat(VkFormat format,
1322 const struct vk_format_description *desc,
1323 int first_non_void);
1324 bool radv_format_pack_clear_color(VkFormat format,
1325 uint32_t clear_vals[2],
1326 VkClearColorValue *value);
1327 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1328 bool radv_dcc_formats_compatible(VkFormat format1,
1329 VkFormat format2);
1330
1331 struct radv_fmask_info {
1332 uint64_t offset;
1333 uint64_t size;
1334 unsigned alignment;
1335 unsigned pitch_in_pixels;
1336 unsigned bank_height;
1337 unsigned slice_tile_max;
1338 unsigned tile_mode_index;
1339 unsigned tile_swizzle;
1340 };
1341
1342 struct radv_cmask_info {
1343 uint64_t offset;
1344 uint64_t size;
1345 unsigned alignment;
1346 unsigned slice_tile_max;
1347 };
1348
1349 struct radv_image {
1350 VkImageType type;
1351 /* The original VkFormat provided by the client. This may not match any
1352 * of the actual surface formats.
1353 */
1354 VkFormat vk_format;
1355 VkImageAspectFlags aspects;
1356 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1357 struct ac_surf_info info;
1358 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1359 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1360
1361 VkDeviceSize size;
1362 uint32_t alignment;
1363
1364 unsigned queue_family_mask;
1365 bool exclusive;
1366 bool shareable;
1367
1368 /* Set when bound */
1369 struct radeon_winsys_bo *bo;
1370 VkDeviceSize offset;
1371 uint64_t dcc_offset;
1372 uint64_t htile_offset;
1373 bool tc_compatible_htile;
1374 struct radeon_surf surface;
1375
1376 struct radv_fmask_info fmask;
1377 struct radv_cmask_info cmask;
1378 uint64_t clear_value_offset;
1379 uint64_t dcc_pred_offset;
1380
1381 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1382 VkDeviceMemory owned_memory;
1383 };
1384
1385 /* Whether the image has a htile that is known consistent with the contents of
1386 * the image. */
1387 bool radv_layout_has_htile(const struct radv_image *image,
1388 VkImageLayout layout,
1389 unsigned queue_mask);
1390
1391 /* Whether the image has a htile that is known consistent with the contents of
1392 * the image and is allowed to be in compressed form.
1393 *
1394 * If this is false reads that don't use the htile should be able to return
1395 * correct results.
1396 */
1397 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1398 VkImageLayout layout,
1399 unsigned queue_mask);
1400
1401 bool radv_layout_can_fast_clear(const struct radv_image *image,
1402 VkImageLayout layout,
1403 unsigned queue_mask);
1404
1405 bool radv_layout_dcc_compressed(const struct radv_image *image,
1406 VkImageLayout layout,
1407 unsigned queue_mask);
1408
1409 /**
1410 * Return whether the image has CMASK metadata for color surfaces.
1411 */
1412 static inline bool
1413 radv_image_has_cmask(const struct radv_image *image)
1414 {
1415 return image->cmask.size;
1416 }
1417
1418 /**
1419 * Return whether the image has FMASK metadata for color surfaces.
1420 */
1421 static inline bool
1422 radv_image_has_fmask(const struct radv_image *image)
1423 {
1424 return image->fmask.size;
1425 }
1426
1427 /**
1428 * Return whether the image has DCC metadata for color surfaces.
1429 */
1430 static inline bool
1431 radv_image_has_dcc(const struct radv_image *image)
1432 {
1433 return image->surface.dcc_size;
1434 }
1435
1436 /**
1437 * Return whether DCC metadata is enabled for a level.
1438 */
1439 static inline bool
1440 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1441 {
1442 return radv_image_has_dcc(image) &&
1443 level < image->surface.num_dcc_levels;
1444 }
1445
1446 /**
1447 * Return whether the image has HTILE metadata for depth surfaces.
1448 */
1449 static inline bool
1450 radv_image_has_htile(const struct radv_image *image)
1451 {
1452 return image->surface.htile_size;
1453 }
1454
1455 /**
1456 * Return whether HTILE metadata is enabled for a level.
1457 */
1458 static inline bool
1459 radv_htile_enabled(const struct radv_image *image, unsigned level)
1460 {
1461 return radv_image_has_htile(image) && level == 0;
1462 }
1463
1464 /**
1465 * Return whether the image is TC-compatible HTILE.
1466 */
1467 static inline bool
1468 radv_image_is_tc_compat_htile(const struct radv_image *image)
1469 {
1470 return radv_image_has_htile(image) && image->tc_compatible_htile;
1471 }
1472
1473 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1474
1475 static inline uint32_t
1476 radv_get_layerCount(const struct radv_image *image,
1477 const VkImageSubresourceRange *range)
1478 {
1479 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1480 image->info.array_size - range->baseArrayLayer : range->layerCount;
1481 }
1482
1483 static inline uint32_t
1484 radv_get_levelCount(const struct radv_image *image,
1485 const VkImageSubresourceRange *range)
1486 {
1487 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1488 image->info.levels - range->baseMipLevel : range->levelCount;
1489 }
1490
1491 struct radeon_bo_metadata;
1492 void
1493 radv_init_metadata(struct radv_device *device,
1494 struct radv_image *image,
1495 struct radeon_bo_metadata *metadata);
1496
1497 struct radv_image_view {
1498 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1499 struct radeon_winsys_bo *bo;
1500
1501 VkImageViewType type;
1502 VkImageAspectFlags aspect_mask;
1503 VkFormat vk_format;
1504 uint32_t base_layer;
1505 uint32_t layer_count;
1506 uint32_t base_mip;
1507 uint32_t level_count;
1508 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1509
1510 uint32_t descriptor[16];
1511
1512 /* Descriptor for use as a storage image as opposed to a sampled image.
1513 * This has a few differences for cube maps (e.g. type).
1514 */
1515 uint32_t storage_descriptor[16];
1516 };
1517
1518 struct radv_image_create_info {
1519 const VkImageCreateInfo *vk_info;
1520 bool scanout;
1521 bool no_metadata_planes;
1522 };
1523
1524 VkResult radv_image_create(VkDevice _device,
1525 const struct radv_image_create_info *info,
1526 const VkAllocationCallbacks* alloc,
1527 VkImage *pImage);
1528
1529 VkResult
1530 radv_image_from_gralloc(VkDevice device_h,
1531 const VkImageCreateInfo *base_info,
1532 const VkNativeBufferANDROID *gralloc_info,
1533 const VkAllocationCallbacks *alloc,
1534 VkImage *out_image_h);
1535
1536 void radv_image_view_init(struct radv_image_view *view,
1537 struct radv_device *device,
1538 const VkImageViewCreateInfo* pCreateInfo);
1539
1540 struct radv_buffer_view {
1541 struct radeon_winsys_bo *bo;
1542 VkFormat vk_format;
1543 uint64_t range; /**< VkBufferViewCreateInfo::range */
1544 uint32_t state[4];
1545 };
1546 void radv_buffer_view_init(struct radv_buffer_view *view,
1547 struct radv_device *device,
1548 const VkBufferViewCreateInfo* pCreateInfo);
1549
1550 static inline struct VkExtent3D
1551 radv_sanitize_image_extent(const VkImageType imageType,
1552 const struct VkExtent3D imageExtent)
1553 {
1554 switch (imageType) {
1555 case VK_IMAGE_TYPE_1D:
1556 return (VkExtent3D) { imageExtent.width, 1, 1 };
1557 case VK_IMAGE_TYPE_2D:
1558 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1559 case VK_IMAGE_TYPE_3D:
1560 return imageExtent;
1561 default:
1562 unreachable("invalid image type");
1563 }
1564 }
1565
1566 static inline struct VkOffset3D
1567 radv_sanitize_image_offset(const VkImageType imageType,
1568 const struct VkOffset3D imageOffset)
1569 {
1570 switch (imageType) {
1571 case VK_IMAGE_TYPE_1D:
1572 return (VkOffset3D) { imageOffset.x, 0, 0 };
1573 case VK_IMAGE_TYPE_2D:
1574 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1575 case VK_IMAGE_TYPE_3D:
1576 return imageOffset;
1577 default:
1578 unreachable("invalid image type");
1579 }
1580 }
1581
1582 static inline bool
1583 radv_image_extent_compare(const struct radv_image *image,
1584 const VkExtent3D *extent)
1585 {
1586 if (extent->width != image->info.width ||
1587 extent->height != image->info.height ||
1588 extent->depth != image->info.depth)
1589 return false;
1590 return true;
1591 }
1592
1593 struct radv_sampler {
1594 uint32_t state[4];
1595 };
1596
1597 struct radv_color_buffer_info {
1598 uint64_t cb_color_base;
1599 uint64_t cb_color_cmask;
1600 uint64_t cb_color_fmask;
1601 uint64_t cb_dcc_base;
1602 uint32_t cb_color_pitch;
1603 uint32_t cb_color_slice;
1604 uint32_t cb_color_view;
1605 uint32_t cb_color_info;
1606 uint32_t cb_color_attrib;
1607 uint32_t cb_color_attrib2;
1608 uint32_t cb_dcc_control;
1609 uint32_t cb_color_cmask_slice;
1610 uint32_t cb_color_fmask_slice;
1611 };
1612
1613 struct radv_ds_buffer_info {
1614 uint64_t db_z_read_base;
1615 uint64_t db_stencil_read_base;
1616 uint64_t db_z_write_base;
1617 uint64_t db_stencil_write_base;
1618 uint64_t db_htile_data_base;
1619 uint32_t db_depth_info;
1620 uint32_t db_z_info;
1621 uint32_t db_stencil_info;
1622 uint32_t db_depth_view;
1623 uint32_t db_depth_size;
1624 uint32_t db_depth_slice;
1625 uint32_t db_htile_surface;
1626 uint32_t pa_su_poly_offset_db_fmt_cntl;
1627 uint32_t db_z_info2;
1628 uint32_t db_stencil_info2;
1629 float offset_scale;
1630 };
1631
1632 struct radv_attachment_info {
1633 union {
1634 struct radv_color_buffer_info cb;
1635 struct radv_ds_buffer_info ds;
1636 };
1637 struct radv_image_view *attachment;
1638 };
1639
1640 struct radv_framebuffer {
1641 uint32_t width;
1642 uint32_t height;
1643 uint32_t layers;
1644
1645 uint32_t attachment_count;
1646 struct radv_attachment_info attachments[0];
1647 };
1648
1649 struct radv_subpass_barrier {
1650 VkPipelineStageFlags src_stage_mask;
1651 VkAccessFlags src_access_mask;
1652 VkAccessFlags dst_access_mask;
1653 };
1654
1655 struct radv_subpass {
1656 uint32_t input_count;
1657 uint32_t color_count;
1658 VkAttachmentReference * input_attachments;
1659 VkAttachmentReference * color_attachments;
1660 VkAttachmentReference * resolve_attachments;
1661 VkAttachmentReference depth_stencil_attachment;
1662
1663 /** Subpass has at least one resolve attachment */
1664 bool has_resolve;
1665
1666 struct radv_subpass_barrier start_barrier;
1667
1668 uint32_t view_mask;
1669 VkSampleCountFlagBits max_sample_count;
1670 };
1671
1672 struct radv_render_pass_attachment {
1673 VkFormat format;
1674 uint32_t samples;
1675 VkAttachmentLoadOp load_op;
1676 VkAttachmentLoadOp stencil_load_op;
1677 VkImageLayout initial_layout;
1678 VkImageLayout final_layout;
1679 uint32_t view_mask;
1680 };
1681
1682 struct radv_render_pass {
1683 uint32_t attachment_count;
1684 uint32_t subpass_count;
1685 VkAttachmentReference * subpass_attachments;
1686 struct radv_render_pass_attachment * attachments;
1687 struct radv_subpass_barrier end_barrier;
1688 struct radv_subpass subpasses[0];
1689 };
1690
1691 VkResult radv_device_init_meta(struct radv_device *device);
1692 void radv_device_finish_meta(struct radv_device *device);
1693
1694 struct radv_query_pool {
1695 struct radeon_winsys_bo *bo;
1696 uint32_t stride;
1697 uint32_t availability_offset;
1698 uint64_t size;
1699 char *ptr;
1700 VkQueryType type;
1701 uint32_t pipeline_stats_mask;
1702 };
1703
1704 struct radv_semaphore {
1705 /* use a winsys sem for non-exportable */
1706 struct radeon_winsys_sem *sem;
1707 uint32_t syncobj;
1708 uint32_t temp_syncobj;
1709 };
1710
1711 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1712 int num_wait_sems,
1713 const VkSemaphore *wait_sems,
1714 int num_signal_sems,
1715 const VkSemaphore *signal_sems,
1716 VkFence fence);
1717 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1718
1719 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1720 VkPipelineBindPoint bind_point,
1721 struct radv_descriptor_set *set,
1722 unsigned idx);
1723
1724 void
1725 radv_update_descriptor_sets(struct radv_device *device,
1726 struct radv_cmd_buffer *cmd_buffer,
1727 VkDescriptorSet overrideSet,
1728 uint32_t descriptorWriteCount,
1729 const VkWriteDescriptorSet *pDescriptorWrites,
1730 uint32_t descriptorCopyCount,
1731 const VkCopyDescriptorSet *pDescriptorCopies);
1732
1733 void
1734 radv_update_descriptor_set_with_template(struct radv_device *device,
1735 struct radv_cmd_buffer *cmd_buffer,
1736 struct radv_descriptor_set *set,
1737 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1738 const void *pData);
1739
1740 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1741 VkPipelineBindPoint pipelineBindPoint,
1742 VkPipelineLayout _layout,
1743 uint32_t set,
1744 uint32_t descriptorWriteCount,
1745 const VkWriteDescriptorSet *pDescriptorWrites);
1746
1747 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1748 struct radv_image *image, uint32_t value);
1749
1750 struct radv_fence {
1751 struct radeon_winsys_fence *fence;
1752 bool submitted;
1753 bool signalled;
1754
1755 uint32_t syncobj;
1756 uint32_t temp_syncobj;
1757 };
1758
1759 /* radv_nir_to_llvm.c */
1760 struct radv_shader_variant_info;
1761 struct radv_nir_compiler_options;
1762
1763 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1764 struct nir_shader *geom_shader,
1765 struct ac_shader_binary *binary,
1766 struct ac_shader_config *config,
1767 struct radv_shader_variant_info *shader_info,
1768 const struct radv_nir_compiler_options *option);
1769
1770 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1771 struct ac_shader_binary *binary,
1772 struct ac_shader_config *config,
1773 struct radv_shader_variant_info *shader_info,
1774 struct nir_shader *const *nir,
1775 int nir_count,
1776 const struct radv_nir_compiler_options *options);
1777
1778 /* radv_shader_info.h */
1779 struct radv_shader_info;
1780
1781 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1782 const struct radv_nir_compiler_options *options,
1783 struct radv_shader_info *info);
1784
1785 struct radeon_winsys_sem;
1786
1787 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1788 \
1789 static inline struct __radv_type * \
1790 __radv_type ## _from_handle(__VkType _handle) \
1791 { \
1792 return (struct __radv_type *) _handle; \
1793 } \
1794 \
1795 static inline __VkType \
1796 __radv_type ## _to_handle(struct __radv_type *_obj) \
1797 { \
1798 return (__VkType) _obj; \
1799 }
1800
1801 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1802 \
1803 static inline struct __radv_type * \
1804 __radv_type ## _from_handle(__VkType _handle) \
1805 { \
1806 return (struct __radv_type *)(uintptr_t) _handle; \
1807 } \
1808 \
1809 static inline __VkType \
1810 __radv_type ## _to_handle(struct __radv_type *_obj) \
1811 { \
1812 return (__VkType)(uintptr_t) _obj; \
1813 }
1814
1815 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1816 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1817
1818 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1819 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1820 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1821 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1822 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1823
1824 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1825 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1826 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1827 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1828 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1829 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1830 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1831 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1832 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1833 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1834 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1835 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1836 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1837 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1838 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1839 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1840 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1841 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1842 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1843 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1844 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1845
1846 #endif /* RADV_PRIVATE_H */