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radv/gfx9: fix buffer to image for 3d images on compute queues
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280
281 VkPhysicalDeviceMemoryProperties memory_properties;
282 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 uint64_t perftest_flags;
296 };
297
298 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
299 void radv_finish_wsi(struct radv_physical_device *physical_device);
300
301 bool radv_instance_extension_supported(const char *name);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
303 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
304 const char *name);
305
306 struct cache_entry;
307
308 struct radv_pipeline_cache {
309 struct radv_device * device;
310 pthread_mutex_t mutex;
311
312 uint32_t total_size;
313 uint32_t table_size;
314 uint32_t kernel_count;
315 struct cache_entry ** hash_table;
316 bool modified;
317
318 VkAllocationCallbacks alloc;
319 };
320
321 struct radv_pipeline_key {
322 uint32_t instance_rate_inputs;
323 unsigned tess_input_vertices;
324 uint32_t col_format;
325 uint32_t is_int8;
326 uint32_t is_int10;
327 uint32_t multisample : 1;
328 uint32_t has_multiview_view_index : 1;
329 };
330
331 void
332 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
333 struct radv_device *device);
334 void
335 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
336 void
337 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
338 const void *data, size_t size);
339
340 struct radv_shader_variant;
341
342 bool
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
344 struct radv_pipeline_cache *cache,
345 const unsigned char *sha1,
346 struct radv_shader_variant **variants);
347
348 void
349 radv_pipeline_cache_insert_shaders(struct radv_device *device,
350 struct radv_pipeline_cache *cache,
351 const unsigned char *sha1,
352 struct radv_shader_variant **variants,
353 const void *const *codes,
354 const unsigned *code_sizes);
355
356 enum radv_blit_ds_layout {
357 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
358 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
359 RADV_BLIT_DS_LAYOUT_COUNT,
360 };
361
362 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
363 {
364 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
365 }
366
367 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
368 {
369 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
370 }
371
372 struct radv_meta_state {
373 VkAllocationCallbacks alloc;
374
375 struct radv_pipeline_cache cache;
376
377 /**
378 * Use array element `i` for images with `2^i` samples.
379 */
380 struct {
381 VkRenderPass render_pass[NUM_META_FS_KEYS];
382 VkPipeline color_pipelines[NUM_META_FS_KEYS];
383
384 VkRenderPass depthstencil_rp;
385 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
386 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
387 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
388 } clear[1 + MAX_SAMPLES_LOG2];
389
390 VkPipelineLayout clear_color_p_layout;
391 VkPipelineLayout clear_depth_p_layout;
392 struct {
393 VkRenderPass render_pass[NUM_META_FS_KEYS];
394
395 /** Pipeline that blits from a 1D image. */
396 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
397
398 /** Pipeline that blits from a 2D image. */
399 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
400
401 /** Pipeline that blits from a 3D image. */
402 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
403
404 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
405 VkPipeline depth_only_1d_pipeline;
406 VkPipeline depth_only_2d_pipeline;
407 VkPipeline depth_only_3d_pipeline;
408
409 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
410 VkPipeline stencil_only_1d_pipeline;
411 VkPipeline stencil_only_2d_pipeline;
412 VkPipeline stencil_only_3d_pipeline;
413 VkPipelineLayout pipeline_layout;
414 VkDescriptorSetLayout ds_layout;
415 } blit;
416
417 struct {
418 VkRenderPass render_passes[NUM_META_FS_KEYS];
419
420 VkPipelineLayout p_layouts[3];
421 VkDescriptorSetLayout ds_layouts[3];
422 VkPipeline pipelines[3][NUM_META_FS_KEYS];
423
424 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
425 VkPipeline depth_only_pipeline[3];
426
427 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
428 VkPipeline stencil_only_pipeline[3];
429 } blit2d;
430
431 struct {
432 VkPipelineLayout img_p_layout;
433 VkDescriptorSetLayout img_ds_layout;
434 VkPipeline pipeline;
435 VkPipeline pipeline_3d;
436 } itob;
437 struct {
438 VkPipelineLayout img_p_layout;
439 VkDescriptorSetLayout img_ds_layout;
440 VkPipeline pipeline;
441 VkPipeline pipeline_3d;
442 } btoi;
443 struct {
444 VkPipelineLayout img_p_layout;
445 VkDescriptorSetLayout img_ds_layout;
446 VkPipeline pipeline;
447 VkPipeline pipeline_3d;
448 } itoi;
449 struct {
450 VkPipelineLayout img_p_layout;
451 VkDescriptorSetLayout img_ds_layout;
452 VkPipeline pipeline;
453 VkPipeline pipeline_3d;
454 } cleari;
455
456 struct {
457 VkPipelineLayout p_layout;
458 VkPipeline pipeline;
459 VkRenderPass pass;
460 } resolve;
461
462 struct {
463 VkDescriptorSetLayout ds_layout;
464 VkPipelineLayout p_layout;
465 struct {
466 VkPipeline pipeline;
467 VkPipeline i_pipeline;
468 VkPipeline srgb_pipeline;
469 } rc[MAX_SAMPLES_LOG2];
470 } resolve_compute;
471
472 struct {
473 VkDescriptorSetLayout ds_layout;
474 VkPipelineLayout p_layout;
475
476 struct {
477 VkRenderPass render_pass[NUM_META_FS_KEYS];
478 VkPipeline pipeline[NUM_META_FS_KEYS];
479 } rc[MAX_SAMPLES_LOG2];
480 } resolve_fragment;
481
482 struct {
483 VkPipelineLayout p_layout;
484 VkPipeline decompress_pipeline;
485 VkPipeline resummarize_pipeline;
486 VkRenderPass pass;
487 } depth_decomp[1 + MAX_SAMPLES_LOG2];
488
489 struct {
490 VkPipelineLayout p_layout;
491 VkPipeline cmask_eliminate_pipeline;
492 VkPipeline fmask_decompress_pipeline;
493 VkRenderPass pass;
494 } fast_clear_flush;
495
496 struct {
497 VkPipelineLayout fill_p_layout;
498 VkPipelineLayout copy_p_layout;
499 VkDescriptorSetLayout fill_ds_layout;
500 VkDescriptorSetLayout copy_ds_layout;
501 VkPipeline fill_pipeline;
502 VkPipeline copy_pipeline;
503 } buffer;
504
505 struct {
506 VkDescriptorSetLayout ds_layout;
507 VkPipelineLayout p_layout;
508 VkPipeline occlusion_query_pipeline;
509 VkPipeline pipeline_statistics_query_pipeline;
510 } query;
511 };
512
513 /* queue types */
514 #define RADV_QUEUE_GENERAL 0
515 #define RADV_QUEUE_COMPUTE 1
516 #define RADV_QUEUE_TRANSFER 2
517
518 #define RADV_MAX_QUEUE_FAMILIES 3
519
520 enum ring_type radv_queue_family_to_ring(int f);
521
522 struct radv_queue {
523 VK_LOADER_DATA _loader_data;
524 struct radv_device * device;
525 struct radeon_winsys_ctx *hw_ctx;
526 enum radeon_ctx_priority priority;
527 uint32_t queue_family_index;
528 int queue_idx;
529
530 uint32_t scratch_size;
531 uint32_t compute_scratch_size;
532 uint32_t esgs_ring_size;
533 uint32_t gsvs_ring_size;
534 bool has_tess_rings;
535 bool has_sample_positions;
536
537 struct radeon_winsys_bo *scratch_bo;
538 struct radeon_winsys_bo *descriptor_bo;
539 struct radeon_winsys_bo *compute_scratch_bo;
540 struct radeon_winsys_bo *esgs_ring_bo;
541 struct radeon_winsys_bo *gsvs_ring_bo;
542 struct radeon_winsys_bo *tess_factor_ring_bo;
543 struct radeon_winsys_bo *tess_offchip_ring_bo;
544 struct radeon_winsys_cs *initial_preamble_cs;
545 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
546 struct radeon_winsys_cs *continue_preamble_cs;
547 };
548
549 struct radv_device {
550 VK_LOADER_DATA _loader_data;
551
552 VkAllocationCallbacks alloc;
553
554 struct radv_instance * instance;
555 struct radeon_winsys *ws;
556
557 struct radv_meta_state meta_state;
558
559 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
560 int queue_count[RADV_MAX_QUEUE_FAMILIES];
561 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
562
563 bool llvm_supports_spill;
564 bool has_distributed_tess;
565 bool dfsm_allowed;
566 uint32_t tess_offchip_block_dw_size;
567 uint32_t scratch_waves;
568 uint32_t dispatch_initiator;
569
570 uint32_t gs_table_depth;
571
572 /* MSAA sample locations.
573 * The first index is the sample index.
574 * The second index is the coordinate: X, Y. */
575 float sample_locations_1x[1][2];
576 float sample_locations_2x[2][2];
577 float sample_locations_4x[4][2];
578 float sample_locations_8x[8][2];
579 float sample_locations_16x[16][2];
580
581 /* CIK and later */
582 uint32_t gfx_init_size_dw;
583 struct radeon_winsys_bo *gfx_init;
584
585 struct radeon_winsys_bo *trace_bo;
586 uint32_t *trace_id_ptr;
587
588 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
589 bool keep_shader_info;
590
591 struct radv_physical_device *physical_device;
592
593 /* Backup in-memory cache to be used if the app doesn't provide one */
594 struct radv_pipeline_cache * mem_cache;
595
596 /*
597 * use different counters so MSAA MRTs get consecutive surface indices,
598 * even if MASK is allocated in between.
599 */
600 uint32_t image_mrt_offset_counter;
601 uint32_t fmask_mrt_offset_counter;
602 struct list_head shader_slabs;
603 mtx_t shader_slab_mutex;
604
605 /* For detecting VM faults reported by dmesg. */
606 uint64_t dmesg_timestamp;
607 };
608
609 struct radv_device_memory {
610 struct radeon_winsys_bo *bo;
611 /* for dedicated allocations */
612 struct radv_image *image;
613 struct radv_buffer *buffer;
614 uint32_t type_index;
615 VkDeviceSize map_size;
616 void * map;
617 };
618
619
620 struct radv_descriptor_range {
621 uint64_t va;
622 uint32_t size;
623 };
624
625 struct radv_descriptor_set {
626 const struct radv_descriptor_set_layout *layout;
627 uint32_t size;
628
629 struct radeon_winsys_bo *bo;
630 uint64_t va;
631 uint32_t *mapped_ptr;
632 struct radv_descriptor_range *dynamic_descriptors;
633
634 struct radeon_winsys_bo *descriptors[0];
635 };
636
637 struct radv_push_descriptor_set
638 {
639 struct radv_descriptor_set set;
640 uint32_t capacity;
641 };
642
643 struct radv_descriptor_pool_entry {
644 uint32_t offset;
645 uint32_t size;
646 struct radv_descriptor_set *set;
647 };
648
649 struct radv_descriptor_pool {
650 struct radeon_winsys_bo *bo;
651 uint8_t *mapped_ptr;
652 uint64_t current_offset;
653 uint64_t size;
654
655 uint8_t *host_memory_base;
656 uint8_t *host_memory_ptr;
657 uint8_t *host_memory_end;
658
659 uint32_t entry_count;
660 uint32_t max_entry_count;
661 struct radv_descriptor_pool_entry entries[0];
662 };
663
664 struct radv_descriptor_update_template_entry {
665 VkDescriptorType descriptor_type;
666
667 /* The number of descriptors to update */
668 uint32_t descriptor_count;
669
670 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
671 uint32_t dst_offset;
672
673 /* In dwords. Not valid/used for dynamic descriptors */
674 uint32_t dst_stride;
675
676 uint32_t buffer_offset;
677
678 /* Only valid for combined image samplers and samplers */
679 uint16_t has_sampler;
680
681 /* In bytes */
682 size_t src_offset;
683 size_t src_stride;
684
685 /* For push descriptors */
686 const uint32_t *immutable_samplers;
687 };
688
689 struct radv_descriptor_update_template {
690 uint32_t entry_count;
691 struct radv_descriptor_update_template_entry entry[0];
692 };
693
694 struct radv_buffer {
695 struct radv_device * device;
696 VkDeviceSize size;
697
698 VkBufferUsageFlags usage;
699 VkBufferCreateFlags flags;
700
701 /* Set when bound */
702 struct radeon_winsys_bo * bo;
703 VkDeviceSize offset;
704
705 bool shareable;
706 };
707
708
709 enum radv_cmd_dirty_bits {
710 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
711 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
712 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
713 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
714 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
715 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
716 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
717 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
718 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
719 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
720 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
721 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
722 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
723 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
724 };
725
726 enum radv_cmd_flush_bits {
727 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
728 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
729 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
730 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
731 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
732 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
733 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
734 /* Same as above, but only writes back and doesn't invalidate */
735 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
736 /* Framebuffer caches */
737 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
738 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
739 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
740 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
741 /* Engine synchronization. */
742 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
743 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
744 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
745 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
746
747 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
748 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
749 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
750 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
751 };
752
753 struct radv_vertex_binding {
754 struct radv_buffer * buffer;
755 VkDeviceSize offset;
756 };
757
758 struct radv_viewport_state {
759 uint32_t count;
760 VkViewport viewports[MAX_VIEWPORTS];
761 };
762
763 struct radv_scissor_state {
764 uint32_t count;
765 VkRect2D scissors[MAX_SCISSORS];
766 };
767
768 struct radv_dynamic_state {
769 /**
770 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
771 * Defines the set of saved dynamic state.
772 */
773 uint32_t mask;
774
775 struct radv_viewport_state viewport;
776
777 struct radv_scissor_state scissor;
778
779 float line_width;
780
781 struct {
782 float bias;
783 float clamp;
784 float slope;
785 } depth_bias;
786
787 float blend_constants[4];
788
789 struct {
790 float min;
791 float max;
792 } depth_bounds;
793
794 struct {
795 uint32_t front;
796 uint32_t back;
797 } stencil_compare_mask;
798
799 struct {
800 uint32_t front;
801 uint32_t back;
802 } stencil_write_mask;
803
804 struct {
805 uint32_t front;
806 uint32_t back;
807 } stencil_reference;
808 };
809
810 extern const struct radv_dynamic_state default_dynamic_state;
811
812 const char *
813 radv_get_debug_option_name(int id);
814
815 const char *
816 radv_get_perftest_option_name(int id);
817
818 /**
819 * Attachment state when recording a renderpass instance.
820 *
821 * The clear value is valid only if there exists a pending clear.
822 */
823 struct radv_attachment_state {
824 VkImageAspectFlags pending_clear_aspects;
825 uint32_t cleared_views;
826 VkClearValue clear_value;
827 VkImageLayout current_layout;
828 };
829
830 struct radv_cmd_state {
831 /* Vertex descriptors */
832 bool vb_prefetch_dirty;
833 uint64_t vb_va;
834 unsigned vb_size;
835
836 bool push_descriptors_dirty;
837 bool predicating;
838 uint32_t dirty;
839
840 struct radv_pipeline * pipeline;
841 struct radv_pipeline * emitted_pipeline;
842 struct radv_pipeline * compute_pipeline;
843 struct radv_pipeline * emitted_compute_pipeline;
844 struct radv_framebuffer * framebuffer;
845 struct radv_render_pass * pass;
846 const struct radv_subpass * subpass;
847 struct radv_dynamic_state dynamic;
848 struct radv_attachment_state * attachments;
849 VkRect2D render_area;
850
851 /* Index buffer */
852 struct radv_buffer *index_buffer;
853 uint64_t index_offset;
854 uint32_t index_type;
855 uint32_t max_index_count;
856 uint64_t index_va;
857 int32_t last_index_type;
858
859 int32_t last_primitive_reset_en;
860 uint32_t last_primitive_reset_index;
861 enum radv_cmd_flush_bits flush_bits;
862 unsigned active_occlusion_queries;
863 float offset_scale;
864 uint32_t descriptors_dirty;
865 uint32_t valid_descriptors;
866 uint32_t trace_id;
867 uint32_t last_ia_multi_vgt_param;
868 };
869
870 struct radv_cmd_pool {
871 VkAllocationCallbacks alloc;
872 struct list_head cmd_buffers;
873 struct list_head free_cmd_buffers;
874 uint32_t queue_family_index;
875 };
876
877 struct radv_cmd_buffer_upload {
878 uint8_t *map;
879 unsigned offset;
880 uint64_t size;
881 struct radeon_winsys_bo *upload_bo;
882 struct list_head list;
883 };
884
885 enum radv_cmd_buffer_status {
886 RADV_CMD_BUFFER_STATUS_INVALID,
887 RADV_CMD_BUFFER_STATUS_INITIAL,
888 RADV_CMD_BUFFER_STATUS_RECORDING,
889 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
890 RADV_CMD_BUFFER_STATUS_PENDING,
891 };
892
893 struct radv_cmd_buffer {
894 VK_LOADER_DATA _loader_data;
895
896 struct radv_device * device;
897
898 struct radv_cmd_pool * pool;
899 struct list_head pool_link;
900
901 VkCommandBufferUsageFlags usage_flags;
902 VkCommandBufferLevel level;
903 enum radv_cmd_buffer_status status;
904 struct radeon_winsys_cs *cs;
905 struct radv_cmd_state state;
906 struct radv_vertex_binding vertex_bindings[MAX_VBS];
907 uint32_t queue_family_index;
908
909 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
910 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
911 VkShaderStageFlags push_constant_stages;
912 struct radv_push_descriptor_set push_descriptors;
913 struct radv_descriptor_set meta_push_descriptors;
914 struct radv_descriptor_set *descriptors[MAX_SETS];
915
916 struct radv_cmd_buffer_upload upload;
917
918 uint32_t scratch_size_needed;
919 uint32_t compute_scratch_size_needed;
920 uint32_t esgs_ring_size_needed;
921 uint32_t gsvs_ring_size_needed;
922 bool tess_rings_needed;
923 bool sample_positions_needed;
924
925 VkResult record_result;
926
927 int ring_offsets_idx; /* just used for verification */
928 uint32_t gfx9_fence_offset;
929 struct radeon_winsys_bo *gfx9_fence_bo;
930 uint32_t gfx9_fence_idx;
931 };
932
933 struct radv_image;
934
935 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
936
937 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
938 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
939
940 void cik_create_gfx_config(struct radv_device *device);
941
942 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
943 int count, const VkViewport *viewports);
944 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
945 int count, const VkRect2D *scissors,
946 const VkViewport *viewports, bool can_use_guardband);
947 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
948 bool instanced_draw, bool indirect_draw,
949 uint32_t draw_vertex_count);
950 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
951 bool predicated,
952 enum chip_class chip_class,
953 bool is_mec,
954 unsigned event, unsigned event_flags,
955 unsigned data_sel,
956 uint64_t va,
957 uint32_t old_fence,
958 uint32_t new_fence);
959
960 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
961 bool predicated,
962 uint64_t va, uint32_t ref,
963 uint32_t mask);
964 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
965 bool predicated,
966 enum chip_class chip_class,
967 uint32_t *fence_ptr, uint64_t va,
968 bool is_mec,
969 enum radv_cmd_flush_bits flush_bits);
970 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
971 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
972 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
973 uint64_t src_va, uint64_t dest_va,
974 uint64_t size);
975 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
976 unsigned size);
977 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
978 uint64_t size, unsigned value);
979 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
980 bool
981 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
982 unsigned size,
983 unsigned alignment,
984 unsigned *out_offset,
985 void **ptr);
986 void
987 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
988 const struct radv_subpass *subpass,
989 bool transitions);
990 bool
991 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
992 unsigned size, unsigned alignmnet,
993 const void *data, unsigned *out_offset);
994
995 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
996 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
997 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
998 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
999 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1000 unsigned radv_cayman_get_maxdist(int log_samples);
1001 void radv_device_init_msaa(struct radv_device *device);
1002 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1003 struct radv_image *image,
1004 VkClearDepthStencilValue ds_clear_value,
1005 VkImageAspectFlags aspects);
1006 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1007 struct radv_image *image,
1008 int idx,
1009 uint32_t color_values[2]);
1010 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1011 struct radv_image *image,
1012 bool value);
1013 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1014 struct radeon_winsys_bo *bo,
1015 uint64_t offset, uint64_t size, uint32_t value);
1016 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1017 bool radv_get_memory_fd(struct radv_device *device,
1018 struct radv_device_memory *memory,
1019 int *pFD);
1020
1021 /*
1022 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1023 *
1024 * Limitations: Can't call normal dispatch functions without binding or rebinding
1025 * the compute pipeline.
1026 */
1027 void radv_unaligned_dispatch(
1028 struct radv_cmd_buffer *cmd_buffer,
1029 uint32_t x,
1030 uint32_t y,
1031 uint32_t z);
1032
1033 struct radv_event {
1034 struct radeon_winsys_bo *bo;
1035 uint64_t *map;
1036 };
1037
1038 struct radv_shader_module;
1039
1040 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1041 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1042 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1043 void
1044 radv_hash_shaders(unsigned char *hash,
1045 const VkPipelineShaderStageCreateInfo **stages,
1046 const struct radv_pipeline_layout *layout,
1047 const struct radv_pipeline_key *key,
1048 uint32_t flags);
1049
1050 static inline gl_shader_stage
1051 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1052 {
1053 assert(__builtin_popcount(vk_stage) == 1);
1054 return ffs(vk_stage) - 1;
1055 }
1056
1057 static inline VkShaderStageFlagBits
1058 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1059 {
1060 return (1 << mesa_stage);
1061 }
1062
1063 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1064
1065 #define radv_foreach_stage(stage, stage_bits) \
1066 for (gl_shader_stage stage, \
1067 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1068 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1069 __tmp &= ~(1 << (stage)))
1070
1071 struct radv_depth_stencil_state {
1072 uint32_t db_depth_control;
1073 uint32_t db_stencil_control;
1074 uint32_t db_render_control;
1075 uint32_t db_render_override2;
1076 };
1077
1078 struct radv_blend_state {
1079 uint32_t cb_color_control;
1080 uint32_t cb_target_mask;
1081 uint32_t sx_mrt_blend_opt[8];
1082 uint32_t cb_blend_control[8];
1083
1084 uint32_t spi_shader_col_format;
1085 uint32_t cb_shader_mask;
1086 uint32_t db_alpha_to_mask;
1087 };
1088
1089 unsigned radv_format_meta_fs_key(VkFormat format);
1090
1091 struct radv_raster_state {
1092 uint32_t pa_cl_clip_cntl;
1093 uint32_t spi_interp_control;
1094 uint32_t pa_su_vtx_cntl;
1095 uint32_t pa_su_sc_mode_cntl;
1096 };
1097
1098 struct radv_multisample_state {
1099 uint32_t db_eqaa;
1100 uint32_t pa_sc_line_cntl;
1101 uint32_t pa_sc_mode_cntl_0;
1102 uint32_t pa_sc_mode_cntl_1;
1103 uint32_t pa_sc_aa_config;
1104 uint32_t pa_sc_aa_mask[2];
1105 unsigned num_samples;
1106 };
1107
1108 struct radv_prim_vertex_count {
1109 uint8_t min;
1110 uint8_t incr;
1111 };
1112
1113 struct radv_tessellation_state {
1114 uint32_t ls_hs_config;
1115 uint32_t tcs_in_layout;
1116 uint32_t tcs_out_layout;
1117 uint32_t tcs_out_offsets;
1118 uint32_t offchip_layout;
1119 unsigned num_patches;
1120 unsigned lds_size;
1121 unsigned num_tcs_input_cp;
1122 uint32_t tf_param;
1123 };
1124
1125 struct radv_gs_state {
1126 uint32_t vgt_gs_onchip_cntl;
1127 uint32_t vgt_gs_max_prims_per_subgroup;
1128 uint32_t vgt_esgs_ring_itemsize;
1129 uint32_t lds_size;
1130 };
1131
1132 struct radv_vertex_elements_info {
1133 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1134 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1135 uint32_t binding[MAX_VERTEX_ATTRIBS];
1136 uint32_t offset[MAX_VERTEX_ATTRIBS];
1137 uint32_t count;
1138 };
1139
1140 struct radv_vs_state {
1141 uint32_t pa_cl_vs_out_cntl;
1142 uint32_t spi_shader_pos_format;
1143 uint32_t spi_vs_out_config;
1144 uint32_t vgt_reuse_off;
1145 };
1146
1147 #define SI_GS_PER_ES 128
1148
1149 struct radv_pipeline {
1150 struct radv_device * device;
1151 struct radv_dynamic_state dynamic_state;
1152
1153 struct radv_pipeline_layout * layout;
1154
1155 bool needs_data_cache;
1156 bool need_indirect_descriptor_sets;
1157 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1158 struct radv_shader_variant *gs_copy_shader;
1159 VkShaderStageFlags active_stages;
1160
1161 struct radv_vertex_elements_info vertex_elements;
1162
1163 uint32_t binding_stride[MAX_VBS];
1164
1165 uint32_t user_data_0[MESA_SHADER_STAGES];
1166 union {
1167 struct {
1168 struct radv_blend_state blend;
1169 struct radv_depth_stencil_state ds;
1170 struct radv_raster_state raster;
1171 struct radv_multisample_state ms;
1172 struct radv_tessellation_state tess;
1173 struct radv_gs_state gs;
1174 struct radv_vs_state vs;
1175 uint32_t db_shader_control;
1176 uint32_t shader_z_format;
1177 unsigned prim;
1178 unsigned gs_out;
1179 uint32_t vgt_gs_mode;
1180 bool vgt_primitiveid_en;
1181 bool prim_restart_enable;
1182 bool partial_es_wave;
1183 uint8_t primgroup_size;
1184 unsigned esgs_ring_size;
1185 unsigned gsvs_ring_size;
1186 uint32_t ps_input_cntl[32];
1187 uint32_t ps_input_cntl_num;
1188 uint32_t vgt_shader_stages_en;
1189 uint32_t vtx_base_sgpr;
1190 uint32_t base_ia_multi_vgt_param;
1191 bool wd_switch_on_eop;
1192 bool ia_switch_on_eoi;
1193 bool partial_vs_wave;
1194 uint8_t vtx_emit_num;
1195 uint32_t vtx_reuse_depth;
1196 struct radv_prim_vertex_count prim_vertex_count;
1197 bool can_use_guardband;
1198 } graphics;
1199 };
1200
1201 unsigned max_waves;
1202 unsigned scratch_bytes_per_wave;
1203 };
1204
1205 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1206 {
1207 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1208 }
1209
1210 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1211 {
1212 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1213 }
1214
1215 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1216 gl_shader_stage stage,
1217 int idx);
1218
1219 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1220
1221 struct radv_graphics_pipeline_create_info {
1222 bool use_rectlist;
1223 bool db_depth_clear;
1224 bool db_stencil_clear;
1225 bool db_depth_disable_expclear;
1226 bool db_stencil_disable_expclear;
1227 bool db_flush_depth_inplace;
1228 bool db_flush_stencil_inplace;
1229 bool db_resummarize;
1230 uint32_t custom_blend_mode;
1231 };
1232
1233 VkResult
1234 radv_graphics_pipeline_create(VkDevice device,
1235 VkPipelineCache cache,
1236 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1237 const struct radv_graphics_pipeline_create_info *extra,
1238 const VkAllocationCallbacks *alloc,
1239 VkPipeline *pPipeline);
1240
1241 struct vk_format_description;
1242 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1243 int first_non_void);
1244 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1245 int first_non_void);
1246 uint32_t radv_translate_colorformat(VkFormat format);
1247 uint32_t radv_translate_color_numformat(VkFormat format,
1248 const struct vk_format_description *desc,
1249 int first_non_void);
1250 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1251 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1252 uint32_t radv_translate_dbformat(VkFormat format);
1253 uint32_t radv_translate_tex_dataformat(VkFormat format,
1254 const struct vk_format_description *desc,
1255 int first_non_void);
1256 uint32_t radv_translate_tex_numformat(VkFormat format,
1257 const struct vk_format_description *desc,
1258 int first_non_void);
1259 bool radv_format_pack_clear_color(VkFormat format,
1260 uint32_t clear_vals[2],
1261 VkClearColorValue *value);
1262 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1263 bool radv_dcc_formats_compatible(VkFormat format1,
1264 VkFormat format2);
1265
1266 struct radv_fmask_info {
1267 uint64_t offset;
1268 uint64_t size;
1269 unsigned alignment;
1270 unsigned pitch_in_pixels;
1271 unsigned bank_height;
1272 unsigned slice_tile_max;
1273 unsigned tile_mode_index;
1274 unsigned tile_swizzle;
1275 };
1276
1277 struct radv_cmask_info {
1278 uint64_t offset;
1279 uint64_t size;
1280 unsigned alignment;
1281 unsigned slice_tile_max;
1282 };
1283
1284 struct radv_image {
1285 VkImageType type;
1286 /* The original VkFormat provided by the client. This may not match any
1287 * of the actual surface formats.
1288 */
1289 VkFormat vk_format;
1290 VkImageAspectFlags aspects;
1291 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1292 struct ac_surf_info info;
1293 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1294 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1295
1296 VkDeviceSize size;
1297 uint32_t alignment;
1298
1299 unsigned queue_family_mask;
1300 bool exclusive;
1301 bool shareable;
1302
1303 /* Set when bound */
1304 struct radeon_winsys_bo *bo;
1305 VkDeviceSize offset;
1306 uint64_t dcc_offset;
1307 uint64_t htile_offset;
1308 bool tc_compatible_htile;
1309 struct radeon_surf surface;
1310
1311 struct radv_fmask_info fmask;
1312 struct radv_cmask_info cmask;
1313 uint64_t clear_value_offset;
1314 uint64_t dcc_pred_offset;
1315 };
1316
1317 /* Whether the image has a htile that is known consistent with the contents of
1318 * the image. */
1319 bool radv_layout_has_htile(const struct radv_image *image,
1320 VkImageLayout layout,
1321 unsigned queue_mask);
1322
1323 /* Whether the image has a htile that is known consistent with the contents of
1324 * the image and is allowed to be in compressed form.
1325 *
1326 * If this is false reads that don't use the htile should be able to return
1327 * correct results.
1328 */
1329 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1330 VkImageLayout layout,
1331 unsigned queue_mask);
1332
1333 bool radv_layout_can_fast_clear(const struct radv_image *image,
1334 VkImageLayout layout,
1335 unsigned queue_mask);
1336
1337 static inline bool
1338 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1339 {
1340 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1341 }
1342
1343 static inline bool
1344 radv_htile_enabled(const struct radv_image *image, unsigned level)
1345 {
1346 return image->surface.htile_size && level == 0;
1347 }
1348
1349 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1350
1351 static inline uint32_t
1352 radv_get_layerCount(const struct radv_image *image,
1353 const VkImageSubresourceRange *range)
1354 {
1355 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1356 image->info.array_size - range->baseArrayLayer : range->layerCount;
1357 }
1358
1359 static inline uint32_t
1360 radv_get_levelCount(const struct radv_image *image,
1361 const VkImageSubresourceRange *range)
1362 {
1363 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1364 image->info.levels - range->baseMipLevel : range->levelCount;
1365 }
1366
1367 struct radeon_bo_metadata;
1368 void
1369 radv_init_metadata(struct radv_device *device,
1370 struct radv_image *image,
1371 struct radeon_bo_metadata *metadata);
1372
1373 struct radv_image_view {
1374 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1375 struct radeon_winsys_bo *bo;
1376
1377 VkImageViewType type;
1378 VkImageAspectFlags aspect_mask;
1379 VkFormat vk_format;
1380 uint32_t base_layer;
1381 uint32_t layer_count;
1382 uint32_t base_mip;
1383 uint32_t level_count;
1384 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1385
1386 uint32_t descriptor[16];
1387
1388 /* Descriptor for use as a storage image as opposed to a sampled image.
1389 * This has a few differences for cube maps (e.g. type).
1390 */
1391 uint32_t storage_descriptor[16];
1392 };
1393
1394 struct radv_image_create_info {
1395 const VkImageCreateInfo *vk_info;
1396 bool scanout;
1397 };
1398
1399 VkResult radv_image_create(VkDevice _device,
1400 const struct radv_image_create_info *info,
1401 const VkAllocationCallbacks* alloc,
1402 VkImage *pImage);
1403
1404 void radv_image_view_init(struct radv_image_view *view,
1405 struct radv_device *device,
1406 const VkImageViewCreateInfo* pCreateInfo);
1407
1408 struct radv_buffer_view {
1409 struct radeon_winsys_bo *bo;
1410 VkFormat vk_format;
1411 uint64_t range; /**< VkBufferViewCreateInfo::range */
1412 uint32_t state[4];
1413 };
1414 void radv_buffer_view_init(struct radv_buffer_view *view,
1415 struct radv_device *device,
1416 const VkBufferViewCreateInfo* pCreateInfo);
1417
1418 static inline struct VkExtent3D
1419 radv_sanitize_image_extent(const VkImageType imageType,
1420 const struct VkExtent3D imageExtent)
1421 {
1422 switch (imageType) {
1423 case VK_IMAGE_TYPE_1D:
1424 return (VkExtent3D) { imageExtent.width, 1, 1 };
1425 case VK_IMAGE_TYPE_2D:
1426 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1427 case VK_IMAGE_TYPE_3D:
1428 return imageExtent;
1429 default:
1430 unreachable("invalid image type");
1431 }
1432 }
1433
1434 static inline struct VkOffset3D
1435 radv_sanitize_image_offset(const VkImageType imageType,
1436 const struct VkOffset3D imageOffset)
1437 {
1438 switch (imageType) {
1439 case VK_IMAGE_TYPE_1D:
1440 return (VkOffset3D) { imageOffset.x, 0, 0 };
1441 case VK_IMAGE_TYPE_2D:
1442 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1443 case VK_IMAGE_TYPE_3D:
1444 return imageOffset;
1445 default:
1446 unreachable("invalid image type");
1447 }
1448 }
1449
1450 static inline bool
1451 radv_image_extent_compare(const struct radv_image *image,
1452 const VkExtent3D *extent)
1453 {
1454 if (extent->width != image->info.width ||
1455 extent->height != image->info.height ||
1456 extent->depth != image->info.depth)
1457 return false;
1458 return true;
1459 }
1460
1461 struct radv_sampler {
1462 uint32_t state[4];
1463 };
1464
1465 struct radv_color_buffer_info {
1466 uint64_t cb_color_base;
1467 uint64_t cb_color_cmask;
1468 uint64_t cb_color_fmask;
1469 uint64_t cb_dcc_base;
1470 uint32_t cb_color_pitch;
1471 uint32_t cb_color_slice;
1472 uint32_t cb_color_view;
1473 uint32_t cb_color_info;
1474 uint32_t cb_color_attrib;
1475 uint32_t cb_color_attrib2;
1476 uint32_t cb_dcc_control;
1477 uint32_t cb_color_cmask_slice;
1478 uint32_t cb_color_fmask_slice;
1479 uint32_t cb_clear_value0;
1480 uint32_t cb_clear_value1;
1481 };
1482
1483 struct radv_ds_buffer_info {
1484 uint64_t db_z_read_base;
1485 uint64_t db_stencil_read_base;
1486 uint64_t db_z_write_base;
1487 uint64_t db_stencil_write_base;
1488 uint64_t db_htile_data_base;
1489 uint32_t db_depth_info;
1490 uint32_t db_z_info;
1491 uint32_t db_stencil_info;
1492 uint32_t db_depth_view;
1493 uint32_t db_depth_size;
1494 uint32_t db_depth_slice;
1495 uint32_t db_htile_surface;
1496 uint32_t pa_su_poly_offset_db_fmt_cntl;
1497 uint32_t db_z_info2;
1498 uint32_t db_stencil_info2;
1499 float offset_scale;
1500 };
1501
1502 struct radv_attachment_info {
1503 union {
1504 struct radv_color_buffer_info cb;
1505 struct radv_ds_buffer_info ds;
1506 };
1507 struct radv_image_view *attachment;
1508 };
1509
1510 struct radv_framebuffer {
1511 uint32_t width;
1512 uint32_t height;
1513 uint32_t layers;
1514
1515 uint32_t attachment_count;
1516 struct radv_attachment_info attachments[0];
1517 };
1518
1519 struct radv_subpass_barrier {
1520 VkPipelineStageFlags src_stage_mask;
1521 VkAccessFlags src_access_mask;
1522 VkAccessFlags dst_access_mask;
1523 };
1524
1525 struct radv_subpass {
1526 uint32_t input_count;
1527 uint32_t color_count;
1528 VkAttachmentReference * input_attachments;
1529 VkAttachmentReference * color_attachments;
1530 VkAttachmentReference * resolve_attachments;
1531 VkAttachmentReference depth_stencil_attachment;
1532
1533 /** Subpass has at least one resolve attachment */
1534 bool has_resolve;
1535
1536 struct radv_subpass_barrier start_barrier;
1537
1538 uint32_t view_mask;
1539 };
1540
1541 struct radv_render_pass_attachment {
1542 VkFormat format;
1543 uint32_t samples;
1544 VkAttachmentLoadOp load_op;
1545 VkAttachmentLoadOp stencil_load_op;
1546 VkImageLayout initial_layout;
1547 VkImageLayout final_layout;
1548 uint32_t view_mask;
1549 };
1550
1551 struct radv_render_pass {
1552 uint32_t attachment_count;
1553 uint32_t subpass_count;
1554 VkAttachmentReference * subpass_attachments;
1555 struct radv_render_pass_attachment * attachments;
1556 struct radv_subpass_barrier end_barrier;
1557 struct radv_subpass subpasses[0];
1558 };
1559
1560 VkResult radv_device_init_meta(struct radv_device *device);
1561 void radv_device_finish_meta(struct radv_device *device);
1562
1563 struct radv_query_pool {
1564 struct radeon_winsys_bo *bo;
1565 uint32_t stride;
1566 uint32_t availability_offset;
1567 char *ptr;
1568 VkQueryType type;
1569 uint32_t pipeline_stats_mask;
1570 };
1571
1572 struct radv_semaphore {
1573 /* use a winsys sem for non-exportable */
1574 struct radeon_winsys_sem *sem;
1575 uint32_t syncobj;
1576 uint32_t temp_syncobj;
1577 };
1578
1579 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1580 int num_wait_sems,
1581 const VkSemaphore *wait_sems,
1582 int num_signal_sems,
1583 const VkSemaphore *signal_sems,
1584 VkFence fence);
1585 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1586
1587 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1588 struct radv_descriptor_set *set,
1589 unsigned idx);
1590
1591 void
1592 radv_update_descriptor_sets(struct radv_device *device,
1593 struct radv_cmd_buffer *cmd_buffer,
1594 VkDescriptorSet overrideSet,
1595 uint32_t descriptorWriteCount,
1596 const VkWriteDescriptorSet *pDescriptorWrites,
1597 uint32_t descriptorCopyCount,
1598 const VkCopyDescriptorSet *pDescriptorCopies);
1599
1600 void
1601 radv_update_descriptor_set_with_template(struct radv_device *device,
1602 struct radv_cmd_buffer *cmd_buffer,
1603 struct radv_descriptor_set *set,
1604 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1605 const void *pData);
1606
1607 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1608 VkPipelineBindPoint pipelineBindPoint,
1609 VkPipelineLayout _layout,
1610 uint32_t set,
1611 uint32_t descriptorWriteCount,
1612 const VkWriteDescriptorSet *pDescriptorWrites);
1613
1614 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1615 struct radv_image *image, uint32_t value);
1616 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1617 struct radv_image *image, uint32_t value);
1618
1619 struct radv_fence {
1620 struct radeon_winsys_fence *fence;
1621 bool submitted;
1622 bool signalled;
1623
1624 uint32_t syncobj;
1625 uint32_t temp_syncobj;
1626 };
1627
1628 struct radeon_winsys_sem;
1629
1630 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1631 \
1632 static inline struct __radv_type * \
1633 __radv_type ## _from_handle(__VkType _handle) \
1634 { \
1635 return (struct __radv_type *) _handle; \
1636 } \
1637 \
1638 static inline __VkType \
1639 __radv_type ## _to_handle(struct __radv_type *_obj) \
1640 { \
1641 return (__VkType) _obj; \
1642 }
1643
1644 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1645 \
1646 static inline struct __radv_type * \
1647 __radv_type ## _from_handle(__VkType _handle) \
1648 { \
1649 return (struct __radv_type *)(uintptr_t) _handle; \
1650 } \
1651 \
1652 static inline __VkType \
1653 __radv_type ## _to_handle(struct __radv_type *_obj) \
1654 { \
1655 return (__VkType)(uintptr_t) _obj; \
1656 }
1657
1658 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1659 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1660
1661 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1662 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1663 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1664 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1665 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1666
1667 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1668 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1669 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1670 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1671 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1672 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1673 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1674 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1675 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1676 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1677 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1678 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1679 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1680 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1681 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1682 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1683 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1684 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1685 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1686 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1687 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1688
1689 #endif /* RADV_PRIVATE_H */