projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: do not need to double zero-init the meta state structures
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_extensions {
257 VkExtensionProperties *ext_array;
258 uint32_t num_ext;
259 };
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 struct radv_instance * instance;
265
266 struct radeon_winsys *ws;
267 struct radeon_info rad_info;
268 char path[20];
269 const char * name;
270 uint8_t driver_uuid[VK_UUID_SIZE];
271 uint8_t device_uuid[VK_UUID_SIZE];
272 uint8_t cache_uuid[VK_UUID_SIZE];
273
274 int local_fd;
275 struct wsi_device wsi_device;
276 struct radv_extensions extensions;
277
278 bool has_rbplus; /* if RB+ register exist */
279 bool rbplus_allowed; /* if RB+ is allowed */
280 };
281
282 struct radv_instance {
283 VK_LOADER_DATA _loader_data;
284
285 VkAllocationCallbacks alloc;
286
287 uint32_t apiVersion;
288 int physicalDeviceCount;
289 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
290
291 uint64_t debug_flags;
292 uint64_t perftest_flags;
293 };
294
295 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
296 void radv_finish_wsi(struct radv_physical_device *physical_device);
297
298 struct cache_entry;
299
300 struct radv_pipeline_cache {
301 struct radv_device * device;
302 pthread_mutex_t mutex;
303
304 uint32_t total_size;
305 uint32_t table_size;
306 uint32_t kernel_count;
307 struct cache_entry ** hash_table;
308 bool modified;
309
310 VkAllocationCallbacks alloc;
311 };
312
313 void
314 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
315 struct radv_device *device);
316 void
317 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
318 void
319 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
320 const void *data, size_t size);
321
322 struct radv_shader_variant *
323 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
324 struct radv_pipeline_cache *cache,
325 const unsigned char *sha1);
326
327 struct radv_shader_variant *
328 radv_pipeline_cache_insert_shader(struct radv_device *device,
329 struct radv_pipeline_cache *cache,
330 const unsigned char *sha1,
331 struct radv_shader_variant *variant,
332 const void *code, unsigned code_size);
333
334 struct radv_meta_state {
335 VkAllocationCallbacks alloc;
336
337 struct radv_pipeline_cache cache;
338
339 /**
340 * Use array element `i` for images with `2^i` samples.
341 */
342 struct {
343 VkRenderPass render_pass[NUM_META_FS_KEYS];
344 VkPipeline color_pipelines[NUM_META_FS_KEYS];
345
346 VkRenderPass depthstencil_rp;
347 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
348 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
349 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
350 } clear[1 + MAX_SAMPLES_LOG2];
351
352 VkPipelineLayout clear_color_p_layout;
353 VkPipelineLayout clear_depth_p_layout;
354 struct {
355 VkRenderPass render_pass[NUM_META_FS_KEYS];
356
357 /** Pipeline that blits from a 1D image. */
358 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
359
360 /** Pipeline that blits from a 2D image. */
361 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
362
363 /** Pipeline that blits from a 3D image. */
364 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
365
366 VkRenderPass depth_only_rp;
367 VkPipeline depth_only_1d_pipeline;
368 VkPipeline depth_only_2d_pipeline;
369 VkPipeline depth_only_3d_pipeline;
370
371 VkRenderPass stencil_only_rp;
372 VkPipeline stencil_only_1d_pipeline;
373 VkPipeline stencil_only_2d_pipeline;
374 VkPipeline stencil_only_3d_pipeline;
375 VkPipelineLayout pipeline_layout;
376 VkDescriptorSetLayout ds_layout;
377 } blit;
378
379 struct {
380 VkRenderPass render_passes[NUM_META_FS_KEYS];
381
382 VkPipelineLayout p_layouts[2];
383 VkDescriptorSetLayout ds_layouts[2];
384 VkPipeline pipelines[2][NUM_META_FS_KEYS];
385
386 VkRenderPass depth_only_rp;
387 VkPipeline depth_only_pipeline[2];
388
389 VkRenderPass stencil_only_rp;
390 VkPipeline stencil_only_pipeline[2];
391 } blit2d;
392
393 struct {
394 VkPipelineLayout img_p_layout;
395 VkDescriptorSetLayout img_ds_layout;
396 VkPipeline pipeline;
397 } itob;
398 struct {
399 VkRenderPass render_pass;
400 VkPipelineLayout img_p_layout;
401 VkDescriptorSetLayout img_ds_layout;
402 VkPipeline pipeline;
403 } btoi;
404 struct {
405 VkPipelineLayout img_p_layout;
406 VkDescriptorSetLayout img_ds_layout;
407 VkPipeline pipeline;
408 } itoi;
409 struct {
410 VkPipelineLayout img_p_layout;
411 VkDescriptorSetLayout img_ds_layout;
412 VkPipeline pipeline;
413 } cleari;
414
415 struct {
416 VkPipeline pipeline;
417 VkRenderPass pass;
418 } resolve;
419
420 struct {
421 VkDescriptorSetLayout ds_layout;
422 VkPipelineLayout p_layout;
423 struct {
424 VkPipeline pipeline;
425 VkPipeline i_pipeline;
426 VkPipeline srgb_pipeline;
427 } rc[MAX_SAMPLES_LOG2];
428 } resolve_compute;
429
430 struct {
431 VkDescriptorSetLayout ds_layout;
432 VkPipelineLayout p_layout;
433
434 struct {
435 VkRenderPass render_pass[NUM_META_FS_KEYS];
436 VkPipeline pipeline[NUM_META_FS_KEYS];
437 } rc[MAX_SAMPLES_LOG2];
438 } resolve_fragment;
439
440 struct {
441 VkPipeline decompress_pipeline;
442 VkPipeline resummarize_pipeline;
443 VkRenderPass pass;
444 } depth_decomp[1 + MAX_SAMPLES_LOG2];
445
446 struct {
447 VkPipeline cmask_eliminate_pipeline;
448 VkPipeline fmask_decompress_pipeline;
449 VkRenderPass pass;
450 } fast_clear_flush;
451
452 struct {
453 VkPipelineLayout fill_p_layout;
454 VkPipelineLayout copy_p_layout;
455 VkDescriptorSetLayout fill_ds_layout;
456 VkDescriptorSetLayout copy_ds_layout;
457 VkPipeline fill_pipeline;
458 VkPipeline copy_pipeline;
459 } buffer;
460
461 struct {
462 VkDescriptorSetLayout ds_layout;
463 VkPipelineLayout p_layout;
464 VkPipeline occlusion_query_pipeline;
465 VkPipeline pipeline_statistics_query_pipeline;
466 } query;
467 };
468
469 /* queue types */
470 #define RADV_QUEUE_GENERAL 0
471 #define RADV_QUEUE_COMPUTE 1
472 #define RADV_QUEUE_TRANSFER 2
473
474 #define RADV_MAX_QUEUE_FAMILIES 3
475
476 enum ring_type radv_queue_family_to_ring(int f);
477
478 struct radv_queue {
479 VK_LOADER_DATA _loader_data;
480 struct radv_device * device;
481 struct radeon_winsys_ctx *hw_ctx;
482 int queue_family_index;
483 int queue_idx;
484
485 uint32_t scratch_size;
486 uint32_t compute_scratch_size;
487 uint32_t esgs_ring_size;
488 uint32_t gsvs_ring_size;
489 bool has_tess_rings;
490 bool has_sample_positions;
491
492 struct radeon_winsys_bo *scratch_bo;
493 struct radeon_winsys_bo *descriptor_bo;
494 struct radeon_winsys_bo *compute_scratch_bo;
495 struct radeon_winsys_bo *esgs_ring_bo;
496 struct radeon_winsys_bo *gsvs_ring_bo;
497 struct radeon_winsys_bo *tess_factor_ring_bo;
498 struct radeon_winsys_bo *tess_offchip_ring_bo;
499 struct radeon_winsys_cs *initial_preamble_cs;
500 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
501 struct radeon_winsys_cs *continue_preamble_cs;
502 };
503
504 struct radv_device {
505 VK_LOADER_DATA _loader_data;
506
507 VkAllocationCallbacks alloc;
508
509 struct radv_instance * instance;
510 struct radeon_winsys *ws;
511
512 struct radv_meta_state meta_state;
513
514 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
515 int queue_count[RADV_MAX_QUEUE_FAMILIES];
516 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
517 uint64_t debug_flags;
518
519 bool llvm_supports_spill;
520 bool has_distributed_tess;
521 uint32_t tess_offchip_block_dw_size;
522 uint32_t scratch_waves;
523
524 uint32_t gs_table_depth;
525
526 /* MSAA sample locations.
527 * The first index is the sample index.
528 * The second index is the coordinate: X, Y. */
529 float sample_locations_1x[1][2];
530 float sample_locations_2x[2][2];
531 float sample_locations_4x[4][2];
532 float sample_locations_8x[8][2];
533 float sample_locations_16x[16][2];
534
535 /* CIK and later */
536 uint32_t gfx_init_size_dw;
537 struct radeon_winsys_bo *gfx_init;
538
539 struct radeon_winsys_bo *trace_bo;
540 uint32_t *trace_id_ptr;
541
542 struct radv_physical_device *physical_device;
543
544 /* Backup in-memory cache to be used if the app doesn't provide one */
545 struct radv_pipeline_cache * mem_cache;
546
547 /*
548 * use different counters so MSAA MRTs get consecutive surface indices,
549 * even if MASK is allocated in between.
550 */
551 uint32_t image_mrt_offset_counter;
552 uint32_t fmask_mrt_offset_counter;
553 struct list_head shader_slabs;
554 mtx_t shader_slab_mutex;
555
556 /* For detecting VM faults reported by dmesg. */
557 uint64_t dmesg_timestamp;
558 };
559
560 struct radv_device_memory {
561 struct radeon_winsys_bo *bo;
562 /* for dedicated allocations */
563 struct radv_image *image;
564 struct radv_buffer *buffer;
565 uint32_t type_index;
566 VkDeviceSize map_size;
567 void * map;
568 };
569
570
571 struct radv_descriptor_range {
572 uint64_t va;
573 uint32_t size;
574 };
575
576 struct radv_descriptor_set {
577 const struct radv_descriptor_set_layout *layout;
578 uint32_t size;
579
580 struct radeon_winsys_bo *bo;
581 uint64_t va;
582 uint32_t *mapped_ptr;
583 struct radv_descriptor_range *dynamic_descriptors;
584
585 struct list_head vram_list;
586
587 struct radeon_winsys_bo *descriptors[0];
588 };
589
590 struct radv_push_descriptor_set
591 {
592 struct radv_descriptor_set set;
593 uint32_t capacity;
594 };
595
596 struct radv_descriptor_pool {
597 struct radeon_winsys_bo *bo;
598 uint8_t *mapped_ptr;
599 uint64_t current_offset;
600 uint64_t size;
601
602 struct list_head vram_list;
603
604 uint8_t *host_memory_base;
605 uint8_t *host_memory_ptr;
606 uint8_t *host_memory_end;
607 };
608
609 struct radv_descriptor_update_template_entry {
610 VkDescriptorType descriptor_type;
611
612 /* The number of descriptors to update */
613 uint32_t descriptor_count;
614
615 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
616 uint32_t dst_offset;
617
618 /* In dwords. Not valid/used for dynamic descriptors */
619 uint32_t dst_stride;
620
621 uint32_t buffer_offset;
622
623 /* Only valid for combined image samplers and samplers */
624 uint16_t has_sampler;
625
626 /* In bytes */
627 size_t src_offset;
628 size_t src_stride;
629
630 /* For push descriptors */
631 const uint32_t *immutable_samplers;
632 };
633
634 struct radv_descriptor_update_template {
635 uint32_t entry_count;
636 struct radv_descriptor_update_template_entry entry[0];
637 };
638
639 struct radv_buffer {
640 struct radv_device * device;
641 VkDeviceSize size;
642
643 VkBufferUsageFlags usage;
644 VkBufferCreateFlags flags;
645
646 /* Set when bound */
647 struct radeon_winsys_bo * bo;
648 VkDeviceSize offset;
649 };
650
651
652 enum radv_cmd_dirty_bits {
653 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
654 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
655 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
656 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
657 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
658 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
659 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
660 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
661 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
662 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
663 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
664 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
665 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
666 };
667 typedef uint32_t radv_cmd_dirty_mask_t;
668
669 enum radv_cmd_flush_bits {
670 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
671 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
672 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
673 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
674 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
675 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
676 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
677 /* Same as above, but only writes back and doesn't invalidate */
678 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
679 /* Framebuffer caches */
680 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
681 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
682 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
683 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
684 /* Engine synchronization. */
685 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
686 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
687 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
688 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
689
690 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
691 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
692 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
693 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
694 };
695
696 struct radv_vertex_binding {
697 struct radv_buffer * buffer;
698 VkDeviceSize offset;
699 };
700
701 struct radv_viewport_state {
702 uint32_t count;
703 VkViewport viewports[MAX_VIEWPORTS];
704 };
705
706 struct radv_scissor_state {
707 uint32_t count;
708 VkRect2D scissors[MAX_SCISSORS];
709 };
710
711 struct radv_dynamic_state {
712 struct radv_viewport_state viewport;
713
714 struct radv_scissor_state scissor;
715
716 float line_width;
717
718 struct {
719 float bias;
720 float clamp;
721 float slope;
722 } depth_bias;
723
724 float blend_constants[4];
725
726 struct {
727 float min;
728 float max;
729 } depth_bounds;
730
731 struct {
732 uint32_t front;
733 uint32_t back;
734 } stencil_compare_mask;
735
736 struct {
737 uint32_t front;
738 uint32_t back;
739 } stencil_write_mask;
740
741 struct {
742 uint32_t front;
743 uint32_t back;
744 } stencil_reference;
745 };
746
747 extern const struct radv_dynamic_state default_dynamic_state;
748
749 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
750 const struct radv_dynamic_state *src,
751 uint32_t copy_mask);
752
753 const char *
754 radv_get_debug_option_name(int id);
755
756 const char *
757 radv_get_perftest_option_name(int id);
758
759 /**
760 * Attachment state when recording a renderpass instance.
761 *
762 * The clear value is valid only if there exists a pending clear.
763 */
764 struct radv_attachment_state {
765 VkImageAspectFlags pending_clear_aspects;
766 uint32_t cleared_views;
767 VkClearValue clear_value;
768 VkImageLayout current_layout;
769 };
770
771 struct radv_cmd_state {
772 bool vb_dirty;
773 radv_cmd_dirty_mask_t dirty;
774 bool push_descriptors_dirty;
775 bool predicating;
776
777 struct radv_pipeline * pipeline;
778 struct radv_pipeline * emitted_pipeline;
779 struct radv_pipeline * compute_pipeline;
780 struct radv_pipeline * emitted_compute_pipeline;
781 struct radv_framebuffer * framebuffer;
782 struct radv_render_pass * pass;
783 const struct radv_subpass * subpass;
784 struct radv_dynamic_state dynamic;
785 struct radv_vertex_binding vertex_bindings[MAX_VBS];
786 struct radv_descriptor_set * descriptors[MAX_SETS];
787 struct radv_attachment_state * attachments;
788 VkRect2D render_area;
789 uint32_t index_type;
790 uint32_t max_index_count;
791 uint64_t index_va;
792 int32_t last_primitive_reset_en;
793 uint32_t last_primitive_reset_index;
794 enum radv_cmd_flush_bits flush_bits;
795 unsigned active_occlusion_queries;
796 float offset_scale;
797 uint32_t descriptors_dirty;
798 uint32_t trace_id;
799 uint32_t last_ia_multi_vgt_param;
800 };
801
802 struct radv_cmd_pool {
803 VkAllocationCallbacks alloc;
804 struct list_head cmd_buffers;
805 struct list_head free_cmd_buffers;
806 uint32_t queue_family_index;
807 };
808
809 struct radv_cmd_buffer_upload {
810 uint8_t *map;
811 unsigned offset;
812 uint64_t size;
813 struct radeon_winsys_bo *upload_bo;
814 struct list_head list;
815 };
816
817 struct radv_cmd_buffer {
818 VK_LOADER_DATA _loader_data;
819
820 struct radv_device * device;
821
822 struct radv_cmd_pool * pool;
823 struct list_head pool_link;
824
825 VkCommandBufferUsageFlags usage_flags;
826 VkCommandBufferLevel level;
827 struct radeon_winsys_cs *cs;
828 struct radv_cmd_state state;
829 uint32_t queue_family_index;
830
831 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
832 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
833 VkShaderStageFlags push_constant_stages;
834 struct radv_push_descriptor_set push_descriptors;
835 struct radv_descriptor_set meta_push_descriptors;
836
837 struct radv_cmd_buffer_upload upload;
838
839 uint32_t scratch_size_needed;
840 uint32_t compute_scratch_size_needed;
841 uint32_t esgs_ring_size_needed;
842 uint32_t gsvs_ring_size_needed;
843 bool tess_rings_needed;
844 bool sample_positions_needed;
845
846 VkResult record_result;
847
848 int ring_offsets_idx; /* just used for verification */
849 uint32_t gfx9_fence_offset;
850 struct radeon_winsys_bo *gfx9_fence_bo;
851 uint32_t gfx9_fence_idx;
852 };
853
854 struct radv_image;
855
856 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
857
858 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
859 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
860
861 void cik_create_gfx_config(struct radv_device *device);
862
863 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
864 int count, const VkViewport *viewports);
865 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
866 int count, const VkRect2D *scissors,
867 const VkViewport *viewports, bool can_use_guardband);
868 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
869 bool instanced_draw, bool indirect_draw,
870 uint32_t draw_vertex_count);
871 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
872 bool predicated,
873 enum chip_class chip_class,
874 bool is_mec,
875 unsigned event, unsigned event_flags,
876 unsigned data_sel,
877 uint64_t va,
878 uint32_t old_fence,
879 uint32_t new_fence);
880
881 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
882 bool predicated,
883 uint64_t va, uint32_t ref,
884 uint32_t mask);
885 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
886 bool predicated,
887 enum chip_class chip_class,
888 uint32_t *fence_ptr, uint64_t va,
889 bool is_mec,
890 enum radv_cmd_flush_bits flush_bits);
891 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
892 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
893 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
894 uint64_t src_va, uint64_t dest_va,
895 uint64_t size);
896 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
897 unsigned size);
898 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
899 uint64_t size, unsigned value);
900 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
901 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
902 struct radv_descriptor_set *set,
903 unsigned idx);
904 bool
905 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
906 unsigned size,
907 unsigned alignment,
908 unsigned *out_offset,
909 void **ptr);
910 void
911 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
912 const struct radv_subpass *subpass,
913 bool transitions);
914 bool
915 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
916 unsigned size, unsigned alignmnet,
917 const void *data, unsigned *out_offset);
918 void
919 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
920 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
921 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
922 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
923 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
924 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
925 unsigned radv_cayman_get_maxdist(int log_samples);
926 void radv_device_init_msaa(struct radv_device *device);
927 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
928 struct radv_image *image,
929 VkClearDepthStencilValue ds_clear_value,
930 VkImageAspectFlags aspects);
931 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
932 struct radv_image *image,
933 int idx,
934 uint32_t color_values[2]);
935 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
936 struct radv_image *image,
937 bool value);
938 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
939 struct radeon_winsys_bo *bo,
940 uint64_t offset, uint64_t size, uint32_t value);
941 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
942 bool radv_get_memory_fd(struct radv_device *device,
943 struct radv_device_memory *memory,
944 int *pFD);
945 /*
946 * Takes x,y,z as exact numbers of invocations, instead of blocks.
947 *
948 * Limitations: Can't call normal dispatch functions without binding or rebinding
949 * the compute pipeline.
950 */
951 void radv_unaligned_dispatch(
952 struct radv_cmd_buffer *cmd_buffer,
953 uint32_t x,
954 uint32_t y,
955 uint32_t z);
956
957 struct radv_event {
958 struct radeon_winsys_bo *bo;
959 uint64_t *map;
960 };
961
962 struct radv_shader_module;
963 struct ac_shader_variant_key;
964
965 void
966 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
967 const char *entrypoint,
968 const VkSpecializationInfo *spec_info,
969 const struct radv_pipeline_layout *layout,
970 const struct ac_shader_variant_key *key,
971 uint32_t is_geom_copy_shader);
972
973 static inline gl_shader_stage
974 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
975 {
976 assert(__builtin_popcount(vk_stage) == 1);
977 return ffs(vk_stage) - 1;
978 }
979
980 static inline VkShaderStageFlagBits
981 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
982 {
983 return (1 << mesa_stage);
984 }
985
986 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
987
988 #define radv_foreach_stage(stage, stage_bits) \
989 for (gl_shader_stage stage, \
990 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
991 stage = __builtin_ffs(__tmp) - 1, __tmp; \
992 __tmp &= ~(1 << (stage)))
993
994 struct radv_depth_stencil_state {
995 uint32_t db_depth_control;
996 uint32_t db_stencil_control;
997 uint32_t db_render_control;
998 uint32_t db_render_override2;
999 };
1000
1001 struct radv_blend_state {
1002 uint32_t cb_color_control;
1003 uint32_t cb_target_mask;
1004 uint32_t sx_mrt_blend_opt[8];
1005 uint32_t cb_blend_control[8];
1006
1007 uint32_t spi_shader_col_format;
1008 uint32_t cb_shader_mask;
1009 uint32_t db_alpha_to_mask;
1010 };
1011
1012 unsigned radv_format_meta_fs_key(VkFormat format);
1013
1014 struct radv_raster_state {
1015 uint32_t pa_cl_clip_cntl;
1016 uint32_t spi_interp_control;
1017 uint32_t pa_su_point_size;
1018 uint32_t pa_su_point_minmax;
1019 uint32_t pa_su_line_cntl;
1020 uint32_t pa_su_vtx_cntl;
1021 uint32_t pa_su_sc_mode_cntl;
1022 };
1023
1024 struct radv_multisample_state {
1025 uint32_t db_eqaa;
1026 uint32_t pa_sc_line_cntl;
1027 uint32_t pa_sc_mode_cntl_0;
1028 uint32_t pa_sc_mode_cntl_1;
1029 uint32_t pa_sc_aa_config;
1030 uint32_t pa_sc_aa_mask[2];
1031 unsigned num_samples;
1032 };
1033
1034 struct radv_prim_vertex_count {
1035 uint8_t min;
1036 uint8_t incr;
1037 };
1038
1039 struct radv_tessellation_state {
1040 uint32_t ls_hs_config;
1041 uint32_t tcs_in_layout;
1042 uint32_t tcs_out_layout;
1043 uint32_t tcs_out_offsets;
1044 uint32_t offchip_layout;
1045 unsigned num_patches;
1046 unsigned lds_size;
1047 unsigned num_tcs_input_cp;
1048 uint32_t tf_param;
1049 };
1050
1051 struct radv_vertex_elements_info {
1052 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1053 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1054 uint32_t binding[MAX_VERTEX_ATTRIBS];
1055 uint32_t offset[MAX_VERTEX_ATTRIBS];
1056 uint32_t count;
1057 };
1058
1059 #define SI_GS_PER_ES 128
1060
1061 struct radv_pipeline {
1062 struct radv_device * device;
1063 uint32_t dynamic_state_mask;
1064 struct radv_dynamic_state dynamic_state;
1065
1066 struct radv_pipeline_layout * layout;
1067
1068 bool needs_data_cache;
1069 bool need_indirect_descriptor_sets;
1070 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1071 struct radv_shader_variant *gs_copy_shader;
1072 VkShaderStageFlags active_stages;
1073
1074 struct radv_vertex_elements_info vertex_elements;
1075
1076 uint32_t binding_stride[MAX_VBS];
1077
1078 union {
1079 struct {
1080 struct radv_blend_state blend;
1081 struct radv_depth_stencil_state ds;
1082 struct radv_raster_state raster;
1083 struct radv_multisample_state ms;
1084 struct radv_tessellation_state tess;
1085 uint32_t db_shader_control;
1086 uint32_t shader_z_format;
1087 unsigned prim;
1088 unsigned gs_out;
1089 uint32_t vgt_gs_mode;
1090 bool vgt_primitiveid_en;
1091 bool prim_restart_enable;
1092 bool partial_es_wave;
1093 uint8_t primgroup_size;
1094 unsigned esgs_ring_size;
1095 unsigned gsvs_ring_size;
1096 uint32_t ps_input_cntl[32];
1097 uint32_t ps_input_cntl_num;
1098 uint32_t pa_cl_vs_out_cntl;
1099 uint32_t vgt_shader_stages_en;
1100 uint32_t vtx_base_sgpr;
1101 uint32_t base_ia_multi_vgt_param;
1102 bool wd_switch_on_eop;
1103 bool ia_switch_on_eoi;
1104 bool partial_vs_wave;
1105 uint8_t vtx_emit_num;
1106 struct radv_prim_vertex_count prim_vertex_count;
1107 bool can_use_guardband;
1108 } graphics;
1109 };
1110
1111 unsigned max_waves;
1112 unsigned scratch_bytes_per_wave;
1113 };
1114
1115 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1116 {
1117 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1118 }
1119
1120 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1121 {
1122 return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
1123 }
1124
1125 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1126 gl_shader_stage stage,
1127 int idx);
1128
1129 struct radv_graphics_pipeline_create_info {
1130 bool use_rectlist;
1131 bool db_depth_clear;
1132 bool db_stencil_clear;
1133 bool db_depth_disable_expclear;
1134 bool db_stencil_disable_expclear;
1135 bool db_flush_depth_inplace;
1136 bool db_flush_stencil_inplace;
1137 bool db_resummarize;
1138 uint32_t custom_blend_mode;
1139 };
1140
1141 VkResult
1142 radv_graphics_pipeline_create(VkDevice device,
1143 VkPipelineCache cache,
1144 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1145 const struct radv_graphics_pipeline_create_info *extra,
1146 const VkAllocationCallbacks *alloc,
1147 VkPipeline *pPipeline);
1148
1149 struct vk_format_description;
1150 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1151 int first_non_void);
1152 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1153 int first_non_void);
1154 uint32_t radv_translate_colorformat(VkFormat format);
1155 uint32_t radv_translate_color_numformat(VkFormat format,
1156 const struct vk_format_description *desc,
1157 int first_non_void);
1158 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1159 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1160 uint32_t radv_translate_dbformat(VkFormat format);
1161 uint32_t radv_translate_tex_dataformat(VkFormat format,
1162 const struct vk_format_description *desc,
1163 int first_non_void);
1164 uint32_t radv_translate_tex_numformat(VkFormat format,
1165 const struct vk_format_description *desc,
1166 int first_non_void);
1167 bool radv_format_pack_clear_color(VkFormat format,
1168 uint32_t clear_vals[2],
1169 VkClearColorValue *value);
1170 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1171 bool radv_dcc_formats_compatible(VkFormat format1,
1172 VkFormat format2);
1173
1174 struct radv_fmask_info {
1175 uint64_t offset;
1176 uint64_t size;
1177 unsigned alignment;
1178 unsigned pitch_in_pixels;
1179 unsigned bank_height;
1180 unsigned slice_tile_max;
1181 unsigned tile_mode_index;
1182 unsigned tile_swizzle;
1183 };
1184
1185 struct radv_cmask_info {
1186 uint64_t offset;
1187 uint64_t size;
1188 unsigned alignment;
1189 unsigned slice_tile_max;
1190 unsigned base_address_reg;
1191 };
1192
1193 struct r600_htile_info {
1194 uint64_t offset;
1195 uint64_t size;
1196 unsigned pitch;
1197 unsigned height;
1198 unsigned xalign;
1199 unsigned yalign;
1200 };
1201
1202 struct radv_image {
1203 VkImageType type;
1204 /* The original VkFormat provided by the client. This may not match any
1205 * of the actual surface formats.
1206 */
1207 VkFormat vk_format;
1208 VkImageAspectFlags aspects;
1209 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1210 struct ac_surf_info info;
1211 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1212 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1213
1214 VkDeviceSize size;
1215 uint32_t alignment;
1216
1217 unsigned queue_family_mask;
1218 bool exclusive;
1219 bool shareable;
1220
1221 /* Set when bound */
1222 struct radeon_winsys_bo *bo;
1223 VkDeviceSize offset;
1224 uint32_t dcc_offset;
1225 uint32_t htile_offset;
1226 struct radeon_surf surface;
1227
1228 struct radv_fmask_info fmask;
1229 struct radv_cmask_info cmask;
1230 uint32_t clear_value_offset;
1231 uint32_t dcc_pred_offset;
1232 };
1233
1234 /* Whether the image has a htile that is known consistent with the contents of
1235 * the image. */
1236 bool radv_layout_has_htile(const struct radv_image *image,
1237 VkImageLayout layout,
1238 unsigned queue_mask);
1239
1240 /* Whether the image has a htile that is known consistent with the contents of
1241 * the image and is allowed to be in compressed form.
1242 *
1243 * If this is false reads that don't use the htile should be able to return
1244 * correct results.
1245 */
1246 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1247 VkImageLayout layout,
1248 unsigned queue_mask);
1249
1250 bool radv_layout_can_fast_clear(const struct radv_image *image,
1251 VkImageLayout layout,
1252 unsigned queue_mask);
1253
1254
1255 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1256
1257 static inline uint32_t
1258 radv_get_layerCount(const struct radv_image *image,
1259 const VkImageSubresourceRange *range)
1260 {
1261 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1262 image->info.array_size - range->baseArrayLayer : range->layerCount;
1263 }
1264
1265 static inline uint32_t
1266 radv_get_levelCount(const struct radv_image *image,
1267 const VkImageSubresourceRange *range)
1268 {
1269 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1270 image->info.levels - range->baseMipLevel : range->levelCount;
1271 }
1272
1273 struct radeon_bo_metadata;
1274 void
1275 radv_init_metadata(struct radv_device *device,
1276 struct radv_image *image,
1277 struct radeon_bo_metadata *metadata);
1278
1279 struct radv_image_view {
1280 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1281 struct radeon_winsys_bo *bo;
1282
1283 VkImageViewType type;
1284 VkImageAspectFlags aspect_mask;
1285 VkFormat vk_format;
1286 uint32_t base_layer;
1287 uint32_t layer_count;
1288 uint32_t base_mip;
1289 uint32_t level_count;
1290 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1291
1292 uint32_t descriptor[8];
1293 uint32_t fmask_descriptor[8];
1294
1295 /* Descriptor for use as a storage image as opposed to a sampled image.
1296 * This has a few differences for cube maps (e.g. type).
1297 */
1298 uint32_t storage_descriptor[8];
1299 uint32_t storage_fmask_descriptor[8];
1300 };
1301
1302 struct radv_image_create_info {
1303 const VkImageCreateInfo *vk_info;
1304 bool scanout;
1305 };
1306
1307 VkResult radv_image_create(VkDevice _device,
1308 const struct radv_image_create_info *info,
1309 const VkAllocationCallbacks* alloc,
1310 VkImage *pImage);
1311
1312 void radv_image_view_init(struct radv_image_view *view,
1313 struct radv_device *device,
1314 const VkImageViewCreateInfo* pCreateInfo);
1315
1316 struct radv_buffer_view {
1317 struct radeon_winsys_bo *bo;
1318 VkFormat vk_format;
1319 uint64_t range; /**< VkBufferViewCreateInfo::range */
1320 uint32_t state[4];
1321 };
1322 void radv_buffer_view_init(struct radv_buffer_view *view,
1323 struct radv_device *device,
1324 const VkBufferViewCreateInfo* pCreateInfo);
1325
1326 static inline struct VkExtent3D
1327 radv_sanitize_image_extent(const VkImageType imageType,
1328 const struct VkExtent3D imageExtent)
1329 {
1330 switch (imageType) {
1331 case VK_IMAGE_TYPE_1D:
1332 return (VkExtent3D) { imageExtent.width, 1, 1 };
1333 case VK_IMAGE_TYPE_2D:
1334 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1335 case VK_IMAGE_TYPE_3D:
1336 return imageExtent;
1337 default:
1338 unreachable("invalid image type");
1339 }
1340 }
1341
1342 static inline struct VkOffset3D
1343 radv_sanitize_image_offset(const VkImageType imageType,
1344 const struct VkOffset3D imageOffset)
1345 {
1346 switch (imageType) {
1347 case VK_IMAGE_TYPE_1D:
1348 return (VkOffset3D) { imageOffset.x, 0, 0 };
1349 case VK_IMAGE_TYPE_2D:
1350 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1351 case VK_IMAGE_TYPE_3D:
1352 return imageOffset;
1353 default:
1354 unreachable("invalid image type");
1355 }
1356 }
1357
1358 static inline bool
1359 radv_image_extent_compare(const struct radv_image *image,
1360 const VkExtent3D *extent)
1361 {
1362 if (extent->width != image->info.width ||
1363 extent->height != image->info.height ||
1364 extent->depth != image->info.depth)
1365 return false;
1366 return true;
1367 }
1368
1369 struct radv_sampler {
1370 uint32_t state[4];
1371 };
1372
1373 struct radv_color_buffer_info {
1374 uint64_t cb_color_base;
1375 uint64_t cb_color_cmask;
1376 uint64_t cb_color_fmask;
1377 uint64_t cb_dcc_base;
1378 uint32_t cb_color_pitch;
1379 uint32_t cb_color_slice;
1380 uint32_t cb_color_view;
1381 uint32_t cb_color_info;
1382 uint32_t cb_color_attrib;
1383 uint32_t cb_color_attrib2;
1384 uint32_t cb_dcc_control;
1385 uint32_t cb_color_cmask_slice;
1386 uint32_t cb_color_fmask_slice;
1387 uint32_t cb_clear_value0;
1388 uint32_t cb_clear_value1;
1389 uint32_t micro_tile_mode;
1390 uint32_t gfx9_epitch;
1391 };
1392
1393 struct radv_ds_buffer_info {
1394 uint64_t db_z_read_base;
1395 uint64_t db_stencil_read_base;
1396 uint64_t db_z_write_base;
1397 uint64_t db_stencil_write_base;
1398 uint64_t db_htile_data_base;
1399 uint32_t db_depth_info;
1400 uint32_t db_z_info;
1401 uint32_t db_stencil_info;
1402 uint32_t db_depth_view;
1403 uint32_t db_depth_size;
1404 uint32_t db_depth_slice;
1405 uint32_t db_htile_surface;
1406 uint32_t pa_su_poly_offset_db_fmt_cntl;
1407 uint32_t db_z_info2;
1408 uint32_t db_stencil_info2;
1409 float offset_scale;
1410 };
1411
1412 struct radv_attachment_info {
1413 union {
1414 struct radv_color_buffer_info cb;
1415 struct radv_ds_buffer_info ds;
1416 };
1417 struct radv_image_view *attachment;
1418 };
1419
1420 struct radv_framebuffer {
1421 uint32_t width;
1422 uint32_t height;
1423 uint32_t layers;
1424
1425 uint32_t attachment_count;
1426 struct radv_attachment_info attachments[0];
1427 };
1428
1429 struct radv_subpass_barrier {
1430 VkPipelineStageFlags src_stage_mask;
1431 VkAccessFlags src_access_mask;
1432 VkAccessFlags dst_access_mask;
1433 };
1434
1435 struct radv_subpass {
1436 uint32_t input_count;
1437 uint32_t color_count;
1438 VkAttachmentReference * input_attachments;
1439 VkAttachmentReference * color_attachments;
1440 VkAttachmentReference * resolve_attachments;
1441 VkAttachmentReference depth_stencil_attachment;
1442
1443 /** Subpass has at least one resolve attachment */
1444 bool has_resolve;
1445
1446 struct radv_subpass_barrier start_barrier;
1447
1448 uint32_t view_mask;
1449 };
1450
1451 struct radv_render_pass_attachment {
1452 VkFormat format;
1453 uint32_t samples;
1454 VkAttachmentLoadOp load_op;
1455 VkAttachmentLoadOp stencil_load_op;
1456 VkImageLayout initial_layout;
1457 VkImageLayout final_layout;
1458 uint32_t view_mask;
1459 };
1460
1461 struct radv_render_pass {
1462 uint32_t attachment_count;
1463 uint32_t subpass_count;
1464 VkAttachmentReference * subpass_attachments;
1465 struct radv_render_pass_attachment * attachments;
1466 struct radv_subpass_barrier end_barrier;
1467 struct radv_subpass subpasses[0];
1468 };
1469
1470 VkResult radv_device_init_meta(struct radv_device *device);
1471 void radv_device_finish_meta(struct radv_device *device);
1472
1473 struct radv_query_pool {
1474 struct radeon_winsys_bo *bo;
1475 uint32_t stride;
1476 uint32_t availability_offset;
1477 char *ptr;
1478 VkQueryType type;
1479 uint32_t pipeline_stats_mask;
1480 };
1481
1482 struct radv_semaphore {
1483 /* use a winsys sem for non-exportable */
1484 struct radeon_winsys_sem *sem;
1485 uint32_t syncobj;
1486 uint32_t temp_syncobj;
1487 };
1488
1489 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1490 int num_wait_sems,
1491 const VkSemaphore *wait_sems,
1492 int num_signal_sems,
1493 const VkSemaphore *signal_sems);
1494 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1495
1496 void
1497 radv_update_descriptor_sets(struct radv_device *device,
1498 struct radv_cmd_buffer *cmd_buffer,
1499 VkDescriptorSet overrideSet,
1500 uint32_t descriptorWriteCount,
1501 const VkWriteDescriptorSet *pDescriptorWrites,
1502 uint32_t descriptorCopyCount,
1503 const VkCopyDescriptorSet *pDescriptorCopies);
1504
1505 void
1506 radv_update_descriptor_set_with_template(struct radv_device *device,
1507 struct radv_cmd_buffer *cmd_buffer,
1508 struct radv_descriptor_set *set,
1509 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1510 const void *pData);
1511
1512 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1513 VkPipelineBindPoint pipelineBindPoint,
1514 VkPipelineLayout _layout,
1515 uint32_t set,
1516 uint32_t descriptorWriteCount,
1517 const VkWriteDescriptorSet *pDescriptorWrites);
1518
1519 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1520 struct radv_image *image, uint32_t value);
1521 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1522 struct radv_image *image, uint32_t value);
1523
1524 struct radv_fence {
1525 struct radeon_winsys_fence *fence;
1526 bool submitted;
1527 bool signalled;
1528 };
1529
1530 struct radeon_winsys_sem;
1531
1532 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1533 \
1534 static inline struct __radv_type * \
1535 __radv_type ## _from_handle(__VkType _handle) \
1536 { \
1537 return (struct __radv_type *) _handle; \
1538 } \
1539 \
1540 static inline __VkType \
1541 __radv_type ## _to_handle(struct __radv_type *_obj) \
1542 { \
1543 return (__VkType) _obj; \
1544 }
1545
1546 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1547 \
1548 static inline struct __radv_type * \
1549 __radv_type ## _from_handle(__VkType _handle) \
1550 { \
1551 return (struct __radv_type *)(uintptr_t) _handle; \
1552 } \
1553 \
1554 static inline __VkType \
1555 __radv_type ## _to_handle(struct __radv_type *_obj) \
1556 { \
1557 return (__VkType)(uintptr_t) _obj; \
1558 }
1559
1560 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1561 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1562
1563 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1564 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1565 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1566 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1567 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1568
1569 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1570 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1571 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1572 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1573 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1574 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1575 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1576 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1577 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1578 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1579 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1580 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1581 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1582 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1583 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1584 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1585 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1586 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1587 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1588 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1589 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1590
1591 #endif /* RADV_PRIVATE_H */