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radv: Keep a global BO list for VkMemory.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "radv_descriptor_set.h"
61 #include "radv_extensions.h"
62
63 #include <llvm-c/TargetMachine.h>
64
65 /* Pre-declarations needed for WSI entrypoints */
66 struct wl_surface;
67 struct wl_display;
68 typedef struct xcb_connection_t xcb_connection_t;
69 typedef uint32_t xcb_visualid_t;
70 typedef uint32_t xcb_window_t;
71
72 #include <vulkan/vulkan.h>
73 #include <vulkan/vulkan_intel.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vk_android_native_buffer.h>
76
77 #include "radv_entrypoints.h"
78
79 #include "wsi_common.h"
80
81 #define ATI_VENDOR_ID 0x1002
82
83 #define MAX_VBS 32
84 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_RTS 8
86 #define MAX_VIEWPORTS 16
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
94 #define MAX_SAMPLES_LOG2 4
95 #define NUM_META_FS_KEYS 13
96 #define RADV_MAX_DRM_DEVICES 8
97 #define MAX_VIEWS 8
98
99 #define NUM_DEPTH_CLEAR_PIPELINES 3
100
101 /*
102 * This is the point we switch from using CP to compute shader
103 * for certain buffer operations.
104 */
105 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
106
107 enum radv_mem_heap {
108 RADV_MEM_HEAP_VRAM,
109 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
110 RADV_MEM_HEAP_GTT,
111 RADV_MEM_HEAP_COUNT
112 };
113
114 enum radv_mem_type {
115 RADV_MEM_TYPE_VRAM,
116 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
117 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
118 RADV_MEM_TYPE_GTT_CACHED,
119 RADV_MEM_TYPE_COUNT
120 };
121
122 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
123
124 static inline uint32_t
125 align_u32(uint32_t v, uint32_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline uint32_t
132 align_u32_npot(uint32_t v, uint32_t a)
133 {
134 return (v + a - 1) / a * a;
135 }
136
137 static inline uint64_t
138 align_u64(uint64_t v, uint64_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 static inline int32_t
145 align_i32(int32_t v, int32_t a)
146 {
147 assert(a != 0 && a == (a & -a));
148 return (v + a - 1) & ~(a - 1);
149 }
150
151 /** Alignment must be a power of 2. */
152 static inline bool
153 radv_is_aligned(uintmax_t n, uintmax_t a)
154 {
155 assert(a == (a & -a));
156 return (n & (a - 1)) == 0;
157 }
158
159 static inline uint32_t
160 round_up_u32(uint32_t v, uint32_t a)
161 {
162 return (v + a - 1) / a;
163 }
164
165 static inline uint64_t
166 round_up_u64(uint64_t v, uint64_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint32_t
172 radv_minify(uint32_t n, uint32_t levels)
173 {
174 if (unlikely(n == 0))
175 return 0;
176 else
177 return MAX2(n >> levels, 1);
178 }
179 static inline float
180 radv_clamp_f(float f, float min, float max)
181 {
182 assert(min < max);
183
184 if (f > max)
185 return max;
186 else if (f < min)
187 return min;
188 else
189 return f;
190 }
191
192 static inline bool
193 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
194 {
195 if (*inout_mask & clear_mask) {
196 *inout_mask &= ~clear_mask;
197 return true;
198 } else {
199 return false;
200 }
201 }
202
203 #define for_each_bit(b, dword) \
204 for (uint32_t __dword = (dword); \
205 (b) = __builtin_ffs(__dword) - 1, __dword; \
206 __dword &= ~(1 << (b)))
207
208 #define typed_memcpy(dest, src, count) ({ \
209 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
210 memcpy((dest), (src), (count) * sizeof(*(src))); \
211 })
212
213 /* Whenever we generate an error, pass it through this function. Useful for
214 * debugging, where we can break on it. Only call at error site, not when
215 * propagating errors. Might be useful to plug in a stack trace here.
216 */
217
218 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
219
220 #ifdef DEBUG
221 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
222 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
223 #else
224 #define vk_error(error) error
225 #define vk_errorf(error, format, ...) error
226 #endif
227
228 void __radv_finishme(const char *file, int line, const char *format, ...)
229 radv_printflike(3, 4);
230 void radv_loge(const char *format, ...) radv_printflike(1, 2);
231 void radv_loge_v(const char *format, va_list va);
232
233 /**
234 * Print a FINISHME message, including its source location.
235 */
236 #define radv_finishme(format, ...) \
237 do { \
238 static bool reported = false; \
239 if (!reported) { \
240 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
241 reported = true; \
242 } \
243 } while (0)
244
245 /* A non-fatal assert. Useful for debugging. */
246 #ifdef DEBUG
247 #define radv_assert(x) ({ \
248 if (unlikely(!(x))) \
249 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
250 })
251 #else
252 #define radv_assert(x)
253 #endif
254
255 #define stub_return(v) \
256 do { \
257 radv_finishme("stub %s", __func__); \
258 return (v); \
259 } while (0)
260
261 #define stub() \
262 do { \
263 radv_finishme("stub %s", __func__); \
264 return; \
265 } while (0)
266
267 void *radv_lookup_entrypoint_unchecked(const char *name);
268 void *radv_lookup_entrypoint_checked(const char *name,
269 uint32_t core_version,
270 const struct radv_instance_extension_table *instance,
271 const struct radv_device_extension_table *device);
272
273 struct radv_physical_device {
274 VK_LOADER_DATA _loader_data;
275
276 struct radv_instance * instance;
277
278 struct radeon_winsys *ws;
279 struct radeon_info rad_info;
280 char path[20];
281 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
282 uint8_t driver_uuid[VK_UUID_SIZE];
283 uint8_t device_uuid[VK_UUID_SIZE];
284 uint8_t cache_uuid[VK_UUID_SIZE];
285
286 int local_fd;
287 struct wsi_device wsi_device;
288
289 bool has_rbplus; /* if RB+ register exist */
290 bool rbplus_allowed; /* if RB+ is allowed */
291 bool has_clear_state;
292 bool cpdma_prefetch_writes_memory;
293 bool has_scissor_bug;
294
295 bool has_out_of_order_rast;
296 bool out_of_order_rast_allowed;
297
298 /* This is the drivers on-disk cache used as a fallback as opposed to
299 * the pipeline cache defined by apps.
300 */
301 struct disk_cache * disk_cache;
302
303 VkPhysicalDeviceMemoryProperties memory_properties;
304 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
305
306 struct radv_device_extension_table supported_extensions;
307 };
308
309 struct radv_instance {
310 VK_LOADER_DATA _loader_data;
311
312 VkAllocationCallbacks alloc;
313
314 uint32_t apiVersion;
315 int physicalDeviceCount;
316 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
317
318 uint64_t debug_flags;
319 uint64_t perftest_flags;
320
321 struct vk_debug_report_instance debug_report_callbacks;
322
323 struct radv_instance_extension_table enabled_extensions;
324 };
325
326 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
327 void radv_finish_wsi(struct radv_physical_device *physical_device);
328
329 bool radv_instance_extension_supported(const char *name);
330 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
331 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
332 const char *name);
333
334 struct cache_entry;
335
336 struct radv_pipeline_cache {
337 struct radv_device * device;
338 pthread_mutex_t mutex;
339
340 uint32_t total_size;
341 uint32_t table_size;
342 uint32_t kernel_count;
343 struct cache_entry ** hash_table;
344 bool modified;
345
346 VkAllocationCallbacks alloc;
347 };
348
349 struct radv_pipeline_key {
350 uint32_t instance_rate_inputs;
351 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
352 unsigned tess_input_vertices;
353 uint32_t col_format;
354 uint32_t is_int8;
355 uint32_t is_int10;
356 uint8_t log2_ps_iter_samples;
357 uint8_t log2_num_samples;
358 uint32_t multisample : 1;
359 uint32_t has_multiview_view_index : 1;
360 };
361
362 void
363 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
364 struct radv_device *device);
365 void
366 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
367 void
368 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
369 const void *data, size_t size);
370
371 struct radv_shader_variant;
372
373 bool
374 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
375 struct radv_pipeline_cache *cache,
376 const unsigned char *sha1,
377 struct radv_shader_variant **variants);
378
379 void
380 radv_pipeline_cache_insert_shaders(struct radv_device *device,
381 struct radv_pipeline_cache *cache,
382 const unsigned char *sha1,
383 struct radv_shader_variant **variants,
384 const void *const *codes,
385 const unsigned *code_sizes);
386
387 enum radv_blit_ds_layout {
388 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
389 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
390 RADV_BLIT_DS_LAYOUT_COUNT,
391 };
392
393 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
394 {
395 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
396 }
397
398 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
399 {
400 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
401 }
402
403 enum radv_meta_dst_layout {
404 RADV_META_DST_LAYOUT_GENERAL,
405 RADV_META_DST_LAYOUT_OPTIMAL,
406 RADV_META_DST_LAYOUT_COUNT,
407 };
408
409 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
410 {
411 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
412 }
413
414 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
415 {
416 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
417 }
418
419 struct radv_meta_state {
420 VkAllocationCallbacks alloc;
421
422 struct radv_pipeline_cache cache;
423
424 /**
425 * Use array element `i` for images with `2^i` samples.
426 */
427 struct {
428 VkRenderPass render_pass[NUM_META_FS_KEYS];
429 VkPipeline color_pipelines[NUM_META_FS_KEYS];
430
431 VkRenderPass depthstencil_rp;
432 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
433 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
434 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
435 } clear[1 + MAX_SAMPLES_LOG2];
436
437 VkPipelineLayout clear_color_p_layout;
438 VkPipelineLayout clear_depth_p_layout;
439 struct {
440 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
441
442 /** Pipeline that blits from a 1D image. */
443 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
444
445 /** Pipeline that blits from a 2D image. */
446 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
447
448 /** Pipeline that blits from a 3D image. */
449 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
450
451 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
452 VkPipeline depth_only_1d_pipeline;
453 VkPipeline depth_only_2d_pipeline;
454 VkPipeline depth_only_3d_pipeline;
455
456 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
457 VkPipeline stencil_only_1d_pipeline;
458 VkPipeline stencil_only_2d_pipeline;
459 VkPipeline stencil_only_3d_pipeline;
460 VkPipelineLayout pipeline_layout;
461 VkDescriptorSetLayout ds_layout;
462 } blit;
463
464 struct {
465 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
466
467 VkPipelineLayout p_layouts[3];
468 VkDescriptorSetLayout ds_layouts[3];
469 VkPipeline pipelines[3][NUM_META_FS_KEYS];
470
471 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
472 VkPipeline depth_only_pipeline[3];
473
474 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
475 VkPipeline stencil_only_pipeline[3];
476 } blit2d;
477
478 struct {
479 VkPipelineLayout img_p_layout;
480 VkDescriptorSetLayout img_ds_layout;
481 VkPipeline pipeline;
482 VkPipeline pipeline_3d;
483 } itob;
484 struct {
485 VkPipelineLayout img_p_layout;
486 VkDescriptorSetLayout img_ds_layout;
487 VkPipeline pipeline;
488 VkPipeline pipeline_3d;
489 } btoi;
490 struct {
491 VkPipelineLayout img_p_layout;
492 VkDescriptorSetLayout img_ds_layout;
493 VkPipeline pipeline;
494 VkPipeline pipeline_3d;
495 } itoi;
496 struct {
497 VkPipelineLayout img_p_layout;
498 VkDescriptorSetLayout img_ds_layout;
499 VkPipeline pipeline;
500 VkPipeline pipeline_3d;
501 } cleari;
502
503 struct {
504 VkPipelineLayout p_layout;
505 VkPipeline pipeline[NUM_META_FS_KEYS];
506 VkRenderPass pass[NUM_META_FS_KEYS];
507 } resolve;
508
509 struct {
510 VkDescriptorSetLayout ds_layout;
511 VkPipelineLayout p_layout;
512 struct {
513 VkPipeline pipeline;
514 VkPipeline i_pipeline;
515 VkPipeline srgb_pipeline;
516 } rc[MAX_SAMPLES_LOG2];
517 } resolve_compute;
518
519 struct {
520 VkDescriptorSetLayout ds_layout;
521 VkPipelineLayout p_layout;
522
523 struct {
524 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
525 VkPipeline pipeline[NUM_META_FS_KEYS];
526 } rc[MAX_SAMPLES_LOG2];
527 } resolve_fragment;
528
529 struct {
530 VkPipelineLayout p_layout;
531 VkPipeline decompress_pipeline;
532 VkPipeline resummarize_pipeline;
533 VkRenderPass pass;
534 } depth_decomp[1 + MAX_SAMPLES_LOG2];
535
536 struct {
537 VkPipelineLayout p_layout;
538 VkPipeline cmask_eliminate_pipeline;
539 VkPipeline fmask_decompress_pipeline;
540 VkPipeline dcc_decompress_pipeline;
541 VkRenderPass pass;
542
543 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
544 VkPipelineLayout dcc_decompress_compute_p_layout;
545 VkPipeline dcc_decompress_compute_pipeline;
546 } fast_clear_flush;
547
548 struct {
549 VkPipelineLayout fill_p_layout;
550 VkPipelineLayout copy_p_layout;
551 VkDescriptorSetLayout fill_ds_layout;
552 VkDescriptorSetLayout copy_ds_layout;
553 VkPipeline fill_pipeline;
554 VkPipeline copy_pipeline;
555 } buffer;
556
557 struct {
558 VkDescriptorSetLayout ds_layout;
559 VkPipelineLayout p_layout;
560 VkPipeline occlusion_query_pipeline;
561 VkPipeline pipeline_statistics_query_pipeline;
562 } query;
563 };
564
565 /* queue types */
566 #define RADV_QUEUE_GENERAL 0
567 #define RADV_QUEUE_COMPUTE 1
568 #define RADV_QUEUE_TRANSFER 2
569
570 #define RADV_MAX_QUEUE_FAMILIES 3
571
572 enum ring_type radv_queue_family_to_ring(int f);
573
574 struct radv_queue {
575 VK_LOADER_DATA _loader_data;
576 struct radv_device * device;
577 struct radeon_winsys_ctx *hw_ctx;
578 enum radeon_ctx_priority priority;
579 uint32_t queue_family_index;
580 int queue_idx;
581 VkDeviceQueueCreateFlags flags;
582
583 uint32_t scratch_size;
584 uint32_t compute_scratch_size;
585 uint32_t esgs_ring_size;
586 uint32_t gsvs_ring_size;
587 bool has_tess_rings;
588 bool has_sample_positions;
589
590 struct radeon_winsys_bo *scratch_bo;
591 struct radeon_winsys_bo *descriptor_bo;
592 struct radeon_winsys_bo *compute_scratch_bo;
593 struct radeon_winsys_bo *esgs_ring_bo;
594 struct radeon_winsys_bo *gsvs_ring_bo;
595 struct radeon_winsys_bo *tess_rings_bo;
596 struct radeon_winsys_cs *initial_preamble_cs;
597 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
598 struct radeon_winsys_cs *continue_preamble_cs;
599 };
600
601 struct radv_bo_list {
602 struct radv_winsys_bo_list list;
603 unsigned capacity;
604 pthread_mutex_t mutex;
605 };
606
607 struct radv_device {
608 VK_LOADER_DATA _loader_data;
609
610 VkAllocationCallbacks alloc;
611
612 struct radv_instance * instance;
613 struct radeon_winsys *ws;
614
615 struct radv_meta_state meta_state;
616
617 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
618 int queue_count[RADV_MAX_QUEUE_FAMILIES];
619 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
620
621 bool always_use_syncobj;
622 bool llvm_supports_spill;
623 bool has_distributed_tess;
624 bool pbb_allowed;
625 bool dfsm_allowed;
626 uint32_t tess_offchip_block_dw_size;
627 uint32_t scratch_waves;
628 uint32_t dispatch_initiator;
629
630 uint32_t gs_table_depth;
631
632 /* MSAA sample locations.
633 * The first index is the sample index.
634 * The second index is the coordinate: X, Y. */
635 float sample_locations_1x[1][2];
636 float sample_locations_2x[2][2];
637 float sample_locations_4x[4][2];
638 float sample_locations_8x[8][2];
639 float sample_locations_16x[16][2];
640
641 /* CIK and later */
642 uint32_t gfx_init_size_dw;
643 struct radeon_winsys_bo *gfx_init;
644
645 struct radeon_winsys_bo *trace_bo;
646 uint32_t *trace_id_ptr;
647
648 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
649 bool keep_shader_info;
650
651 struct radv_physical_device *physical_device;
652
653 /* Backup in-memory cache to be used if the app doesn't provide one */
654 struct radv_pipeline_cache * mem_cache;
655
656 /*
657 * use different counters so MSAA MRTs get consecutive surface indices,
658 * even if MASK is allocated in between.
659 */
660 uint32_t image_mrt_offset_counter;
661 uint32_t fmask_mrt_offset_counter;
662 struct list_head shader_slabs;
663 mtx_t shader_slab_mutex;
664
665 /* For detecting VM faults reported by dmesg. */
666 uint64_t dmesg_timestamp;
667
668 struct radv_device_extension_table enabled_extensions;
669
670 struct radv_bo_list bo_list;
671 };
672
673 struct radv_device_memory {
674 struct radeon_winsys_bo *bo;
675 /* for dedicated allocations */
676 struct radv_image *image;
677 struct radv_buffer *buffer;
678 uint32_t type_index;
679 VkDeviceSize map_size;
680 void * map;
681 void * user_ptr;
682 };
683
684
685 struct radv_descriptor_range {
686 uint64_t va;
687 uint32_t size;
688 };
689
690 struct radv_descriptor_set {
691 const struct radv_descriptor_set_layout *layout;
692 uint32_t size;
693
694 struct radeon_winsys_bo *bo;
695 uint64_t va;
696 uint32_t *mapped_ptr;
697 struct radv_descriptor_range *dynamic_descriptors;
698
699 struct radeon_winsys_bo *descriptors[0];
700 };
701
702 struct radv_push_descriptor_set
703 {
704 struct radv_descriptor_set set;
705 uint32_t capacity;
706 };
707
708 struct radv_descriptor_pool_entry {
709 uint32_t offset;
710 uint32_t size;
711 struct radv_descriptor_set *set;
712 };
713
714 struct radv_descriptor_pool {
715 struct radeon_winsys_bo *bo;
716 uint8_t *mapped_ptr;
717 uint64_t current_offset;
718 uint64_t size;
719
720 uint8_t *host_memory_base;
721 uint8_t *host_memory_ptr;
722 uint8_t *host_memory_end;
723
724 uint32_t entry_count;
725 uint32_t max_entry_count;
726 struct radv_descriptor_pool_entry entries[0];
727 };
728
729 struct radv_descriptor_update_template_entry {
730 VkDescriptorType descriptor_type;
731
732 /* The number of descriptors to update */
733 uint32_t descriptor_count;
734
735 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
736 uint32_t dst_offset;
737
738 /* In dwords. Not valid/used for dynamic descriptors */
739 uint32_t dst_stride;
740
741 uint32_t buffer_offset;
742
743 /* Only valid for combined image samplers and samplers */
744 uint16_t has_sampler;
745
746 /* In bytes */
747 size_t src_offset;
748 size_t src_stride;
749
750 /* For push descriptors */
751 const uint32_t *immutable_samplers;
752 };
753
754 struct radv_descriptor_update_template {
755 uint32_t entry_count;
756 VkPipelineBindPoint bind_point;
757 struct radv_descriptor_update_template_entry entry[0];
758 };
759
760 struct radv_buffer {
761 VkDeviceSize size;
762
763 VkBufferUsageFlags usage;
764 VkBufferCreateFlags flags;
765
766 /* Set when bound */
767 struct radeon_winsys_bo * bo;
768 VkDeviceSize offset;
769
770 bool shareable;
771 };
772
773 enum radv_dynamic_state_bits {
774 RADV_DYNAMIC_VIEWPORT = 1 << 0,
775 RADV_DYNAMIC_SCISSOR = 1 << 1,
776 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
777 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
778 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
779 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
780 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
781 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
782 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
783 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
784 RADV_DYNAMIC_ALL = (1 << 10) - 1,
785 };
786
787 enum radv_cmd_dirty_bits {
788 /* Keep the dynamic state dirty bits in sync with
789 * enum radv_dynamic_state_bits */
790 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
791 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
792 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
793 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
794 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
795 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
796 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
797 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
798 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
799 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
800 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
801 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
802 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
803 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
804 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
805 };
806
807 enum radv_cmd_flush_bits {
808 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
809 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
810 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
811 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
812 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
813 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
814 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
815 /* Same as above, but only writes back and doesn't invalidate */
816 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
817 /* Framebuffer caches */
818 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
819 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
820 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
821 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
822 /* Engine synchronization. */
823 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
824 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
825 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
826 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
827
828 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
829 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
830 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
831 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
832 };
833
834 struct radv_vertex_binding {
835 struct radv_buffer * buffer;
836 VkDeviceSize offset;
837 };
838
839 struct radv_viewport_state {
840 uint32_t count;
841 VkViewport viewports[MAX_VIEWPORTS];
842 };
843
844 struct radv_scissor_state {
845 uint32_t count;
846 VkRect2D scissors[MAX_SCISSORS];
847 };
848
849 struct radv_discard_rectangle_state {
850 uint32_t count;
851 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
852 };
853
854 struct radv_dynamic_state {
855 /**
856 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
857 * Defines the set of saved dynamic state.
858 */
859 uint32_t mask;
860
861 struct radv_viewport_state viewport;
862
863 struct radv_scissor_state scissor;
864
865 float line_width;
866
867 struct {
868 float bias;
869 float clamp;
870 float slope;
871 } depth_bias;
872
873 float blend_constants[4];
874
875 struct {
876 float min;
877 float max;
878 } depth_bounds;
879
880 struct {
881 uint32_t front;
882 uint32_t back;
883 } stencil_compare_mask;
884
885 struct {
886 uint32_t front;
887 uint32_t back;
888 } stencil_write_mask;
889
890 struct {
891 uint32_t front;
892 uint32_t back;
893 } stencil_reference;
894
895 struct radv_discard_rectangle_state discard_rectangle;
896 };
897
898 extern const struct radv_dynamic_state default_dynamic_state;
899
900 const char *
901 radv_get_debug_option_name(int id);
902
903 const char *
904 radv_get_perftest_option_name(int id);
905
906 /**
907 * Attachment state when recording a renderpass instance.
908 *
909 * The clear value is valid only if there exists a pending clear.
910 */
911 struct radv_attachment_state {
912 VkImageAspectFlags pending_clear_aspects;
913 uint32_t cleared_views;
914 VkClearValue clear_value;
915 VkImageLayout current_layout;
916 };
917
918 struct radv_descriptor_state {
919 struct radv_descriptor_set *sets[MAX_SETS];
920 uint32_t dirty;
921 uint32_t valid;
922 struct radv_push_descriptor_set push_set;
923 bool push_dirty;
924 };
925
926 struct radv_cmd_state {
927 /* Vertex descriptors */
928 uint64_t vb_va;
929 unsigned vb_size;
930
931 bool predicating;
932 uint32_t dirty;
933
934 uint32_t prefetch_L2_mask;
935
936 struct radv_pipeline * pipeline;
937 struct radv_pipeline * emitted_pipeline;
938 struct radv_pipeline * compute_pipeline;
939 struct radv_pipeline * emitted_compute_pipeline;
940 struct radv_framebuffer * framebuffer;
941 struct radv_render_pass * pass;
942 const struct radv_subpass * subpass;
943 struct radv_dynamic_state dynamic;
944 struct radv_attachment_state * attachments;
945 VkRect2D render_area;
946
947 /* Index buffer */
948 struct radv_buffer *index_buffer;
949 uint64_t index_offset;
950 uint32_t index_type;
951 uint32_t max_index_count;
952 uint64_t index_va;
953 int32_t last_index_type;
954
955 int32_t last_primitive_reset_en;
956 uint32_t last_primitive_reset_index;
957 enum radv_cmd_flush_bits flush_bits;
958 unsigned active_occlusion_queries;
959 bool perfect_occlusion_queries_enabled;
960 float offset_scale;
961 uint32_t trace_id;
962 uint32_t last_ia_multi_vgt_param;
963
964 uint32_t last_num_instances;
965 uint32_t last_first_instance;
966 uint32_t last_vertex_offset;
967 };
968
969 struct radv_cmd_pool {
970 VkAllocationCallbacks alloc;
971 struct list_head cmd_buffers;
972 struct list_head free_cmd_buffers;
973 uint32_t queue_family_index;
974 };
975
976 struct radv_cmd_buffer_upload {
977 uint8_t *map;
978 unsigned offset;
979 uint64_t size;
980 struct radeon_winsys_bo *upload_bo;
981 struct list_head list;
982 };
983
984 enum radv_cmd_buffer_status {
985 RADV_CMD_BUFFER_STATUS_INVALID,
986 RADV_CMD_BUFFER_STATUS_INITIAL,
987 RADV_CMD_BUFFER_STATUS_RECORDING,
988 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
989 RADV_CMD_BUFFER_STATUS_PENDING,
990 };
991
992 struct radv_cmd_buffer {
993 VK_LOADER_DATA _loader_data;
994
995 struct radv_device * device;
996
997 struct radv_cmd_pool * pool;
998 struct list_head pool_link;
999
1000 VkCommandBufferUsageFlags usage_flags;
1001 VkCommandBufferLevel level;
1002 enum radv_cmd_buffer_status status;
1003 struct radeon_winsys_cs *cs;
1004 struct radv_cmd_state state;
1005 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1006 uint32_t queue_family_index;
1007
1008 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1009 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1010 VkShaderStageFlags push_constant_stages;
1011 struct radv_descriptor_set meta_push_descriptors;
1012
1013 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1014
1015 struct radv_cmd_buffer_upload upload;
1016
1017 uint32_t scratch_size_needed;
1018 uint32_t compute_scratch_size_needed;
1019 uint32_t esgs_ring_size_needed;
1020 uint32_t gsvs_ring_size_needed;
1021 bool tess_rings_needed;
1022 bool sample_positions_needed;
1023
1024 VkResult record_result;
1025
1026 int ring_offsets_idx; /* just used for verification */
1027 uint32_t gfx9_fence_offset;
1028 struct radeon_winsys_bo *gfx9_fence_bo;
1029 uint32_t gfx9_fence_idx;
1030
1031 /**
1032 * Whether a query pool has been resetted and we have to flush caches.
1033 */
1034 bool pending_reset_query;
1035 };
1036
1037 struct radv_image;
1038
1039 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1040
1041 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1042 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1043
1044 void cik_create_gfx_config(struct radv_device *device);
1045
1046 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1047 int count, const VkViewport *viewports);
1048 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1049 int count, const VkRect2D *scissors,
1050 const VkViewport *viewports, bool can_use_guardband);
1051 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1052 bool instanced_draw, bool indirect_draw,
1053 uint32_t draw_vertex_count);
1054 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1055 bool predicated,
1056 enum chip_class chip_class,
1057 bool is_mec,
1058 unsigned event, unsigned event_flags,
1059 unsigned data_sel,
1060 uint64_t va,
1061 uint32_t old_fence,
1062 uint32_t new_fence);
1063
1064 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1065 bool predicated,
1066 uint64_t va, uint32_t ref,
1067 uint32_t mask);
1068 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1069 enum chip_class chip_class,
1070 uint32_t *fence_ptr, uint64_t va,
1071 bool is_mec,
1072 enum radv_cmd_flush_bits flush_bits);
1073 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1074 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1075 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1076 uint64_t src_va, uint64_t dest_va,
1077 uint64_t size);
1078 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1079 unsigned size);
1080 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1081 uint64_t size, unsigned value);
1082 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1083 bool
1084 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1085 unsigned size,
1086 unsigned alignment,
1087 unsigned *out_offset,
1088 void **ptr);
1089 void
1090 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1091 const struct radv_subpass *subpass,
1092 bool transitions);
1093 bool
1094 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1095 unsigned size, unsigned alignmnet,
1096 const void *data, unsigned *out_offset);
1097
1098 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1099 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1100 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1101 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1102 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1103 unsigned radv_cayman_get_maxdist(int log_samples);
1104 void radv_device_init_msaa(struct radv_device *device);
1105 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1106 struct radv_image *image,
1107 VkClearDepthStencilValue ds_clear_value,
1108 VkImageAspectFlags aspects);
1109 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1110 struct radv_image *image,
1111 int idx,
1112 uint32_t color_values[2]);
1113 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1114 struct radv_image *image,
1115 bool value);
1116 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1117 struct radeon_winsys_bo *bo,
1118 uint64_t offset, uint64_t size, uint32_t value);
1119 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1120 bool radv_get_memory_fd(struct radv_device *device,
1121 struct radv_device_memory *memory,
1122 int *pFD);
1123
1124 static inline struct radv_descriptor_state *
1125 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1126 VkPipelineBindPoint bind_point)
1127 {
1128 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1129 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1130 return &cmd_buffer->descriptors[bind_point];
1131 }
1132
1133 /*
1134 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1135 *
1136 * Limitations: Can't call normal dispatch functions without binding or rebinding
1137 * the compute pipeline.
1138 */
1139 void radv_unaligned_dispatch(
1140 struct radv_cmd_buffer *cmd_buffer,
1141 uint32_t x,
1142 uint32_t y,
1143 uint32_t z);
1144
1145 struct radv_event {
1146 struct radeon_winsys_bo *bo;
1147 uint64_t *map;
1148 };
1149
1150 struct radv_shader_module;
1151
1152 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1153 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1154 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1155 void
1156 radv_hash_shaders(unsigned char *hash,
1157 const VkPipelineShaderStageCreateInfo **stages,
1158 const struct radv_pipeline_layout *layout,
1159 const struct radv_pipeline_key *key,
1160 uint32_t flags);
1161
1162 static inline gl_shader_stage
1163 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1164 {
1165 assert(__builtin_popcount(vk_stage) == 1);
1166 return ffs(vk_stage) - 1;
1167 }
1168
1169 static inline VkShaderStageFlagBits
1170 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1171 {
1172 return (1 << mesa_stage);
1173 }
1174
1175 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1176
1177 #define radv_foreach_stage(stage, stage_bits) \
1178 for (gl_shader_stage stage, \
1179 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1180 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1181 __tmp &= ~(1 << (stage)))
1182
1183 unsigned radv_format_meta_fs_key(VkFormat format);
1184
1185 struct radv_multisample_state {
1186 uint32_t db_eqaa;
1187 uint32_t pa_sc_line_cntl;
1188 uint32_t pa_sc_mode_cntl_0;
1189 uint32_t pa_sc_mode_cntl_1;
1190 uint32_t pa_sc_aa_config;
1191 uint32_t pa_sc_aa_mask[2];
1192 unsigned num_samples;
1193 };
1194
1195 struct radv_prim_vertex_count {
1196 uint8_t min;
1197 uint8_t incr;
1198 };
1199
1200 struct radv_vertex_elements_info {
1201 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1202 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1203 uint32_t binding[MAX_VERTEX_ATTRIBS];
1204 uint32_t offset[MAX_VERTEX_ATTRIBS];
1205 uint32_t count;
1206 };
1207
1208 struct radv_ia_multi_vgt_param_helpers {
1209 uint32_t base;
1210 bool partial_es_wave;
1211 uint8_t primgroup_size;
1212 bool wd_switch_on_eop;
1213 bool ia_switch_on_eoi;
1214 bool partial_vs_wave;
1215 };
1216
1217 #define SI_GS_PER_ES 128
1218
1219 struct radv_pipeline {
1220 struct radv_device * device;
1221 struct radv_dynamic_state dynamic_state;
1222
1223 struct radv_pipeline_layout * layout;
1224
1225 bool need_indirect_descriptor_sets;
1226 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1227 struct radv_shader_variant *gs_copy_shader;
1228 VkShaderStageFlags active_stages;
1229
1230 struct radeon_winsys_cs cs;
1231
1232 struct radv_vertex_elements_info vertex_elements;
1233
1234 uint32_t binding_stride[MAX_VBS];
1235
1236 uint32_t user_data_0[MESA_SHADER_STAGES];
1237 union {
1238 struct {
1239 struct radv_multisample_state ms;
1240 uint32_t spi_baryc_cntl;
1241 bool prim_restart_enable;
1242 unsigned esgs_ring_size;
1243 unsigned gsvs_ring_size;
1244 uint32_t vtx_base_sgpr;
1245 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1246 uint8_t vtx_emit_num;
1247 struct radv_prim_vertex_count prim_vertex_count;
1248 bool can_use_guardband;
1249 uint32_t needed_dynamic_state;
1250 bool disable_out_of_order_rast_for_occlusion;
1251
1252 /* Used for rbplus */
1253 uint32_t col_format;
1254 uint32_t cb_target_mask;
1255 } graphics;
1256 };
1257
1258 unsigned max_waves;
1259 unsigned scratch_bytes_per_wave;
1260 };
1261
1262 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1263 {
1264 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1265 }
1266
1267 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1268 {
1269 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1270 }
1271
1272 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1273 gl_shader_stage stage,
1274 int idx);
1275
1276 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1277
1278 struct radv_graphics_pipeline_create_info {
1279 bool use_rectlist;
1280 bool db_depth_clear;
1281 bool db_stencil_clear;
1282 bool db_depth_disable_expclear;
1283 bool db_stencil_disable_expclear;
1284 bool db_flush_depth_inplace;
1285 bool db_flush_stencil_inplace;
1286 bool db_resummarize;
1287 uint32_t custom_blend_mode;
1288 };
1289
1290 VkResult
1291 radv_graphics_pipeline_create(VkDevice device,
1292 VkPipelineCache cache,
1293 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1294 const struct radv_graphics_pipeline_create_info *extra,
1295 const VkAllocationCallbacks *alloc,
1296 VkPipeline *pPipeline);
1297
1298 struct vk_format_description;
1299 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1300 int first_non_void);
1301 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1302 int first_non_void);
1303 uint32_t radv_translate_colorformat(VkFormat format);
1304 uint32_t radv_translate_color_numformat(VkFormat format,
1305 const struct vk_format_description *desc,
1306 int first_non_void);
1307 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1308 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1309 uint32_t radv_translate_dbformat(VkFormat format);
1310 uint32_t radv_translate_tex_dataformat(VkFormat format,
1311 const struct vk_format_description *desc,
1312 int first_non_void);
1313 uint32_t radv_translate_tex_numformat(VkFormat format,
1314 const struct vk_format_description *desc,
1315 int first_non_void);
1316 bool radv_format_pack_clear_color(VkFormat format,
1317 uint32_t clear_vals[2],
1318 VkClearColorValue *value);
1319 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1320 bool radv_dcc_formats_compatible(VkFormat format1,
1321 VkFormat format2);
1322
1323 struct radv_fmask_info {
1324 uint64_t offset;
1325 uint64_t size;
1326 unsigned alignment;
1327 unsigned pitch_in_pixels;
1328 unsigned bank_height;
1329 unsigned slice_tile_max;
1330 unsigned tile_mode_index;
1331 unsigned tile_swizzle;
1332 };
1333
1334 struct radv_cmask_info {
1335 uint64_t offset;
1336 uint64_t size;
1337 unsigned alignment;
1338 unsigned slice_tile_max;
1339 };
1340
1341 struct radv_image {
1342 VkImageType type;
1343 /* The original VkFormat provided by the client. This may not match any
1344 * of the actual surface formats.
1345 */
1346 VkFormat vk_format;
1347 VkImageAspectFlags aspects;
1348 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1349 struct ac_surf_info info;
1350 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1351 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1352
1353 VkDeviceSize size;
1354 uint32_t alignment;
1355
1356 unsigned queue_family_mask;
1357 bool exclusive;
1358 bool shareable;
1359
1360 /* Set when bound */
1361 struct radeon_winsys_bo *bo;
1362 VkDeviceSize offset;
1363 uint64_t dcc_offset;
1364 uint64_t htile_offset;
1365 bool tc_compatible_htile;
1366 struct radeon_surf surface;
1367
1368 struct radv_fmask_info fmask;
1369 struct radv_cmask_info cmask;
1370 uint64_t clear_value_offset;
1371 uint64_t dcc_pred_offset;
1372
1373 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1374 VkDeviceMemory owned_memory;
1375 };
1376
1377 /* Whether the image has a htile that is known consistent with the contents of
1378 * the image. */
1379 bool radv_layout_has_htile(const struct radv_image *image,
1380 VkImageLayout layout,
1381 unsigned queue_mask);
1382
1383 /* Whether the image has a htile that is known consistent with the contents of
1384 * the image and is allowed to be in compressed form.
1385 *
1386 * If this is false reads that don't use the htile should be able to return
1387 * correct results.
1388 */
1389 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1390 VkImageLayout layout,
1391 unsigned queue_mask);
1392
1393 bool radv_layout_can_fast_clear(const struct radv_image *image,
1394 VkImageLayout layout,
1395 unsigned queue_mask);
1396
1397 bool radv_layout_dcc_compressed(const struct radv_image *image,
1398 VkImageLayout layout,
1399 unsigned queue_mask);
1400
1401 /**
1402 * Return whether the image has CMASK metadata for color surfaces.
1403 */
1404 static inline bool
1405 radv_image_has_cmask(const struct radv_image *image)
1406 {
1407 return image->cmask.size;
1408 }
1409
1410 /**
1411 * Return whether the image has FMASK metadata for color surfaces.
1412 */
1413 static inline bool
1414 radv_image_has_fmask(const struct radv_image *image)
1415 {
1416 return image->fmask.size;
1417 }
1418
1419 /**
1420 * Return whether the image has DCC metadata for color surfaces.
1421 */
1422 static inline bool
1423 radv_image_has_dcc(const struct radv_image *image)
1424 {
1425 return image->surface.dcc_size;
1426 }
1427
1428 /**
1429 * Return whether DCC metadata is enabled for a level.
1430 */
1431 static inline bool
1432 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1433 {
1434 return radv_image_has_dcc(image) &&
1435 level < image->surface.num_dcc_levels;
1436 }
1437
1438 /**
1439 * Return whether the image has HTILE metadata for depth surfaces.
1440 */
1441 static inline bool
1442 radv_image_has_htile(const struct radv_image *image)
1443 {
1444 return image->surface.htile_size;
1445 }
1446
1447 /**
1448 * Return whether HTILE metadata is enabled for a level.
1449 */
1450 static inline bool
1451 radv_htile_enabled(const struct radv_image *image, unsigned level)
1452 {
1453 return radv_image_has_htile(image) && level == 0;
1454 }
1455
1456 /**
1457 * Return whether the image is TC-compatible HTILE.
1458 */
1459 static inline bool
1460 radv_image_is_tc_compat_htile(const struct radv_image *image)
1461 {
1462 return radv_image_has_htile(image) && image->tc_compatible_htile;
1463 }
1464
1465 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1466
1467 static inline uint32_t
1468 radv_get_layerCount(const struct radv_image *image,
1469 const VkImageSubresourceRange *range)
1470 {
1471 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1472 image->info.array_size - range->baseArrayLayer : range->layerCount;
1473 }
1474
1475 static inline uint32_t
1476 radv_get_levelCount(const struct radv_image *image,
1477 const VkImageSubresourceRange *range)
1478 {
1479 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1480 image->info.levels - range->baseMipLevel : range->levelCount;
1481 }
1482
1483 struct radeon_bo_metadata;
1484 void
1485 radv_init_metadata(struct radv_device *device,
1486 struct radv_image *image,
1487 struct radeon_bo_metadata *metadata);
1488
1489 struct radv_image_view {
1490 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1491 struct radeon_winsys_bo *bo;
1492
1493 VkImageViewType type;
1494 VkImageAspectFlags aspect_mask;
1495 VkFormat vk_format;
1496 uint32_t base_layer;
1497 uint32_t layer_count;
1498 uint32_t base_mip;
1499 uint32_t level_count;
1500 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1501
1502 uint32_t descriptor[16];
1503
1504 /* Descriptor for use as a storage image as opposed to a sampled image.
1505 * This has a few differences for cube maps (e.g. type).
1506 */
1507 uint32_t storage_descriptor[16];
1508 };
1509
1510 struct radv_image_create_info {
1511 const VkImageCreateInfo *vk_info;
1512 bool scanout;
1513 bool no_metadata_planes;
1514 };
1515
1516 VkResult radv_image_create(VkDevice _device,
1517 const struct radv_image_create_info *info,
1518 const VkAllocationCallbacks* alloc,
1519 VkImage *pImage);
1520
1521 VkResult
1522 radv_image_from_gralloc(VkDevice device_h,
1523 const VkImageCreateInfo *base_info,
1524 const VkNativeBufferANDROID *gralloc_info,
1525 const VkAllocationCallbacks *alloc,
1526 VkImage *out_image_h);
1527
1528 void radv_image_view_init(struct radv_image_view *view,
1529 struct radv_device *device,
1530 const VkImageViewCreateInfo* pCreateInfo);
1531
1532 struct radv_buffer_view {
1533 struct radeon_winsys_bo *bo;
1534 VkFormat vk_format;
1535 uint64_t range; /**< VkBufferViewCreateInfo::range */
1536 uint32_t state[4];
1537 };
1538 void radv_buffer_view_init(struct radv_buffer_view *view,
1539 struct radv_device *device,
1540 const VkBufferViewCreateInfo* pCreateInfo);
1541
1542 static inline struct VkExtent3D
1543 radv_sanitize_image_extent(const VkImageType imageType,
1544 const struct VkExtent3D imageExtent)
1545 {
1546 switch (imageType) {
1547 case VK_IMAGE_TYPE_1D:
1548 return (VkExtent3D) { imageExtent.width, 1, 1 };
1549 case VK_IMAGE_TYPE_2D:
1550 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1551 case VK_IMAGE_TYPE_3D:
1552 return imageExtent;
1553 default:
1554 unreachable("invalid image type");
1555 }
1556 }
1557
1558 static inline struct VkOffset3D
1559 radv_sanitize_image_offset(const VkImageType imageType,
1560 const struct VkOffset3D imageOffset)
1561 {
1562 switch (imageType) {
1563 case VK_IMAGE_TYPE_1D:
1564 return (VkOffset3D) { imageOffset.x, 0, 0 };
1565 case VK_IMAGE_TYPE_2D:
1566 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1567 case VK_IMAGE_TYPE_3D:
1568 return imageOffset;
1569 default:
1570 unreachable("invalid image type");
1571 }
1572 }
1573
1574 static inline bool
1575 radv_image_extent_compare(const struct radv_image *image,
1576 const VkExtent3D *extent)
1577 {
1578 if (extent->width != image->info.width ||
1579 extent->height != image->info.height ||
1580 extent->depth != image->info.depth)
1581 return false;
1582 return true;
1583 }
1584
1585 struct radv_sampler {
1586 uint32_t state[4];
1587 };
1588
1589 struct radv_color_buffer_info {
1590 uint64_t cb_color_base;
1591 uint64_t cb_color_cmask;
1592 uint64_t cb_color_fmask;
1593 uint64_t cb_dcc_base;
1594 uint32_t cb_color_pitch;
1595 uint32_t cb_color_slice;
1596 uint32_t cb_color_view;
1597 uint32_t cb_color_info;
1598 uint32_t cb_color_attrib;
1599 uint32_t cb_color_attrib2;
1600 uint32_t cb_dcc_control;
1601 uint32_t cb_color_cmask_slice;
1602 uint32_t cb_color_fmask_slice;
1603 };
1604
1605 struct radv_ds_buffer_info {
1606 uint64_t db_z_read_base;
1607 uint64_t db_stencil_read_base;
1608 uint64_t db_z_write_base;
1609 uint64_t db_stencil_write_base;
1610 uint64_t db_htile_data_base;
1611 uint32_t db_depth_info;
1612 uint32_t db_z_info;
1613 uint32_t db_stencil_info;
1614 uint32_t db_depth_view;
1615 uint32_t db_depth_size;
1616 uint32_t db_depth_slice;
1617 uint32_t db_htile_surface;
1618 uint32_t pa_su_poly_offset_db_fmt_cntl;
1619 uint32_t db_z_info2;
1620 uint32_t db_stencil_info2;
1621 float offset_scale;
1622 };
1623
1624 struct radv_attachment_info {
1625 union {
1626 struct radv_color_buffer_info cb;
1627 struct radv_ds_buffer_info ds;
1628 };
1629 struct radv_image_view *attachment;
1630 };
1631
1632 struct radv_framebuffer {
1633 uint32_t width;
1634 uint32_t height;
1635 uint32_t layers;
1636
1637 uint32_t attachment_count;
1638 struct radv_attachment_info attachments[0];
1639 };
1640
1641 struct radv_subpass_barrier {
1642 VkPipelineStageFlags src_stage_mask;
1643 VkAccessFlags src_access_mask;
1644 VkAccessFlags dst_access_mask;
1645 };
1646
1647 struct radv_subpass {
1648 uint32_t input_count;
1649 uint32_t color_count;
1650 VkAttachmentReference * input_attachments;
1651 VkAttachmentReference * color_attachments;
1652 VkAttachmentReference * resolve_attachments;
1653 VkAttachmentReference depth_stencil_attachment;
1654
1655 /** Subpass has at least one resolve attachment */
1656 bool has_resolve;
1657
1658 struct radv_subpass_barrier start_barrier;
1659
1660 uint32_t view_mask;
1661 VkSampleCountFlagBits max_sample_count;
1662 };
1663
1664 struct radv_render_pass_attachment {
1665 VkFormat format;
1666 uint32_t samples;
1667 VkAttachmentLoadOp load_op;
1668 VkAttachmentLoadOp stencil_load_op;
1669 VkImageLayout initial_layout;
1670 VkImageLayout final_layout;
1671 uint32_t view_mask;
1672 };
1673
1674 struct radv_render_pass {
1675 uint32_t attachment_count;
1676 uint32_t subpass_count;
1677 VkAttachmentReference * subpass_attachments;
1678 struct radv_render_pass_attachment * attachments;
1679 struct radv_subpass_barrier end_barrier;
1680 struct radv_subpass subpasses[0];
1681 };
1682
1683 VkResult radv_device_init_meta(struct radv_device *device);
1684 void radv_device_finish_meta(struct radv_device *device);
1685
1686 struct radv_query_pool {
1687 struct radeon_winsys_bo *bo;
1688 uint32_t stride;
1689 uint32_t availability_offset;
1690 uint64_t size;
1691 char *ptr;
1692 VkQueryType type;
1693 uint32_t pipeline_stats_mask;
1694 };
1695
1696 struct radv_semaphore {
1697 /* use a winsys sem for non-exportable */
1698 struct radeon_winsys_sem *sem;
1699 uint32_t syncobj;
1700 uint32_t temp_syncobj;
1701 };
1702
1703 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1704 int num_wait_sems,
1705 const VkSemaphore *wait_sems,
1706 int num_signal_sems,
1707 const VkSemaphore *signal_sems,
1708 VkFence fence);
1709 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1710
1711 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1712 VkPipelineBindPoint bind_point,
1713 struct radv_descriptor_set *set,
1714 unsigned idx);
1715
1716 void
1717 radv_update_descriptor_sets(struct radv_device *device,
1718 struct radv_cmd_buffer *cmd_buffer,
1719 VkDescriptorSet overrideSet,
1720 uint32_t descriptorWriteCount,
1721 const VkWriteDescriptorSet *pDescriptorWrites,
1722 uint32_t descriptorCopyCount,
1723 const VkCopyDescriptorSet *pDescriptorCopies);
1724
1725 void
1726 radv_update_descriptor_set_with_template(struct radv_device *device,
1727 struct radv_cmd_buffer *cmd_buffer,
1728 struct radv_descriptor_set *set,
1729 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1730 const void *pData);
1731
1732 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1733 VkPipelineBindPoint pipelineBindPoint,
1734 VkPipelineLayout _layout,
1735 uint32_t set,
1736 uint32_t descriptorWriteCount,
1737 const VkWriteDescriptorSet *pDescriptorWrites);
1738
1739 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1740 struct radv_image *image, uint32_t value);
1741
1742 struct radv_fence {
1743 struct radeon_winsys_fence *fence;
1744 bool submitted;
1745 bool signalled;
1746
1747 uint32_t syncobj;
1748 uint32_t temp_syncobj;
1749 };
1750
1751 /* radv_nir_to_llvm.c */
1752 struct radv_shader_variant_info;
1753 struct radv_nir_compiler_options;
1754
1755 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1756 struct nir_shader *geom_shader,
1757 struct ac_shader_binary *binary,
1758 struct ac_shader_config *config,
1759 struct radv_shader_variant_info *shader_info,
1760 const struct radv_nir_compiler_options *option);
1761
1762 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1763 struct ac_shader_binary *binary,
1764 struct ac_shader_config *config,
1765 struct radv_shader_variant_info *shader_info,
1766 struct nir_shader *const *nir,
1767 int nir_count,
1768 const struct radv_nir_compiler_options *options);
1769
1770 /* radv_shader_info.h */
1771 struct radv_shader_info;
1772
1773 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1774 const struct radv_nir_compiler_options *options,
1775 struct radv_shader_info *info);
1776
1777 struct radeon_winsys_sem;
1778
1779 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1780 \
1781 static inline struct __radv_type * \
1782 __radv_type ## _from_handle(__VkType _handle) \
1783 { \
1784 return (struct __radv_type *) _handle; \
1785 } \
1786 \
1787 static inline __VkType \
1788 __radv_type ## _to_handle(struct __radv_type *_obj) \
1789 { \
1790 return (__VkType) _obj; \
1791 }
1792
1793 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1794 \
1795 static inline struct __radv_type * \
1796 __radv_type ## _from_handle(__VkType _handle) \
1797 { \
1798 return (struct __radv_type *)(uintptr_t) _handle; \
1799 } \
1800 \
1801 static inline __VkType \
1802 __radv_type ## _to_handle(struct __radv_type *_obj) \
1803 { \
1804 return (__VkType)(uintptr_t) _obj; \
1805 }
1806
1807 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1808 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1809
1810 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1811 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1812 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1813 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1814 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1815
1816 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1817 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1818 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1819 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1820 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1821 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1822 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1823 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1824 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1825 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1826 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1827 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1828 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1829 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1830 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1831 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1832 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1833 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1834 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1835 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1836 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1837
1838 #endif /* RADV_PRIVATE_H */