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radv: Put supported extensions in a struct.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52 #include "vk_debug_report.h"
53
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60 #include "radv_extensions.h"
61
62 #include <llvm-c/TargetMachine.h>
63
64 /* Pre-declarations needed for WSI entrypoints */
65 struct wl_surface;
66 struct wl_display;
67 typedef struct xcb_connection_t xcb_connection_t;
68 typedef uint32_t xcb_visualid_t;
69 typedef uint32_t xcb_window_t;
70
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
75
76 #include "radv_entrypoints.h"
77
78 #include "wsi_common.h"
79
80 #define ATI_VENDOR_ID 0x1002
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VIEWPORTS 16
86 #define MAX_SCISSORS 16
87 #define MAX_DISCARD_RECTANGLES 4
88 #define MAX_PUSH_CONSTANTS_SIZE 128
89 #define MAX_PUSH_DESCRIPTORS 32
90 #define MAX_DYNAMIC_BUFFERS 16
91 #define MAX_SAMPLES_LOG2 4
92 #define NUM_META_FS_KEYS 13
93 #define RADV_MAX_DRM_DEVICES 8
94 #define MAX_VIEWS 8
95
96 #define NUM_DEPTH_CLEAR_PIPELINES 3
97
98 enum radv_mem_heap {
99 RADV_MEM_HEAP_VRAM,
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
101 RADV_MEM_HEAP_GTT,
102 RADV_MEM_HEAP_COUNT
103 };
104
105 enum radv_mem_type {
106 RADV_MEM_TYPE_VRAM,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
109 RADV_MEM_TYPE_GTT_CACHED,
110 RADV_MEM_TYPE_COUNT
111 };
112
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
114
115 static inline uint32_t
116 align_u32(uint32_t v, uint32_t a)
117 {
118 assert(a != 0 && a == (a & -a));
119 return (v + a - 1) & ~(a - 1);
120 }
121
122 static inline uint32_t
123 align_u32_npot(uint32_t v, uint32_t a)
124 {
125 return (v + a - 1) / a * a;
126 }
127
128 static inline uint64_t
129 align_u64(uint64_t v, uint64_t a)
130 {
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
133 }
134
135 static inline int32_t
136 align_i32(int32_t v, int32_t a)
137 {
138 assert(a != 0 && a == (a & -a));
139 return (v + a - 1) & ~(a - 1);
140 }
141
142 /** Alignment must be a power of 2. */
143 static inline bool
144 radv_is_aligned(uintmax_t n, uintmax_t a)
145 {
146 assert(a == (a & -a));
147 return (n & (a - 1)) == 0;
148 }
149
150 static inline uint32_t
151 round_up_u32(uint32_t v, uint32_t a)
152 {
153 return (v + a - 1) / a;
154 }
155
156 static inline uint64_t
157 round_up_u64(uint64_t v, uint64_t a)
158 {
159 return (v + a - 1) / a;
160 }
161
162 static inline uint32_t
163 radv_minify(uint32_t n, uint32_t levels)
164 {
165 if (unlikely(n == 0))
166 return 0;
167 else
168 return MAX2(n >> levels, 1);
169 }
170 static inline float
171 radv_clamp_f(float f, float min, float max)
172 {
173 assert(min < max);
174
175 if (f > max)
176 return max;
177 else if (f < min)
178 return min;
179 else
180 return f;
181 }
182
183 static inline bool
184 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
185 {
186 if (*inout_mask & clear_mask) {
187 *inout_mask &= ~clear_mask;
188 return true;
189 } else {
190 return false;
191 }
192 }
193
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
198
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
202 })
203
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
207 */
208
209 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
210
211 #ifdef DEBUG
212 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
213 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
214 #else
215 #define vk_error(error) error
216 #define vk_errorf(error, format, ...) error
217 #endif
218
219 void __radv_finishme(const char *file, int line, const char *format, ...)
220 radv_printflike(3, 4);
221 void radv_loge(const char *format, ...) radv_printflike(1, 2);
222 void radv_loge_v(const char *format, va_list va);
223
224 /**
225 * Print a FINISHME message, including its source location.
226 */
227 #define radv_finishme(format, ...) \
228 do { \
229 static bool reported = false; \
230 if (!reported) { \
231 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
232 reported = true; \
233 } \
234 } while (0)
235
236 /* A non-fatal assert. Useful for debugging. */
237 #ifdef DEBUG
238 #define radv_assert(x) ({ \
239 if (unlikely(!(x))) \
240 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
241 })
242 #else
243 #define radv_assert(x)
244 #endif
245
246 #define stub_return(v) \
247 do { \
248 radv_finishme("stub %s", __func__); \
249 return (v); \
250 } while (0)
251
252 #define stub() \
253 do { \
254 radv_finishme("stub %s", __func__); \
255 return; \
256 } while (0)
257
258 void *radv_lookup_entrypoint(const char *name);
259
260 struct radv_physical_device {
261 VK_LOADER_DATA _loader_data;
262
263 struct radv_instance * instance;
264
265 struct radeon_winsys *ws;
266 struct radeon_info rad_info;
267 char path[20];
268 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
269 uint8_t driver_uuid[VK_UUID_SIZE];
270 uint8_t device_uuid[VK_UUID_SIZE];
271 uint8_t cache_uuid[VK_UUID_SIZE];
272
273 int local_fd;
274 struct wsi_device wsi_device;
275
276 bool has_rbplus; /* if RB+ register exist */
277 bool rbplus_allowed; /* if RB+ is allowed */
278 bool has_clear_state;
279 bool cpdma_prefetch_writes_memory;
280 bool has_scissor_bug;
281
282 /* This is the drivers on-disk cache used as a fallback as opposed to
283 * the pipeline cache defined by apps.
284 */
285 struct disk_cache * disk_cache;
286
287 VkPhysicalDeviceMemoryProperties memory_properties;
288 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
289
290 struct radv_device_extension_table supported_extensions;
291 };
292
293 struct radv_instance {
294 VK_LOADER_DATA _loader_data;
295
296 VkAllocationCallbacks alloc;
297
298 uint32_t apiVersion;
299 int physicalDeviceCount;
300 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
301
302 uint64_t debug_flags;
303 uint64_t perftest_flags;
304
305 struct vk_debug_report_instance debug_report_callbacks;
306 };
307
308 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
309 void radv_finish_wsi(struct radv_physical_device *physical_device);
310
311 bool radv_instance_extension_supported(const char *name);
312 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
313 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
314 const char *name);
315
316 struct cache_entry;
317
318 struct radv_pipeline_cache {
319 struct radv_device * device;
320 pthread_mutex_t mutex;
321
322 uint32_t total_size;
323 uint32_t table_size;
324 uint32_t kernel_count;
325 struct cache_entry ** hash_table;
326 bool modified;
327
328 VkAllocationCallbacks alloc;
329 };
330
331 struct radv_pipeline_key {
332 uint32_t instance_rate_inputs;
333 unsigned tess_input_vertices;
334 uint32_t col_format;
335 uint32_t is_int8;
336 uint32_t is_int10;
337 uint8_t log2_ps_iter_samples;
338 uint8_t log2_num_samples;
339 uint32_t multisample : 1;
340 uint32_t has_multiview_view_index : 1;
341 };
342
343 void
344 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
345 struct radv_device *device);
346 void
347 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
348 void
349 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
350 const void *data, size_t size);
351
352 struct radv_shader_variant;
353
354 bool
355 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
356 struct radv_pipeline_cache *cache,
357 const unsigned char *sha1,
358 struct radv_shader_variant **variants);
359
360 void
361 radv_pipeline_cache_insert_shaders(struct radv_device *device,
362 struct radv_pipeline_cache *cache,
363 const unsigned char *sha1,
364 struct radv_shader_variant **variants,
365 const void *const *codes,
366 const unsigned *code_sizes);
367
368 enum radv_blit_ds_layout {
369 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
370 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
371 RADV_BLIT_DS_LAYOUT_COUNT,
372 };
373
374 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
375 {
376 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
377 }
378
379 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
380 {
381 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
382 }
383
384 enum radv_meta_dst_layout {
385 RADV_META_DST_LAYOUT_GENERAL,
386 RADV_META_DST_LAYOUT_OPTIMAL,
387 RADV_META_DST_LAYOUT_COUNT,
388 };
389
390 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
391 {
392 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
393 }
394
395 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
396 {
397 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
398 }
399
400 struct radv_meta_state {
401 VkAllocationCallbacks alloc;
402
403 struct radv_pipeline_cache cache;
404
405 /**
406 * Use array element `i` for images with `2^i` samples.
407 */
408 struct {
409 VkRenderPass render_pass[NUM_META_FS_KEYS];
410 VkPipeline color_pipelines[NUM_META_FS_KEYS];
411
412 VkRenderPass depthstencil_rp;
413 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
414 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
415 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
416 } clear[1 + MAX_SAMPLES_LOG2];
417
418 VkPipelineLayout clear_color_p_layout;
419 VkPipelineLayout clear_depth_p_layout;
420 struct {
421 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
422
423 /** Pipeline that blits from a 1D image. */
424 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
425
426 /** Pipeline that blits from a 2D image. */
427 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
428
429 /** Pipeline that blits from a 3D image. */
430 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
431
432 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
433 VkPipeline depth_only_1d_pipeline;
434 VkPipeline depth_only_2d_pipeline;
435 VkPipeline depth_only_3d_pipeline;
436
437 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
438 VkPipeline stencil_only_1d_pipeline;
439 VkPipeline stencil_only_2d_pipeline;
440 VkPipeline stencil_only_3d_pipeline;
441 VkPipelineLayout pipeline_layout;
442 VkDescriptorSetLayout ds_layout;
443 } blit;
444
445 struct {
446 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
447
448 VkPipelineLayout p_layouts[3];
449 VkDescriptorSetLayout ds_layouts[3];
450 VkPipeline pipelines[3][NUM_META_FS_KEYS];
451
452 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
453 VkPipeline depth_only_pipeline[3];
454
455 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
456 VkPipeline stencil_only_pipeline[3];
457 } blit2d;
458
459 struct {
460 VkPipelineLayout img_p_layout;
461 VkDescriptorSetLayout img_ds_layout;
462 VkPipeline pipeline;
463 VkPipeline pipeline_3d;
464 } itob;
465 struct {
466 VkPipelineLayout img_p_layout;
467 VkDescriptorSetLayout img_ds_layout;
468 VkPipeline pipeline;
469 VkPipeline pipeline_3d;
470 } btoi;
471 struct {
472 VkPipelineLayout img_p_layout;
473 VkDescriptorSetLayout img_ds_layout;
474 VkPipeline pipeline;
475 VkPipeline pipeline_3d;
476 } itoi;
477 struct {
478 VkPipelineLayout img_p_layout;
479 VkDescriptorSetLayout img_ds_layout;
480 VkPipeline pipeline;
481 VkPipeline pipeline_3d;
482 } cleari;
483
484 struct {
485 VkPipelineLayout p_layout;
486 VkPipeline pipeline[NUM_META_FS_KEYS];
487 VkRenderPass pass[NUM_META_FS_KEYS];
488 } resolve;
489
490 struct {
491 VkDescriptorSetLayout ds_layout;
492 VkPipelineLayout p_layout;
493 struct {
494 VkPipeline pipeline;
495 VkPipeline i_pipeline;
496 VkPipeline srgb_pipeline;
497 } rc[MAX_SAMPLES_LOG2];
498 } resolve_compute;
499
500 struct {
501 VkDescriptorSetLayout ds_layout;
502 VkPipelineLayout p_layout;
503
504 struct {
505 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
506 VkPipeline pipeline[NUM_META_FS_KEYS];
507 } rc[MAX_SAMPLES_LOG2];
508 } resolve_fragment;
509
510 struct {
511 VkPipelineLayout p_layout;
512 VkPipeline decompress_pipeline;
513 VkPipeline resummarize_pipeline;
514 VkRenderPass pass;
515 } depth_decomp[1 + MAX_SAMPLES_LOG2];
516
517 struct {
518 VkPipelineLayout p_layout;
519 VkPipeline cmask_eliminate_pipeline;
520 VkPipeline fmask_decompress_pipeline;
521 VkPipeline dcc_decompress_pipeline;
522 VkRenderPass pass;
523
524 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
525 VkPipelineLayout dcc_decompress_compute_p_layout;
526 VkPipeline dcc_decompress_compute_pipeline;
527 } fast_clear_flush;
528
529 struct {
530 VkPipelineLayout fill_p_layout;
531 VkPipelineLayout copy_p_layout;
532 VkDescriptorSetLayout fill_ds_layout;
533 VkDescriptorSetLayout copy_ds_layout;
534 VkPipeline fill_pipeline;
535 VkPipeline copy_pipeline;
536 } buffer;
537
538 struct {
539 VkDescriptorSetLayout ds_layout;
540 VkPipelineLayout p_layout;
541 VkPipeline occlusion_query_pipeline;
542 VkPipeline pipeline_statistics_query_pipeline;
543 } query;
544 };
545
546 /* queue types */
547 #define RADV_QUEUE_GENERAL 0
548 #define RADV_QUEUE_COMPUTE 1
549 #define RADV_QUEUE_TRANSFER 2
550
551 #define RADV_MAX_QUEUE_FAMILIES 3
552
553 enum ring_type radv_queue_family_to_ring(int f);
554
555 struct radv_queue {
556 VK_LOADER_DATA _loader_data;
557 struct radv_device * device;
558 struct radeon_winsys_ctx *hw_ctx;
559 enum radeon_ctx_priority priority;
560 uint32_t queue_family_index;
561 int queue_idx;
562
563 uint32_t scratch_size;
564 uint32_t compute_scratch_size;
565 uint32_t esgs_ring_size;
566 uint32_t gsvs_ring_size;
567 bool has_tess_rings;
568 bool has_sample_positions;
569
570 struct radeon_winsys_bo *scratch_bo;
571 struct radeon_winsys_bo *descriptor_bo;
572 struct radeon_winsys_bo *compute_scratch_bo;
573 struct radeon_winsys_bo *esgs_ring_bo;
574 struct radeon_winsys_bo *gsvs_ring_bo;
575 struct radeon_winsys_bo *tess_factor_ring_bo;
576 struct radeon_winsys_bo *tess_offchip_ring_bo;
577 struct radeon_winsys_cs *initial_preamble_cs;
578 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
579 struct radeon_winsys_cs *continue_preamble_cs;
580 };
581
582 struct radv_device {
583 VK_LOADER_DATA _loader_data;
584
585 VkAllocationCallbacks alloc;
586
587 struct radv_instance * instance;
588 struct radeon_winsys *ws;
589
590 struct radv_meta_state meta_state;
591
592 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
593 int queue_count[RADV_MAX_QUEUE_FAMILIES];
594 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
595
596 bool always_use_syncobj;
597 bool llvm_supports_spill;
598 bool has_distributed_tess;
599 bool pbb_allowed;
600 bool dfsm_allowed;
601 uint32_t tess_offchip_block_dw_size;
602 uint32_t scratch_waves;
603 uint32_t dispatch_initiator;
604
605 uint32_t gs_table_depth;
606
607 /* MSAA sample locations.
608 * The first index is the sample index.
609 * The second index is the coordinate: X, Y. */
610 float sample_locations_1x[1][2];
611 float sample_locations_2x[2][2];
612 float sample_locations_4x[4][2];
613 float sample_locations_8x[8][2];
614 float sample_locations_16x[16][2];
615
616 /* CIK and later */
617 uint32_t gfx_init_size_dw;
618 struct radeon_winsys_bo *gfx_init;
619
620 struct radeon_winsys_bo *trace_bo;
621 uint32_t *trace_id_ptr;
622
623 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
624 bool keep_shader_info;
625
626 struct radv_physical_device *physical_device;
627
628 /* Backup in-memory cache to be used if the app doesn't provide one */
629 struct radv_pipeline_cache * mem_cache;
630
631 /*
632 * use different counters so MSAA MRTs get consecutive surface indices,
633 * even if MASK is allocated in between.
634 */
635 uint32_t image_mrt_offset_counter;
636 uint32_t fmask_mrt_offset_counter;
637 struct list_head shader_slabs;
638 mtx_t shader_slab_mutex;
639
640 /* For detecting VM faults reported by dmesg. */
641 uint64_t dmesg_timestamp;
642 };
643
644 struct radv_device_memory {
645 struct radeon_winsys_bo *bo;
646 /* for dedicated allocations */
647 struct radv_image *image;
648 struct radv_buffer *buffer;
649 uint32_t type_index;
650 VkDeviceSize map_size;
651 void * map;
652 void * user_ptr;
653 };
654
655
656 struct radv_descriptor_range {
657 uint64_t va;
658 uint32_t size;
659 };
660
661 struct radv_descriptor_set {
662 const struct radv_descriptor_set_layout *layout;
663 uint32_t size;
664
665 struct radeon_winsys_bo *bo;
666 uint64_t va;
667 uint32_t *mapped_ptr;
668 struct radv_descriptor_range *dynamic_descriptors;
669
670 struct radeon_winsys_bo *descriptors[0];
671 };
672
673 struct radv_push_descriptor_set
674 {
675 struct radv_descriptor_set set;
676 uint32_t capacity;
677 };
678
679 struct radv_descriptor_pool_entry {
680 uint32_t offset;
681 uint32_t size;
682 struct radv_descriptor_set *set;
683 };
684
685 struct radv_descriptor_pool {
686 struct radeon_winsys_bo *bo;
687 uint8_t *mapped_ptr;
688 uint64_t current_offset;
689 uint64_t size;
690
691 uint8_t *host_memory_base;
692 uint8_t *host_memory_ptr;
693 uint8_t *host_memory_end;
694
695 uint32_t entry_count;
696 uint32_t max_entry_count;
697 struct radv_descriptor_pool_entry entries[0];
698 };
699
700 struct radv_descriptor_update_template_entry {
701 VkDescriptorType descriptor_type;
702
703 /* The number of descriptors to update */
704 uint32_t descriptor_count;
705
706 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
707 uint32_t dst_offset;
708
709 /* In dwords. Not valid/used for dynamic descriptors */
710 uint32_t dst_stride;
711
712 uint32_t buffer_offset;
713
714 /* Only valid for combined image samplers and samplers */
715 uint16_t has_sampler;
716
717 /* In bytes */
718 size_t src_offset;
719 size_t src_stride;
720
721 /* For push descriptors */
722 const uint32_t *immutable_samplers;
723 };
724
725 struct radv_descriptor_update_template {
726 uint32_t entry_count;
727 VkPipelineBindPoint bind_point;
728 struct radv_descriptor_update_template_entry entry[0];
729 };
730
731 struct radv_buffer {
732 struct radv_device * device;
733 VkDeviceSize size;
734
735 VkBufferUsageFlags usage;
736 VkBufferCreateFlags flags;
737
738 /* Set when bound */
739 struct radeon_winsys_bo * bo;
740 VkDeviceSize offset;
741
742 bool shareable;
743 };
744
745 enum radv_dynamic_state_bits {
746 RADV_DYNAMIC_VIEWPORT = 1 << 0,
747 RADV_DYNAMIC_SCISSOR = 1 << 1,
748 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
749 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
750 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
751 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
752 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
753 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
754 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
755 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
756 RADV_DYNAMIC_ALL = (1 << 10) - 1,
757 };
758
759 enum radv_cmd_dirty_bits {
760 /* Keep the dynamic state dirty bits in sync with
761 * enum radv_dynamic_state_bits */
762 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
763 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
764 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
765 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
766 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
767 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
768 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
769 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
770 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
771 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
772 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
773 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
774 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
775 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
776 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
777 };
778
779 enum radv_cmd_flush_bits {
780 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
781 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
782 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
783 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
784 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
785 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
786 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
787 /* Same as above, but only writes back and doesn't invalidate */
788 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
789 /* Framebuffer caches */
790 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
791 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
792 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
793 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
794 /* Engine synchronization. */
795 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
796 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
797 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
798 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
799
800 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
801 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
802 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
803 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
804 };
805
806 struct radv_vertex_binding {
807 struct radv_buffer * buffer;
808 VkDeviceSize offset;
809 };
810
811 struct radv_viewport_state {
812 uint32_t count;
813 VkViewport viewports[MAX_VIEWPORTS];
814 };
815
816 struct radv_scissor_state {
817 uint32_t count;
818 VkRect2D scissors[MAX_SCISSORS];
819 };
820
821 struct radv_discard_rectangle_state {
822 uint32_t count;
823 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
824 };
825
826 struct radv_dynamic_state {
827 /**
828 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
829 * Defines the set of saved dynamic state.
830 */
831 uint32_t mask;
832
833 struct radv_viewport_state viewport;
834
835 struct radv_scissor_state scissor;
836
837 float line_width;
838
839 struct {
840 float bias;
841 float clamp;
842 float slope;
843 } depth_bias;
844
845 float blend_constants[4];
846
847 struct {
848 float min;
849 float max;
850 } depth_bounds;
851
852 struct {
853 uint32_t front;
854 uint32_t back;
855 } stencil_compare_mask;
856
857 struct {
858 uint32_t front;
859 uint32_t back;
860 } stencil_write_mask;
861
862 struct {
863 uint32_t front;
864 uint32_t back;
865 } stencil_reference;
866
867 struct radv_discard_rectangle_state discard_rectangle;
868 };
869
870 extern const struct radv_dynamic_state default_dynamic_state;
871
872 const char *
873 radv_get_debug_option_name(int id);
874
875 const char *
876 radv_get_perftest_option_name(int id);
877
878 /**
879 * Attachment state when recording a renderpass instance.
880 *
881 * The clear value is valid only if there exists a pending clear.
882 */
883 struct radv_attachment_state {
884 VkImageAspectFlags pending_clear_aspects;
885 uint32_t cleared_views;
886 VkClearValue clear_value;
887 VkImageLayout current_layout;
888 };
889
890 struct radv_descriptor_state {
891 struct radv_descriptor_set *sets[MAX_SETS];
892 uint32_t dirty;
893 uint32_t valid;
894 struct radv_push_descriptor_set push_set;
895 bool push_dirty;
896 };
897
898 struct radv_cmd_state {
899 /* Vertex descriptors */
900 bool vb_prefetch_dirty;
901 uint64_t vb_va;
902 unsigned vb_size;
903
904 bool predicating;
905 uint32_t dirty;
906
907 struct radv_pipeline * pipeline;
908 struct radv_pipeline * emitted_pipeline;
909 struct radv_pipeline * compute_pipeline;
910 struct radv_pipeline * emitted_compute_pipeline;
911 struct radv_framebuffer * framebuffer;
912 struct radv_render_pass * pass;
913 const struct radv_subpass * subpass;
914 struct radv_dynamic_state dynamic;
915 struct radv_attachment_state * attachments;
916 VkRect2D render_area;
917
918 /* Index buffer */
919 struct radv_buffer *index_buffer;
920 uint64_t index_offset;
921 uint32_t index_type;
922 uint32_t max_index_count;
923 uint64_t index_va;
924 int32_t last_index_type;
925
926 int32_t last_primitive_reset_en;
927 uint32_t last_primitive_reset_index;
928 enum radv_cmd_flush_bits flush_bits;
929 unsigned active_occlusion_queries;
930 float offset_scale;
931 uint32_t trace_id;
932 uint32_t last_ia_multi_vgt_param;
933
934 uint32_t last_num_instances;
935 uint32_t last_first_instance;
936 uint32_t last_vertex_offset;
937 };
938
939 struct radv_cmd_pool {
940 VkAllocationCallbacks alloc;
941 struct list_head cmd_buffers;
942 struct list_head free_cmd_buffers;
943 uint32_t queue_family_index;
944 };
945
946 struct radv_cmd_buffer_upload {
947 uint8_t *map;
948 unsigned offset;
949 uint64_t size;
950 struct radeon_winsys_bo *upload_bo;
951 struct list_head list;
952 };
953
954 enum radv_cmd_buffer_status {
955 RADV_CMD_BUFFER_STATUS_INVALID,
956 RADV_CMD_BUFFER_STATUS_INITIAL,
957 RADV_CMD_BUFFER_STATUS_RECORDING,
958 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
959 RADV_CMD_BUFFER_STATUS_PENDING,
960 };
961
962 struct radv_cmd_buffer {
963 VK_LOADER_DATA _loader_data;
964
965 struct radv_device * device;
966
967 struct radv_cmd_pool * pool;
968 struct list_head pool_link;
969
970 VkCommandBufferUsageFlags usage_flags;
971 VkCommandBufferLevel level;
972 enum radv_cmd_buffer_status status;
973 struct radeon_winsys_cs *cs;
974 struct radv_cmd_state state;
975 struct radv_vertex_binding vertex_bindings[MAX_VBS];
976 uint32_t queue_family_index;
977
978 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
979 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
980 VkShaderStageFlags push_constant_stages;
981 struct radv_descriptor_set meta_push_descriptors;
982
983 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
984
985 struct radv_cmd_buffer_upload upload;
986
987 uint32_t scratch_size_needed;
988 uint32_t compute_scratch_size_needed;
989 uint32_t esgs_ring_size_needed;
990 uint32_t gsvs_ring_size_needed;
991 bool tess_rings_needed;
992 bool sample_positions_needed;
993
994 VkResult record_result;
995
996 int ring_offsets_idx; /* just used for verification */
997 uint32_t gfx9_fence_offset;
998 struct radeon_winsys_bo *gfx9_fence_bo;
999 uint32_t gfx9_fence_idx;
1000 };
1001
1002 struct radv_image;
1003
1004 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1005
1006 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1007 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1008
1009 void cik_create_gfx_config(struct radv_device *device);
1010
1011 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1012 int count, const VkViewport *viewports);
1013 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1014 int count, const VkRect2D *scissors,
1015 const VkViewport *viewports, bool can_use_guardband);
1016 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1017 bool instanced_draw, bool indirect_draw,
1018 uint32_t draw_vertex_count);
1019 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1020 bool predicated,
1021 enum chip_class chip_class,
1022 bool is_mec,
1023 unsigned event, unsigned event_flags,
1024 unsigned data_sel,
1025 uint64_t va,
1026 uint32_t old_fence,
1027 uint32_t new_fence);
1028
1029 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1030 bool predicated,
1031 uint64_t va, uint32_t ref,
1032 uint32_t mask);
1033 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1034 enum chip_class chip_class,
1035 uint32_t *fence_ptr, uint64_t va,
1036 bool is_mec,
1037 enum radv_cmd_flush_bits flush_bits);
1038 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1039 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1040 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1041 uint64_t src_va, uint64_t dest_va,
1042 uint64_t size);
1043 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1044 unsigned size);
1045 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1046 uint64_t size, unsigned value);
1047 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1048 bool
1049 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1050 unsigned size,
1051 unsigned alignment,
1052 unsigned *out_offset,
1053 void **ptr);
1054 void
1055 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1056 const struct radv_subpass *subpass,
1057 bool transitions);
1058 bool
1059 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1060 unsigned size, unsigned alignmnet,
1061 const void *data, unsigned *out_offset);
1062
1063 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1064 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1065 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1066 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1067 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1068 unsigned radv_cayman_get_maxdist(int log_samples);
1069 void radv_device_init_msaa(struct radv_device *device);
1070 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1071 struct radv_image *image,
1072 VkClearDepthStencilValue ds_clear_value,
1073 VkImageAspectFlags aspects);
1074 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1075 struct radv_image *image,
1076 int idx,
1077 uint32_t color_values[2]);
1078 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1079 struct radv_image *image,
1080 bool value);
1081 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1082 struct radeon_winsys_bo *bo,
1083 uint64_t offset, uint64_t size, uint32_t value);
1084 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1085 bool radv_get_memory_fd(struct radv_device *device,
1086 struct radv_device_memory *memory,
1087 int *pFD);
1088
1089 static inline struct radv_descriptor_state *
1090 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1091 VkPipelineBindPoint bind_point)
1092 {
1093 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1094 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1095 return &cmd_buffer->descriptors[bind_point];
1096 }
1097
1098 /*
1099 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1100 *
1101 * Limitations: Can't call normal dispatch functions without binding or rebinding
1102 * the compute pipeline.
1103 */
1104 void radv_unaligned_dispatch(
1105 struct radv_cmd_buffer *cmd_buffer,
1106 uint32_t x,
1107 uint32_t y,
1108 uint32_t z);
1109
1110 struct radv_event {
1111 struct radeon_winsys_bo *bo;
1112 uint64_t *map;
1113 };
1114
1115 struct radv_shader_module;
1116
1117 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1118 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1119 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1120 void
1121 radv_hash_shaders(unsigned char *hash,
1122 const VkPipelineShaderStageCreateInfo **stages,
1123 const struct radv_pipeline_layout *layout,
1124 const struct radv_pipeline_key *key,
1125 uint32_t flags);
1126
1127 static inline gl_shader_stage
1128 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1129 {
1130 assert(__builtin_popcount(vk_stage) == 1);
1131 return ffs(vk_stage) - 1;
1132 }
1133
1134 static inline VkShaderStageFlagBits
1135 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1136 {
1137 return (1 << mesa_stage);
1138 }
1139
1140 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1141
1142 #define radv_foreach_stage(stage, stage_bits) \
1143 for (gl_shader_stage stage, \
1144 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1145 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1146 __tmp &= ~(1 << (stage)))
1147
1148 unsigned radv_format_meta_fs_key(VkFormat format);
1149
1150 struct radv_multisample_state {
1151 uint32_t db_eqaa;
1152 uint32_t pa_sc_line_cntl;
1153 uint32_t pa_sc_mode_cntl_0;
1154 uint32_t pa_sc_mode_cntl_1;
1155 uint32_t pa_sc_aa_config;
1156 uint32_t pa_sc_aa_mask[2];
1157 unsigned num_samples;
1158 };
1159
1160 struct radv_prim_vertex_count {
1161 uint8_t min;
1162 uint8_t incr;
1163 };
1164
1165 struct radv_vertex_elements_info {
1166 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1167 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1168 uint32_t binding[MAX_VERTEX_ATTRIBS];
1169 uint32_t offset[MAX_VERTEX_ATTRIBS];
1170 uint32_t count;
1171 };
1172
1173 struct radv_ia_multi_vgt_param_helpers {
1174 uint32_t base;
1175 bool partial_es_wave;
1176 uint8_t primgroup_size;
1177 bool wd_switch_on_eop;
1178 bool ia_switch_on_eoi;
1179 bool partial_vs_wave;
1180 };
1181
1182 #define SI_GS_PER_ES 128
1183
1184 struct radv_pipeline {
1185 struct radv_device * device;
1186 struct radv_dynamic_state dynamic_state;
1187
1188 struct radv_pipeline_layout * layout;
1189
1190 bool needs_data_cache;
1191 bool need_indirect_descriptor_sets;
1192 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1193 struct radv_shader_variant *gs_copy_shader;
1194 VkShaderStageFlags active_stages;
1195
1196 struct radeon_winsys_cs cs;
1197
1198 struct radv_vertex_elements_info vertex_elements;
1199
1200 uint32_t binding_stride[MAX_VBS];
1201
1202 uint32_t user_data_0[MESA_SHADER_STAGES];
1203 union {
1204 struct {
1205 struct radv_multisample_state ms;
1206 uint32_t spi_baryc_cntl;
1207 bool prim_restart_enable;
1208 unsigned esgs_ring_size;
1209 unsigned gsvs_ring_size;
1210 uint32_t vtx_base_sgpr;
1211 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1212 uint8_t vtx_emit_num;
1213 struct radv_prim_vertex_count prim_vertex_count;
1214 bool can_use_guardband;
1215 uint32_t needed_dynamic_state;
1216 } graphics;
1217 };
1218
1219 unsigned max_waves;
1220 unsigned scratch_bytes_per_wave;
1221 };
1222
1223 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1224 {
1225 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1226 }
1227
1228 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1229 {
1230 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1231 }
1232
1233 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1234 gl_shader_stage stage,
1235 int idx);
1236
1237 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1238
1239 struct radv_graphics_pipeline_create_info {
1240 bool use_rectlist;
1241 bool db_depth_clear;
1242 bool db_stencil_clear;
1243 bool db_depth_disable_expclear;
1244 bool db_stencil_disable_expclear;
1245 bool db_flush_depth_inplace;
1246 bool db_flush_stencil_inplace;
1247 bool db_resummarize;
1248 uint32_t custom_blend_mode;
1249 };
1250
1251 VkResult
1252 radv_graphics_pipeline_create(VkDevice device,
1253 VkPipelineCache cache,
1254 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1255 const struct radv_graphics_pipeline_create_info *extra,
1256 const VkAllocationCallbacks *alloc,
1257 VkPipeline *pPipeline);
1258
1259 struct vk_format_description;
1260 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1261 int first_non_void);
1262 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1263 int first_non_void);
1264 uint32_t radv_translate_colorformat(VkFormat format);
1265 uint32_t radv_translate_color_numformat(VkFormat format,
1266 const struct vk_format_description *desc,
1267 int first_non_void);
1268 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1269 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1270 uint32_t radv_translate_dbformat(VkFormat format);
1271 uint32_t radv_translate_tex_dataformat(VkFormat format,
1272 const struct vk_format_description *desc,
1273 int first_non_void);
1274 uint32_t radv_translate_tex_numformat(VkFormat format,
1275 const struct vk_format_description *desc,
1276 int first_non_void);
1277 bool radv_format_pack_clear_color(VkFormat format,
1278 uint32_t clear_vals[2],
1279 VkClearColorValue *value);
1280 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1281 bool radv_dcc_formats_compatible(VkFormat format1,
1282 VkFormat format2);
1283
1284 struct radv_fmask_info {
1285 uint64_t offset;
1286 uint64_t size;
1287 unsigned alignment;
1288 unsigned pitch_in_pixels;
1289 unsigned bank_height;
1290 unsigned slice_tile_max;
1291 unsigned tile_mode_index;
1292 unsigned tile_swizzle;
1293 };
1294
1295 struct radv_cmask_info {
1296 uint64_t offset;
1297 uint64_t size;
1298 unsigned alignment;
1299 unsigned slice_tile_max;
1300 };
1301
1302 struct radv_image {
1303 VkImageType type;
1304 /* The original VkFormat provided by the client. This may not match any
1305 * of the actual surface formats.
1306 */
1307 VkFormat vk_format;
1308 VkImageAspectFlags aspects;
1309 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1310 struct ac_surf_info info;
1311 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1312 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1313
1314 VkDeviceSize size;
1315 uint32_t alignment;
1316
1317 unsigned queue_family_mask;
1318 bool exclusive;
1319 bool shareable;
1320
1321 /* Set when bound */
1322 struct radeon_winsys_bo *bo;
1323 VkDeviceSize offset;
1324 uint64_t dcc_offset;
1325 uint64_t htile_offset;
1326 bool tc_compatible_htile;
1327 struct radeon_surf surface;
1328
1329 struct radv_fmask_info fmask;
1330 struct radv_cmask_info cmask;
1331 uint64_t clear_value_offset;
1332 uint64_t dcc_pred_offset;
1333
1334 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1335 VkDeviceMemory owned_memory;
1336 };
1337
1338 /* Whether the image has a htile that is known consistent with the contents of
1339 * the image. */
1340 bool radv_layout_has_htile(const struct radv_image *image,
1341 VkImageLayout layout,
1342 unsigned queue_mask);
1343
1344 /* Whether the image has a htile that is known consistent with the contents of
1345 * the image and is allowed to be in compressed form.
1346 *
1347 * If this is false reads that don't use the htile should be able to return
1348 * correct results.
1349 */
1350 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1351 VkImageLayout layout,
1352 unsigned queue_mask);
1353
1354 bool radv_layout_can_fast_clear(const struct radv_image *image,
1355 VkImageLayout layout,
1356 unsigned queue_mask);
1357
1358 bool radv_layout_dcc_compressed(const struct radv_image *image,
1359 VkImageLayout layout,
1360 unsigned queue_mask);
1361
1362 static inline bool
1363 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1364 {
1365 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1366 }
1367
1368 static inline bool
1369 radv_htile_enabled(const struct radv_image *image, unsigned level)
1370 {
1371 return image->surface.htile_size && level == 0;
1372 }
1373
1374 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1375
1376 static inline uint32_t
1377 radv_get_layerCount(const struct radv_image *image,
1378 const VkImageSubresourceRange *range)
1379 {
1380 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1381 image->info.array_size - range->baseArrayLayer : range->layerCount;
1382 }
1383
1384 static inline uint32_t
1385 radv_get_levelCount(const struct radv_image *image,
1386 const VkImageSubresourceRange *range)
1387 {
1388 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1389 image->info.levels - range->baseMipLevel : range->levelCount;
1390 }
1391
1392 struct radeon_bo_metadata;
1393 void
1394 radv_init_metadata(struct radv_device *device,
1395 struct radv_image *image,
1396 struct radeon_bo_metadata *metadata);
1397
1398 struct radv_image_view {
1399 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1400 struct radeon_winsys_bo *bo;
1401
1402 VkImageViewType type;
1403 VkImageAspectFlags aspect_mask;
1404 VkFormat vk_format;
1405 uint32_t base_layer;
1406 uint32_t layer_count;
1407 uint32_t base_mip;
1408 uint32_t level_count;
1409 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1410
1411 uint32_t descriptor[16];
1412
1413 /* Descriptor for use as a storage image as opposed to a sampled image.
1414 * This has a few differences for cube maps (e.g. type).
1415 */
1416 uint32_t storage_descriptor[16];
1417 };
1418
1419 struct radv_image_create_info {
1420 const VkImageCreateInfo *vk_info;
1421 bool scanout;
1422 bool no_metadata_planes;
1423 };
1424
1425 VkResult radv_image_create(VkDevice _device,
1426 const struct radv_image_create_info *info,
1427 const VkAllocationCallbacks* alloc,
1428 VkImage *pImage);
1429
1430 VkResult
1431 radv_image_from_gralloc(VkDevice device_h,
1432 const VkImageCreateInfo *base_info,
1433 const VkNativeBufferANDROID *gralloc_info,
1434 const VkAllocationCallbacks *alloc,
1435 VkImage *out_image_h);
1436
1437 void radv_image_view_init(struct radv_image_view *view,
1438 struct radv_device *device,
1439 const VkImageViewCreateInfo* pCreateInfo);
1440
1441 struct radv_buffer_view {
1442 struct radeon_winsys_bo *bo;
1443 VkFormat vk_format;
1444 uint64_t range; /**< VkBufferViewCreateInfo::range */
1445 uint32_t state[4];
1446 };
1447 void radv_buffer_view_init(struct radv_buffer_view *view,
1448 struct radv_device *device,
1449 const VkBufferViewCreateInfo* pCreateInfo);
1450
1451 static inline struct VkExtent3D
1452 radv_sanitize_image_extent(const VkImageType imageType,
1453 const struct VkExtent3D imageExtent)
1454 {
1455 switch (imageType) {
1456 case VK_IMAGE_TYPE_1D:
1457 return (VkExtent3D) { imageExtent.width, 1, 1 };
1458 case VK_IMAGE_TYPE_2D:
1459 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1460 case VK_IMAGE_TYPE_3D:
1461 return imageExtent;
1462 default:
1463 unreachable("invalid image type");
1464 }
1465 }
1466
1467 static inline struct VkOffset3D
1468 radv_sanitize_image_offset(const VkImageType imageType,
1469 const struct VkOffset3D imageOffset)
1470 {
1471 switch (imageType) {
1472 case VK_IMAGE_TYPE_1D:
1473 return (VkOffset3D) { imageOffset.x, 0, 0 };
1474 case VK_IMAGE_TYPE_2D:
1475 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1476 case VK_IMAGE_TYPE_3D:
1477 return imageOffset;
1478 default:
1479 unreachable("invalid image type");
1480 }
1481 }
1482
1483 static inline bool
1484 radv_image_extent_compare(const struct radv_image *image,
1485 const VkExtent3D *extent)
1486 {
1487 if (extent->width != image->info.width ||
1488 extent->height != image->info.height ||
1489 extent->depth != image->info.depth)
1490 return false;
1491 return true;
1492 }
1493
1494 struct radv_sampler {
1495 uint32_t state[4];
1496 };
1497
1498 struct radv_color_buffer_info {
1499 uint64_t cb_color_base;
1500 uint64_t cb_color_cmask;
1501 uint64_t cb_color_fmask;
1502 uint64_t cb_dcc_base;
1503 uint32_t cb_color_pitch;
1504 uint32_t cb_color_slice;
1505 uint32_t cb_color_view;
1506 uint32_t cb_color_info;
1507 uint32_t cb_color_attrib;
1508 uint32_t cb_color_attrib2;
1509 uint32_t cb_dcc_control;
1510 uint32_t cb_color_cmask_slice;
1511 uint32_t cb_color_fmask_slice;
1512 };
1513
1514 struct radv_ds_buffer_info {
1515 uint64_t db_z_read_base;
1516 uint64_t db_stencil_read_base;
1517 uint64_t db_z_write_base;
1518 uint64_t db_stencil_write_base;
1519 uint64_t db_htile_data_base;
1520 uint32_t db_depth_info;
1521 uint32_t db_z_info;
1522 uint32_t db_stencil_info;
1523 uint32_t db_depth_view;
1524 uint32_t db_depth_size;
1525 uint32_t db_depth_slice;
1526 uint32_t db_htile_surface;
1527 uint32_t pa_su_poly_offset_db_fmt_cntl;
1528 uint32_t db_z_info2;
1529 uint32_t db_stencil_info2;
1530 float offset_scale;
1531 };
1532
1533 struct radv_attachment_info {
1534 union {
1535 struct radv_color_buffer_info cb;
1536 struct radv_ds_buffer_info ds;
1537 };
1538 struct radv_image_view *attachment;
1539 };
1540
1541 struct radv_framebuffer {
1542 uint32_t width;
1543 uint32_t height;
1544 uint32_t layers;
1545
1546 uint32_t attachment_count;
1547 struct radv_attachment_info attachments[0];
1548 };
1549
1550 struct radv_subpass_barrier {
1551 VkPipelineStageFlags src_stage_mask;
1552 VkAccessFlags src_access_mask;
1553 VkAccessFlags dst_access_mask;
1554 };
1555
1556 struct radv_subpass {
1557 uint32_t input_count;
1558 uint32_t color_count;
1559 VkAttachmentReference * input_attachments;
1560 VkAttachmentReference * color_attachments;
1561 VkAttachmentReference * resolve_attachments;
1562 VkAttachmentReference depth_stencil_attachment;
1563
1564 /** Subpass has at least one resolve attachment */
1565 bool has_resolve;
1566
1567 struct radv_subpass_barrier start_barrier;
1568
1569 uint32_t view_mask;
1570 };
1571
1572 struct radv_render_pass_attachment {
1573 VkFormat format;
1574 uint32_t samples;
1575 VkAttachmentLoadOp load_op;
1576 VkAttachmentLoadOp stencil_load_op;
1577 VkImageLayout initial_layout;
1578 VkImageLayout final_layout;
1579 uint32_t view_mask;
1580 };
1581
1582 struct radv_render_pass {
1583 uint32_t attachment_count;
1584 uint32_t subpass_count;
1585 VkAttachmentReference * subpass_attachments;
1586 struct radv_render_pass_attachment * attachments;
1587 struct radv_subpass_barrier end_barrier;
1588 struct radv_subpass subpasses[0];
1589 };
1590
1591 VkResult radv_device_init_meta(struct radv_device *device);
1592 void radv_device_finish_meta(struct radv_device *device);
1593
1594 struct radv_query_pool {
1595 struct radeon_winsys_bo *bo;
1596 uint32_t stride;
1597 uint32_t availability_offset;
1598 char *ptr;
1599 VkQueryType type;
1600 uint32_t pipeline_stats_mask;
1601 };
1602
1603 struct radv_semaphore {
1604 /* use a winsys sem for non-exportable */
1605 struct radeon_winsys_sem *sem;
1606 uint32_t syncobj;
1607 uint32_t temp_syncobj;
1608 };
1609
1610 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1611 int num_wait_sems,
1612 const VkSemaphore *wait_sems,
1613 int num_signal_sems,
1614 const VkSemaphore *signal_sems,
1615 VkFence fence);
1616 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1617
1618 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1619 VkPipelineBindPoint bind_point,
1620 struct radv_descriptor_set *set,
1621 unsigned idx);
1622
1623 void
1624 radv_update_descriptor_sets(struct radv_device *device,
1625 struct radv_cmd_buffer *cmd_buffer,
1626 VkDescriptorSet overrideSet,
1627 uint32_t descriptorWriteCount,
1628 const VkWriteDescriptorSet *pDescriptorWrites,
1629 uint32_t descriptorCopyCount,
1630 const VkCopyDescriptorSet *pDescriptorCopies);
1631
1632 void
1633 radv_update_descriptor_set_with_template(struct radv_device *device,
1634 struct radv_cmd_buffer *cmd_buffer,
1635 struct radv_descriptor_set *set,
1636 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1637 const void *pData);
1638
1639 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1640 VkPipelineBindPoint pipelineBindPoint,
1641 VkPipelineLayout _layout,
1642 uint32_t set,
1643 uint32_t descriptorWriteCount,
1644 const VkWriteDescriptorSet *pDescriptorWrites);
1645
1646 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1647 struct radv_image *image, uint32_t value);
1648 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1649 struct radv_image *image, uint32_t value);
1650
1651 struct radv_fence {
1652 struct radeon_winsys_fence *fence;
1653 bool submitted;
1654 bool signalled;
1655
1656 uint32_t syncobj;
1657 uint32_t temp_syncobj;
1658 };
1659
1660 struct radeon_winsys_sem;
1661
1662 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1663 \
1664 static inline struct __radv_type * \
1665 __radv_type ## _from_handle(__VkType _handle) \
1666 { \
1667 return (struct __radv_type *) _handle; \
1668 } \
1669 \
1670 static inline __VkType \
1671 __radv_type ## _to_handle(struct __radv_type *_obj) \
1672 { \
1673 return (__VkType) _obj; \
1674 }
1675
1676 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1677 \
1678 static inline struct __radv_type * \
1679 __radv_type ## _from_handle(__VkType _handle) \
1680 { \
1681 return (struct __radv_type *)(uintptr_t) _handle; \
1682 } \
1683 \
1684 static inline __VkType \
1685 __radv_type ## _to_handle(struct __radv_type *_obj) \
1686 { \
1687 return (__VkType)(uintptr_t) _obj; \
1688 }
1689
1690 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1691 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1692
1693 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1694 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1695 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1696 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1697 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1698
1699 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1700 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1701 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1702 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1703 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1704 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1705 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1706 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1709 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1710 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1711 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1712 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1715 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1716 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1719 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1720
1721 #endif /* RADV_PRIVATE_H */