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radv: always initialize the clear depth/stencil values to 0
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "radv_descriptor_set.h"
62 #include "radv_extensions.h"
63 #include "radv_cs.h"
64
65 #include <llvm-c/TargetMachine.h>
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vk_icd.h>
77 #include <vulkan/vk_android_native_buffer.h>
78
79 #include "radv_entrypoints.h"
80
81 #include "wsi_common.h"
82 #include "wsi_common_display.h"
83
84 #define ATI_VENDOR_ID 0x1002
85
86 #define MAX_VBS 32
87 #define MAX_VERTEX_ATTRIBS 32
88 #define MAX_RTS 8
89 #define MAX_VIEWPORTS 16
90 #define MAX_SCISSORS 16
91 #define MAX_DISCARD_RECTANGLES 4
92 #define MAX_PUSH_CONSTANTS_SIZE 128
93 #define MAX_PUSH_DESCRIPTORS 32
94 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
95 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
96 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
97 #define MAX_SAMPLES_LOG2 4
98 #define NUM_META_FS_KEYS 13
99 #define RADV_MAX_DRM_DEVICES 8
100 #define MAX_VIEWS 8
101
102 #define NUM_DEPTH_CLEAR_PIPELINES 3
103
104 /*
105 * This is the point we switch from using CP to compute shader
106 * for certain buffer operations.
107 */
108 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
109
110 enum radv_mem_heap {
111 RADV_MEM_HEAP_VRAM,
112 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
113 RADV_MEM_HEAP_GTT,
114 RADV_MEM_HEAP_COUNT
115 };
116
117 enum radv_mem_type {
118 RADV_MEM_TYPE_VRAM,
119 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
120 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
121 RADV_MEM_TYPE_GTT_CACHED,
122 RADV_MEM_TYPE_COUNT
123 };
124
125 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
126
127 static inline uint32_t
128 align_u32(uint32_t v, uint32_t a)
129 {
130 assert(a != 0 && a == (a & -a));
131 return (v + a - 1) & ~(a - 1);
132 }
133
134 static inline uint32_t
135 align_u32_npot(uint32_t v, uint32_t a)
136 {
137 return (v + a - 1) / a * a;
138 }
139
140 static inline uint64_t
141 align_u64(uint64_t v, uint64_t a)
142 {
143 assert(a != 0 && a == (a & -a));
144 return (v + a - 1) & ~(a - 1);
145 }
146
147 static inline int32_t
148 align_i32(int32_t v, int32_t a)
149 {
150 assert(a != 0 && a == (a & -a));
151 return (v + a - 1) & ~(a - 1);
152 }
153
154 /** Alignment must be a power of 2. */
155 static inline bool
156 radv_is_aligned(uintmax_t n, uintmax_t a)
157 {
158 assert(a == (a & -a));
159 return (n & (a - 1)) == 0;
160 }
161
162 static inline uint32_t
163 round_up_u32(uint32_t v, uint32_t a)
164 {
165 return (v + a - 1) / a;
166 }
167
168 static inline uint64_t
169 round_up_u64(uint64_t v, uint64_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint32_t
175 radv_minify(uint32_t n, uint32_t levels)
176 {
177 if (unlikely(n == 0))
178 return 0;
179 else
180 return MAX2(n >> levels, 1);
181 }
182 static inline float
183 radv_clamp_f(float f, float min, float max)
184 {
185 assert(min < max);
186
187 if (f > max)
188 return max;
189 else if (f < min)
190 return min;
191 else
192 return f;
193 }
194
195 static inline bool
196 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
197 {
198 if (*inout_mask & clear_mask) {
199 *inout_mask &= ~clear_mask;
200 return true;
201 } else {
202 return false;
203 }
204 }
205
206 #define for_each_bit(b, dword) \
207 for (uint32_t __dword = (dword); \
208 (b) = __builtin_ffs(__dword) - 1, __dword; \
209 __dword &= ~(1 << (b)))
210
211 #define typed_memcpy(dest, src, count) ({ \
212 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
213 memcpy((dest), (src), (count) * sizeof(*(src))); \
214 })
215
216 /* Whenever we generate an error, pass it through this function. Useful for
217 * debugging, where we can break on it. Only call at error site, not when
218 * propagating errors. Might be useful to plug in a stack trace here.
219 */
220
221 struct radv_instance;
222
223 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
224
225 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
226 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
227
228 void __radv_finishme(const char *file, int line, const char *format, ...)
229 radv_printflike(3, 4);
230 void radv_loge(const char *format, ...) radv_printflike(1, 2);
231 void radv_loge_v(const char *format, va_list va);
232 void radv_logi(const char *format, ...) radv_printflike(1, 2);
233 void radv_logi_v(const char *format, va_list va);
234
235 /**
236 * Print a FINISHME message, including its source location.
237 */
238 #define radv_finishme(format, ...) \
239 do { \
240 static bool reported = false; \
241 if (!reported) { \
242 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
243 reported = true; \
244 } \
245 } while (0)
246
247 /* A non-fatal assert. Useful for debugging. */
248 #ifdef DEBUG
249 #define radv_assert(x) ({ \
250 if (unlikely(!(x))) \
251 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
252 })
253 #else
254 #define radv_assert(x)
255 #endif
256
257 #define stub_return(v) \
258 do { \
259 radv_finishme("stub %s", __func__); \
260 return (v); \
261 } while (0)
262
263 #define stub() \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return; \
267 } while (0)
268
269 void *radv_lookup_entrypoint_unchecked(const char *name);
270 void *radv_lookup_entrypoint_checked(const char *name,
271 uint32_t core_version,
272 const struct radv_instance_extension_table *instance,
273 const struct radv_device_extension_table *device);
274
275 struct radv_physical_device {
276 VK_LOADER_DATA _loader_data;
277
278 struct radv_instance * instance;
279
280 struct radeon_winsys *ws;
281 struct radeon_info rad_info;
282 char path[20];
283 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
284 uint8_t driver_uuid[VK_UUID_SIZE];
285 uint8_t device_uuid[VK_UUID_SIZE];
286 uint8_t cache_uuid[VK_UUID_SIZE];
287
288 int local_fd;
289 int master_fd;
290 struct wsi_device wsi_device;
291
292 bool has_rbplus; /* if RB+ register exist */
293 bool rbplus_allowed; /* if RB+ is allowed */
294 bool has_clear_state;
295 bool cpdma_prefetch_writes_memory;
296 bool has_scissor_bug;
297
298 bool has_out_of_order_rast;
299 bool out_of_order_rast_allowed;
300
301 /* Whether DCC should be enabled for MSAA textures. */
302 bool dcc_msaa_allowed;
303
304 /* This is the drivers on-disk cache used as a fallback as opposed to
305 * the pipeline cache defined by apps.
306 */
307 struct disk_cache * disk_cache;
308
309 VkPhysicalDeviceMemoryProperties memory_properties;
310 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
311
312 struct radv_device_extension_table supported_extensions;
313 };
314
315 struct radv_instance {
316 VK_LOADER_DATA _loader_data;
317
318 VkAllocationCallbacks alloc;
319
320 uint32_t apiVersion;
321 int physicalDeviceCount;
322 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
323
324 uint64_t debug_flags;
325 uint64_t perftest_flags;
326
327 struct vk_debug_report_instance debug_report_callbacks;
328
329 struct radv_instance_extension_table enabled_extensions;
330 };
331
332 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
333 void radv_finish_wsi(struct radv_physical_device *physical_device);
334
335 bool radv_instance_extension_supported(const char *name);
336 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
337 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
338 const char *name);
339
340 struct cache_entry;
341
342 struct radv_pipeline_cache {
343 struct radv_device * device;
344 pthread_mutex_t mutex;
345
346 uint32_t total_size;
347 uint32_t table_size;
348 uint32_t kernel_count;
349 struct cache_entry ** hash_table;
350 bool modified;
351
352 VkAllocationCallbacks alloc;
353 };
354
355 struct radv_pipeline_key {
356 uint32_t instance_rate_inputs;
357 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
358 uint64_t vertex_alpha_adjust;
359 unsigned tess_input_vertices;
360 uint32_t col_format;
361 uint32_t is_int8;
362 uint32_t is_int10;
363 uint8_t log2_ps_iter_samples;
364 uint8_t num_samples;
365 uint32_t has_multiview_view_index : 1;
366 uint32_t optimisations_disabled : 1;
367 };
368
369 void
370 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
371 struct radv_device *device);
372 void
373 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
374 void
375 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
376 const void *data, size_t size);
377
378 struct radv_shader_variant;
379
380 bool
381 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
382 struct radv_pipeline_cache *cache,
383 const unsigned char *sha1,
384 struct radv_shader_variant **variants);
385
386 void
387 radv_pipeline_cache_insert_shaders(struct radv_device *device,
388 struct radv_pipeline_cache *cache,
389 const unsigned char *sha1,
390 struct radv_shader_variant **variants,
391 const void *const *codes,
392 const unsigned *code_sizes);
393
394 enum radv_blit_ds_layout {
395 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
396 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
397 RADV_BLIT_DS_LAYOUT_COUNT,
398 };
399
400 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
401 {
402 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
403 }
404
405 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
406 {
407 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
408 }
409
410 enum radv_meta_dst_layout {
411 RADV_META_DST_LAYOUT_GENERAL,
412 RADV_META_DST_LAYOUT_OPTIMAL,
413 RADV_META_DST_LAYOUT_COUNT,
414 };
415
416 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
417 {
418 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
419 }
420
421 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
422 {
423 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
424 }
425
426 struct radv_meta_state {
427 VkAllocationCallbacks alloc;
428
429 struct radv_pipeline_cache cache;
430
431 /**
432 * Use array element `i` for images with `2^i` samples.
433 */
434 struct {
435 VkRenderPass render_pass[NUM_META_FS_KEYS];
436 VkPipeline color_pipelines[NUM_META_FS_KEYS];
437
438 VkRenderPass depthstencil_rp;
439 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
440 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
441 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
442 } clear[1 + MAX_SAMPLES_LOG2];
443
444 VkPipelineLayout clear_color_p_layout;
445 VkPipelineLayout clear_depth_p_layout;
446 struct {
447 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
448
449 /** Pipeline that blits from a 1D image. */
450 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
451
452 /** Pipeline that blits from a 2D image. */
453 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
454
455 /** Pipeline that blits from a 3D image. */
456 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
457
458 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
459 VkPipeline depth_only_1d_pipeline;
460 VkPipeline depth_only_2d_pipeline;
461 VkPipeline depth_only_3d_pipeline;
462
463 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
464 VkPipeline stencil_only_1d_pipeline;
465 VkPipeline stencil_only_2d_pipeline;
466 VkPipeline stencil_only_3d_pipeline;
467 VkPipelineLayout pipeline_layout;
468 VkDescriptorSetLayout ds_layout;
469 } blit;
470
471 struct {
472 VkPipelineLayout p_layouts[5];
473 VkDescriptorSetLayout ds_layouts[5];
474 VkPipeline pipelines[5][NUM_META_FS_KEYS];
475
476 VkPipeline depth_only_pipeline[5];
477
478 VkPipeline stencil_only_pipeline[5];
479 } blit2d[1 + MAX_SAMPLES_LOG2];
480
481 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
482 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
483 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
484
485 struct {
486 VkPipelineLayout img_p_layout;
487 VkDescriptorSetLayout img_ds_layout;
488 VkPipeline pipeline;
489 VkPipeline pipeline_3d;
490 } itob;
491 struct {
492 VkPipelineLayout img_p_layout;
493 VkDescriptorSetLayout img_ds_layout;
494 VkPipeline pipeline;
495 VkPipeline pipeline_3d;
496 } btoi;
497 struct {
498 VkPipelineLayout img_p_layout;
499 VkDescriptorSetLayout img_ds_layout;
500 VkPipeline pipeline;
501 VkPipeline pipeline_3d;
502 } itoi;
503 struct {
504 VkPipelineLayout img_p_layout;
505 VkDescriptorSetLayout img_ds_layout;
506 VkPipeline pipeline;
507 VkPipeline pipeline_3d;
508 } cleari;
509
510 struct {
511 VkPipelineLayout p_layout;
512 VkPipeline pipeline[NUM_META_FS_KEYS];
513 VkRenderPass pass[NUM_META_FS_KEYS];
514 } resolve;
515
516 struct {
517 VkDescriptorSetLayout ds_layout;
518 VkPipelineLayout p_layout;
519 struct {
520 VkPipeline pipeline;
521 VkPipeline i_pipeline;
522 VkPipeline srgb_pipeline;
523 } rc[MAX_SAMPLES_LOG2];
524 } resolve_compute;
525
526 struct {
527 VkDescriptorSetLayout ds_layout;
528 VkPipelineLayout p_layout;
529
530 struct {
531 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
532 VkPipeline pipeline[NUM_META_FS_KEYS];
533 } rc[MAX_SAMPLES_LOG2];
534 } resolve_fragment;
535
536 struct {
537 VkPipelineLayout p_layout;
538 VkPipeline decompress_pipeline;
539 VkPipeline resummarize_pipeline;
540 VkRenderPass pass;
541 } depth_decomp[1 + MAX_SAMPLES_LOG2];
542
543 struct {
544 VkPipelineLayout p_layout;
545 VkPipeline cmask_eliminate_pipeline;
546 VkPipeline fmask_decompress_pipeline;
547 VkPipeline dcc_decompress_pipeline;
548 VkRenderPass pass;
549
550 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
551 VkPipelineLayout dcc_decompress_compute_p_layout;
552 VkPipeline dcc_decompress_compute_pipeline;
553 } fast_clear_flush;
554
555 struct {
556 VkPipelineLayout fill_p_layout;
557 VkPipelineLayout copy_p_layout;
558 VkDescriptorSetLayout fill_ds_layout;
559 VkDescriptorSetLayout copy_ds_layout;
560 VkPipeline fill_pipeline;
561 VkPipeline copy_pipeline;
562 } buffer;
563
564 struct {
565 VkDescriptorSetLayout ds_layout;
566 VkPipelineLayout p_layout;
567 VkPipeline occlusion_query_pipeline;
568 VkPipeline pipeline_statistics_query_pipeline;
569 } query;
570 };
571
572 /* queue types */
573 #define RADV_QUEUE_GENERAL 0
574 #define RADV_QUEUE_COMPUTE 1
575 #define RADV_QUEUE_TRANSFER 2
576
577 #define RADV_MAX_QUEUE_FAMILIES 3
578
579 enum ring_type radv_queue_family_to_ring(int f);
580
581 struct radv_queue {
582 VK_LOADER_DATA _loader_data;
583 struct radv_device * device;
584 struct radeon_winsys_ctx *hw_ctx;
585 enum radeon_ctx_priority priority;
586 uint32_t queue_family_index;
587 int queue_idx;
588 VkDeviceQueueCreateFlags flags;
589
590 uint32_t scratch_size;
591 uint32_t compute_scratch_size;
592 uint32_t esgs_ring_size;
593 uint32_t gsvs_ring_size;
594 bool has_tess_rings;
595 bool has_sample_positions;
596
597 struct radeon_winsys_bo *scratch_bo;
598 struct radeon_winsys_bo *descriptor_bo;
599 struct radeon_winsys_bo *compute_scratch_bo;
600 struct radeon_winsys_bo *esgs_ring_bo;
601 struct radeon_winsys_bo *gsvs_ring_bo;
602 struct radeon_winsys_bo *tess_rings_bo;
603 struct radeon_cmdbuf *initial_preamble_cs;
604 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
605 struct radeon_cmdbuf *continue_preamble_cs;
606 };
607
608 struct radv_bo_list {
609 struct radv_winsys_bo_list list;
610 unsigned capacity;
611 pthread_mutex_t mutex;
612 };
613
614 struct radv_device {
615 VK_LOADER_DATA _loader_data;
616
617 VkAllocationCallbacks alloc;
618
619 struct radv_instance * instance;
620 struct radeon_winsys *ws;
621
622 struct radv_meta_state meta_state;
623
624 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
625 int queue_count[RADV_MAX_QUEUE_FAMILIES];
626 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
627
628 bool always_use_syncobj;
629 bool has_distributed_tess;
630 bool pbb_allowed;
631 bool dfsm_allowed;
632 uint32_t tess_offchip_block_dw_size;
633 uint32_t scratch_waves;
634 uint32_t dispatch_initiator;
635
636 uint32_t gs_table_depth;
637
638 /* MSAA sample locations.
639 * The first index is the sample index.
640 * The second index is the coordinate: X, Y. */
641 float sample_locations_1x[1][2];
642 float sample_locations_2x[2][2];
643 float sample_locations_4x[4][2];
644 float sample_locations_8x[8][2];
645 float sample_locations_16x[16][2];
646
647 /* CIK and later */
648 uint32_t gfx_init_size_dw;
649 struct radeon_winsys_bo *gfx_init;
650
651 struct radeon_winsys_bo *trace_bo;
652 uint32_t *trace_id_ptr;
653
654 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
655 bool keep_shader_info;
656
657 struct radv_physical_device *physical_device;
658
659 /* Backup in-memory cache to be used if the app doesn't provide one */
660 struct radv_pipeline_cache * mem_cache;
661
662 /*
663 * use different counters so MSAA MRTs get consecutive surface indices,
664 * even if MASK is allocated in between.
665 */
666 uint32_t image_mrt_offset_counter;
667 uint32_t fmask_mrt_offset_counter;
668 struct list_head shader_slabs;
669 mtx_t shader_slab_mutex;
670
671 /* For detecting VM faults reported by dmesg. */
672 uint64_t dmesg_timestamp;
673
674 struct radv_device_extension_table enabled_extensions;
675
676 /* Whether the driver uses a global BO list. */
677 bool use_global_bo_list;
678
679 struct radv_bo_list bo_list;
680 };
681
682 struct radv_device_memory {
683 struct radeon_winsys_bo *bo;
684 /* for dedicated allocations */
685 struct radv_image *image;
686 struct radv_buffer *buffer;
687 uint32_t type_index;
688 VkDeviceSize map_size;
689 void * map;
690 void * user_ptr;
691 };
692
693
694 struct radv_descriptor_range {
695 uint64_t va;
696 uint32_t size;
697 };
698
699 struct radv_descriptor_set {
700 const struct radv_descriptor_set_layout *layout;
701 uint32_t size;
702
703 struct radeon_winsys_bo *bo;
704 uint64_t va;
705 uint32_t *mapped_ptr;
706 struct radv_descriptor_range *dynamic_descriptors;
707
708 struct radeon_winsys_bo *descriptors[0];
709 };
710
711 struct radv_push_descriptor_set
712 {
713 struct radv_descriptor_set set;
714 uint32_t capacity;
715 };
716
717 struct radv_descriptor_pool_entry {
718 uint32_t offset;
719 uint32_t size;
720 struct radv_descriptor_set *set;
721 };
722
723 struct radv_descriptor_pool {
724 struct radeon_winsys_bo *bo;
725 uint8_t *mapped_ptr;
726 uint64_t current_offset;
727 uint64_t size;
728
729 uint8_t *host_memory_base;
730 uint8_t *host_memory_ptr;
731 uint8_t *host_memory_end;
732
733 uint32_t entry_count;
734 uint32_t max_entry_count;
735 struct radv_descriptor_pool_entry entries[0];
736 };
737
738 struct radv_descriptor_update_template_entry {
739 VkDescriptorType descriptor_type;
740
741 /* The number of descriptors to update */
742 uint32_t descriptor_count;
743
744 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
745 uint32_t dst_offset;
746
747 /* In dwords. Not valid/used for dynamic descriptors */
748 uint32_t dst_stride;
749
750 uint32_t buffer_offset;
751
752 /* Only valid for combined image samplers and samplers */
753 uint16_t has_sampler;
754
755 /* In bytes */
756 size_t src_offset;
757 size_t src_stride;
758
759 /* For push descriptors */
760 const uint32_t *immutable_samplers;
761 };
762
763 struct radv_descriptor_update_template {
764 uint32_t entry_count;
765 VkPipelineBindPoint bind_point;
766 struct radv_descriptor_update_template_entry entry[0];
767 };
768
769 struct radv_buffer {
770 VkDeviceSize size;
771
772 VkBufferUsageFlags usage;
773 VkBufferCreateFlags flags;
774
775 /* Set when bound */
776 struct radeon_winsys_bo * bo;
777 VkDeviceSize offset;
778
779 bool shareable;
780 };
781
782 enum radv_dynamic_state_bits {
783 RADV_DYNAMIC_VIEWPORT = 1 << 0,
784 RADV_DYNAMIC_SCISSOR = 1 << 1,
785 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
786 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
787 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
788 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
789 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
790 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
791 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
792 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
793 RADV_DYNAMIC_ALL = (1 << 10) - 1,
794 };
795
796 enum radv_cmd_dirty_bits {
797 /* Keep the dynamic state dirty bits in sync with
798 * enum radv_dynamic_state_bits */
799 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
800 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
801 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
802 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
803 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
804 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
805 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
806 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
807 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
808 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
809 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
810 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
811 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
812 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
813 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
814 };
815
816 enum radv_cmd_flush_bits {
817 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
818 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
819 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
820 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
821 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
822 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
823 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
824 /* Same as above, but only writes back and doesn't invalidate */
825 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
826 /* Framebuffer caches */
827 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
828 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
829 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
830 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
831 /* Engine synchronization. */
832 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
833 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
834 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
835 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
836
837 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
838 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
839 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
840 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
841 };
842
843 struct radv_vertex_binding {
844 struct radv_buffer * buffer;
845 VkDeviceSize offset;
846 };
847
848 struct radv_viewport_state {
849 uint32_t count;
850 VkViewport viewports[MAX_VIEWPORTS];
851 };
852
853 struct radv_scissor_state {
854 uint32_t count;
855 VkRect2D scissors[MAX_SCISSORS];
856 };
857
858 struct radv_discard_rectangle_state {
859 uint32_t count;
860 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
861 };
862
863 struct radv_dynamic_state {
864 /**
865 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
866 * Defines the set of saved dynamic state.
867 */
868 uint32_t mask;
869
870 struct radv_viewport_state viewport;
871
872 struct radv_scissor_state scissor;
873
874 float line_width;
875
876 struct {
877 float bias;
878 float clamp;
879 float slope;
880 } depth_bias;
881
882 float blend_constants[4];
883
884 struct {
885 float min;
886 float max;
887 } depth_bounds;
888
889 struct {
890 uint32_t front;
891 uint32_t back;
892 } stencil_compare_mask;
893
894 struct {
895 uint32_t front;
896 uint32_t back;
897 } stencil_write_mask;
898
899 struct {
900 uint32_t front;
901 uint32_t back;
902 } stencil_reference;
903
904 struct radv_discard_rectangle_state discard_rectangle;
905 };
906
907 extern const struct radv_dynamic_state default_dynamic_state;
908
909 const char *
910 radv_get_debug_option_name(int id);
911
912 const char *
913 radv_get_perftest_option_name(int id);
914
915 /**
916 * Attachment state when recording a renderpass instance.
917 *
918 * The clear value is valid only if there exists a pending clear.
919 */
920 struct radv_attachment_state {
921 VkImageAspectFlags pending_clear_aspects;
922 uint32_t cleared_views;
923 VkClearValue clear_value;
924 VkImageLayout current_layout;
925 };
926
927 struct radv_descriptor_state {
928 struct radv_descriptor_set *sets[MAX_SETS];
929 uint32_t dirty;
930 uint32_t valid;
931 struct radv_push_descriptor_set push_set;
932 bool push_dirty;
933 };
934
935 struct radv_cmd_state {
936 /* Vertex descriptors */
937 uint64_t vb_va;
938 unsigned vb_size;
939
940 bool predicating;
941 uint32_t dirty;
942
943 uint32_t prefetch_L2_mask;
944
945 struct radv_pipeline * pipeline;
946 struct radv_pipeline * emitted_pipeline;
947 struct radv_pipeline * compute_pipeline;
948 struct radv_pipeline * emitted_compute_pipeline;
949 struct radv_framebuffer * framebuffer;
950 struct radv_render_pass * pass;
951 const struct radv_subpass * subpass;
952 struct radv_dynamic_state dynamic;
953 struct radv_attachment_state * attachments;
954 VkRect2D render_area;
955
956 /* Index buffer */
957 struct radv_buffer *index_buffer;
958 uint64_t index_offset;
959 uint32_t index_type;
960 uint32_t max_index_count;
961 uint64_t index_va;
962 int32_t last_index_type;
963
964 int32_t last_primitive_reset_en;
965 uint32_t last_primitive_reset_index;
966 enum radv_cmd_flush_bits flush_bits;
967 unsigned active_occlusion_queries;
968 bool perfect_occlusion_queries_enabled;
969 float offset_scale;
970 uint32_t trace_id;
971 uint32_t last_ia_multi_vgt_param;
972
973 uint32_t last_num_instances;
974 uint32_t last_first_instance;
975 uint32_t last_vertex_offset;
976 };
977
978 struct radv_cmd_pool {
979 VkAllocationCallbacks alloc;
980 struct list_head cmd_buffers;
981 struct list_head free_cmd_buffers;
982 uint32_t queue_family_index;
983 };
984
985 struct radv_cmd_buffer_upload {
986 uint8_t *map;
987 unsigned offset;
988 uint64_t size;
989 struct radeon_winsys_bo *upload_bo;
990 struct list_head list;
991 };
992
993 enum radv_cmd_buffer_status {
994 RADV_CMD_BUFFER_STATUS_INVALID,
995 RADV_CMD_BUFFER_STATUS_INITIAL,
996 RADV_CMD_BUFFER_STATUS_RECORDING,
997 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
998 RADV_CMD_BUFFER_STATUS_PENDING,
999 };
1000
1001 struct radv_cmd_buffer {
1002 VK_LOADER_DATA _loader_data;
1003
1004 struct radv_device * device;
1005
1006 struct radv_cmd_pool * pool;
1007 struct list_head pool_link;
1008
1009 VkCommandBufferUsageFlags usage_flags;
1010 VkCommandBufferLevel level;
1011 enum radv_cmd_buffer_status status;
1012 struct radeon_cmdbuf *cs;
1013 struct radv_cmd_state state;
1014 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1015 uint32_t queue_family_index;
1016
1017 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1018 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1019 VkShaderStageFlags push_constant_stages;
1020 struct radv_descriptor_set meta_push_descriptors;
1021
1022 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1023
1024 struct radv_cmd_buffer_upload upload;
1025
1026 uint32_t scratch_size_needed;
1027 uint32_t compute_scratch_size_needed;
1028 uint32_t esgs_ring_size_needed;
1029 uint32_t gsvs_ring_size_needed;
1030 bool tess_rings_needed;
1031 bool sample_positions_needed;
1032
1033 VkResult record_result;
1034
1035 int ring_offsets_idx; /* just used for verification */
1036 uint32_t gfx9_fence_offset;
1037 struct radeon_winsys_bo *gfx9_fence_bo;
1038 uint32_t gfx9_fence_idx;
1039
1040 /**
1041 * Whether a query pool has been resetted and we have to flush caches.
1042 */
1043 bool pending_reset_query;
1044 };
1045
1046 struct radv_image;
1047
1048 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1049
1050 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1051 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1052
1053 void cik_create_gfx_config(struct radv_device *device);
1054
1055 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1056 int count, const VkViewport *viewports);
1057 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1058 int count, const VkRect2D *scissors,
1059 const VkViewport *viewports, bool can_use_guardband);
1060 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1061 bool instanced_draw, bool indirect_draw,
1062 uint32_t draw_vertex_count);
1063 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1064 bool predicated,
1065 enum chip_class chip_class,
1066 bool is_mec,
1067 unsigned event, unsigned event_flags,
1068 unsigned data_sel,
1069 uint64_t va,
1070 uint32_t old_fence,
1071 uint32_t new_fence);
1072
1073 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1074 bool predicated,
1075 uint64_t va, uint32_t ref,
1076 uint32_t mask);
1077 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1078 enum chip_class chip_class,
1079 uint32_t *fence_ptr, uint64_t va,
1080 bool is_mec,
1081 enum radv_cmd_flush_bits flush_bits);
1082 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1083 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1084 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1085 uint64_t src_va, uint64_t dest_va,
1086 uint64_t size);
1087 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1088 unsigned size);
1089 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1090 uint64_t size, unsigned value);
1091 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1092 bool
1093 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1094 unsigned size,
1095 unsigned alignment,
1096 unsigned *out_offset,
1097 void **ptr);
1098 void
1099 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1100 const struct radv_subpass *subpass,
1101 bool transitions);
1102 bool
1103 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1104 unsigned size, unsigned alignmnet,
1105 const void *data, unsigned *out_offset);
1106
1107 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1108 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1109 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1110 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1111 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1112 unsigned radv_cayman_get_maxdist(int log_samples);
1113 void radv_device_init_msaa(struct radv_device *device);
1114
1115 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1116 struct radv_image *image,
1117 VkClearDepthStencilValue ds_clear_value,
1118 VkImageAspectFlags aspects);
1119
1120 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1121 struct radv_image *image,
1122 int cb_idx,
1123 uint32_t color_values[2]);
1124
1125 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1126 struct radv_image *image,
1127 bool value);
1128 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1129 struct radeon_winsys_bo *bo,
1130 uint64_t offset, uint64_t size, uint32_t value);
1131 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1132 bool radv_get_memory_fd(struct radv_device *device,
1133 struct radv_device_memory *memory,
1134 int *pFD);
1135
1136 static inline void
1137 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1138 unsigned sh_offset, unsigned pointer_count,
1139 bool use_32bit_pointers)
1140 {
1141 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1142 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1143 }
1144
1145 static inline void
1146 radv_emit_shader_pointer_body(struct radv_device *device,
1147 struct radeon_cmdbuf *cs,
1148 uint64_t va, bool use_32bit_pointers)
1149 {
1150 radeon_emit(cs, va);
1151
1152 if (use_32bit_pointers) {
1153 assert(va == 0 ||
1154 (va >> 32) == device->physical_device->rad_info.address32_hi);
1155 } else {
1156 radeon_emit(cs, va >> 32);
1157 }
1158 }
1159
1160 static inline void
1161 radv_emit_shader_pointer(struct radv_device *device,
1162 struct radeon_cmdbuf *cs,
1163 uint32_t sh_offset, uint64_t va, bool global)
1164 {
1165 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1166
1167 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1168 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1169 }
1170
1171 static inline struct radv_descriptor_state *
1172 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1173 VkPipelineBindPoint bind_point)
1174 {
1175 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1176 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1177 return &cmd_buffer->descriptors[bind_point];
1178 }
1179
1180 /*
1181 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1182 *
1183 * Limitations: Can't call normal dispatch functions without binding or rebinding
1184 * the compute pipeline.
1185 */
1186 void radv_unaligned_dispatch(
1187 struct radv_cmd_buffer *cmd_buffer,
1188 uint32_t x,
1189 uint32_t y,
1190 uint32_t z);
1191
1192 struct radv_event {
1193 struct radeon_winsys_bo *bo;
1194 uint64_t *map;
1195 };
1196
1197 struct radv_shader_module;
1198
1199 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1200 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1201 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1202 void
1203 radv_hash_shaders(unsigned char *hash,
1204 const VkPipelineShaderStageCreateInfo **stages,
1205 const struct radv_pipeline_layout *layout,
1206 const struct radv_pipeline_key *key,
1207 uint32_t flags);
1208
1209 static inline gl_shader_stage
1210 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1211 {
1212 assert(__builtin_popcount(vk_stage) == 1);
1213 return ffs(vk_stage) - 1;
1214 }
1215
1216 static inline VkShaderStageFlagBits
1217 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1218 {
1219 return (1 << mesa_stage);
1220 }
1221
1222 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1223
1224 #define radv_foreach_stage(stage, stage_bits) \
1225 for (gl_shader_stage stage, \
1226 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1227 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1228 __tmp &= ~(1 << (stage)))
1229
1230 unsigned radv_format_meta_fs_key(VkFormat format);
1231
1232 struct radv_multisample_state {
1233 uint32_t db_eqaa;
1234 uint32_t pa_sc_line_cntl;
1235 uint32_t pa_sc_mode_cntl_0;
1236 uint32_t pa_sc_mode_cntl_1;
1237 uint32_t pa_sc_aa_config;
1238 uint32_t pa_sc_aa_mask[2];
1239 unsigned num_samples;
1240 };
1241
1242 struct radv_prim_vertex_count {
1243 uint8_t min;
1244 uint8_t incr;
1245 };
1246
1247 struct radv_vertex_elements_info {
1248 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1249 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1250 uint32_t binding[MAX_VERTEX_ATTRIBS];
1251 uint32_t offset[MAX_VERTEX_ATTRIBS];
1252 uint32_t count;
1253 };
1254
1255 struct radv_ia_multi_vgt_param_helpers {
1256 uint32_t base;
1257 bool partial_es_wave;
1258 uint8_t primgroup_size;
1259 bool wd_switch_on_eop;
1260 bool ia_switch_on_eoi;
1261 bool partial_vs_wave;
1262 };
1263
1264 #define SI_GS_PER_ES 128
1265
1266 struct radv_pipeline {
1267 struct radv_device * device;
1268 struct radv_dynamic_state dynamic_state;
1269
1270 struct radv_pipeline_layout * layout;
1271
1272 bool need_indirect_descriptor_sets;
1273 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1274 struct radv_shader_variant *gs_copy_shader;
1275 VkShaderStageFlags active_stages;
1276
1277 struct radeon_cmdbuf cs;
1278
1279 struct radv_vertex_elements_info vertex_elements;
1280
1281 uint32_t binding_stride[MAX_VBS];
1282
1283 uint32_t user_data_0[MESA_SHADER_STAGES];
1284 union {
1285 struct {
1286 struct radv_multisample_state ms;
1287 uint32_t spi_baryc_cntl;
1288 bool prim_restart_enable;
1289 unsigned esgs_ring_size;
1290 unsigned gsvs_ring_size;
1291 uint32_t vtx_base_sgpr;
1292 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1293 uint8_t vtx_emit_num;
1294 struct radv_prim_vertex_count prim_vertex_count;
1295 bool can_use_guardband;
1296 uint32_t needed_dynamic_state;
1297 bool disable_out_of_order_rast_for_occlusion;
1298
1299 /* Used for rbplus */
1300 uint32_t col_format;
1301 uint32_t cb_target_mask;
1302 } graphics;
1303 };
1304
1305 unsigned max_waves;
1306 unsigned scratch_bytes_per_wave;
1307 };
1308
1309 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1310 {
1311 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1312 }
1313
1314 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1315 {
1316 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1317 }
1318
1319 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1320 gl_shader_stage stage,
1321 int idx);
1322
1323 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1324 gl_shader_stage stage);
1325
1326 struct radv_graphics_pipeline_create_info {
1327 bool use_rectlist;
1328 bool db_depth_clear;
1329 bool db_stencil_clear;
1330 bool db_depth_disable_expclear;
1331 bool db_stencil_disable_expclear;
1332 bool db_flush_depth_inplace;
1333 bool db_flush_stencil_inplace;
1334 bool db_resummarize;
1335 uint32_t custom_blend_mode;
1336 };
1337
1338 VkResult
1339 radv_graphics_pipeline_create(VkDevice device,
1340 VkPipelineCache cache,
1341 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1342 const struct radv_graphics_pipeline_create_info *extra,
1343 const VkAllocationCallbacks *alloc,
1344 VkPipeline *pPipeline);
1345
1346 struct vk_format_description;
1347 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1348 int first_non_void);
1349 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1350 int first_non_void);
1351 uint32_t radv_translate_colorformat(VkFormat format);
1352 uint32_t radv_translate_color_numformat(VkFormat format,
1353 const struct vk_format_description *desc,
1354 int first_non_void);
1355 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1356 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1357 uint32_t radv_translate_dbformat(VkFormat format);
1358 uint32_t radv_translate_tex_dataformat(VkFormat format,
1359 const struct vk_format_description *desc,
1360 int first_non_void);
1361 uint32_t radv_translate_tex_numformat(VkFormat format,
1362 const struct vk_format_description *desc,
1363 int first_non_void);
1364 bool radv_format_pack_clear_color(VkFormat format,
1365 uint32_t clear_vals[2],
1366 VkClearColorValue *value);
1367 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1368 bool radv_dcc_formats_compatible(VkFormat format1,
1369 VkFormat format2);
1370
1371 struct radv_fmask_info {
1372 uint64_t offset;
1373 uint64_t size;
1374 unsigned alignment;
1375 unsigned pitch_in_pixels;
1376 unsigned bank_height;
1377 unsigned slice_tile_max;
1378 unsigned tile_mode_index;
1379 unsigned tile_swizzle;
1380 };
1381
1382 struct radv_cmask_info {
1383 uint64_t offset;
1384 uint64_t size;
1385 unsigned alignment;
1386 unsigned slice_tile_max;
1387 };
1388
1389 struct radv_image {
1390 VkImageType type;
1391 /* The original VkFormat provided by the client. This may not match any
1392 * of the actual surface formats.
1393 */
1394 VkFormat vk_format;
1395 VkImageAspectFlags aspects;
1396 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1397 struct ac_surf_info info;
1398 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1399 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1400
1401 VkDeviceSize size;
1402 uint32_t alignment;
1403
1404 unsigned queue_family_mask;
1405 bool exclusive;
1406 bool shareable;
1407
1408 /* Set when bound */
1409 struct radeon_winsys_bo *bo;
1410 VkDeviceSize offset;
1411 uint64_t dcc_offset;
1412 uint64_t htile_offset;
1413 bool tc_compatible_htile;
1414 struct radeon_surf surface;
1415
1416 struct radv_fmask_info fmask;
1417 struct radv_cmask_info cmask;
1418 uint64_t clear_value_offset;
1419 uint64_t dcc_pred_offset;
1420
1421 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1422 VkDeviceMemory owned_memory;
1423 };
1424
1425 /* Whether the image has a htile that is known consistent with the contents of
1426 * the image. */
1427 bool radv_layout_has_htile(const struct radv_image *image,
1428 VkImageLayout layout,
1429 unsigned queue_mask);
1430
1431 /* Whether the image has a htile that is known consistent with the contents of
1432 * the image and is allowed to be in compressed form.
1433 *
1434 * If this is false reads that don't use the htile should be able to return
1435 * correct results.
1436 */
1437 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1438 VkImageLayout layout,
1439 unsigned queue_mask);
1440
1441 bool radv_layout_can_fast_clear(const struct radv_image *image,
1442 VkImageLayout layout,
1443 unsigned queue_mask);
1444
1445 bool radv_layout_dcc_compressed(const struct radv_image *image,
1446 VkImageLayout layout,
1447 unsigned queue_mask);
1448
1449 /**
1450 * Return whether the image has CMASK metadata for color surfaces.
1451 */
1452 static inline bool
1453 radv_image_has_cmask(const struct radv_image *image)
1454 {
1455 return image->cmask.size;
1456 }
1457
1458 /**
1459 * Return whether the image has FMASK metadata for color surfaces.
1460 */
1461 static inline bool
1462 radv_image_has_fmask(const struct radv_image *image)
1463 {
1464 return image->fmask.size;
1465 }
1466
1467 /**
1468 * Return whether the image has DCC metadata for color surfaces.
1469 */
1470 static inline bool
1471 radv_image_has_dcc(const struct radv_image *image)
1472 {
1473 return image->surface.dcc_size;
1474 }
1475
1476 /**
1477 * Return whether DCC metadata is enabled for a level.
1478 */
1479 static inline bool
1480 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1481 {
1482 return radv_image_has_dcc(image) &&
1483 level < image->surface.num_dcc_levels;
1484 }
1485
1486 /**
1487 * Return whether the image has HTILE metadata for depth surfaces.
1488 */
1489 static inline bool
1490 radv_image_has_htile(const struct radv_image *image)
1491 {
1492 return image->surface.htile_size;
1493 }
1494
1495 /**
1496 * Return whether HTILE metadata is enabled for a level.
1497 */
1498 static inline bool
1499 radv_htile_enabled(const struct radv_image *image, unsigned level)
1500 {
1501 return radv_image_has_htile(image) && level == 0;
1502 }
1503
1504 /**
1505 * Return whether the image is TC-compatible HTILE.
1506 */
1507 static inline bool
1508 radv_image_is_tc_compat_htile(const struct radv_image *image)
1509 {
1510 return radv_image_has_htile(image) && image->tc_compatible_htile;
1511 }
1512
1513 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1514
1515 static inline uint32_t
1516 radv_get_layerCount(const struct radv_image *image,
1517 const VkImageSubresourceRange *range)
1518 {
1519 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1520 image->info.array_size - range->baseArrayLayer : range->layerCount;
1521 }
1522
1523 static inline uint32_t
1524 radv_get_levelCount(const struct radv_image *image,
1525 const VkImageSubresourceRange *range)
1526 {
1527 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1528 image->info.levels - range->baseMipLevel : range->levelCount;
1529 }
1530
1531 struct radeon_bo_metadata;
1532 void
1533 radv_init_metadata(struct radv_device *device,
1534 struct radv_image *image,
1535 struct radeon_bo_metadata *metadata);
1536
1537 struct radv_image_view {
1538 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1539 struct radeon_winsys_bo *bo;
1540
1541 VkImageViewType type;
1542 VkImageAspectFlags aspect_mask;
1543 VkFormat vk_format;
1544 uint32_t base_layer;
1545 uint32_t layer_count;
1546 uint32_t base_mip;
1547 uint32_t level_count;
1548 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1549
1550 uint32_t descriptor[16];
1551
1552 /* Descriptor for use as a storage image as opposed to a sampled image.
1553 * This has a few differences for cube maps (e.g. type).
1554 */
1555 uint32_t storage_descriptor[16];
1556 };
1557
1558 struct radv_image_create_info {
1559 const VkImageCreateInfo *vk_info;
1560 bool scanout;
1561 bool no_metadata_planes;
1562 };
1563
1564 VkResult radv_image_create(VkDevice _device,
1565 const struct radv_image_create_info *info,
1566 const VkAllocationCallbacks* alloc,
1567 VkImage *pImage);
1568
1569 VkResult
1570 radv_image_from_gralloc(VkDevice device_h,
1571 const VkImageCreateInfo *base_info,
1572 const VkNativeBufferANDROID *gralloc_info,
1573 const VkAllocationCallbacks *alloc,
1574 VkImage *out_image_h);
1575
1576 void radv_image_view_init(struct radv_image_view *view,
1577 struct radv_device *device,
1578 const VkImageViewCreateInfo* pCreateInfo);
1579
1580 struct radv_buffer_view {
1581 struct radeon_winsys_bo *bo;
1582 VkFormat vk_format;
1583 uint64_t range; /**< VkBufferViewCreateInfo::range */
1584 uint32_t state[4];
1585 };
1586 void radv_buffer_view_init(struct radv_buffer_view *view,
1587 struct radv_device *device,
1588 const VkBufferViewCreateInfo* pCreateInfo);
1589
1590 static inline struct VkExtent3D
1591 radv_sanitize_image_extent(const VkImageType imageType,
1592 const struct VkExtent3D imageExtent)
1593 {
1594 switch (imageType) {
1595 case VK_IMAGE_TYPE_1D:
1596 return (VkExtent3D) { imageExtent.width, 1, 1 };
1597 case VK_IMAGE_TYPE_2D:
1598 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1599 case VK_IMAGE_TYPE_3D:
1600 return imageExtent;
1601 default:
1602 unreachable("invalid image type");
1603 }
1604 }
1605
1606 static inline struct VkOffset3D
1607 radv_sanitize_image_offset(const VkImageType imageType,
1608 const struct VkOffset3D imageOffset)
1609 {
1610 switch (imageType) {
1611 case VK_IMAGE_TYPE_1D:
1612 return (VkOffset3D) { imageOffset.x, 0, 0 };
1613 case VK_IMAGE_TYPE_2D:
1614 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1615 case VK_IMAGE_TYPE_3D:
1616 return imageOffset;
1617 default:
1618 unreachable("invalid image type");
1619 }
1620 }
1621
1622 static inline bool
1623 radv_image_extent_compare(const struct radv_image *image,
1624 const VkExtent3D *extent)
1625 {
1626 if (extent->width != image->info.width ||
1627 extent->height != image->info.height ||
1628 extent->depth != image->info.depth)
1629 return false;
1630 return true;
1631 }
1632
1633 struct radv_sampler {
1634 uint32_t state[4];
1635 };
1636
1637 struct radv_color_buffer_info {
1638 uint64_t cb_color_base;
1639 uint64_t cb_color_cmask;
1640 uint64_t cb_color_fmask;
1641 uint64_t cb_dcc_base;
1642 uint32_t cb_color_pitch;
1643 uint32_t cb_color_slice;
1644 uint32_t cb_color_view;
1645 uint32_t cb_color_info;
1646 uint32_t cb_color_attrib;
1647 uint32_t cb_color_attrib2;
1648 uint32_t cb_dcc_control;
1649 uint32_t cb_color_cmask_slice;
1650 uint32_t cb_color_fmask_slice;
1651 };
1652
1653 struct radv_ds_buffer_info {
1654 uint64_t db_z_read_base;
1655 uint64_t db_stencil_read_base;
1656 uint64_t db_z_write_base;
1657 uint64_t db_stencil_write_base;
1658 uint64_t db_htile_data_base;
1659 uint32_t db_depth_info;
1660 uint32_t db_z_info;
1661 uint32_t db_stencil_info;
1662 uint32_t db_depth_view;
1663 uint32_t db_depth_size;
1664 uint32_t db_depth_slice;
1665 uint32_t db_htile_surface;
1666 uint32_t pa_su_poly_offset_db_fmt_cntl;
1667 uint32_t db_z_info2;
1668 uint32_t db_stencil_info2;
1669 float offset_scale;
1670 };
1671
1672 struct radv_attachment_info {
1673 union {
1674 struct radv_color_buffer_info cb;
1675 struct radv_ds_buffer_info ds;
1676 };
1677 struct radv_image_view *attachment;
1678 };
1679
1680 struct radv_framebuffer {
1681 uint32_t width;
1682 uint32_t height;
1683 uint32_t layers;
1684
1685 uint32_t attachment_count;
1686 struct radv_attachment_info attachments[0];
1687 };
1688
1689 struct radv_subpass_barrier {
1690 VkPipelineStageFlags src_stage_mask;
1691 VkAccessFlags src_access_mask;
1692 VkAccessFlags dst_access_mask;
1693 };
1694
1695 struct radv_subpass {
1696 uint32_t input_count;
1697 uint32_t color_count;
1698 VkAttachmentReference * input_attachments;
1699 VkAttachmentReference * color_attachments;
1700 VkAttachmentReference * resolve_attachments;
1701 VkAttachmentReference depth_stencil_attachment;
1702
1703 /** Subpass has at least one resolve attachment */
1704 bool has_resolve;
1705
1706 struct radv_subpass_barrier start_barrier;
1707
1708 uint32_t view_mask;
1709 VkSampleCountFlagBits max_sample_count;
1710 };
1711
1712 struct radv_render_pass_attachment {
1713 VkFormat format;
1714 uint32_t samples;
1715 VkAttachmentLoadOp load_op;
1716 VkAttachmentLoadOp stencil_load_op;
1717 VkImageLayout initial_layout;
1718 VkImageLayout final_layout;
1719 uint32_t view_mask;
1720 };
1721
1722 struct radv_render_pass {
1723 uint32_t attachment_count;
1724 uint32_t subpass_count;
1725 VkAttachmentReference * subpass_attachments;
1726 struct radv_render_pass_attachment * attachments;
1727 struct radv_subpass_barrier end_barrier;
1728 struct radv_subpass subpasses[0];
1729 };
1730
1731 VkResult radv_device_init_meta(struct radv_device *device);
1732 void radv_device_finish_meta(struct radv_device *device);
1733
1734 struct radv_query_pool {
1735 struct radeon_winsys_bo *bo;
1736 uint32_t stride;
1737 uint32_t availability_offset;
1738 uint64_t size;
1739 char *ptr;
1740 VkQueryType type;
1741 uint32_t pipeline_stats_mask;
1742 };
1743
1744 struct radv_semaphore {
1745 /* use a winsys sem for non-exportable */
1746 struct radeon_winsys_sem *sem;
1747 uint32_t syncobj;
1748 uint32_t temp_syncobj;
1749 };
1750
1751 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1752 VkPipelineBindPoint bind_point,
1753 struct radv_descriptor_set *set,
1754 unsigned idx);
1755
1756 void
1757 radv_update_descriptor_sets(struct radv_device *device,
1758 struct radv_cmd_buffer *cmd_buffer,
1759 VkDescriptorSet overrideSet,
1760 uint32_t descriptorWriteCount,
1761 const VkWriteDescriptorSet *pDescriptorWrites,
1762 uint32_t descriptorCopyCount,
1763 const VkCopyDescriptorSet *pDescriptorCopies);
1764
1765 void
1766 radv_update_descriptor_set_with_template(struct radv_device *device,
1767 struct radv_cmd_buffer *cmd_buffer,
1768 struct radv_descriptor_set *set,
1769 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1770 const void *pData);
1771
1772 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1773 VkPipelineBindPoint pipelineBindPoint,
1774 VkPipelineLayout _layout,
1775 uint32_t set,
1776 uint32_t descriptorWriteCount,
1777 const VkWriteDescriptorSet *pDescriptorWrites);
1778
1779 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1780 struct radv_image *image, uint32_t value);
1781
1782 struct radv_fence {
1783 struct radeon_winsys_fence *fence;
1784 bool submitted;
1785 bool signalled;
1786
1787 uint32_t syncobj;
1788 uint32_t temp_syncobj;
1789 };
1790
1791 /* radv_nir_to_llvm.c */
1792 struct radv_shader_variant_info;
1793 struct radv_nir_compiler_options;
1794
1795 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1796 struct nir_shader *geom_shader,
1797 struct ac_shader_binary *binary,
1798 struct ac_shader_config *config,
1799 struct radv_shader_variant_info *shader_info,
1800 const struct radv_nir_compiler_options *option);
1801
1802 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1803 struct ac_shader_binary *binary,
1804 struct ac_shader_config *config,
1805 struct radv_shader_variant_info *shader_info,
1806 struct nir_shader *const *nir,
1807 int nir_count,
1808 const struct radv_nir_compiler_options *options);
1809
1810 /* radv_shader_info.h */
1811 struct radv_shader_info;
1812
1813 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1814 const struct radv_nir_compiler_options *options,
1815 struct radv_shader_info *info);
1816
1817 struct radeon_winsys_sem;
1818
1819 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1820 \
1821 static inline struct __radv_type * \
1822 __radv_type ## _from_handle(__VkType _handle) \
1823 { \
1824 return (struct __radv_type *) _handle; \
1825 } \
1826 \
1827 static inline __VkType \
1828 __radv_type ## _to_handle(struct __radv_type *_obj) \
1829 { \
1830 return (__VkType) _obj; \
1831 }
1832
1833 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1834 \
1835 static inline struct __radv_type * \
1836 __radv_type ## _from_handle(__VkType _handle) \
1837 { \
1838 return (struct __radv_type *)(uintptr_t) _handle; \
1839 } \
1840 \
1841 static inline __VkType \
1842 __radv_type ## _to_handle(struct __radv_type *_obj) \
1843 { \
1844 return (__VkType)(uintptr_t) _obj; \
1845 }
1846
1847 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1848 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1849
1850 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1851 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1852 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1853 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1854 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1855
1856 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1857 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1858 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1859 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1860 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1861 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1862 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1863 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1864 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1865 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1866 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1867 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1868 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1869 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1870 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1871 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1872 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1873 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1874 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1875 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1876 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1877
1878 #endif /* RADV_PRIVATE_H */