src/amd/vulkan/radv_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_PRIVATE_H
  29 #define RADV_PRIVATE_H
  30
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <stdbool.h>
  34 #include <pthread.h>
  35 #include <assert.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <valgrind.h>
  40 #include <memcheck.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x)
  44 #endif
  45
  46 #include "c11/threads.h"
  47 #include <amdgpu.h>
  48 #include "compiler/shader_enums.h"
  49 #include "util/macros.h"
  50 #include "util/list.h"
  51 #include "util/xmlconfig.h"
  52 #include "main/macros.h"
  53 #include "vk_alloc.h"
  54 #include "vk_debug_report.h"
  55
  56 #include "radv_radeon_winsys.h"
  57 #include "ac_binary.h"
  58 #include "ac_nir_to_llvm.h"
  59 #include "ac_gpu_info.h"
  60 #include "ac_surface.h"
  61 #include "ac_llvm_build.h"
  62 #include "ac_llvm_util.h"
  63 #include "radv_constants.h"
  64 #include "radv_descriptor_set.h"
  65 #include "radv_extensions.h"
  66 #include "sid.h"
  67
  68 #include <llvm-c/TargetMachine.h>
  69
  70 /* Pre-declarations needed for WSI entrypoints */
  71 struct wl_surface;
  72 struct wl_display;
  73 typedef struct xcb_connection_t xcb_connection_t;
  74 typedef uint32_t xcb_visualid_t;
  75 typedef uint32_t xcb_window_t;
  76
  77 #include <vulkan/vulkan.h>
  78 #include <vulkan/vulkan_intel.h>
  79 #include <vulkan/vk_icd.h>
  80 #include <vulkan/vk_android_native_buffer.h>
  81
  82 #include "radv_entrypoints.h"
  83
  84 #include "wsi_common.h"
  85 #include "wsi_common_display.h"
  86
  87 struct gfx10_format {
  88     unsigned img_format:9;
  89
  90     /* Various formats are only supported with workarounds for vertex fetch,
  91      * and some 32_32_32 formats are supported natively, but only for buffers
  92      * (possibly with some image support, actually, but no filtering). */
  93     bool buffers_only:1;
  94 };
  95
  96 #include "gfx10_format_table.h"
  97
  98 enum radv_mem_heap {
  99         RADV_MEM_HEAP_VRAM,
 100         RADV_MEM_HEAP_VRAM_CPU_ACCESS,
 101         RADV_MEM_HEAP_GTT,
 102         RADV_MEM_HEAP_COUNT
 103 };
 104
 105 enum radv_mem_type {
 106         RADV_MEM_TYPE_VRAM,
 107         RADV_MEM_TYPE_GTT_WRITE_COMBINE,
 108         RADV_MEM_TYPE_VRAM_CPU_ACCESS,
 109         RADV_MEM_TYPE_GTT_CACHED,
 110         RADV_MEM_TYPE_COUNT
 111 };
 112
 113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 114
 115 static inline uint32_t
 116 align_u32(uint32_t v, uint32_t a)
 117 {
 118         assert(a != 0 && a == (a & -a));
 119         return (v + a - 1) & ~(a - 1);
 120 }
 121
 122 static inline uint32_t
 123 align_u32_npot(uint32_t v, uint32_t a)
 124 {
 125         return (v + a - 1) / a * a;
 126 }
 127
 128 static inline uint64_t
 129 align_u64(uint64_t v, uint64_t a)
 130 {
 131         assert(a != 0 && a == (a & -a));
 132         return (v + a - 1) & ~(a - 1);
 133 }
 134
 135 static inline int32_t
 136 align_i32(int32_t v, int32_t a)
 137 {
 138         assert(a != 0 && a == (a & -a));
 139         return (v + a - 1) & ~(a - 1);
 140 }
 141
 142 /** Alignment must be a power of 2. */
 143 static inline bool
 144 radv_is_aligned(uintmax_t n, uintmax_t a)
 145 {
 146         assert(a == (a & -a));
 147         return (n & (a - 1)) == 0;
 148 }
 149
 150 static inline uint32_t
 151 round_up_u32(uint32_t v, uint32_t a)
 152 {
 153         return (v + a - 1) / a;
 154 }
 155
 156 static inline uint64_t
 157 round_up_u64(uint64_t v, uint64_t a)
 158 {
 159         return (v + a - 1) / a;
 160 }
 161
 162 static inline uint32_t
 163 radv_minify(uint32_t n, uint32_t levels)
 164 {
 165         if (unlikely(n == 0))
 166                 return 0;
 167         else
 168                 return MAX2(n >> levels, 1);
 169 }
 170 static inline float
 171 radv_clamp_f(float f, float min, float max)
 172 {
 173         assert(min < max);
 174
 175         if (f > max)
 176                 return max;
 177         else if (f < min)
 178                 return min;
 179         else
 180                 return f;
 181 }
 182
 183 static inline bool
 184 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
 185 {
 186         if (*inout_mask & clear_mask) {
 187                 *inout_mask &= ~clear_mask;
 188                 return true;
 189         } else {
 190                 return false;
 191         }
 192 }
 193
 194 #define for_each_bit(b, dword)                          \
 195         for (uint32_t __dword = (dword);                \
 196              (b) = __builtin_ffs(__dword) - 1, __dword; \
 197              __dword &= ~(1 << (b)))
 198
 199 #define typed_memcpy(dest, src, count) ({                               \
 200                         STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
 201                         memcpy((dest), (src), (count) * sizeof(*(src))); \
 202                 })
 203
 204 /* Whenever we generate an error, pass it through this function. Useful for
 205  * debugging, where we can break on it. Only call at error site, not when
 206  * propagating errors. Might be useful to plug in a stack trace here.
 207  */
 208
 209 struct radv_image_view;
 210 struct radv_instance;
 211
 212 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
 213
 214 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
 215 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
 216
 217 void __radv_finishme(const char *file, int line, const char *format, ...)
 218         radv_printflike(3, 4);
 219 void radv_loge(const char *format, ...) radv_printflike(1, 2);
 220 void radv_loge_v(const char *format, va_list va);
 221 void radv_logi(const char *format, ...) radv_printflike(1, 2);
 222 void radv_logi_v(const char *format, va_list va);
 223
 224 /**
 225  * Print a FINISHME message, including its source location.
 226  */
 227 #define radv_finishme(format, ...)                                      \
 228         do { \
 229                 static bool reported = false; \
 230                 if (!reported) { \
 231                         __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
 232                         reported = true; \
 233                 } \
 234         } while (0)
 235
 236 /* A non-fatal assert.  Useful for debugging. */
 237 #ifdef DEBUG
 238 #define radv_assert(x) ({                                               \
 239                         if (unlikely(!(x)))                             \
 240                                 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
 241                 })
 242 #else
 243 #define radv_assert(x)
 244 #endif
 245
 246 #define stub_return(v)                                  \
 247         do {                                            \
 248                 radv_finishme("stub %s", __func__);     \
 249                 return (v);                             \
 250         } while (0)
 251
 252 #define stub()                                          \
 253         do {                                            \
 254                 radv_finishme("stub %s", __func__);     \
 255                 return;                                 \
 256         } while (0)
 257
 258 void *radv_lookup_entrypoint_unchecked(const char *name);
 259 void *radv_lookup_entrypoint_checked(const char *name,
 260                                     uint32_t core_version,
 261                                     const struct radv_instance_extension_table *instance,
 262                                     const struct radv_device_extension_table *device);
 263 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
 264                                                      uint32_t core_version,
 265                                                      const struct radv_instance_extension_table *instance);
 266
 267 struct radv_physical_device {
 268         VK_LOADER_DATA                              _loader_data;
 269
 270         struct radv_instance *                       instance;
 271
 272         struct radeon_winsys *ws;
 273         struct radeon_info rad_info;
 274         char                                        name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
 275         uint8_t                                     driver_uuid[VK_UUID_SIZE];
 276         uint8_t                                     device_uuid[VK_UUID_SIZE];
 277         uint8_t                                     cache_uuid[VK_UUID_SIZE];
 278
 279         int local_fd;
 280         int master_fd;
 281         struct wsi_device                       wsi_device;
 282
 283         bool has_rbplus; /* if RB+ register exist */
 284         bool rbplus_allowed; /* if RB+ is allowed */
 285         bool has_clear_state;
 286         bool cpdma_prefetch_writes_memory;
 287         bool has_scissor_bug;
 288         bool has_tc_compat_zrange_bug;
 289
 290         bool has_out_of_order_rast;
 291         bool out_of_order_rast_allowed;
 292
 293         /* Whether DCC should be enabled for MSAA textures. */
 294         bool dcc_msaa_allowed;
 295
 296         /* Whether LOAD_CONTEXT_REG packets are supported. */
 297         bool has_load_ctx_reg_pkt;
 298
 299         /* Whether to enable the AMD_shader_ballot extension */
 300         bool use_shader_ballot;
 301
 302         /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
 303         bool has_dcc_constant_encode;
 304
 305         /* Number of threads per wave. */
 306         uint8_t ps_wave_size;
 307         uint8_t cs_wave_size;
 308         uint8_t ge_wave_size;
 309
 310         /* This is the drivers on-disk cache used as a fallback as opposed to
 311          * the pipeline cache defined by apps.
 312          */
 313         struct disk_cache *                          disk_cache;
 314
 315         VkPhysicalDeviceMemoryProperties memory_properties;
 316         enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
 317
 318         drmPciBusInfo bus_info;
 319
 320         struct radv_device_extension_table supported_extensions;
 321 };
 322
 323 struct radv_instance {
 324         VK_LOADER_DATA                              _loader_data;
 325
 326         VkAllocationCallbacks                       alloc;
 327
 328         uint32_t                                    apiVersion;
 329         int                                         physicalDeviceCount;
 330         struct radv_physical_device                 physicalDevices[RADV_MAX_DRM_DEVICES];
 331
 332         uint64_t debug_flags;
 333         uint64_t perftest_flags;
 334
 335         struct vk_debug_report_instance             debug_report_callbacks;
 336
 337         struct radv_instance_extension_table enabled_extensions;
 338
 339         struct driOptionCache dri_options;
 340         struct driOptionCache available_dri_options;
 341 };
 342
 343 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
 344 void radv_finish_wsi(struct radv_physical_device *physical_device);
 345
 346 bool radv_instance_extension_supported(const char *name);
 347 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
 348 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
 349                                               const char *name);
 350
 351 struct cache_entry;
 352
 353 struct radv_pipeline_cache {
 354         struct radv_device *                          device;
 355         pthread_mutex_t                              mutex;
 356
 357         uint32_t                                     total_size;
 358         uint32_t                                     table_size;
 359         uint32_t                                     kernel_count;
 360         struct cache_entry **                        hash_table;
 361         bool                                         modified;
 362
 363         VkAllocationCallbacks                        alloc;
 364 };
 365
 366 struct radv_pipeline_key {
 367         uint32_t instance_rate_inputs;
 368         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
 369         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
 370         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
 371         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
 372         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
 373         uint64_t vertex_alpha_adjust;
 374         uint32_t vertex_post_shuffle;
 375         unsigned tess_input_vertices;
 376         uint32_t col_format;
 377         uint32_t is_int8;
 378         uint32_t is_int10;
 379         uint8_t log2_ps_iter_samples;
 380         uint8_t num_samples;
 381         uint32_t has_multiview_view_index : 1;
 382         uint32_t optimisations_disabled : 1;
 383 };
 384
 385 struct radv_shader_binary;
 386 struct radv_shader_variant;
 387
 388 void
 389 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 390                          struct radv_device *device);
 391 void
 392 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
 393 bool
 394 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 395                          const void *data, size_t size);
 396
 397 bool
 398 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
 399                                                 struct radv_pipeline_cache *cache,
 400                                                 const unsigned char *sha1,
 401                                                 struct radv_shader_variant **variants,
 402                                                 bool *found_in_application_cache);
 403
 404 void
 405 radv_pipeline_cache_insert_shaders(struct radv_device *device,
 406                                    struct radv_pipeline_cache *cache,
 407                                    const unsigned char *sha1,
 408                                    struct radv_shader_variant **variants,
 409                                    struct radv_shader_binary *const *binaries);
 410
 411 enum radv_blit_ds_layout {
 412         RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
 413         RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
 414         RADV_BLIT_DS_LAYOUT_COUNT,
 415 };
 416
 417 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
 418 {
 419         return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
 420 }
 421
 422 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
 423 {
 424         return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
 425 }
 426
 427 enum radv_meta_dst_layout {
 428         RADV_META_DST_LAYOUT_GENERAL,
 429         RADV_META_DST_LAYOUT_OPTIMAL,
 430         RADV_META_DST_LAYOUT_COUNT,
 431 };
 432
 433 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
 434 {
 435         return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
 436 }
 437
 438 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
 439 {
 440         return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
 441 }
 442
 443 struct radv_meta_state {
 444         VkAllocationCallbacks alloc;
 445
 446         struct radv_pipeline_cache cache;
 447
 448         /*
 449          * For on-demand pipeline creation, makes sure that
 450          * only one thread tries to build a pipeline at the same time.
 451          */
 452         mtx_t mtx;
 453
 454         /**
 455          * Use array element `i` for images with `2^i` samples.
 456          */
 457         struct {
 458                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 459                 VkPipeline color_pipelines[NUM_META_FS_KEYS];
 460
 461                 VkRenderPass depthstencil_rp;
 462                 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 463                 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 464                 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 465         } clear[1 + MAX_SAMPLES_LOG2];
 466
 467         VkPipelineLayout                          clear_color_p_layout;
 468         VkPipelineLayout                          clear_depth_p_layout;
 469
 470         /* Optimized compute fast HTILE clear for stencil or depth only. */
 471         VkPipeline clear_htile_mask_pipeline;
 472         VkPipelineLayout clear_htile_mask_p_layout;
 473         VkDescriptorSetLayout clear_htile_mask_ds_layout;
 474
 475         struct {
 476                 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 477
 478                 /** Pipeline that blits from a 1D image. */
 479                 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
 480
 481                 /** Pipeline that blits from a 2D image. */
 482                 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
 483
 484                 /** Pipeline that blits from a 3D image. */
 485                 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 486
 487                 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 488                 VkPipeline depth_only_1d_pipeline;
 489                 VkPipeline depth_only_2d_pipeline;
 490                 VkPipeline depth_only_3d_pipeline;
 491
 492                 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 493                 VkPipeline stencil_only_1d_pipeline;
 494                 VkPipeline stencil_only_2d_pipeline;
 495                 VkPipeline stencil_only_3d_pipeline;
 496                 VkPipelineLayout                          pipeline_layout;
 497                 VkDescriptorSetLayout                     ds_layout;
 498         } blit;
 499
 500         struct {
 501                 VkPipelineLayout p_layouts[5];
 502                 VkDescriptorSetLayout ds_layouts[5];
 503                 VkPipeline pipelines[5][NUM_META_FS_KEYS];
 504
 505                 VkPipeline depth_only_pipeline[5];
 506
 507                 VkPipeline stencil_only_pipeline[5];
 508         } blit2d[1 + MAX_SAMPLES_LOG2];
 509
 510         VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 511         VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 512         VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 513
 514         struct {
 515                 VkPipelineLayout                          img_p_layout;
 516                 VkDescriptorSetLayout                     img_ds_layout;
 517                 VkPipeline pipeline;
 518                 VkPipeline pipeline_3d;
 519         } itob;
 520         struct {
 521                 VkPipelineLayout                          img_p_layout;
 522                 VkDescriptorSetLayout                     img_ds_layout;
 523                 VkPipeline pipeline;
 524                 VkPipeline pipeline_3d;
 525         } btoi;
 526         struct {
 527                 VkPipelineLayout                          img_p_layout;
 528                 VkDescriptorSetLayout                     img_ds_layout;
 529                 VkPipeline pipeline;
 530         } btoi_r32g32b32;
 531         struct {
 532                 VkPipelineLayout                          img_p_layout;
 533                 VkDescriptorSetLayout                     img_ds_layout;
 534                 VkPipeline pipeline;
 535                 VkPipeline pipeline_3d;
 536         } itoi;
 537         struct {
 538                 VkPipelineLayout                          img_p_layout;
 539                 VkDescriptorSetLayout                     img_ds_layout;
 540                 VkPipeline pipeline;
 541         } itoi_r32g32b32;
 542         struct {
 543                 VkPipelineLayout                          img_p_layout;
 544                 VkDescriptorSetLayout                     img_ds_layout;
 545                 VkPipeline pipeline;
 546                 VkPipeline pipeline_3d;
 547         } cleari;
 548         struct {
 549                 VkPipelineLayout                          img_p_layout;
 550                 VkDescriptorSetLayout                     img_ds_layout;
 551                 VkPipeline pipeline;
 552         } cleari_r32g32b32;
 553
 554         struct {
 555                 VkPipelineLayout                          p_layout;
 556                 VkPipeline                                pipeline[NUM_META_FS_KEYS];
 557                 VkRenderPass                              pass[NUM_META_FS_KEYS];
 558         } resolve;
 559
 560         struct {
 561                 VkDescriptorSetLayout                     ds_layout;
 562                 VkPipelineLayout                          p_layout;
 563                 struct {
 564                         VkPipeline                                pipeline;
 565                         VkPipeline                                i_pipeline;
 566                         VkPipeline                                srgb_pipeline;
 567                 } rc[MAX_SAMPLES_LOG2];
 568
 569                 VkPipeline depth_zero_pipeline;
 570                 struct {
 571                         VkPipeline average_pipeline;
 572                         VkPipeline max_pipeline;
 573                         VkPipeline min_pipeline;
 574                 } depth[MAX_SAMPLES_LOG2];
 575
 576                 VkPipeline stencil_zero_pipeline;
 577                 struct {
 578                         VkPipeline max_pipeline;
 579                         VkPipeline min_pipeline;
 580                 } stencil[MAX_SAMPLES_LOG2];
 581         } resolve_compute;
 582
 583         struct {
 584                 VkDescriptorSetLayout                     ds_layout;
 585                 VkPipelineLayout                          p_layout;
 586
 587                 struct {
 588                         VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 589                         VkPipeline   pipeline[NUM_META_FS_KEYS];
 590                 } rc[MAX_SAMPLES_LOG2];
 591
 592                 VkRenderPass depth_render_pass;
 593                 VkPipeline depth_zero_pipeline;
 594                 struct {
 595                         VkPipeline average_pipeline;
 596                         VkPipeline max_pipeline;
 597                         VkPipeline min_pipeline;
 598                 } depth[MAX_SAMPLES_LOG2];
 599
 600                 VkRenderPass stencil_render_pass;
 601                 VkPipeline stencil_zero_pipeline;
 602                 struct {
 603                         VkPipeline max_pipeline;
 604                         VkPipeline min_pipeline;
 605                 } stencil[MAX_SAMPLES_LOG2];
 606         } resolve_fragment;
 607
 608         struct {
 609                 VkPipelineLayout                          p_layout;
 610                 VkPipeline                                decompress_pipeline;
 611                 VkPipeline                                resummarize_pipeline;
 612                 VkRenderPass                              pass;
 613         } depth_decomp[1 + MAX_SAMPLES_LOG2];
 614
 615         struct {
 616                 VkPipelineLayout                          p_layout;
 617                 VkPipeline                                cmask_eliminate_pipeline;
 618                 VkPipeline                                fmask_decompress_pipeline;
 619                 VkPipeline                                dcc_decompress_pipeline;
 620                 VkRenderPass                              pass;
 621
 622                 VkDescriptorSetLayout                     dcc_decompress_compute_ds_layout;
 623                 VkPipelineLayout                          dcc_decompress_compute_p_layout;
 624                 VkPipeline                                dcc_decompress_compute_pipeline;
 625         } fast_clear_flush;
 626
 627         struct {
 628                 VkPipelineLayout fill_p_layout;
 629                 VkPipelineLayout copy_p_layout;
 630                 VkDescriptorSetLayout fill_ds_layout;
 631                 VkDescriptorSetLayout copy_ds_layout;
 632                 VkPipeline fill_pipeline;
 633                 VkPipeline copy_pipeline;
 634         } buffer;
 635
 636         struct {
 637                 VkDescriptorSetLayout ds_layout;
 638                 VkPipelineLayout p_layout;
 639                 VkPipeline occlusion_query_pipeline;
 640                 VkPipeline pipeline_statistics_query_pipeline;
 641                 VkPipeline tfb_query_pipeline;
 642         } query;
 643
 644         struct {
 645                 VkDescriptorSetLayout ds_layout;
 646                 VkPipelineLayout p_layout;
 647                 VkPipeline pipeline[MAX_SAMPLES_LOG2];
 648         } fmask_expand;
 649 };
 650
 651 /* queue types */
 652 #define RADV_QUEUE_GENERAL 0
 653 #define RADV_QUEUE_COMPUTE 1
 654 #define RADV_QUEUE_TRANSFER 2
 655
 656 #define RADV_MAX_QUEUE_FAMILIES 3
 657
 658 enum ring_type radv_queue_family_to_ring(int f);
 659
 660 struct radv_queue {
 661         VK_LOADER_DATA                              _loader_data;
 662         struct radv_device *                         device;
 663         struct radeon_winsys_ctx                    *hw_ctx;
 664         enum radeon_ctx_priority                     priority;
 665         uint32_t queue_family_index;
 666         int queue_idx;
 667         VkDeviceQueueCreateFlags flags;
 668
 669         uint32_t scratch_size;
 670         uint32_t compute_scratch_size;
 671         uint32_t esgs_ring_size;
 672         uint32_t gsvs_ring_size;
 673         bool has_tess_rings;
 674         bool has_sample_positions;
 675
 676         struct radeon_winsys_bo *scratch_bo;
 677         struct radeon_winsys_bo *descriptor_bo;
 678         struct radeon_winsys_bo *compute_scratch_bo;
 679         struct radeon_winsys_bo *esgs_ring_bo;
 680         struct radeon_winsys_bo *gsvs_ring_bo;
 681         struct radeon_winsys_bo *tess_rings_bo;
 682         struct radeon_cmdbuf *initial_preamble_cs;
 683         struct radeon_cmdbuf *initial_full_flush_preamble_cs;
 684         struct radeon_cmdbuf *continue_preamble_cs;
 685 };
 686
 687 struct radv_bo_list {
 688         struct radv_winsys_bo_list list;
 689         unsigned capacity;
 690         pthread_mutex_t mutex;
 691 };
 692
 693 struct radv_device {
 694         VK_LOADER_DATA                              _loader_data;
 695
 696         VkAllocationCallbacks                       alloc;
 697
 698         struct radv_instance *                       instance;
 699         struct radeon_winsys *ws;
 700
 701         struct radv_meta_state                       meta_state;
 702
 703         struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
 704         int queue_count[RADV_MAX_QUEUE_FAMILIES];
 705         struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 706
 707         bool always_use_syncobj;
 708         bool has_distributed_tess;
 709         bool pbb_allowed;
 710         bool dfsm_allowed;
 711         uint32_t tess_offchip_block_dw_size;
 712         uint32_t scratch_waves;
 713         uint32_t dispatch_initiator;
 714
 715         uint32_t gs_table_depth;
 716
 717         /* MSAA sample locations.
 718          * The first index is the sample index.
 719          * The second index is the coordinate: X, Y. */
 720         float sample_locations_1x[1][2];
 721         float sample_locations_2x[2][2];
 722         float sample_locations_4x[4][2];
 723         float sample_locations_8x[8][2];
 724
 725         /* GFX7 and later */
 726         uint32_t gfx_init_size_dw;
 727         struct radeon_winsys_bo                      *gfx_init;
 728
 729         struct radeon_winsys_bo                      *trace_bo;
 730         uint32_t                                     *trace_id_ptr;
 731
 732         /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
 733         bool                                         keep_shader_info;
 734
 735         struct radv_physical_device                  *physical_device;
 736
 737         /* Backup in-memory cache to be used if the app doesn't provide one */
 738         struct radv_pipeline_cache *                mem_cache;
 739
 740         /*
 741          * use different counters so MSAA MRTs get consecutive surface indices,
 742          * even if MASK is allocated in between.
 743          */
 744         uint32_t image_mrt_offset_counter;
 745         uint32_t fmask_mrt_offset_counter;
 746         struct list_head shader_slabs;
 747         mtx_t shader_slab_mutex;
 748
 749         /* For detecting VM faults reported by dmesg. */
 750         uint64_t dmesg_timestamp;
 751
 752         struct radv_device_extension_table enabled_extensions;
 753
 754         /* Whether the app has enabled the robustBufferAccess feature. */
 755         bool robust_buffer_access;
 756
 757         /* Whether the driver uses a global BO list. */
 758         bool use_global_bo_list;
 759
 760         struct radv_bo_list bo_list;
 761
 762         /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
 763         int force_aniso;
 764 };
 765
 766 struct radv_device_memory {
 767         struct radeon_winsys_bo                      *bo;
 768         /* for dedicated allocations */
 769         struct radv_image                            *image;
 770         struct radv_buffer                           *buffer;
 771         uint32_t                                     type_index;
 772         VkDeviceSize                                 map_size;
 773         void *                                       map;
 774         void *                                       user_ptr;
 775 };
 776
 777
 778 struct radv_descriptor_range {
 779         uint64_t va;
 780         uint32_t size;
 781 };
 782
 783 struct radv_descriptor_set {
 784         const struct radv_descriptor_set_layout *layout;
 785         uint32_t size;
 786
 787         struct radeon_winsys_bo *bo;
 788         uint64_t va;
 789         uint32_t *mapped_ptr;
 790         struct radv_descriptor_range *dynamic_descriptors;
 791
 792         struct radeon_winsys_bo *descriptors[0];
 793 };
 794
 795 struct radv_push_descriptor_set
 796 {
 797         struct radv_descriptor_set set;
 798         uint32_t capacity;
 799 };
 800
 801 struct radv_descriptor_pool_entry {
 802         uint32_t offset;
 803         uint32_t size;
 804         struct radv_descriptor_set *set;
 805 };
 806
 807 struct radv_descriptor_pool {
 808         struct radeon_winsys_bo *bo;
 809         uint8_t *mapped_ptr;
 810         uint64_t current_offset;
 811         uint64_t size;
 812
 813         uint8_t *host_memory_base;
 814         uint8_t *host_memory_ptr;
 815         uint8_t *host_memory_end;
 816
 817         uint32_t entry_count;
 818         uint32_t max_entry_count;
 819         struct radv_descriptor_pool_entry entries[0];
 820 };
 821
 822 struct radv_descriptor_update_template_entry {
 823         VkDescriptorType descriptor_type;
 824
 825         /* The number of descriptors to update */
 826         uint32_t descriptor_count;
 827
 828         /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
 829         uint32_t dst_offset;
 830
 831         /* In dwords. Not valid/used for dynamic descriptors */
 832         uint32_t dst_stride;
 833
 834         uint32_t buffer_offset;
 835
 836         /* Only valid for combined image samplers and samplers */
 837         uint8_t has_sampler;
 838         uint8_t sampler_offset;
 839
 840         /* In bytes */
 841         size_t src_offset;
 842         size_t src_stride;
 843
 844         /* For push descriptors */
 845         const uint32_t *immutable_samplers;
 846 };
 847
 848 struct radv_descriptor_update_template {
 849         uint32_t entry_count;
 850         VkPipelineBindPoint bind_point;
 851         struct radv_descriptor_update_template_entry entry[0];
 852 };
 853
 854 struct radv_buffer {
 855         VkDeviceSize                                 size;
 856
 857         VkBufferUsageFlags                           usage;
 858         VkBufferCreateFlags                          flags;
 859
 860         /* Set when bound */
 861         struct radeon_winsys_bo *                      bo;
 862         VkDeviceSize                                 offset;
 863
 864         bool shareable;
 865 };
 866
 867 enum radv_dynamic_state_bits {
 868         RADV_DYNAMIC_VIEWPORT             = 1 << 0,
 869         RADV_DYNAMIC_SCISSOR              = 1 << 1,
 870         RADV_DYNAMIC_LINE_WIDTH           = 1 << 2,
 871         RADV_DYNAMIC_DEPTH_BIAS           = 1 << 3,
 872         RADV_DYNAMIC_BLEND_CONSTANTS      = 1 << 4,
 873         RADV_DYNAMIC_DEPTH_BOUNDS         = 1 << 5,
 874         RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
 875         RADV_DYNAMIC_STENCIL_WRITE_MASK   = 1 << 7,
 876         RADV_DYNAMIC_STENCIL_REFERENCE    = 1 << 8,
 877         RADV_DYNAMIC_DISCARD_RECTANGLE    = 1 << 9,
 878         RADV_DYNAMIC_SAMPLE_LOCATIONS     = 1 << 10,
 879         RADV_DYNAMIC_ALL                  = (1 << 11) - 1,
 880 };
 881
 882 enum radv_cmd_dirty_bits {
 883         /* Keep the dynamic state dirty bits in sync with
 884          * enum radv_dynamic_state_bits */
 885         RADV_CMD_DIRTY_DYNAMIC_VIEWPORT                  = 1 << 0,
 886         RADV_CMD_DIRTY_DYNAMIC_SCISSOR                   = 1 << 1,
 887         RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH                = 1 << 2,
 888         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS                = 1 << 3,
 889         RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS           = 1 << 4,
 890         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS              = 1 << 5,
 891         RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6,
 892         RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7,
 893         RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8,
 894         RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE         = 1 << 9,
 895         RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS          = 1 << 10,
 896         RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 11) - 1,
 897         RADV_CMD_DIRTY_PIPELINE                          = 1 << 11,
 898         RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 12,
 899         RADV_CMD_DIRTY_FRAMEBUFFER                       = 1 << 13,
 900         RADV_CMD_DIRTY_VERTEX_BUFFER                     = 1 << 14,
 901         RADV_CMD_DIRTY_STREAMOUT_BUFFER                  = 1 << 15,
 902 };
 903
 904 enum radv_cmd_flush_bits {
 905         /* Instruction cache. */
 906         RADV_CMD_FLAG_INV_ICACHE                         = 1 << 0,
 907         /* Scalar L1 cache. */
 908         RADV_CMD_FLAG_INV_SCACHE                         = 1 << 1,
 909         /* Vector L1 cache. */
 910         RADV_CMD_FLAG_INV_VCACHE                         = 1 << 2,
 911         /* L2 cache + L2 metadata cache writeback & invalidate.
 912          * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
 913         RADV_CMD_FLAG_INV_L2                             = 1 << 3,
 914         /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
 915          * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
 916          * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
 917         RADV_CMD_FLAG_WB_L2                              = 1 << 4,
 918         /* Framebuffer caches */
 919         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META              = 1 << 5,
 920         RADV_CMD_FLAG_FLUSH_AND_INV_DB_META              = 1 << 6,
 921         RADV_CMD_FLAG_FLUSH_AND_INV_DB                   = 1 << 7,
 922         RADV_CMD_FLAG_FLUSH_AND_INV_CB                   = 1 << 8,
 923         /* Engine synchronization. */
 924         RADV_CMD_FLAG_VS_PARTIAL_FLUSH                   = 1 << 9,
 925         RADV_CMD_FLAG_PS_PARTIAL_FLUSH                   = 1 << 10,
 926         RADV_CMD_FLAG_CS_PARTIAL_FLUSH                   = 1 << 11,
 927         RADV_CMD_FLAG_VGT_FLUSH                          = 1 << 12,
 928         /* Pipeline query controls. */
 929         RADV_CMD_FLAG_START_PIPELINE_STATS               = 1 << 13,
 930         RADV_CMD_FLAG_STOP_PIPELINE_STATS                = 1 << 14,
 931         RADV_CMD_FLAG_VGT_STREAMOUT_SYNC                 = 1 << 15,
 932
 933         RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 934                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
 935                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 936                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
 937 };
 938
 939 struct radv_vertex_binding {
 940         struct radv_buffer *                          buffer;
 941         VkDeviceSize                                 offset;
 942 };
 943
 944 struct radv_streamout_binding {
 945         struct radv_buffer *buffer;
 946         VkDeviceSize offset;
 947         VkDeviceSize size;
 948 };
 949
 950 struct radv_streamout_state {
 951         /* Mask of bound streamout buffers. */
 952         uint8_t enabled_mask;
 953
 954         /* External state that comes from the last vertex stage, it must be
 955          * set explicitely when binding a new graphics pipeline.
 956          */
 957         uint16_t stride_in_dw[MAX_SO_BUFFERS];
 958         uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 959
 960         /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
 961         uint32_t hw_enabled_mask;
 962
 963         /* State of VGT_STRMOUT_(CONFIG|EN) */
 964         bool streamout_enabled;
 965 };
 966
 967 struct radv_viewport_state {
 968         uint32_t                                          count;
 969         VkViewport                                        viewports[MAX_VIEWPORTS];
 970 };
 971
 972 struct radv_scissor_state {
 973         uint32_t                                          count;
 974         VkRect2D                                          scissors[MAX_SCISSORS];
 975 };
 976
 977 struct radv_discard_rectangle_state {
 978         uint32_t                                          count;
 979         VkRect2D                                          rectangles[MAX_DISCARD_RECTANGLES];
 980 };
 981
 982 struct radv_sample_locations_state {
 983         VkSampleCountFlagBits per_pixel;
 984         VkExtent2D grid_size;
 985         uint32_t count;
 986         VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
 987 };
 988
 989 struct radv_dynamic_state {
 990         /**
 991          * Bitmask of (1 << VK_DYNAMIC_STATE_*).
 992          * Defines the set of saved dynamic state.
 993          */
 994         uint32_t mask;
 995
 996         struct radv_viewport_state                        viewport;
 997
 998         struct radv_scissor_state                         scissor;
 999
1000         float                                        line_width;
1001
1002         struct {
1003                 float                                     bias;
1004                 float                                     clamp;
1005                 float                                     slope;
1006         } depth_bias;
1007
1008         float                                        blend_constants[4];
1009
1010         struct {
1011                 float                                     min;
1012                 float                                     max;
1013         } depth_bounds;
1014
1015         struct {
1016                 uint32_t                                  front;
1017                 uint32_t                                  back;
1018         } stencil_compare_mask;
1019
1020         struct {
1021                 uint32_t                                  front;
1022                 uint32_t                                  back;
1023         } stencil_write_mask;
1024
1025         struct {
1026                 uint32_t                                  front;
1027                 uint32_t                                  back;
1028         } stencil_reference;
1029
1030         struct radv_discard_rectangle_state               discard_rectangle;
1031
1032         struct radv_sample_locations_state                sample_location;
1033 };
1034
1035 extern const struct radv_dynamic_state default_dynamic_state;
1036
1037 const char *
1038 radv_get_debug_option_name(int id);
1039
1040 const char *
1041 radv_get_perftest_option_name(int id);
1042
1043 struct radv_color_buffer_info {
1044         uint64_t cb_color_base;
1045         uint64_t cb_color_cmask;
1046         uint64_t cb_color_fmask;
1047         uint64_t cb_dcc_base;
1048         uint32_t cb_color_slice;
1049         uint32_t cb_color_view;
1050         uint32_t cb_color_info;
1051         uint32_t cb_color_attrib;
1052         uint32_t cb_color_attrib2; /* GFX9 and later */
1053         uint32_t cb_color_attrib3; /* GFX10 and later */
1054         uint32_t cb_dcc_control;
1055         uint32_t cb_color_cmask_slice;
1056         uint32_t cb_color_fmask_slice;
1057         union {
1058                 uint32_t cb_color_pitch; // GFX6-GFX8
1059                 uint32_t cb_mrt_epitch; // GFX9+
1060         };
1061 };
1062
1063 struct radv_ds_buffer_info {
1064         uint64_t db_z_read_base;
1065         uint64_t db_stencil_read_base;
1066         uint64_t db_z_write_base;
1067         uint64_t db_stencil_write_base;
1068         uint64_t db_htile_data_base;
1069         uint32_t db_depth_info;
1070         uint32_t db_z_info;
1071         uint32_t db_stencil_info;
1072         uint32_t db_depth_view;
1073         uint32_t db_depth_size;
1074         uint32_t db_depth_slice;
1075         uint32_t db_htile_surface;
1076         uint32_t pa_su_poly_offset_db_fmt_cntl;
1077         uint32_t db_z_info2; /* GFX9 only */
1078         uint32_t db_stencil_info2; /* GFX9 only */
1079         float offset_scale;
1080 };
1081
1082 void
1083 radv_initialise_color_surface(struct radv_device *device,
1084                               struct radv_color_buffer_info *cb,
1085                               struct radv_image_view *iview);
1086 void
1087 radv_initialise_ds_surface(struct radv_device *device,
1088                            struct radv_ds_buffer_info *ds,
1089                            struct radv_image_view *iview);
1090
1091 /**
1092  * Attachment state when recording a renderpass instance.
1093  *
1094  * The clear value is valid only if there exists a pending clear.
1095  */
1096 struct radv_attachment_state {
1097         VkImageAspectFlags                           pending_clear_aspects;
1098         uint32_t                                     cleared_views;
1099         VkClearValue                                 clear_value;
1100         VkImageLayout                                current_layout;
1101         bool                                         current_in_render_loop;
1102         struct radv_sample_locations_state           sample_location;
1103
1104         union {
1105                 struct radv_color_buffer_info cb;
1106                 struct radv_ds_buffer_info ds;
1107         };
1108         struct radv_image_view *iview;
1109 };
1110
1111 struct radv_descriptor_state {
1112         struct radv_descriptor_set *sets[MAX_SETS];
1113         uint32_t dirty;
1114         uint32_t valid;
1115         struct radv_push_descriptor_set push_set;
1116         bool push_dirty;
1117         uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1118 };
1119
1120 struct radv_subpass_sample_locs_state {
1121         uint32_t subpass_idx;
1122         struct radv_sample_locations_state sample_location;
1123 };
1124
1125 struct radv_cmd_state {
1126         /* Vertex descriptors */
1127         uint64_t                                      vb_va;
1128         unsigned                                      vb_size;
1129
1130         bool predicating;
1131         uint32_t                                      dirty;
1132
1133         uint32_t                                      prefetch_L2_mask;
1134
1135         struct radv_pipeline *                        pipeline;
1136         struct radv_pipeline *                        emitted_pipeline;
1137         struct radv_pipeline *                        compute_pipeline;
1138         struct radv_pipeline *                        emitted_compute_pipeline;
1139         struct radv_framebuffer *                     framebuffer;
1140         struct radv_render_pass *                     pass;
1141         const struct radv_subpass *                         subpass;
1142         struct radv_dynamic_state                     dynamic;
1143         struct radv_attachment_state *                attachments;
1144         struct radv_streamout_state                  streamout;
1145         VkRect2D                                     render_area;
1146
1147         uint32_t                                     num_subpass_sample_locs;
1148         struct radv_subpass_sample_locs_state *      subpass_sample_locs;
1149
1150         /* Index buffer */
1151         struct radv_buffer                           *index_buffer;
1152         uint64_t                                     index_offset;
1153         uint32_t                                     index_type;
1154         uint32_t                                     max_index_count;
1155         uint64_t                                     index_va;
1156         int32_t                                      last_index_type;
1157
1158         int32_t                                      last_primitive_reset_en;
1159         uint32_t                                     last_primitive_reset_index;
1160         enum radv_cmd_flush_bits                     flush_bits;
1161         unsigned                                     active_occlusion_queries;
1162         bool                                         perfect_occlusion_queries_enabled;
1163         unsigned                                     active_pipeline_queries;
1164         float                                        offset_scale;
1165         uint32_t                                      trace_id;
1166         uint32_t                                      last_ia_multi_vgt_param;
1167
1168         uint32_t last_num_instances;
1169         uint32_t last_first_instance;
1170         uint32_t last_vertex_offset;
1171
1172         /* Whether CP DMA is busy/idle. */
1173         bool dma_is_busy;
1174
1175         /* Conditional rendering info. */
1176         int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1177         uint64_t predication_va;
1178
1179         bool context_roll_without_scissor_emitted;
1180 };
1181
1182 struct radv_cmd_pool {
1183         VkAllocationCallbacks                        alloc;
1184         struct list_head                             cmd_buffers;
1185         struct list_head                             free_cmd_buffers;
1186         uint32_t queue_family_index;
1187 };
1188
1189 struct radv_cmd_buffer_upload {
1190         uint8_t *map;
1191         unsigned offset;
1192         uint64_t size;
1193         struct radeon_winsys_bo *upload_bo;
1194         struct list_head list;
1195 };
1196
1197 enum radv_cmd_buffer_status {
1198         RADV_CMD_BUFFER_STATUS_INVALID,
1199         RADV_CMD_BUFFER_STATUS_INITIAL,
1200         RADV_CMD_BUFFER_STATUS_RECORDING,
1201         RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1202         RADV_CMD_BUFFER_STATUS_PENDING,
1203 };
1204
1205 struct radv_cmd_buffer {
1206         VK_LOADER_DATA                               _loader_data;
1207
1208         struct radv_device *                          device;
1209
1210         struct radv_cmd_pool *                        pool;
1211         struct list_head                             pool_link;
1212
1213         VkCommandBufferUsageFlags                    usage_flags;
1214         VkCommandBufferLevel                         level;
1215         enum radv_cmd_buffer_status status;
1216         struct radeon_cmdbuf *cs;
1217         struct radv_cmd_state state;
1218         struct radv_vertex_binding                   vertex_bindings[MAX_VBS];
1219         struct radv_streamout_binding                streamout_bindings[MAX_SO_BUFFERS];
1220         uint32_t queue_family_index;
1221
1222         uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1223         VkShaderStageFlags push_constant_stages;
1224         struct radv_descriptor_set meta_push_descriptors;
1225
1226         struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1227
1228         struct radv_cmd_buffer_upload upload;
1229
1230         uint32_t scratch_size_needed;
1231         uint32_t compute_scratch_size_needed;
1232         uint32_t esgs_ring_size_needed;
1233         uint32_t gsvs_ring_size_needed;
1234         bool tess_rings_needed;
1235         bool sample_positions_needed;
1236
1237         VkResult record_result;
1238
1239         uint64_t gfx9_fence_va;
1240         uint32_t gfx9_fence_idx;
1241         uint64_t gfx9_eop_bug_va;
1242
1243         /**
1244          * Whether a query pool has been resetted and we have to flush caches.
1245          */
1246         bool pending_reset_query;
1247
1248         /**
1249          * Bitmask of pending active query flushes.
1250          */
1251         enum radv_cmd_flush_bits active_query_flush_bits;
1252 };
1253
1254 struct radv_image;
1255 struct radv_image_view;
1256
1257 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1258
1259 void si_emit_graphics(struct radv_physical_device *physical_device,
1260                       struct radeon_cmdbuf *cs);
1261 void si_emit_compute(struct radv_physical_device *physical_device,
1262                       struct radeon_cmdbuf *cs);
1263
1264 void cik_create_gfx_config(struct radv_device *device);
1265
1266 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1267                        int count, const VkViewport *viewports);
1268 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1269                        int count, const VkRect2D *scissors,
1270                        const VkViewport *viewports, bool can_use_guardband);
1271 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1272                                    bool instanced_draw, bool indirect_draw,
1273                                    bool count_from_stream_output,
1274                                    uint32_t draw_vertex_count);
1275 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1276                                 enum chip_class chip_class,
1277                                 bool is_mec,
1278                                 unsigned event, unsigned event_flags,
1279                                 unsigned dst_sel, unsigned data_sel,
1280                                 uint64_t va,
1281                                 uint32_t new_fence,
1282                                 uint64_t gfx9_eop_bug_va);
1283
1284 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1285                       uint32_t ref, uint32_t mask);
1286 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1287                             enum chip_class chip_class,
1288                             uint32_t *fence_ptr, uint64_t va,
1289                             bool is_mec,
1290                             enum radv_cmd_flush_bits flush_bits,
1291                             uint64_t gfx9_eop_bug_va);
1292 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1293 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1294                                    bool inverted, uint64_t va);
1295 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1296                            uint64_t src_va, uint64_t dest_va,
1297                            uint64_t size);
1298 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1299                         unsigned size);
1300 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1301                             uint64_t size, unsigned value);
1302 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1303
1304 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1305 bool
1306 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1307                              unsigned size,
1308                              unsigned alignment,
1309                              unsigned *out_offset,
1310                              void **ptr);
1311 void
1312 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1313                             const struct radv_subpass *subpass);
1314 bool
1315 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1316                             unsigned size, unsigned alignmnet,
1317                             const void *data, unsigned *out_offset);
1318
1319 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1320 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1321 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1322 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1323                                            VkImageAspectFlags aspects,
1324                                            VkResolveModeFlagBitsKHR resolve_mode);
1325 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1326 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1327                                            VkImageAspectFlags aspects,
1328                                            VkResolveModeFlagBitsKHR resolve_mode);
1329 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1330 unsigned radv_get_default_max_sample_dist(int log_samples);
1331 void radv_device_init_msaa(struct radv_device *device);
1332
1333 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1334                                    struct radv_image *image,
1335                                    VkClearDepthStencilValue ds_clear_value,
1336                                    VkImageAspectFlags aspects);
1337
1338 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1339                                       const struct radv_image_view *iview,
1340                                       int cb_idx,
1341                                       uint32_t color_values[2]);
1342
1343 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1344                               struct radv_image *image,
1345                               const VkImageSubresourceRange *range, bool value);
1346
1347 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1348                               struct radv_image *image,
1349                               const VkImageSubresourceRange *range, bool value);
1350
1351 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1352                           struct radeon_winsys_bo *bo,
1353                           uint64_t offset, uint64_t size, uint32_t value);
1354 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1355 bool radv_get_memory_fd(struct radv_device *device,
1356                         struct radv_device_memory *memory,
1357                         int *pFD);
1358
1359 static inline void
1360 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1361                               unsigned sh_offset, unsigned pointer_count,
1362                               bool use_32bit_pointers)
1363 {
1364         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1365         radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1366 }
1367
1368 static inline void
1369 radv_emit_shader_pointer_body(struct radv_device *device,
1370                               struct radeon_cmdbuf *cs,
1371                               uint64_t va, bool use_32bit_pointers)
1372 {
1373         radeon_emit(cs, va);
1374
1375         if (use_32bit_pointers) {
1376                 assert(va == 0 ||
1377                        (va >> 32) == device->physical_device->rad_info.address32_hi);
1378         } else {
1379                 radeon_emit(cs, va >> 32);
1380         }
1381 }
1382
1383 static inline void
1384 radv_emit_shader_pointer(struct radv_device *device,
1385                          struct radeon_cmdbuf *cs,
1386                          uint32_t sh_offset, uint64_t va, bool global)
1387 {
1388         bool use_32bit_pointers = !global;
1389
1390         radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1391         radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1392 }
1393
1394 static inline struct radv_descriptor_state *
1395 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1396                            VkPipelineBindPoint bind_point)
1397 {
1398         assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1399                bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1400         return &cmd_buffer->descriptors[bind_point];
1401 }
1402
1403 /*
1404  * Takes x,y,z as exact numbers of invocations, instead of blocks.
1405  *
1406  * Limitations: Can't call normal dispatch functions without binding or rebinding
1407  *              the compute pipeline.
1408  */
1409 void radv_unaligned_dispatch(
1410         struct radv_cmd_buffer                      *cmd_buffer,
1411         uint32_t                                    x,
1412         uint32_t                                    y,
1413         uint32_t                                    z);
1414
1415 struct radv_event {
1416         struct radeon_winsys_bo *bo;
1417         uint64_t *map;
1418 };
1419
1420 struct radv_shader_module;
1421
1422 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1423 #define RADV_HASH_SHADER_SISCHED             (1 << 1)
1424 #define RADV_HASH_SHADER_UNSAFE_MATH         (1 << 2)
1425 #define RADV_HASH_SHADER_NO_NGG              (1 << 3)
1426
1427 void
1428 radv_hash_shaders(unsigned char *hash,
1429                   const VkPipelineShaderStageCreateInfo **stages,
1430                   const struct radv_pipeline_layout *layout,
1431                   const struct radv_pipeline_key *key,
1432                   uint32_t flags);
1433
1434 static inline gl_shader_stage
1435 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1436 {
1437         assert(__builtin_popcount(vk_stage) == 1);
1438         return ffs(vk_stage) - 1;
1439 }
1440
1441 static inline VkShaderStageFlagBits
1442 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1443 {
1444         return (1 << mesa_stage);
1445 }
1446
1447 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1448
1449 #define radv_foreach_stage(stage, stage_bits)                           \
1450         for (gl_shader_stage stage,                                     \
1451                      __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1452              stage = __builtin_ffs(__tmp) - 1, __tmp;                   \
1453              __tmp &= ~(1 << (stage)))
1454
1455 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1456 unsigned radv_format_meta_fs_key(VkFormat format);
1457
1458 struct radv_multisample_state {
1459         uint32_t db_eqaa;
1460         uint32_t pa_sc_line_cntl;
1461         uint32_t pa_sc_mode_cntl_0;
1462         uint32_t pa_sc_mode_cntl_1;
1463         uint32_t pa_sc_aa_config;
1464         uint32_t pa_sc_aa_mask[2];
1465         unsigned num_samples;
1466 };
1467
1468 struct radv_prim_vertex_count {
1469         uint8_t min;
1470         uint8_t incr;
1471 };
1472
1473 struct radv_vertex_elements_info {
1474         uint32_t format_size[MAX_VERTEX_ATTRIBS];
1475 };
1476
1477 struct radv_ia_multi_vgt_param_helpers {
1478         uint32_t base;
1479         bool partial_es_wave;
1480         uint8_t primgroup_size;
1481         bool wd_switch_on_eop;
1482         bool ia_switch_on_eoi;
1483         bool partial_vs_wave;
1484 };
1485
1486 struct radv_binning_state {
1487         uint32_t pa_sc_binner_cntl_0;
1488         uint32_t db_dfsm_control;
1489 };
1490
1491 #define SI_GS_PER_ES 128
1492
1493 struct radv_pipeline {
1494         struct radv_device *                          device;
1495         struct radv_dynamic_state                     dynamic_state;
1496
1497         struct radv_pipeline_layout *                 layout;
1498
1499         bool                                         need_indirect_descriptor_sets;
1500         struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
1501         struct radv_shader_variant *gs_copy_shader;
1502         VkShaderStageFlags                           active_stages;
1503
1504         struct radeon_cmdbuf                      cs;
1505         uint32_t                                  ctx_cs_hash;
1506         struct radeon_cmdbuf                      ctx_cs;
1507
1508         struct radv_vertex_elements_info             vertex_elements;
1509
1510         uint32_t                                     binding_stride[MAX_VBS];
1511         uint8_t                                      num_vertex_bindings;
1512
1513         uint32_t user_data_0[MESA_SHADER_STAGES];
1514         union {
1515                 struct {
1516                         struct radv_multisample_state ms;
1517                         struct radv_binning_state binning;
1518                         uint32_t spi_baryc_cntl;
1519                         bool prim_restart_enable;
1520                         unsigned esgs_ring_size;
1521                         unsigned gsvs_ring_size;
1522                         uint32_t vtx_base_sgpr;
1523                         struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1524                         uint8_t vtx_emit_num;
1525                         struct radv_prim_vertex_count prim_vertex_count;
1526                         bool can_use_guardband;
1527                         uint32_t needed_dynamic_state;
1528                         bool disable_out_of_order_rast_for_occlusion;
1529
1530                         /* Used for rbplus */
1531                         uint32_t col_format;
1532                         uint32_t cb_target_mask;
1533                 } graphics;
1534         };
1535
1536         unsigned max_waves;
1537         unsigned scratch_bytes_per_wave;
1538
1539         /* Not NULL if graphics pipeline uses streamout. */
1540         struct radv_shader_variant *streamout_shader;
1541 };
1542
1543 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1544 {
1545         return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1546 }
1547
1548 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1549 {
1550         return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1551 }
1552
1553 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1554
1555 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1556
1557 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1558                                                  gl_shader_stage stage,
1559                                                  int idx);
1560
1561 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1562                                             gl_shader_stage stage);
1563
1564 struct radv_graphics_pipeline_create_info {
1565         bool use_rectlist;
1566         bool db_depth_clear;
1567         bool db_stencil_clear;
1568         bool db_depth_disable_expclear;
1569         bool db_stencil_disable_expclear;
1570         bool db_flush_depth_inplace;
1571         bool db_flush_stencil_inplace;
1572         bool db_resummarize;
1573         uint32_t custom_blend_mode;
1574 };
1575
1576 VkResult
1577 radv_graphics_pipeline_create(VkDevice device,
1578                               VkPipelineCache cache,
1579                               const VkGraphicsPipelineCreateInfo *pCreateInfo,
1580                               const struct radv_graphics_pipeline_create_info *extra,
1581                               const VkAllocationCallbacks *alloc,
1582                               VkPipeline *pPipeline);
1583
1584 struct vk_format_description;
1585 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1586                                           int first_non_void);
1587 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1588                                          int first_non_void);
1589 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1590 uint32_t radv_translate_colorformat(VkFormat format);
1591 uint32_t radv_translate_color_numformat(VkFormat format,
1592                                         const struct vk_format_description *desc,
1593                                         int first_non_void);
1594 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1595 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1596 uint32_t radv_translate_dbformat(VkFormat format);
1597 uint32_t radv_translate_tex_dataformat(VkFormat format,
1598                                        const struct vk_format_description *desc,
1599                                        int first_non_void);
1600 uint32_t radv_translate_tex_numformat(VkFormat format,
1601                                       const struct vk_format_description *desc,
1602                                       int first_non_void);
1603 bool radv_format_pack_clear_color(VkFormat format,
1604                                   uint32_t clear_vals[2],
1605                                   VkClearColorValue *value);
1606 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1607 bool radv_dcc_formats_compatible(VkFormat format1,
1608                                  VkFormat format2);
1609 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1610
1611 struct radv_image_plane {
1612         VkFormat format;
1613         struct radeon_surf surface;
1614         uint64_t offset;
1615 };
1616
1617 struct radv_image {
1618         VkImageType type;
1619         /* The original VkFormat provided by the client.  This may not match any
1620          * of the actual surface formats.
1621          */
1622         VkFormat vk_format;
1623         VkImageAspectFlags aspects;
1624         VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1625         struct ac_surf_info info;
1626         VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1627         VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1628
1629         VkDeviceSize size;
1630         uint32_t alignment;
1631
1632         unsigned queue_family_mask;
1633         bool exclusive;
1634         bool shareable;
1635
1636         /* Set when bound */
1637         struct radeon_winsys_bo *bo;
1638         VkDeviceSize offset;
1639         uint64_t dcc_offset;
1640         uint64_t htile_offset;
1641         bool tc_compatible_htile;
1642         bool tc_compatible_cmask;
1643
1644         uint64_t cmask_offset;
1645         uint64_t fmask_offset;
1646         uint64_t clear_value_offset;
1647         uint64_t fce_pred_offset;
1648         uint64_t dcc_pred_offset;
1649
1650         /*
1651          * Metadata for the TC-compat zrange workaround. If the 32-bit value
1652          * stored at this offset is UINT_MAX, the driver will emit
1653          * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1654          * SET_CONTEXT_REG packet.
1655          */
1656         uint64_t tc_compat_zrange_offset;
1657
1658         /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1659         VkDeviceMemory owned_memory;
1660
1661         unsigned plane_count;
1662         struct radv_image_plane planes[0];
1663 };
1664
1665 /* Whether the image has a htile that is known consistent with the contents of
1666  * the image. */
1667 bool radv_layout_has_htile(const struct radv_image *image,
1668                            VkImageLayout layout,
1669                            bool in_render_loop,
1670                            unsigned queue_mask);
1671
1672 /* Whether the image has a htile  that is known consistent with the contents of
1673  * the image and is allowed to be in compressed form.
1674  *
1675  * If this is false reads that don't use the htile should be able to return
1676  * correct results.
1677  */
1678 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1679                                      VkImageLayout layout,
1680                                      bool in_render_loop,
1681                                      unsigned queue_mask);
1682
1683 bool radv_layout_can_fast_clear(const struct radv_image *image,
1684                                 VkImageLayout layout,
1685                                 bool in_render_loop,
1686                                 unsigned queue_mask);
1687
1688 bool radv_layout_dcc_compressed(const struct radv_image *image,
1689                                 VkImageLayout layout,
1690                                 bool in_render_loop,
1691                                 unsigned queue_mask);
1692
1693 /**
1694  * Return whether the image has CMASK metadata for color surfaces.
1695  */
1696 static inline bool
1697 radv_image_has_cmask(const struct radv_image *image)
1698 {
1699         return image->cmask_offset;
1700 }
1701
1702 /**
1703  * Return whether the image has FMASK metadata for color surfaces.
1704  */
1705 static inline bool
1706 radv_image_has_fmask(const struct radv_image *image)
1707 {
1708         return image->fmask_offset;
1709 }
1710
1711 /**
1712  * Return whether the image has DCC metadata for color surfaces.
1713  */
1714 static inline bool
1715 radv_image_has_dcc(const struct radv_image *image)
1716 {
1717         return image->planes[0].surface.dcc_size;
1718 }
1719
1720 /**
1721  * Return whether the image is TC-compatible CMASK.
1722  */
1723 static inline bool
1724 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1725 {
1726         return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1727 }
1728
1729 /**
1730  * Return whether DCC metadata is enabled for a level.
1731  */
1732 static inline bool
1733 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1734 {
1735         return radv_image_has_dcc(image) &&
1736                level < image->planes[0].surface.num_dcc_levels;
1737 }
1738
1739 /**
1740  * Return whether the image has CB metadata.
1741  */
1742 static inline bool
1743 radv_image_has_CB_metadata(const struct radv_image *image)
1744 {
1745         return radv_image_has_cmask(image) ||
1746                radv_image_has_fmask(image) ||
1747                radv_image_has_dcc(image);
1748 }
1749
1750 /**
1751  * Return whether the image has HTILE metadata for depth surfaces.
1752  */
1753 static inline bool
1754 radv_image_has_htile(const struct radv_image *image)
1755 {
1756         return image->planes[0].surface.htile_size;
1757 }
1758
1759 /**
1760  * Return whether HTILE metadata is enabled for a level.
1761  */
1762 static inline bool
1763 radv_htile_enabled(const struct radv_image *image, unsigned level)
1764 {
1765         return radv_image_has_htile(image) && level == 0;
1766 }
1767
1768 /**
1769  * Return whether the image is TC-compatible HTILE.
1770  */
1771 static inline bool
1772 radv_image_is_tc_compat_htile(const struct radv_image *image)
1773 {
1774         return radv_image_has_htile(image) && image->tc_compatible_htile;
1775 }
1776
1777 static inline uint64_t
1778 radv_image_get_fast_clear_va(const struct radv_image *image,
1779                              uint32_t base_level)
1780 {
1781         uint64_t va = radv_buffer_get_va(image->bo);
1782         va += image->offset + image->clear_value_offset + base_level * 8;
1783         return va;
1784 }
1785
1786 static inline uint64_t
1787 radv_image_get_fce_pred_va(const struct radv_image *image,
1788                            uint32_t base_level)
1789 {
1790         uint64_t va = radv_buffer_get_va(image->bo);
1791         va += image->offset + image->fce_pred_offset + base_level * 8;
1792         return va;
1793 }
1794
1795 static inline uint64_t
1796 radv_image_get_dcc_pred_va(const struct radv_image *image,
1797                            uint32_t base_level)
1798 {
1799         uint64_t va = radv_buffer_get_va(image->bo);
1800         va += image->offset + image->dcc_pred_offset + base_level * 8;
1801         return va;
1802 }
1803
1804 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1805
1806 static inline uint32_t
1807 radv_get_layerCount(const struct radv_image *image,
1808                     const VkImageSubresourceRange *range)
1809 {
1810         return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1811                 image->info.array_size - range->baseArrayLayer : range->layerCount;
1812 }
1813
1814 static inline uint32_t
1815 radv_get_levelCount(const struct radv_image *image,
1816                     const VkImageSubresourceRange *range)
1817 {
1818         return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1819                 image->info.levels - range->baseMipLevel : range->levelCount;
1820 }
1821
1822 struct radeon_bo_metadata;
1823 void
1824 radv_init_metadata(struct radv_device *device,
1825                    struct radv_image *image,
1826                    struct radeon_bo_metadata *metadata);
1827
1828 void
1829 radv_image_override_offset_stride(struct radv_device *device,
1830                                   struct radv_image *image,
1831                                   uint64_t offset, uint32_t stride);
1832
1833 union radv_descriptor {
1834         struct {
1835                 uint32_t plane0_descriptor[8];
1836                 uint32_t fmask_descriptor[8];
1837         };
1838         struct {
1839                 uint32_t plane_descriptors[3][8];
1840         };
1841 };
1842
1843 struct radv_image_view {
1844         struct radv_image *image; /**< VkImageViewCreateInfo::image */
1845         struct radeon_winsys_bo *bo;
1846
1847         VkImageViewType type;
1848         VkImageAspectFlags aspect_mask;
1849         VkFormat vk_format;
1850         unsigned plane_id;
1851         bool multiple_planes;
1852         uint32_t base_layer;
1853         uint32_t layer_count;
1854         uint32_t base_mip;
1855         uint32_t level_count;
1856         VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1857
1858         union radv_descriptor descriptor;
1859
1860         /* Descriptor for use as a storage image as opposed to a sampled image.
1861          * This has a few differences for cube maps (e.g. type).
1862          */
1863         union radv_descriptor storage_descriptor;
1864 };
1865
1866 struct radv_image_create_info {
1867         const VkImageCreateInfo *vk_info;
1868         bool scanout;
1869         bool no_metadata_planes;
1870         const struct radeon_bo_metadata *bo_metadata;
1871 };
1872
1873 VkResult radv_image_create(VkDevice _device,
1874                            const struct radv_image_create_info *info,
1875                            const VkAllocationCallbacks* alloc,
1876                            VkImage *pImage);
1877
1878 VkResult
1879 radv_image_from_gralloc(VkDevice device_h,
1880                        const VkImageCreateInfo *base_info,
1881                        const VkNativeBufferANDROID *gralloc_info,
1882                        const VkAllocationCallbacks *alloc,
1883                        VkImage *out_image_h);
1884
1885 void radv_image_view_init(struct radv_image_view *view,
1886                           struct radv_device *device,
1887                           const VkImageViewCreateInfo* pCreateInfo);
1888
1889 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1890
1891 struct radv_sampler_ycbcr_conversion {
1892         VkFormat format;
1893         VkSamplerYcbcrModelConversion ycbcr_model;
1894         VkSamplerYcbcrRange ycbcr_range;
1895         VkComponentMapping components;
1896         VkChromaLocation chroma_offsets[2];
1897         VkFilter chroma_filter;
1898 };
1899
1900 struct radv_buffer_view {
1901         struct radeon_winsys_bo *bo;
1902         VkFormat vk_format;
1903         uint64_t range; /**< VkBufferViewCreateInfo::range */
1904         uint32_t state[4];
1905 };
1906 void radv_buffer_view_init(struct radv_buffer_view *view,
1907                            struct radv_device *device,
1908                            const VkBufferViewCreateInfo* pCreateInfo);
1909
1910 static inline struct VkExtent3D
1911 radv_sanitize_image_extent(const VkImageType imageType,
1912                            const struct VkExtent3D imageExtent)
1913 {
1914         switch (imageType) {
1915         case VK_IMAGE_TYPE_1D:
1916                 return (VkExtent3D) { imageExtent.width, 1, 1 };
1917         case VK_IMAGE_TYPE_2D:
1918                 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1919         case VK_IMAGE_TYPE_3D:
1920                 return imageExtent;
1921         default:
1922                 unreachable("invalid image type");
1923         }
1924 }
1925
1926 static inline struct VkOffset3D
1927 radv_sanitize_image_offset(const VkImageType imageType,
1928                            const struct VkOffset3D imageOffset)
1929 {
1930         switch (imageType) {
1931         case VK_IMAGE_TYPE_1D:
1932                 return (VkOffset3D) { imageOffset.x, 0, 0 };
1933         case VK_IMAGE_TYPE_2D:
1934                 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1935         case VK_IMAGE_TYPE_3D:
1936                 return imageOffset;
1937         default:
1938                 unreachable("invalid image type");
1939         }
1940 }
1941
1942 static inline bool
1943 radv_image_extent_compare(const struct radv_image *image,
1944                           const VkExtent3D *extent)
1945 {
1946         if (extent->width != image->info.width ||
1947             extent->height != image->info.height ||
1948             extent->depth != image->info.depth)
1949                 return false;
1950         return true;
1951 }
1952
1953 struct radv_sampler {
1954         uint32_t state[4];
1955         struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1956 };
1957
1958 struct radv_framebuffer {
1959         uint32_t                                     width;
1960         uint32_t                                     height;
1961         uint32_t                                     layers;
1962
1963         uint32_t                                     attachment_count;
1964         struct radv_image_view                       *attachments[0];
1965 };
1966
1967 struct radv_subpass_barrier {
1968         VkPipelineStageFlags src_stage_mask;
1969         VkAccessFlags        src_access_mask;
1970         VkAccessFlags        dst_access_mask;
1971 };
1972
1973 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1974                           const struct radv_subpass_barrier *barrier);
1975
1976 struct radv_subpass_attachment {
1977         uint32_t         attachment;
1978         VkImageLayout    layout;
1979         bool             in_render_loop;
1980 };
1981
1982 struct radv_subpass {
1983         uint32_t                                     attachment_count;
1984         struct radv_subpass_attachment *             attachments;
1985
1986         uint32_t                                     input_count;
1987         uint32_t                                     color_count;
1988         struct radv_subpass_attachment *             input_attachments;
1989         struct radv_subpass_attachment *             color_attachments;
1990         struct radv_subpass_attachment *             resolve_attachments;
1991         struct radv_subpass_attachment *             depth_stencil_attachment;
1992         struct radv_subpass_attachment *             ds_resolve_attachment;
1993         VkResolveModeFlagBitsKHR                     depth_resolve_mode;
1994         VkResolveModeFlagBitsKHR                     stencil_resolve_mode;
1995
1996         /** Subpass has at least one color resolve attachment */
1997         bool                                         has_color_resolve;
1998
1999         /** Subpass has at least one color attachment */
2000         bool                                         has_color_att;
2001
2002         struct radv_subpass_barrier                  start_barrier;
2003
2004         uint32_t                                     view_mask;
2005         VkSampleCountFlagBits                        max_sample_count;
2006 };
2007
2008 uint32_t
2009 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2010
2011 struct radv_render_pass_attachment {
2012         VkFormat                                     format;
2013         uint32_t                                     samples;
2014         VkAttachmentLoadOp                           load_op;
2015         VkAttachmentLoadOp                           stencil_load_op;
2016         VkImageLayout                                initial_layout;
2017         VkImageLayout                                final_layout;
2018
2019         /* The subpass id in which the attachment will be used first/last. */
2020         uint32_t                                     first_subpass_idx;
2021         uint32_t                                     last_subpass_idx;
2022 };
2023
2024 struct radv_render_pass {
2025         uint32_t                                     attachment_count;
2026         uint32_t                                     subpass_count;
2027         struct radv_subpass_attachment *             subpass_attachments;
2028         struct radv_render_pass_attachment *         attachments;
2029         struct radv_subpass_barrier                  end_barrier;
2030         struct radv_subpass                          subpasses[0];
2031 };
2032
2033 VkResult radv_device_init_meta(struct radv_device *device);
2034 void radv_device_finish_meta(struct radv_device *device);
2035
2036 struct radv_query_pool {
2037         struct radeon_winsys_bo *bo;
2038         uint32_t stride;
2039         uint32_t availability_offset;
2040         uint64_t size;
2041         char *ptr;
2042         VkQueryType type;
2043         uint32_t pipeline_stats_mask;
2044 };
2045
2046 struct radv_semaphore {
2047         /* use a winsys sem for non-exportable */
2048         struct radeon_winsys_sem *sem;
2049         uint32_t syncobj;
2050         uint32_t temp_syncobj;
2051 };
2052
2053 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2054                              VkPipelineBindPoint bind_point,
2055                              struct radv_descriptor_set *set,
2056                              unsigned idx);
2057
2058 void
2059 radv_update_descriptor_sets(struct radv_device *device,
2060                             struct radv_cmd_buffer *cmd_buffer,
2061                             VkDescriptorSet overrideSet,
2062                             uint32_t descriptorWriteCount,
2063                             const VkWriteDescriptorSet *pDescriptorWrites,
2064                             uint32_t descriptorCopyCount,
2065                             const VkCopyDescriptorSet *pDescriptorCopies);
2066
2067 void
2068 radv_update_descriptor_set_with_template(struct radv_device *device,
2069                                          struct radv_cmd_buffer *cmd_buffer,
2070                                          struct radv_descriptor_set *set,
2071                                          VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2072                                          const void *pData);
2073
2074 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2075                                    VkPipelineBindPoint pipelineBindPoint,
2076                                    VkPipelineLayout _layout,
2077                                    uint32_t set,
2078                                    uint32_t descriptorWriteCount,
2079                                    const VkWriteDescriptorSet *pDescriptorWrites);
2080
2081 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2082                          struct radv_image *image,
2083                          const VkImageSubresourceRange *range, uint32_t value);
2084
2085 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2086                            struct radv_image *image,
2087                            const VkImageSubresourceRange *range);
2088
2089 struct radv_fence {
2090         struct radeon_winsys_fence *fence;
2091         struct wsi_fence *fence_wsi;
2092
2093         uint32_t syncobj;
2094         uint32_t temp_syncobj;
2095 };
2096
2097 /* radv_nir_to_llvm.c */
2098 struct radv_shader_variant_info;
2099 struct radv_nir_compiler_options;
2100
2101 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2102                                  struct nir_shader *geom_shader,
2103                                  struct radv_shader_binary **rbinary,
2104                                  struct radv_shader_variant_info *shader_info,
2105                                  const struct radv_nir_compiler_options *option);
2106
2107 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2108                              struct radv_shader_binary **rbinary,
2109                              struct radv_shader_variant_info *shader_info,
2110                              struct nir_shader *const *nir,
2111                              int nir_count,
2112                              const struct radv_nir_compiler_options *options);
2113
2114 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2115                                          gl_shader_stage stage,
2116                                          const struct nir_shader *nir);
2117
2118 /* radv_shader_info.h */
2119 struct radv_shader_info;
2120
2121 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2122                                const struct radv_nir_compiler_options *options,
2123                                struct radv_shader_info *info);
2124
2125 void radv_nir_shader_info_init(struct radv_shader_info *info);
2126
2127 struct radeon_winsys_sem;
2128
2129 uint64_t radv_get_current_time(void);
2130
2131 static inline uint32_t
2132 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2133 {
2134         switch (gl_prim) {
2135         case 0: /* GL_POINTS */
2136                 return 1;
2137         case 1: /* GL_LINES */
2138         case 3: /* GL_LINE_STRIP */
2139                 return 2;
2140         case 4: /* GL_TRIANGLES */
2141         case 5: /* GL_TRIANGLE_STRIP */
2142                 return 3;
2143         case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2144                 return 4;
2145         case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2146                 return 6;
2147         case 7: /* GL_QUADS */
2148                 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2149         default:
2150                 assert(0);
2151                 return 0;
2152         }
2153 }
2154
2155 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)         \
2156                                                                 \
2157         static inline struct __radv_type *                      \
2158         __radv_type ## _from_handle(__VkType _handle)           \
2159         {                                                       \
2160                 return (struct __radv_type *) _handle;          \
2161         }                                                       \
2162                                                                 \
2163         static inline __VkType                                  \
2164         __radv_type ## _to_handle(struct __radv_type *_obj)     \
2165         {                                                       \
2166                 return (__VkType) _obj;                         \
2167         }
2168
2169 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType)         \
2170                                                                         \
2171         static inline struct __radv_type *                              \
2172         __radv_type ## _from_handle(__VkType _handle)                   \
2173         {                                                               \
2174                 return (struct __radv_type *)(uintptr_t) _handle;       \
2175         }                                                               \
2176                                                                         \
2177         static inline __VkType                                          \
2178         __radv_type ## _to_handle(struct __radv_type *_obj)             \
2179         {                                                               \
2180                 return (__VkType)(uintptr_t) _obj;                      \
2181         }
2182
2183 #define RADV_FROM_HANDLE(__radv_type, __name, __handle)                 \
2184         struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2185
2186 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2187 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2188 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2189 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2190 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2191
2192 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2193 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2194 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2195 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2196 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2197 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2198 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2199 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2200 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2201 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2202 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2203 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2204 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2205 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2206 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2207 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2208 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2209 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2210 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2211 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2212 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2213 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2214
2215 #endif /* RADV_PRIVATE_H */