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radv: Implement VK_EXT_pci_bus_info.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102
103 #define NUM_DEPTH_CLEAR_PIPELINES 3
104
105 /*
106 * This is the point we switch from using CP to compute shader
107 * for certain buffer operations.
108 */
109 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
110
111 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
112
113 enum radv_mem_heap {
114 RADV_MEM_HEAP_VRAM,
115 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
116 RADV_MEM_HEAP_GTT,
117 RADV_MEM_HEAP_COUNT
118 };
119
120 enum radv_mem_type {
121 RADV_MEM_TYPE_VRAM,
122 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
123 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
124 RADV_MEM_TYPE_GTT_CACHED,
125 RADV_MEM_TYPE_COUNT
126 };
127
128 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 radv_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 radv_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 radv_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; \
212 __dword &= ~(1 << (b)))
213
214 #define typed_memcpy(dest, src, count) ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 /* Whenever we generate an error, pass it through this function. Useful for
220 * debugging, where we can break on it. Only call at error site, not when
221 * propagating errors. Might be useful to plug in a stack trace here.
222 */
223
224 struct radv_instance;
225
226 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
227
228 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
229 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
230
231 void __radv_finishme(const char *file, int line, const char *format, ...)
232 radv_printflike(3, 4);
233 void radv_loge(const char *format, ...) radv_printflike(1, 2);
234 void radv_loge_v(const char *format, va_list va);
235 void radv_logi(const char *format, ...) radv_printflike(1, 2);
236 void radv_logi_v(const char *format, va_list va);
237
238 /**
239 * Print a FINISHME message, including its source location.
240 */
241 #define radv_finishme(format, ...) \
242 do { \
243 static bool reported = false; \
244 if (!reported) { \
245 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
246 reported = true; \
247 } \
248 } while (0)
249
250 /* A non-fatal assert. Useful for debugging. */
251 #ifdef DEBUG
252 #define radv_assert(x) ({ \
253 if (unlikely(!(x))) \
254 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
255 })
256 #else
257 #define radv_assert(x)
258 #endif
259
260 #define stub_return(v) \
261 do { \
262 radv_finishme("stub %s", __func__); \
263 return (v); \
264 } while (0)
265
266 #define stub() \
267 do { \
268 radv_finishme("stub %s", __func__); \
269 return; \
270 } while (0)
271
272 void *radv_lookup_entrypoint_unchecked(const char *name);
273 void *radv_lookup_entrypoint_checked(const char *name,
274 uint32_t core_version,
275 const struct radv_instance_extension_table *instance,
276 const struct radv_device_extension_table *device);
277
278 struct radv_physical_device {
279 VK_LOADER_DATA _loader_data;
280
281 struct radv_instance * instance;
282
283 struct radeon_winsys *ws;
284 struct radeon_info rad_info;
285 char path[20];
286 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
287 uint8_t driver_uuid[VK_UUID_SIZE];
288 uint8_t device_uuid[VK_UUID_SIZE];
289 uint8_t cache_uuid[VK_UUID_SIZE];
290
291 int local_fd;
292 int master_fd;
293 struct wsi_device wsi_device;
294
295 bool has_rbplus; /* if RB+ register exist */
296 bool rbplus_allowed; /* if RB+ is allowed */
297 bool has_clear_state;
298 bool cpdma_prefetch_writes_memory;
299 bool has_scissor_bug;
300
301 bool has_out_of_order_rast;
302 bool out_of_order_rast_allowed;
303
304 /* Whether DCC should be enabled for MSAA textures. */
305 bool dcc_msaa_allowed;
306
307 /* This is the drivers on-disk cache used as a fallback as opposed to
308 * the pipeline cache defined by apps.
309 */
310 struct disk_cache * disk_cache;
311
312 VkPhysicalDeviceMemoryProperties memory_properties;
313 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
314
315 drmPciBusInfo bus_info;
316
317 struct radv_device_extension_table supported_extensions;
318 };
319
320 struct radv_instance {
321 VK_LOADER_DATA _loader_data;
322
323 VkAllocationCallbacks alloc;
324
325 uint32_t apiVersion;
326 int physicalDeviceCount;
327 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
328
329 uint64_t debug_flags;
330 uint64_t perftest_flags;
331
332 struct vk_debug_report_instance debug_report_callbacks;
333
334 struct radv_instance_extension_table enabled_extensions;
335 };
336
337 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
338 void radv_finish_wsi(struct radv_physical_device *physical_device);
339
340 bool radv_instance_extension_supported(const char *name);
341 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
342 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
343 const char *name);
344
345 struct cache_entry;
346
347 struct radv_pipeline_cache {
348 struct radv_device * device;
349 pthread_mutex_t mutex;
350
351 uint32_t total_size;
352 uint32_t table_size;
353 uint32_t kernel_count;
354 struct cache_entry ** hash_table;
355 bool modified;
356
357 VkAllocationCallbacks alloc;
358 };
359
360 struct radv_pipeline_key {
361 uint32_t instance_rate_inputs;
362 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
363 uint64_t vertex_alpha_adjust;
364 unsigned tess_input_vertices;
365 uint32_t col_format;
366 uint32_t is_int8;
367 uint32_t is_int10;
368 uint8_t log2_ps_iter_samples;
369 uint8_t num_samples;
370 uint32_t has_multiview_view_index : 1;
371 uint32_t optimisations_disabled : 1;
372 };
373
374 void
375 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
376 struct radv_device *device);
377 void
378 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
379 bool
380 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
381 const void *data, size_t size);
382
383 struct radv_shader_variant;
384
385 bool
386 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
387 struct radv_pipeline_cache *cache,
388 const unsigned char *sha1,
389 struct radv_shader_variant **variants);
390
391 void
392 radv_pipeline_cache_insert_shaders(struct radv_device *device,
393 struct radv_pipeline_cache *cache,
394 const unsigned char *sha1,
395 struct radv_shader_variant **variants,
396 const void *const *codes,
397 const unsigned *code_sizes);
398
399 enum radv_blit_ds_layout {
400 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
401 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
402 RADV_BLIT_DS_LAYOUT_COUNT,
403 };
404
405 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
406 {
407 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
408 }
409
410 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
411 {
412 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
413 }
414
415 enum radv_meta_dst_layout {
416 RADV_META_DST_LAYOUT_GENERAL,
417 RADV_META_DST_LAYOUT_OPTIMAL,
418 RADV_META_DST_LAYOUT_COUNT,
419 };
420
421 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
422 {
423 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
424 }
425
426 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
427 {
428 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
429 }
430
431 struct radv_meta_state {
432 VkAllocationCallbacks alloc;
433
434 struct radv_pipeline_cache cache;
435
436 /*
437 * For on-demand pipeline creation, makes sure that
438 * only one thread tries to build a pipeline at the same time.
439 */
440 mtx_t mtx;
441
442 /**
443 * Use array element `i` for images with `2^i` samples.
444 */
445 struct {
446 VkRenderPass render_pass[NUM_META_FS_KEYS];
447 VkPipeline color_pipelines[NUM_META_FS_KEYS];
448
449 VkRenderPass depthstencil_rp;
450 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
451 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
452 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
453 } clear[1 + MAX_SAMPLES_LOG2];
454
455 VkPipelineLayout clear_color_p_layout;
456 VkPipelineLayout clear_depth_p_layout;
457 struct {
458 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
459
460 /** Pipeline that blits from a 1D image. */
461 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
462
463 /** Pipeline that blits from a 2D image. */
464 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
465
466 /** Pipeline that blits from a 3D image. */
467 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
468
469 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
470 VkPipeline depth_only_1d_pipeline;
471 VkPipeline depth_only_2d_pipeline;
472 VkPipeline depth_only_3d_pipeline;
473
474 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
475 VkPipeline stencil_only_1d_pipeline;
476 VkPipeline stencil_only_2d_pipeline;
477 VkPipeline stencil_only_3d_pipeline;
478 VkPipelineLayout pipeline_layout;
479 VkDescriptorSetLayout ds_layout;
480 } blit;
481
482 struct {
483 VkPipelineLayout p_layouts[5];
484 VkDescriptorSetLayout ds_layouts[5];
485 VkPipeline pipelines[5][NUM_META_FS_KEYS];
486
487 VkPipeline depth_only_pipeline[5];
488
489 VkPipeline stencil_only_pipeline[5];
490 } blit2d[1 + MAX_SAMPLES_LOG2];
491
492 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
493 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
494 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
495
496 struct {
497 VkPipelineLayout img_p_layout;
498 VkDescriptorSetLayout img_ds_layout;
499 VkPipeline pipeline;
500 VkPipeline pipeline_3d;
501 } itob;
502 struct {
503 VkPipelineLayout img_p_layout;
504 VkDescriptorSetLayout img_ds_layout;
505 VkPipeline pipeline;
506 VkPipeline pipeline_3d;
507 } btoi;
508 struct {
509 VkPipelineLayout img_p_layout;
510 VkDescriptorSetLayout img_ds_layout;
511 VkPipeline pipeline;
512 VkPipeline pipeline_3d;
513 } itoi;
514 struct {
515 VkPipelineLayout img_p_layout;
516 VkDescriptorSetLayout img_ds_layout;
517 VkPipeline pipeline;
518 VkPipeline pipeline_3d;
519 } cleari;
520 struct {
521 VkPipelineLayout img_p_layout;
522 VkDescriptorSetLayout img_ds_layout;
523 VkPipeline pipeline;
524 } cleari_r32g32b32;
525
526 struct {
527 VkPipelineLayout p_layout;
528 VkPipeline pipeline[NUM_META_FS_KEYS];
529 VkRenderPass pass[NUM_META_FS_KEYS];
530 } resolve;
531
532 struct {
533 VkDescriptorSetLayout ds_layout;
534 VkPipelineLayout p_layout;
535 struct {
536 VkPipeline pipeline;
537 VkPipeline i_pipeline;
538 VkPipeline srgb_pipeline;
539 } rc[MAX_SAMPLES_LOG2];
540 } resolve_compute;
541
542 struct {
543 VkDescriptorSetLayout ds_layout;
544 VkPipelineLayout p_layout;
545
546 struct {
547 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
548 VkPipeline pipeline[NUM_META_FS_KEYS];
549 } rc[MAX_SAMPLES_LOG2];
550 } resolve_fragment;
551
552 struct {
553 VkPipelineLayout p_layout;
554 VkPipeline decompress_pipeline;
555 VkPipeline resummarize_pipeline;
556 VkRenderPass pass;
557 } depth_decomp[1 + MAX_SAMPLES_LOG2];
558
559 struct {
560 VkPipelineLayout p_layout;
561 VkPipeline cmask_eliminate_pipeline;
562 VkPipeline fmask_decompress_pipeline;
563 VkPipeline dcc_decompress_pipeline;
564 VkRenderPass pass;
565
566 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
567 VkPipelineLayout dcc_decompress_compute_p_layout;
568 VkPipeline dcc_decompress_compute_pipeline;
569 } fast_clear_flush;
570
571 struct {
572 VkPipelineLayout fill_p_layout;
573 VkPipelineLayout copy_p_layout;
574 VkDescriptorSetLayout fill_ds_layout;
575 VkDescriptorSetLayout copy_ds_layout;
576 VkPipeline fill_pipeline;
577 VkPipeline copy_pipeline;
578 } buffer;
579
580 struct {
581 VkDescriptorSetLayout ds_layout;
582 VkPipelineLayout p_layout;
583 VkPipeline occlusion_query_pipeline;
584 VkPipeline pipeline_statistics_query_pipeline;
585 } query;
586 };
587
588 /* queue types */
589 #define RADV_QUEUE_GENERAL 0
590 #define RADV_QUEUE_COMPUTE 1
591 #define RADV_QUEUE_TRANSFER 2
592
593 #define RADV_MAX_QUEUE_FAMILIES 3
594
595 enum ring_type radv_queue_family_to_ring(int f);
596
597 struct radv_queue {
598 VK_LOADER_DATA _loader_data;
599 struct radv_device * device;
600 struct radeon_winsys_ctx *hw_ctx;
601 enum radeon_ctx_priority priority;
602 uint32_t queue_family_index;
603 int queue_idx;
604 VkDeviceQueueCreateFlags flags;
605
606 uint32_t scratch_size;
607 uint32_t compute_scratch_size;
608 uint32_t esgs_ring_size;
609 uint32_t gsvs_ring_size;
610 bool has_tess_rings;
611 bool has_sample_positions;
612
613 struct radeon_winsys_bo *scratch_bo;
614 struct radeon_winsys_bo *descriptor_bo;
615 struct radeon_winsys_bo *compute_scratch_bo;
616 struct radeon_winsys_bo *esgs_ring_bo;
617 struct radeon_winsys_bo *gsvs_ring_bo;
618 struct radeon_winsys_bo *tess_rings_bo;
619 struct radeon_cmdbuf *initial_preamble_cs;
620 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
621 struct radeon_cmdbuf *continue_preamble_cs;
622 };
623
624 struct radv_bo_list {
625 struct radv_winsys_bo_list list;
626 unsigned capacity;
627 pthread_mutex_t mutex;
628 };
629
630 struct radv_device {
631 VK_LOADER_DATA _loader_data;
632
633 VkAllocationCallbacks alloc;
634
635 struct radv_instance * instance;
636 struct radeon_winsys *ws;
637
638 struct radv_meta_state meta_state;
639
640 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
641 int queue_count[RADV_MAX_QUEUE_FAMILIES];
642 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
643
644 bool always_use_syncobj;
645 bool has_distributed_tess;
646 bool pbb_allowed;
647 bool dfsm_allowed;
648 uint32_t tess_offchip_block_dw_size;
649 uint32_t scratch_waves;
650 uint32_t dispatch_initiator;
651
652 uint32_t gs_table_depth;
653
654 /* MSAA sample locations.
655 * The first index is the sample index.
656 * The second index is the coordinate: X, Y. */
657 float sample_locations_1x[1][2];
658 float sample_locations_2x[2][2];
659 float sample_locations_4x[4][2];
660 float sample_locations_8x[8][2];
661 float sample_locations_16x[16][2];
662
663 /* CIK and later */
664 uint32_t gfx_init_size_dw;
665 struct radeon_winsys_bo *gfx_init;
666
667 struct radeon_winsys_bo *trace_bo;
668 uint32_t *trace_id_ptr;
669
670 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
671 bool keep_shader_info;
672
673 struct radv_physical_device *physical_device;
674
675 /* Backup in-memory cache to be used if the app doesn't provide one */
676 struct radv_pipeline_cache * mem_cache;
677
678 /*
679 * use different counters so MSAA MRTs get consecutive surface indices,
680 * even if MASK is allocated in between.
681 */
682 uint32_t image_mrt_offset_counter;
683 uint32_t fmask_mrt_offset_counter;
684 struct list_head shader_slabs;
685 mtx_t shader_slab_mutex;
686
687 /* For detecting VM faults reported by dmesg. */
688 uint64_t dmesg_timestamp;
689
690 struct radv_device_extension_table enabled_extensions;
691
692 /* Whether the driver uses a global BO list. */
693 bool use_global_bo_list;
694
695 struct radv_bo_list bo_list;
696
697 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
698 int force_aniso;
699 };
700
701 struct radv_device_memory {
702 struct radeon_winsys_bo *bo;
703 /* for dedicated allocations */
704 struct radv_image *image;
705 struct radv_buffer *buffer;
706 uint32_t type_index;
707 VkDeviceSize map_size;
708 void * map;
709 void * user_ptr;
710 };
711
712
713 struct radv_descriptor_range {
714 uint64_t va;
715 uint32_t size;
716 };
717
718 struct radv_descriptor_set {
719 const struct radv_descriptor_set_layout *layout;
720 uint32_t size;
721
722 struct radeon_winsys_bo *bo;
723 uint64_t va;
724 uint32_t *mapped_ptr;
725 struct radv_descriptor_range *dynamic_descriptors;
726
727 struct radeon_winsys_bo *descriptors[0];
728 };
729
730 struct radv_push_descriptor_set
731 {
732 struct radv_descriptor_set set;
733 uint32_t capacity;
734 };
735
736 struct radv_descriptor_pool_entry {
737 uint32_t offset;
738 uint32_t size;
739 struct radv_descriptor_set *set;
740 };
741
742 struct radv_descriptor_pool {
743 struct radeon_winsys_bo *bo;
744 uint8_t *mapped_ptr;
745 uint64_t current_offset;
746 uint64_t size;
747
748 uint8_t *host_memory_base;
749 uint8_t *host_memory_ptr;
750 uint8_t *host_memory_end;
751
752 uint32_t entry_count;
753 uint32_t max_entry_count;
754 struct radv_descriptor_pool_entry entries[0];
755 };
756
757 struct radv_descriptor_update_template_entry {
758 VkDescriptorType descriptor_type;
759
760 /* The number of descriptors to update */
761 uint32_t descriptor_count;
762
763 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
764 uint32_t dst_offset;
765
766 /* In dwords. Not valid/used for dynamic descriptors */
767 uint32_t dst_stride;
768
769 uint32_t buffer_offset;
770
771 /* Only valid for combined image samplers and samplers */
772 uint16_t has_sampler;
773
774 /* In bytes */
775 size_t src_offset;
776 size_t src_stride;
777
778 /* For push descriptors */
779 const uint32_t *immutable_samplers;
780 };
781
782 struct radv_descriptor_update_template {
783 uint32_t entry_count;
784 VkPipelineBindPoint bind_point;
785 struct radv_descriptor_update_template_entry entry[0];
786 };
787
788 struct radv_buffer {
789 VkDeviceSize size;
790
791 VkBufferUsageFlags usage;
792 VkBufferCreateFlags flags;
793
794 /* Set when bound */
795 struct radeon_winsys_bo * bo;
796 VkDeviceSize offset;
797
798 bool shareable;
799 };
800
801 enum radv_dynamic_state_bits {
802 RADV_DYNAMIC_VIEWPORT = 1 << 0,
803 RADV_DYNAMIC_SCISSOR = 1 << 1,
804 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
805 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
806 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
807 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
808 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
809 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
810 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
811 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
812 RADV_DYNAMIC_ALL = (1 << 10) - 1,
813 };
814
815 enum radv_cmd_dirty_bits {
816 /* Keep the dynamic state dirty bits in sync with
817 * enum radv_dynamic_state_bits */
818 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
819 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
820 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
821 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
822 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
823 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
824 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
825 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
826 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
827 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
828 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
829 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
830 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
831 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
832 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
833 };
834
835 enum radv_cmd_flush_bits {
836 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
837 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
838 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
839 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
840 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
841 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
842 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
843 /* Same as above, but only writes back and doesn't invalidate */
844 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
845 /* Framebuffer caches */
846 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
847 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
848 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
849 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
850 /* Engine synchronization. */
851 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
852 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
853 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
854 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
855 /* Pipeline query controls. */
856 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
857 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
858
859 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
860 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
861 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
862 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
863 };
864
865 struct radv_vertex_binding {
866 struct radv_buffer * buffer;
867 VkDeviceSize offset;
868 };
869
870 struct radv_viewport_state {
871 uint32_t count;
872 VkViewport viewports[MAX_VIEWPORTS];
873 };
874
875 struct radv_scissor_state {
876 uint32_t count;
877 VkRect2D scissors[MAX_SCISSORS];
878 };
879
880 struct radv_discard_rectangle_state {
881 uint32_t count;
882 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
883 };
884
885 struct radv_dynamic_state {
886 /**
887 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
888 * Defines the set of saved dynamic state.
889 */
890 uint32_t mask;
891
892 struct radv_viewport_state viewport;
893
894 struct radv_scissor_state scissor;
895
896 float line_width;
897
898 struct {
899 float bias;
900 float clamp;
901 float slope;
902 } depth_bias;
903
904 float blend_constants[4];
905
906 struct {
907 float min;
908 float max;
909 } depth_bounds;
910
911 struct {
912 uint32_t front;
913 uint32_t back;
914 } stencil_compare_mask;
915
916 struct {
917 uint32_t front;
918 uint32_t back;
919 } stencil_write_mask;
920
921 struct {
922 uint32_t front;
923 uint32_t back;
924 } stencil_reference;
925
926 struct radv_discard_rectangle_state discard_rectangle;
927 };
928
929 extern const struct radv_dynamic_state default_dynamic_state;
930
931 const char *
932 radv_get_debug_option_name(int id);
933
934 const char *
935 radv_get_perftest_option_name(int id);
936
937 /**
938 * Attachment state when recording a renderpass instance.
939 *
940 * The clear value is valid only if there exists a pending clear.
941 */
942 struct radv_attachment_state {
943 VkImageAspectFlags pending_clear_aspects;
944 uint32_t cleared_views;
945 VkClearValue clear_value;
946 VkImageLayout current_layout;
947 };
948
949 struct radv_descriptor_state {
950 struct radv_descriptor_set *sets[MAX_SETS];
951 uint32_t dirty;
952 uint32_t valid;
953 struct radv_push_descriptor_set push_set;
954 bool push_dirty;
955 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
956 };
957
958 struct radv_cmd_state {
959 /* Vertex descriptors */
960 uint64_t vb_va;
961 unsigned vb_size;
962
963 bool predicating;
964 uint32_t dirty;
965
966 uint32_t prefetch_L2_mask;
967
968 struct radv_pipeline * pipeline;
969 struct radv_pipeline * emitted_pipeline;
970 struct radv_pipeline * compute_pipeline;
971 struct radv_pipeline * emitted_compute_pipeline;
972 struct radv_framebuffer * framebuffer;
973 struct radv_render_pass * pass;
974 const struct radv_subpass * subpass;
975 struct radv_dynamic_state dynamic;
976 struct radv_attachment_state * attachments;
977 VkRect2D render_area;
978
979 /* Index buffer */
980 struct radv_buffer *index_buffer;
981 uint64_t index_offset;
982 uint32_t index_type;
983 uint32_t max_index_count;
984 uint64_t index_va;
985 int32_t last_index_type;
986
987 int32_t last_primitive_reset_en;
988 uint32_t last_primitive_reset_index;
989 enum radv_cmd_flush_bits flush_bits;
990 unsigned active_occlusion_queries;
991 bool perfect_occlusion_queries_enabled;
992 unsigned active_pipeline_queries;
993 float offset_scale;
994 uint32_t trace_id;
995 uint32_t last_ia_multi_vgt_param;
996
997 uint32_t last_num_instances;
998 uint32_t last_first_instance;
999 uint32_t last_vertex_offset;
1000
1001 /* Whether CP DMA is busy/idle. */
1002 bool dma_is_busy;
1003
1004 /* Conditional rendering info. */
1005 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1006 uint64_t predication_va;
1007 };
1008
1009 struct radv_cmd_pool {
1010 VkAllocationCallbacks alloc;
1011 struct list_head cmd_buffers;
1012 struct list_head free_cmd_buffers;
1013 uint32_t queue_family_index;
1014 };
1015
1016 struct radv_cmd_buffer_upload {
1017 uint8_t *map;
1018 unsigned offset;
1019 uint64_t size;
1020 struct radeon_winsys_bo *upload_bo;
1021 struct list_head list;
1022 };
1023
1024 enum radv_cmd_buffer_status {
1025 RADV_CMD_BUFFER_STATUS_INVALID,
1026 RADV_CMD_BUFFER_STATUS_INITIAL,
1027 RADV_CMD_BUFFER_STATUS_RECORDING,
1028 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1029 RADV_CMD_BUFFER_STATUS_PENDING,
1030 };
1031
1032 struct radv_cmd_buffer {
1033 VK_LOADER_DATA _loader_data;
1034
1035 struct radv_device * device;
1036
1037 struct radv_cmd_pool * pool;
1038 struct list_head pool_link;
1039
1040 VkCommandBufferUsageFlags usage_flags;
1041 VkCommandBufferLevel level;
1042 enum radv_cmd_buffer_status status;
1043 struct radeon_cmdbuf *cs;
1044 struct radv_cmd_state state;
1045 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1046 uint32_t queue_family_index;
1047
1048 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1049 VkShaderStageFlags push_constant_stages;
1050 struct radv_descriptor_set meta_push_descriptors;
1051
1052 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1053
1054 struct radv_cmd_buffer_upload upload;
1055
1056 uint32_t scratch_size_needed;
1057 uint32_t compute_scratch_size_needed;
1058 uint32_t esgs_ring_size_needed;
1059 uint32_t gsvs_ring_size_needed;
1060 bool tess_rings_needed;
1061 bool sample_positions_needed;
1062
1063 VkResult record_result;
1064
1065 uint32_t gfx9_fence_offset;
1066 struct radeon_winsys_bo *gfx9_fence_bo;
1067 uint32_t gfx9_fence_idx;
1068 uint64_t gfx9_eop_bug_va;
1069
1070 /**
1071 * Whether a query pool has been resetted and we have to flush caches.
1072 */
1073 bool pending_reset_query;
1074 };
1075
1076 struct radv_image;
1077
1078 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1079
1080 void si_emit_graphics(struct radv_physical_device *physical_device,
1081 struct radeon_cmdbuf *cs);
1082 void si_emit_compute(struct radv_physical_device *physical_device,
1083 struct radeon_cmdbuf *cs);
1084
1085 void cik_create_gfx_config(struct radv_device *device);
1086
1087 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1088 int count, const VkViewport *viewports);
1089 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1090 int count, const VkRect2D *scissors,
1091 const VkViewport *viewports, bool can_use_guardband);
1092 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1093 bool instanced_draw, bool indirect_draw,
1094 uint32_t draw_vertex_count);
1095 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1096 enum chip_class chip_class,
1097 bool is_mec,
1098 unsigned event, unsigned event_flags,
1099 unsigned data_sel,
1100 uint64_t va,
1101 uint32_t old_fence,
1102 uint32_t new_fence,
1103 uint64_t gfx9_eop_bug_va);
1104
1105 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1106 uint64_t va, uint32_t ref,
1107 uint32_t mask);
1108 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1109 enum chip_class chip_class,
1110 uint32_t *fence_ptr, uint64_t va,
1111 bool is_mec,
1112 enum radv_cmd_flush_bits flush_bits,
1113 uint64_t gfx9_eop_bug_va);
1114 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1115 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1116 bool inverted, uint64_t va);
1117 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1118 uint64_t src_va, uint64_t dest_va,
1119 uint64_t size);
1120 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1121 unsigned size);
1122 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1123 uint64_t size, unsigned value);
1124 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1125
1126 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1127 bool
1128 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1129 unsigned size,
1130 unsigned alignment,
1131 unsigned *out_offset,
1132 void **ptr);
1133 void
1134 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1135 const struct radv_subpass *subpass,
1136 bool transitions);
1137 bool
1138 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1139 unsigned size, unsigned alignmnet,
1140 const void *data, unsigned *out_offset);
1141
1142 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1143 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1144 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1145 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1146 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1147 unsigned radv_cayman_get_maxdist(int log_samples);
1148 void radv_device_init_msaa(struct radv_device *device);
1149
1150 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1151 struct radv_image *image,
1152 VkClearDepthStencilValue ds_clear_value,
1153 VkImageAspectFlags aspects);
1154
1155 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1156 struct radv_image *image,
1157 int cb_idx,
1158 uint32_t color_values[2]);
1159
1160 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1161 struct radv_image *image,
1162 bool value);
1163 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1164 struct radeon_winsys_bo *bo,
1165 uint64_t offset, uint64_t size, uint32_t value);
1166 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1167 bool radv_get_memory_fd(struct radv_device *device,
1168 struct radv_device_memory *memory,
1169 int *pFD);
1170
1171 static inline void
1172 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1173 unsigned sh_offset, unsigned pointer_count,
1174 bool use_32bit_pointers)
1175 {
1176 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1177 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1178 }
1179
1180 static inline void
1181 radv_emit_shader_pointer_body(struct radv_device *device,
1182 struct radeon_cmdbuf *cs,
1183 uint64_t va, bool use_32bit_pointers)
1184 {
1185 radeon_emit(cs, va);
1186
1187 if (use_32bit_pointers) {
1188 assert(va == 0 ||
1189 (va >> 32) == device->physical_device->rad_info.address32_hi);
1190 } else {
1191 radeon_emit(cs, va >> 32);
1192 }
1193 }
1194
1195 static inline void
1196 radv_emit_shader_pointer(struct radv_device *device,
1197 struct radeon_cmdbuf *cs,
1198 uint32_t sh_offset, uint64_t va, bool global)
1199 {
1200 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1201
1202 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1203 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1204 }
1205
1206 static inline struct radv_descriptor_state *
1207 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1208 VkPipelineBindPoint bind_point)
1209 {
1210 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1211 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1212 return &cmd_buffer->descriptors[bind_point];
1213 }
1214
1215 /*
1216 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1217 *
1218 * Limitations: Can't call normal dispatch functions without binding or rebinding
1219 * the compute pipeline.
1220 */
1221 void radv_unaligned_dispatch(
1222 struct radv_cmd_buffer *cmd_buffer,
1223 uint32_t x,
1224 uint32_t y,
1225 uint32_t z);
1226
1227 struct radv_event {
1228 struct radeon_winsys_bo *bo;
1229 uint64_t *map;
1230 };
1231
1232 struct radv_shader_module;
1233
1234 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1235 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1236 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1237 void
1238 radv_hash_shaders(unsigned char *hash,
1239 const VkPipelineShaderStageCreateInfo **stages,
1240 const struct radv_pipeline_layout *layout,
1241 const struct radv_pipeline_key *key,
1242 uint32_t flags);
1243
1244 static inline gl_shader_stage
1245 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1246 {
1247 assert(__builtin_popcount(vk_stage) == 1);
1248 return ffs(vk_stage) - 1;
1249 }
1250
1251 static inline VkShaderStageFlagBits
1252 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1253 {
1254 return (1 << mesa_stage);
1255 }
1256
1257 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1258
1259 #define radv_foreach_stage(stage, stage_bits) \
1260 for (gl_shader_stage stage, \
1261 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1262 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1263 __tmp &= ~(1 << (stage)))
1264
1265 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1266 unsigned radv_format_meta_fs_key(VkFormat format);
1267
1268 struct radv_multisample_state {
1269 uint32_t db_eqaa;
1270 uint32_t pa_sc_line_cntl;
1271 uint32_t pa_sc_mode_cntl_0;
1272 uint32_t pa_sc_mode_cntl_1;
1273 uint32_t pa_sc_aa_config;
1274 uint32_t pa_sc_aa_mask[2];
1275 unsigned num_samples;
1276 };
1277
1278 struct radv_prim_vertex_count {
1279 uint8_t min;
1280 uint8_t incr;
1281 };
1282
1283 struct radv_vertex_elements_info {
1284 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1285 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1286 uint32_t binding[MAX_VERTEX_ATTRIBS];
1287 uint32_t offset[MAX_VERTEX_ATTRIBS];
1288 uint32_t count;
1289 };
1290
1291 struct radv_ia_multi_vgt_param_helpers {
1292 uint32_t base;
1293 bool partial_es_wave;
1294 uint8_t primgroup_size;
1295 bool wd_switch_on_eop;
1296 bool ia_switch_on_eoi;
1297 bool partial_vs_wave;
1298 };
1299
1300 #define SI_GS_PER_ES 128
1301
1302 struct radv_pipeline {
1303 struct radv_device * device;
1304 struct radv_dynamic_state dynamic_state;
1305
1306 struct radv_pipeline_layout * layout;
1307
1308 bool need_indirect_descriptor_sets;
1309 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1310 struct radv_shader_variant *gs_copy_shader;
1311 VkShaderStageFlags active_stages;
1312
1313 struct radeon_cmdbuf cs;
1314
1315 struct radv_vertex_elements_info vertex_elements;
1316
1317 uint32_t binding_stride[MAX_VBS];
1318
1319 uint32_t user_data_0[MESA_SHADER_STAGES];
1320 union {
1321 struct {
1322 struct radv_multisample_state ms;
1323 uint32_t spi_baryc_cntl;
1324 bool prim_restart_enable;
1325 unsigned esgs_ring_size;
1326 unsigned gsvs_ring_size;
1327 uint32_t vtx_base_sgpr;
1328 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1329 uint8_t vtx_emit_num;
1330 struct radv_prim_vertex_count prim_vertex_count;
1331 bool can_use_guardband;
1332 uint32_t needed_dynamic_state;
1333 bool disable_out_of_order_rast_for_occlusion;
1334
1335 /* Used for rbplus */
1336 uint32_t col_format;
1337 uint32_t cb_target_mask;
1338 } graphics;
1339 };
1340
1341 unsigned max_waves;
1342 unsigned scratch_bytes_per_wave;
1343 };
1344
1345 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1346 {
1347 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1348 }
1349
1350 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1351 {
1352 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1353 }
1354
1355 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1356 gl_shader_stage stage,
1357 int idx);
1358
1359 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1360 gl_shader_stage stage);
1361
1362 struct radv_graphics_pipeline_create_info {
1363 bool use_rectlist;
1364 bool db_depth_clear;
1365 bool db_stencil_clear;
1366 bool db_depth_disable_expclear;
1367 bool db_stencil_disable_expclear;
1368 bool db_flush_depth_inplace;
1369 bool db_flush_stencil_inplace;
1370 bool db_resummarize;
1371 uint32_t custom_blend_mode;
1372 };
1373
1374 VkResult
1375 radv_graphics_pipeline_create(VkDevice device,
1376 VkPipelineCache cache,
1377 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1378 const struct radv_graphics_pipeline_create_info *extra,
1379 const VkAllocationCallbacks *alloc,
1380 VkPipeline *pPipeline);
1381
1382 struct vk_format_description;
1383 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1384 int first_non_void);
1385 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1386 int first_non_void);
1387 uint32_t radv_translate_colorformat(VkFormat format);
1388 uint32_t radv_translate_color_numformat(VkFormat format,
1389 const struct vk_format_description *desc,
1390 int first_non_void);
1391 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1392 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1393 uint32_t radv_translate_dbformat(VkFormat format);
1394 uint32_t radv_translate_tex_dataformat(VkFormat format,
1395 const struct vk_format_description *desc,
1396 int first_non_void);
1397 uint32_t radv_translate_tex_numformat(VkFormat format,
1398 const struct vk_format_description *desc,
1399 int first_non_void);
1400 bool radv_format_pack_clear_color(VkFormat format,
1401 uint32_t clear_vals[2],
1402 VkClearColorValue *value);
1403 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1404 bool radv_dcc_formats_compatible(VkFormat format1,
1405 VkFormat format2);
1406
1407 struct radv_fmask_info {
1408 uint64_t offset;
1409 uint64_t size;
1410 unsigned alignment;
1411 unsigned pitch_in_pixels;
1412 unsigned bank_height;
1413 unsigned slice_tile_max;
1414 unsigned tile_mode_index;
1415 unsigned tile_swizzle;
1416 };
1417
1418 struct radv_cmask_info {
1419 uint64_t offset;
1420 uint64_t size;
1421 unsigned alignment;
1422 unsigned slice_tile_max;
1423 };
1424
1425 struct radv_image {
1426 VkImageType type;
1427 /* The original VkFormat provided by the client. This may not match any
1428 * of the actual surface formats.
1429 */
1430 VkFormat vk_format;
1431 VkImageAspectFlags aspects;
1432 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1433 struct ac_surf_info info;
1434 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1435 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1436
1437 VkDeviceSize size;
1438 uint32_t alignment;
1439
1440 unsigned queue_family_mask;
1441 bool exclusive;
1442 bool shareable;
1443
1444 /* Set when bound */
1445 struct radeon_winsys_bo *bo;
1446 VkDeviceSize offset;
1447 uint64_t dcc_offset;
1448 uint64_t htile_offset;
1449 bool tc_compatible_htile;
1450 struct radeon_surf surface;
1451
1452 struct radv_fmask_info fmask;
1453 struct radv_cmask_info cmask;
1454 uint64_t clear_value_offset;
1455 uint64_t dcc_pred_offset;
1456
1457 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1458 VkDeviceMemory owned_memory;
1459 };
1460
1461 /* Whether the image has a htile that is known consistent with the contents of
1462 * the image. */
1463 bool radv_layout_has_htile(const struct radv_image *image,
1464 VkImageLayout layout,
1465 unsigned queue_mask);
1466
1467 /* Whether the image has a htile that is known consistent with the contents of
1468 * the image and is allowed to be in compressed form.
1469 *
1470 * If this is false reads that don't use the htile should be able to return
1471 * correct results.
1472 */
1473 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1474 VkImageLayout layout,
1475 unsigned queue_mask);
1476
1477 bool radv_layout_can_fast_clear(const struct radv_image *image,
1478 VkImageLayout layout,
1479 unsigned queue_mask);
1480
1481 bool radv_layout_dcc_compressed(const struct radv_image *image,
1482 VkImageLayout layout,
1483 unsigned queue_mask);
1484
1485 /**
1486 * Return whether the image has CMASK metadata for color surfaces.
1487 */
1488 static inline bool
1489 radv_image_has_cmask(const struct radv_image *image)
1490 {
1491 return image->cmask.size;
1492 }
1493
1494 /**
1495 * Return whether the image has FMASK metadata for color surfaces.
1496 */
1497 static inline bool
1498 radv_image_has_fmask(const struct radv_image *image)
1499 {
1500 return image->fmask.size;
1501 }
1502
1503 /**
1504 * Return whether the image has DCC metadata for color surfaces.
1505 */
1506 static inline bool
1507 radv_image_has_dcc(const struct radv_image *image)
1508 {
1509 return image->surface.dcc_size;
1510 }
1511
1512 /**
1513 * Return whether DCC metadata is enabled for a level.
1514 */
1515 static inline bool
1516 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1517 {
1518 return radv_image_has_dcc(image) &&
1519 level < image->surface.num_dcc_levels;
1520 }
1521
1522 /**
1523 * Return whether the image has CB metadata.
1524 */
1525 static inline bool
1526 radv_image_has_CB_metadata(const struct radv_image *image)
1527 {
1528 return radv_image_has_cmask(image) ||
1529 radv_image_has_fmask(image) ||
1530 radv_image_has_dcc(image);
1531 }
1532
1533 /**
1534 * Return whether the image has HTILE metadata for depth surfaces.
1535 */
1536 static inline bool
1537 radv_image_has_htile(const struct radv_image *image)
1538 {
1539 return image->surface.htile_size;
1540 }
1541
1542 /**
1543 * Return whether HTILE metadata is enabled for a level.
1544 */
1545 static inline bool
1546 radv_htile_enabled(const struct radv_image *image, unsigned level)
1547 {
1548 return radv_image_has_htile(image) && level == 0;
1549 }
1550
1551 /**
1552 * Return whether the image is TC-compatible HTILE.
1553 */
1554 static inline bool
1555 radv_image_is_tc_compat_htile(const struct radv_image *image)
1556 {
1557 return radv_image_has_htile(image) && image->tc_compatible_htile;
1558 }
1559
1560 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1561
1562 static inline uint32_t
1563 radv_get_layerCount(const struct radv_image *image,
1564 const VkImageSubresourceRange *range)
1565 {
1566 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1567 image->info.array_size - range->baseArrayLayer : range->layerCount;
1568 }
1569
1570 static inline uint32_t
1571 radv_get_levelCount(const struct radv_image *image,
1572 const VkImageSubresourceRange *range)
1573 {
1574 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1575 image->info.levels - range->baseMipLevel : range->levelCount;
1576 }
1577
1578 struct radeon_bo_metadata;
1579 void
1580 radv_init_metadata(struct radv_device *device,
1581 struct radv_image *image,
1582 struct radeon_bo_metadata *metadata);
1583
1584 struct radv_image_view {
1585 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1586 struct radeon_winsys_bo *bo;
1587
1588 VkImageViewType type;
1589 VkImageAspectFlags aspect_mask;
1590 VkFormat vk_format;
1591 uint32_t base_layer;
1592 uint32_t layer_count;
1593 uint32_t base_mip;
1594 uint32_t level_count;
1595 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1596
1597 uint32_t descriptor[16];
1598
1599 /* Descriptor for use as a storage image as opposed to a sampled image.
1600 * This has a few differences for cube maps (e.g. type).
1601 */
1602 uint32_t storage_descriptor[16];
1603 };
1604
1605 struct radv_image_create_info {
1606 const VkImageCreateInfo *vk_info;
1607 bool scanout;
1608 bool no_metadata_planes;
1609 };
1610
1611 VkResult radv_image_create(VkDevice _device,
1612 const struct radv_image_create_info *info,
1613 const VkAllocationCallbacks* alloc,
1614 VkImage *pImage);
1615
1616 VkResult
1617 radv_image_from_gralloc(VkDevice device_h,
1618 const VkImageCreateInfo *base_info,
1619 const VkNativeBufferANDROID *gralloc_info,
1620 const VkAllocationCallbacks *alloc,
1621 VkImage *out_image_h);
1622
1623 void radv_image_view_init(struct radv_image_view *view,
1624 struct radv_device *device,
1625 const VkImageViewCreateInfo* pCreateInfo);
1626
1627 struct radv_buffer_view {
1628 struct radeon_winsys_bo *bo;
1629 VkFormat vk_format;
1630 uint64_t range; /**< VkBufferViewCreateInfo::range */
1631 uint32_t state[4];
1632 };
1633 void radv_buffer_view_init(struct radv_buffer_view *view,
1634 struct radv_device *device,
1635 const VkBufferViewCreateInfo* pCreateInfo);
1636
1637 static inline struct VkExtent3D
1638 radv_sanitize_image_extent(const VkImageType imageType,
1639 const struct VkExtent3D imageExtent)
1640 {
1641 switch (imageType) {
1642 case VK_IMAGE_TYPE_1D:
1643 return (VkExtent3D) { imageExtent.width, 1, 1 };
1644 case VK_IMAGE_TYPE_2D:
1645 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1646 case VK_IMAGE_TYPE_3D:
1647 return imageExtent;
1648 default:
1649 unreachable("invalid image type");
1650 }
1651 }
1652
1653 static inline struct VkOffset3D
1654 radv_sanitize_image_offset(const VkImageType imageType,
1655 const struct VkOffset3D imageOffset)
1656 {
1657 switch (imageType) {
1658 case VK_IMAGE_TYPE_1D:
1659 return (VkOffset3D) { imageOffset.x, 0, 0 };
1660 case VK_IMAGE_TYPE_2D:
1661 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1662 case VK_IMAGE_TYPE_3D:
1663 return imageOffset;
1664 default:
1665 unreachable("invalid image type");
1666 }
1667 }
1668
1669 static inline bool
1670 radv_image_extent_compare(const struct radv_image *image,
1671 const VkExtent3D *extent)
1672 {
1673 if (extent->width != image->info.width ||
1674 extent->height != image->info.height ||
1675 extent->depth != image->info.depth)
1676 return false;
1677 return true;
1678 }
1679
1680 struct radv_sampler {
1681 uint32_t state[4];
1682 };
1683
1684 struct radv_color_buffer_info {
1685 uint64_t cb_color_base;
1686 uint64_t cb_color_cmask;
1687 uint64_t cb_color_fmask;
1688 uint64_t cb_dcc_base;
1689 uint32_t cb_color_pitch;
1690 uint32_t cb_color_slice;
1691 uint32_t cb_color_view;
1692 uint32_t cb_color_info;
1693 uint32_t cb_color_attrib;
1694 uint32_t cb_color_attrib2;
1695 uint32_t cb_dcc_control;
1696 uint32_t cb_color_cmask_slice;
1697 uint32_t cb_color_fmask_slice;
1698 };
1699
1700 struct radv_ds_buffer_info {
1701 uint64_t db_z_read_base;
1702 uint64_t db_stencil_read_base;
1703 uint64_t db_z_write_base;
1704 uint64_t db_stencil_write_base;
1705 uint64_t db_htile_data_base;
1706 uint32_t db_depth_info;
1707 uint32_t db_z_info;
1708 uint32_t db_stencil_info;
1709 uint32_t db_depth_view;
1710 uint32_t db_depth_size;
1711 uint32_t db_depth_slice;
1712 uint32_t db_htile_surface;
1713 uint32_t pa_su_poly_offset_db_fmt_cntl;
1714 uint32_t db_z_info2;
1715 uint32_t db_stencil_info2;
1716 float offset_scale;
1717 };
1718
1719 struct radv_attachment_info {
1720 union {
1721 struct radv_color_buffer_info cb;
1722 struct radv_ds_buffer_info ds;
1723 };
1724 struct radv_image_view *attachment;
1725 };
1726
1727 struct radv_framebuffer {
1728 uint32_t width;
1729 uint32_t height;
1730 uint32_t layers;
1731
1732 uint32_t attachment_count;
1733 struct radv_attachment_info attachments[0];
1734 };
1735
1736 struct radv_subpass_barrier {
1737 VkPipelineStageFlags src_stage_mask;
1738 VkAccessFlags src_access_mask;
1739 VkAccessFlags dst_access_mask;
1740 };
1741
1742 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1743 const struct radv_subpass_barrier *barrier);
1744
1745 struct radv_subpass_attachment {
1746 uint32_t attachment;
1747 VkImageLayout layout;
1748 };
1749
1750 struct radv_subpass {
1751 uint32_t input_count;
1752 uint32_t color_count;
1753 struct radv_subpass_attachment * input_attachments;
1754 struct radv_subpass_attachment * color_attachments;
1755 struct radv_subpass_attachment * resolve_attachments;
1756 struct radv_subpass_attachment depth_stencil_attachment;
1757
1758 /** Subpass has at least one resolve attachment */
1759 bool has_resolve;
1760
1761 struct radv_subpass_barrier start_barrier;
1762
1763 uint32_t view_mask;
1764 VkSampleCountFlagBits max_sample_count;
1765 };
1766
1767 struct radv_render_pass_attachment {
1768 VkFormat format;
1769 uint32_t samples;
1770 VkAttachmentLoadOp load_op;
1771 VkAttachmentLoadOp stencil_load_op;
1772 VkImageLayout initial_layout;
1773 VkImageLayout final_layout;
1774 uint32_t view_mask;
1775 };
1776
1777 struct radv_render_pass {
1778 uint32_t attachment_count;
1779 uint32_t subpass_count;
1780 struct radv_subpass_attachment * subpass_attachments;
1781 struct radv_render_pass_attachment * attachments;
1782 struct radv_subpass_barrier end_barrier;
1783 struct radv_subpass subpasses[0];
1784 };
1785
1786 VkResult radv_device_init_meta(struct radv_device *device);
1787 void radv_device_finish_meta(struct radv_device *device);
1788
1789 struct radv_query_pool {
1790 struct radeon_winsys_bo *bo;
1791 uint32_t stride;
1792 uint32_t availability_offset;
1793 uint64_t size;
1794 char *ptr;
1795 VkQueryType type;
1796 uint32_t pipeline_stats_mask;
1797 };
1798
1799 struct radv_semaphore {
1800 /* use a winsys sem for non-exportable */
1801 struct radeon_winsys_sem *sem;
1802 uint32_t syncobj;
1803 uint32_t temp_syncobj;
1804 };
1805
1806 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1807 VkPipelineBindPoint bind_point,
1808 struct radv_descriptor_set *set,
1809 unsigned idx);
1810
1811 void
1812 radv_update_descriptor_sets(struct radv_device *device,
1813 struct radv_cmd_buffer *cmd_buffer,
1814 VkDescriptorSet overrideSet,
1815 uint32_t descriptorWriteCount,
1816 const VkWriteDescriptorSet *pDescriptorWrites,
1817 uint32_t descriptorCopyCount,
1818 const VkCopyDescriptorSet *pDescriptorCopies);
1819
1820 void
1821 radv_update_descriptor_set_with_template(struct radv_device *device,
1822 struct radv_cmd_buffer *cmd_buffer,
1823 struct radv_descriptor_set *set,
1824 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1825 const void *pData);
1826
1827 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1828 VkPipelineBindPoint pipelineBindPoint,
1829 VkPipelineLayout _layout,
1830 uint32_t set,
1831 uint32_t descriptorWriteCount,
1832 const VkWriteDescriptorSet *pDescriptorWrites);
1833
1834 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1835 struct radv_image *image, uint32_t value);
1836
1837 struct radv_fence {
1838 struct radeon_winsys_fence *fence;
1839 struct wsi_fence *fence_wsi;
1840 bool submitted;
1841 bool signalled;
1842
1843 uint32_t syncobj;
1844 uint32_t temp_syncobj;
1845 };
1846
1847 /* radv_nir_to_llvm.c */
1848 struct radv_shader_variant_info;
1849 struct radv_nir_compiler_options;
1850
1851 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1852 struct nir_shader *geom_shader,
1853 struct ac_shader_binary *binary,
1854 struct ac_shader_config *config,
1855 struct radv_shader_variant_info *shader_info,
1856 const struct radv_nir_compiler_options *option);
1857
1858 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1859 struct ac_shader_binary *binary,
1860 struct ac_shader_config *config,
1861 struct radv_shader_variant_info *shader_info,
1862 struct nir_shader *const *nir,
1863 int nir_count,
1864 const struct radv_nir_compiler_options *options);
1865
1866 /* radv_shader_info.h */
1867 struct radv_shader_info;
1868
1869 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1870 const struct radv_nir_compiler_options *options,
1871 struct radv_shader_info *info);
1872
1873 struct radeon_winsys_sem;
1874
1875 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1876 \
1877 static inline struct __radv_type * \
1878 __radv_type ## _from_handle(__VkType _handle) \
1879 { \
1880 return (struct __radv_type *) _handle; \
1881 } \
1882 \
1883 static inline __VkType \
1884 __radv_type ## _to_handle(struct __radv_type *_obj) \
1885 { \
1886 return (__VkType) _obj; \
1887 }
1888
1889 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1890 \
1891 static inline struct __radv_type * \
1892 __radv_type ## _from_handle(__VkType _handle) \
1893 { \
1894 return (struct __radv_type *)(uintptr_t) _handle; \
1895 } \
1896 \
1897 static inline __VkType \
1898 __radv_type ## _to_handle(struct __radv_type *_obj) \
1899 { \
1900 return (__VkType)(uintptr_t) _obj; \
1901 }
1902
1903 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1904 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1905
1906 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1907 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1908 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1909 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1910 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1911
1912 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1913 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1914 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1915 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1916 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1917 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1918 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1919 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1920 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1921 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1922 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1923 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1924 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1925 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1926 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1927 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1928 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1929 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1930 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1931 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1932 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1933
1934 #endif /* RADV_PRIVATE_H */